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An embedded 1149.4 extension to support

mixed-signal debugging

Article in Microelectronics Journal · January 2011

DOI: 10.1016/j.mejo.2010.08.007 · Source: DBLP

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Microelectronics Journal 42 (2011) 218–232

Contents lists available at ScienceDirect

Microelectronics Journal
journal homepage: www.elsevier.com/locate/mejo

An embedded 1149.4 extension to support mixed-signal debugging$

Manuel C. Felgueiras a,n, Gustavo R. Alves a, J.M. Martins Ferreira b
a
ISEP/DEE, Rua Dr. António B. de Almeida, 4200-072 Porto, Portugal
b
FEUP/DEEC, Rua Dr. Roberto Frias, 4200-465 Porto, Portugal

a r t i c l e in f o a b s t r a c t

Article history: Debugging electronic circuits is traditionally done with bench equipment directly connected to the
Received 30 July 2009 circuit under debug. In the digital domain, the difficulties associated with the direct physical access to
Received in revised form circuit nodes led to the inclusion of resources providing support to that activity, first at the printed
30 July 2010
circuit level, and then at the integrated circuit level. The experience acquired with those solutions led to
Accepted 9 August 2010
the emergence of dedicated infrastructures for debugging cores at the system-on-chip level. However,
Available online 15 September 2010
all these developments had a small impact in the analog and mixed-signal domain, where debugging
Keywords: still depends, to a large extent, on direct physical access to circuit nodes. As a consequence, when analog
Built-in test and mixed-signal circuits are integrated as cores inside a system-on-chip, the difficulties associated
Diagnostics
with debugging increase, which cause the time-to-market and the prototype verification costs to also
IEEE 1149.4
increase.
Mixed-signals
Verification The present work considers the IEEE1149.4 infrastructure as a means to support the debugging of
mixed-signal circuits, namely to access the circuit nodes and also an embedded debug mechanism
named mixed-signal condition detector, necessary for watch-/breakpoints and real-time analysis
operations. One of the main advantages associated with the proposed solution is the seamless
migration to the system-on-chip level, as the access is done through electronic means, thus easing
debugging operations at different hierarchical levels.
& 2010 Elsevier Ltd. All rights reserved.

1. Introduction test of digital printed circuit boards (PCB) led to the proposal,
development and market acceptance of mechanisms able to surpass
Prototype debugging is one of the development phases of a the restrictions imposed by physical access. The strategy followed
circuit where design errors and, eventually, structural defects are consisted off embedding on the circuit the mechanisms facilitating
typically detected, diagnosed and corrected. This activity is that structural test, thus initially leading to proprietary solutions
traditionally done with the assistance of benchtop equipment inspired in level sensitive scan design (LSSD) [1], and later leading to
directly connected to the circuit under debug. However, the standard solutions such as the IEEE Std. 1149.1 [2], also known as
applicability of this traditional equipment has been progressively Joint Test Action Group (JTAG) or Boundary Scan Test (BST). The BST
impaired by trends such as the ever-increasing circuit complexity infrastructure facilitated both structural and the internal test and so
and miniaturization, and the use of surface mount devices (SMD). the market quickly adopted it, with a large part of its success being
These trends had limited effect with respect to analog and mixed- supported by its potential use as an electronic access port for debug
signal (AMS) circuits due to their reduced complexity and number of operations [3,4,5]. In fact, several integrated circuits (IC) made
pins when compared to their digital counterparts. This meant that, available to the market were specifically designed to increase the
at the digital side, the increasing difficulties in doing the structural controllability/observability levels of digital/analog circuit nodes/
buses. This was the case of components belonging to the System
TM
Controllability/Observability Partitioning Environment (SCOPE ) family
$ TM
The present paper is a condensed compilation of previous papers published by of Texas Instruments [6] and of the SCAN family of National
the authors with new material, namely the methodology for verifying the value of a
Semiconductor [7,8], as well as other components proposed by the
resistor present on an extended interconnection, using the mixed-signal condition
detector. This detector reduces the external test and measurement equipment academic community [9]. Some of these components allowed to
needed for verifying extended interconnections, as required when only using the partition a circuit into sub-circuits where debugging could be done
mandatory IEEE1149.4 infrastructure, in a similar to how simple interconnections with test equipment connected through a standard electronic access
are verified in digital printed circuit boards with IEEE1149.1-compatible compo- port, i.e. the test access port (TAP) [5]. This strategy was however
nents.
n
Corresponding author. Tel.: +351 228340532.
clearly insufficient for debug operations in real-time due to the serial
E-mail addresses: [email protected] (M.C. Felgueiras), [email protected] nature of the BST architecture (i.e. information is serially shifted
(G.R. Alves), [email protected] (J.M. Martins Ferreira). through the 4-pin TAP). In this context, components that reuse the

0026-2692/$ - see front matter & 2010 Elsevier Ltd. All rights reserved.
doi:10.1016/j.mejo.2010.08.007
 Author's personal copy

M.C. Felgueiras et al. / Microelectronics Journal 42 (2011) 218–232 219

IEEE1149.1 infrastructure for supporting advanced debug operations built on top of such infrastructures would also benefit the later
started to emerge, e.g. the digital bus monitor [10] that implements migration to the SOC level, of AMS circuits. In this sort of AMS
a logic/signature analyzer at board-level. This component included a components, which assume every-day an increasing importance, the
digital condition detector that allowed filtering the data captured at analog part accounts for approximately 2% of the total number of
board-level, during a certain functional operation period, and transistors, 20% of the total area, and 40% of the total design effort
subsequently stored in an internal memory. The stored data could [28], a direct consequence of the lack of a common platform to
then be shifted out, through the TAP, for later analysis with external support the debug phase. Although the analog/mixed-signal portion
equipment. The following trend consisted in embedding, inside the is smaller than the digital part, its contribution to the development
IC or system-on-chip (SOC), blocks specifically designed for costs is higher and will continue to grow unless a new debugging
supporting debug operations, reusing once again the TAP as an paradigm is found. A direct consequence of this fact is the extended
interface mechanism. This trend was particularly visible in micro- time spent on the prototype validation phase, which negatively
processors, with several examples provided by industry, e.g. [11], influences the component’s time-to-market (TTM), a key factor for
which converged to a standard solution known as NEXUSTM [12]. In the final product success. The current need for structured mechan-
this context, the problems associated with the migration of entire isms supporting debug operations in AMS circuits is so crucial that, if
digital ICs into SOCs, particularly at the debug phase, benefited from not properly addressed in the near future, it may impair the normal
earlier, proven solutions based on electronic access mechanisms. development curve of several consumer electronic manufacturers
In the AMS area, the dominant situation is practically the opposite, [29]. Another emergent and promising area requiring such mechan-
as this type of circuit is usually designed with restrictive specs, tight isms refers to the use of reconfigurable analog circuits, i.e. field-
tolerance margins, and presents a lower complexity level when programmable analog arrays (FPAA) [30,31,32], which call for
compared to their digital counterparts. This means that, when mixed- effective functional verification methodologies. Notice that in the
signal ICs are present in a PCB that also contains digital ICs, the AMS case of field-programmable gate arrays (FPGA), the IEEE1149.1
part is a relatively small portion of the entire circuit complexity. The infrastructure is presently reused for reconfiguration purposes [33]
debug phase of this type of circuits benefited from the market as well as for accessing internal user-defined registers or even the
appearance of the mixed-signal oscilloscope (MSO) [13,14], which contents of all register elements [34]. In summary, the IEEE1149.1
combined the visualization of several tens of pure digital channels infrastructure proved particularly useful as a structured mechanism
with that of 2–4 analog channels, while accepting trigger conditions for debug operations in digital circuits, and did also provide the basis
in the digital, analog, or mixed-signal domains. The intrinsic for other infrastructures specifically developed for debug purposes.
characteristics of AMS circuits and the lack of a standard infra- Considering the IEEE1149.4 infrastructure to be the formal extension
structure for accessing its nodes supported the long lasting solution of of its predecessor for mixed-signal components, its reuse should be
using physical access for debug purposes. Nevertheless, this type of also analyzed for supporting debug operations in AMS circuits. This
access was to be progressively replaced by ad-hoc and structured is the aim of the present work, which proposes reusing this
electronic access mechanisms [15,16,17]. The publication of the infrastructure for (1) accessing, in an analog fashion, analog/digital
IEEE1149.4 std. [18] raised high expectations in the test/debug nodes (either corresponding to internal nodes or associated
community, as this infrastructure was formally presented as the with component pins), and (2) interfacing with a mixed-signal
natural extension of the IEEE1149.1 std. to the AMS area, aiming at condition detector (MCD), i.e. an internal block specifically designed
facilitating structural, parametric and internal tests. However, its to support debug operations such as breakpoints/watchpoints or
adoption has proved slow, with most cited limitations being related real-time analysis.
to the degradation of the circuit performance [19] and the relative The rest of this paper is organized as follows: Section 2
high overhead in ICs of reduced complexity, typically the case in the presents a debug model for MS circuits; Section 3 explains how
AMS area. While the first limitation can be minimized with proper the IEEE1149.4 infrastructure is re-used for accessing the circuit
design rules [20], the second can only be tackled if the infrastructure nodes under debug; Section 4 introduces and describes the MCD;
proves to be useful for purposes other than the original ones specified Section 5 deals with the validation of the associated debug
in the standard, thus further justifying its inclusion at the IC level. In methodology; Section 6 discusses the impact and cost of the MCD;
this sense, it has already been proposed to reuse it for: and, finally, Section 7 concludes the paper.

! parameter characterization, i.e. VOL, IOL, VOH, IOH, VIL, IIL and IIH [21]; 2. The debug model
! supporting radio-frequency (RF) measurements [22];
! supporting the test of ADCs and DACs [23]; Circuit debugging is traditionally done with the assistance of
! remote test and debug of PCBs with AMS components [24]; benchtop equipment requiring some sort of access type. Some
! monitoring analog signals in automotive environments [25]; debug tools are specific of microprocessor-based circuits, such as
in-circuit emulators (ICE), while others remain generic, such as
Additionally, and following a trend observed in the digital logic analyzers, oscilloscopes or multimeters. Although each tool
domain, some manufacturers made available to the market can do/support a large number of debug operations, these can be
IEEE1149.4-compatible ICs targeting the increment of controll- grouped in a small set of debug operation types. According to the
ability/observability levels of analog nodes in PCBs [26,27]. simple debug model illustrated in Fig. 1, any debug operation fits
In this line of evolution, the natural, subsequent step should now into one of four debug operation types, namely:
be the development of IEEE1149.4-compatible mechanisms offering
the possibility to execute, inside the PCB, debug operations similar to ! Control, observation and verification (COV) of the circuit state
those supported by an MSO. Considering this equipment as a ! Breakpoint/watchpoint
combination of a logic analyzer with an oscilloscope, this step would ! Step-by-step
be equivalent to the introduction of the digital bus monitor [10], ! Real-time analysis
now for the AMS arena. The experience and limitations arising from
the use of such a debug mechanism would allow guiding the COV operations are assumed to be the basic debug operations and
subsequent development of specific infrastructures for supporting are used to control/observe/verify the state of a circuit. Breakpoint/
debug operations in mixed-signal circuits. Any standardization effort watchpoint, step-by-step and real-time analysis are considered
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220 M.C. Felgueiras et al. / Microelectronics Journal 42 (2011) 218–232

Fig. 1. A simple debug model.

Advanced debug operations and are used to control/observe/verify outputs (I/O) and any other circuit access points enabling a direct
the circuits function in the time domain. connection with an automatic test equipment (ATE) or any other
Providing a simple example of a debug sequence in the digital test and measurement equipment. This access type presents serious
domain, suppose one intends to verify if a given memory location limitations due to the ever-increasing circuit miniaturization levels
contains a given value, when the program counter reaches a certain and the existence of components on both PCB sides – surface-mount
address. The sequence of steps is: (1) place a known value in the technology (SMT) – where some totally prevent the physical access
memory target location, using a control operation; (2) place the to the device pins, when encapsulated with the ball grid array (BGA)
circuit in its normal functioning state and then wait till the technology. Even when the direct physical access enables observing
breakpoint condition is met, i.e. the program counter reaches given a given node of the circuit under debug (CUD), it does not imply the
address, causing the circuit to stop; (3) read the contents of the possibility to actually control the node value, which depends on the
memory target location, using an operation of the observation type; limit for the backdriving current. Direct electronic access is done
and (4) verify if the read value matches the expected one, using an through scan chains or any other dedicated logic/circuit paths. Non-
operation of the verification type. These debug operations are direct access is based on signal propagation through internal circuit
generic and hence applicable to any sort of digital circuit. For blocks, which restricts its practical use to circuits of low/medium
instance, a breakpoint operation can be applied in a sequential complexity.
circuit by stopping the clock signal, when a certain circuit condition The IEEE1149.1 and the IEEE1149.4 infrastructures are two
is met, forcing the circuit to retain its present state and enabling the examples of the direct electronic access type. While the first is
use of COV operations to ascertain about the correctness of that largely used as a mechanism for controlling and/or observing the
state. A step-by-step operation can be applied to the same circuit to circuit internal nodes and pins, the second one faces some
observe and verify each one of its possible states. Real-time analysis difficulties for that purpose, according to the study presented in
operations comprehend state recording and the validation of circuit [35]. In fact, the most usual boundary scan cell (BSC) configuration
conditions, in real-time. Typical application examples of this type of described in the IEEE1149.1 std. (i.e. with two 2:1 multiplexers and
debug operation include: store the circuit state until breakpoint two flip-flops) presents a fixed signal flow orientation, allowing at
condition; store the circuit state after a breakpoint condition; among all-times the control of the BSC parallel output, irrespective of the
others usually supported by logic analyzers, oscilloscopes with circuit connected to the pin associated with that BSC. In contrast, the
memory, and also by MSOs. switching structure of the analog boundary module (ABM) described
In realistic terms, this very basic debug model can be extended in the IEEE1149.4 std. presents a fixed pin orientation. According to
to the MS domain. Suppose, for instance, one intends to store the the scheme illustrated in Fig. 2a, it is only possible to control, via
circuit state when an analog value (e.g. a voltage) reaches a given AT1/AB1, the value of the mission circuit connection (MCC) if the
threshold—in basic terms, this would correspond to a breakpoint driving source of the pin connection (PC) can be placed in a high-
operation. In the same line of reasoning, a step-by-step operation impedance state, i.e. the case, for instance, when the IC containing
could be used to verify the cut-off frequency of a digital that driving source is IEEE1149.4-compatible.
programmable filter, by applying at the filter input (at each step) Fig. 2b presents a solution to overcome this limitation by
an analog signal of increasing frequency and observing (at each adding an extra switch to the ABM switching structure. Notice the
step) the filter output. Both debug operation types (breakpoint IEEE1149.4 std. allows placing additional switches inside that
and real-time analysis) imply the evaluation of circuit conditions structure.1 Furthermore, an ABM can also be associated with
and thus require an MCD able to detect them. digital pins to allow controlling/observing the corresponding
The proposed basic debug model and the described debug signals in an analog mode.2,3 In this line of reasoning, Fig. 3
sequences reveal the need for (1) a mechanism enabling the presents the topology of a proposed generic ABM (G-ABM) that
access to the circuit nodes under debug, and (2) an MCD capable allows controlling/observing the nodes located at both sides of the
of supporting the referred advanced debug operations. These two SD switch.
aspects will now be addressed in detail in Sections 3 and 4. For a large number of applications, not all elements that form
the G-ABM are strictly necessary. However, this a starting point to

3. Extending the IEEE1149.4 infrastructure for COV operations

1
(IEEE1149.4—7.3.4): The infrastructure allows adding extra conceptual
The access types that distinguish the possible alternatives for switches to increase the flexibility of the ABM.
2
(IEEE1149.4—7.2.1.1.a): The infrastructure allows associating ABMs or DBMs
implementing COV operations can be divided into: (a) direct to digital pins.
physical access; (b) direct electronic access; and (c) non-direct 3
(IEEE1149.4—3.1.1 NOTE): An ABM may be attached to a digital function pin
access. Direct physical access comprises the circuit primary inputs/ in order to provide analog measurement capability to the pin.
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M.C. Felgueiras et al. / Microelectronics Journal 42 (2011) 218–232 221

mixed-signal circuits have both digital and analog values, the

MCD should support comparison operations in both domains. A
detection circuit operating in the digital domain and fully
compatible with the IEEE1149.1 infrastructure was already
described in [38]. Since this infrastructure uses a serial data
transmission protocol, there is a considerable delay between the
moment a condition occurs (inside the circuit) and the moment
an external detector validates and signals its occurrence. A
possible and obvious solution is to move the condition detector
into the circuit under debug. There are already proposals of such
detection circuits in the analog domain [39,40], which support a
reduced number of analog comparison limits and detectable
condition types. The proposed solutions also face serious limita-
tions due to their inherent dependence of externally defined
analog voltages, corresponding to the comparison limits, which
compromise the overall detector precision.
The design of a MCD can follow several directions, according to
the requirements identified. In our case, we have considered the
following ones:

! Support different comparison operations between observed/

expected values.
! Rely on electronic access rather than physical access.
Fig. 2. Modifying the ABM to allow full-control of the mission circuit connection. ! Guarantee compatibility with the IEEE1149.4 infrastructure.
! Minimize the impact, i.e. the overhead due to the MCD.
! Compare both analog and digital values inside the circuit
under debug.

The comparison operations supported by the MCD require an

expected value and a mask for operations of the type ¼ and a, a
Limit_A for operations of the type 4, Z, o and r, and also a
Limit_B for operations of the type A[Limit_A;Limit_B] and
e[Limit_A;Limit_B].
The most efficient solution to overcome the difficulties
associated with the physical access is to migrate all the
Fig. 3. Topology of the G-ABM. mechanisms needed for doing those operations into the circuit
under debug. This has been the most relevant reason to justify the
allow a systematic approach to the needs raised by each and every inclusion on the target circuit (i.e. the circuit under debug) of ad-
possible case. The present work proposes additions to the hoc mechanisms, plus standard or proprietary infrastructures.
IEEE1149.4 std. allowing (1) the circuit designer to freely choose Also in the present case, the best location will be the one allowing
any ABM resulting from the illustrated G-ABM; (2) the chosen access to both digital and analog nodes. Depending on the
ABMs to be associated with both pins and internal nodes; and, (3) hierarchical level, that location can either correspond to an IC
the corresponding control registers to be part of the boundary inside a PCB or a block inside an IC. The trend towards
scan register (BSR). These proposals are twofold. First, they miniaturization, which increasingly promotes the interest for
increase the flexibility of the IEEE1149.4 infrastructure, following the SOC level, justifies the inclusion of both the MCD, as a built-in
an approach similar to the IEEE149.1 std., which describes several dedicated block, and the mechanisms necessary to access any
BSCs that can be selected according to the specific control/ node under debug.
observation requirements of each node. Second, they support the The overhead introduced by the MCD should be minimized
claim of conformity with the IEEE1149.4 std. of several circuits through the reuse, whenever possible, of the test resources
using variations of the G-ABM. In fact, conformity will still apply already available inside the IC. In this sense, it is possible to reuse
even if partial implementations are used. This is the case, in the IEEE1149.4 test infrastructure to: (1) access this new block;
particular, of several manufacturers that have adopted solutions (2) select the nodes under debug; and (3) store, in a digital form,
based on the IEEE1149.4 std., but following internal requirements values required for the comparison operations (expected value/
that led to simpler/reduced modules, in order to minimize the mask or Limit_A/Limit_B). The register elements of every BSC –
associated overhead [36,37]. In this sense, it is possible to design now called digital bus module (DBM) in the IEEE1149.4 – can be
specific ABM versions targeting the interconnection of internal used for this purpose, as test operations are not concurrent with
nodes to the MCD, so as to extend the range of possible debug operations. In contrast, the register elements pertaining to
breakpoint/watchpoint conditions. the test bus interface circuit (TBIC) and ABM control structures
cannot be reused for this purpose, as the state of the associated
switching structures depends on the current contents of those
4. The mixed-signal condition detector registers. As both the TBIC and ABMs are used to route the signal
from the analog node under debug till the MCD analog input, it is
From a functional point of view, the MCD compares the value not possible to accommodate simultaneously the two concurrent
present at the node(s) under debug with one or two limits. As goals.
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222 M.C. Felgueiras et al. / Microelectronics Journal 42 (2011) 218–232

In order to support detection operations in both domains, the the pure analog domain, is not often supported due to the implicit
MCD must include two independent condition detectors [41], one interaction between the two domains.
for the digital condition and another for the analog condition, as As the comparison operations of the MCD are done in the pure
illustrated in Fig. 4. digital domain, the most direct solution to store all the data
Each detector has the following inputs: the signal(s) from the needed for those operations is to reuse the memory elements
node(s) under debug; the expected value/Limit_A; the mask/ pertaining to the test infrastructure (not simultaneously used for
Limit_B, and a set of configuration lines to define the current other purposes) and include additional registers accessible
operation. The output of each detector is named after its domain, through that same infrastructure. These operations take place
i.e. analog/digital valid condition (AVC/DVC), which is logic high while the CUD is on its normal operational state, so it is possible
(‘‘1’’) whenever a condition is evaluated as true. The MCD output, to reuse the IEEE1149.4 infrastructure for storing part of the data
named output valid condition (OVC), can either exhibit the AVC needed. In fact, the DBM registers can be reused to store the
signal, the DVC signal, or a logic combination of both, following a expected value and the mask (or the Limit_A and the Limit_B) –
typical functionality present in MSO. The OVC signal can be used for the condition in the digital domain – on the update (U) and
for debug purposes inside the CUD (e.g. stop the clock signal on a capture/shift (C/S) stages, respectively. In this way, the BSR is
breakpoint operation) or simply to externally indicate the reused on its full storage capacity (minimizing overhead), as the
detection of a valid condition (e.g. on a watchpoint operation). memory elements of the TBIC and ABM control registers must
Fig. 5 illustrates a debug scenario where the MCD is used to hold their previous values. Notice that while the operational
support a breakpoint operation on an AMS circuit with a mode of a BSC depends mostly on the current test instruction, the
microprocessor. operational mode of the TBIC and ABMs also depend on the
In this sort of circuits (with a microprocessor) it is important to contents stored in the corresponding control registers that are
hold the operation at the very moment a condition is met, either in part of the BSR. In order to store 2 vectors in the U and C/S stages
the digital or analog domain. However, holding the circuit operation of each DBM, the UpdateDR signal (true at logic ‘‘1’’ when the TAP
on the digital/analog domain, upon the occurrence of a condition in controller is on the Update-DR state) must be deactivated to avoid

Fig. 4. Conceptual block diagram of the MCD.

Fig. 5. Using the MCD to support a breakpoint operation.

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M.C. Felgueiras et al. / Microelectronics Journal 42 (2011) 218–232 223

Fig. 6. Structure of a basic (1-bit) condition detector and the corresponding simplified representation.

corrupting the data stored in the Update stage. A DBM can thus Table 1
contain the 3 signals needed for a comparison operation, as Comparison operation types supported by the MCD.
illustrated in Fig. 6.
C2 C1 C0 Operation type Note
The structure composed by a single DBM and a single F block
forms a basic (1-bit) condition detector, whose output (Q2,Q1,Q0) 0 0 0 ¼A Requires a mask
depends on the: 0 0 1 aA Requires a mask
0 1 0 4Limit_A
0 1 1 o Limit_A
! actual observed value, present at the parallel input (PI) of the 1 0 0 Z Limit_A
BSC; 1 0 1 r Limit_A
! expected value/mask or Limit_A/Limit_B stored in the DBM (C/ 1 1 0 Inside the interval [A, B] Requires a Limit_B
1 1 1 Outside the interval [A, B] Requires a Limit_B
S, U stages);
! result from the previous basic condition detector (I2,I1,I0); and
! selected comparison operation (C2,C1,C0).

There are five possible comparison results exhibited at Table 2

(Q2,Q1,Q0): false, true, equal to A, great than A, or less than B; Truth table of the F block for the ‘‘¼ A’’ operation.
thus 3 lines (23) are necessary to codify all possibilities. The F
Coded C/S U PI Coded
block supports 8 comparison operations, which requires 3 lines to
(I2,I1,I0) (Q2,Q1,Q0)
codify them, according to the sequence presented in Table 1.
According to the current operation type (C2,C1,C0), the F block F X X X F
evaluates the result present at (Q2,Q1,Q0), which is a logic T 0 X X T
function of the inputs (I2,I1,I0) and of the contents present at C/S, T 1 O 0 T
T 1 O 1 F
U and PI. Table 2 presents, as an example, the truth table for T 1 1 0 F
operation ‘‘ ¼A’’, selected when (C2,C1,C0)¼(0,0,0). The remaining T 1 1 1 T
7 truth tables are not shown here due to space restrictions.
Fig. 7a illustrates how the several basic condition detectors,
each formed by a DBM+an F block, are concatenated to form a
digital condition detector register (DCDR), which allows detecting
n-bit digital conditions. This register acts as a word comparator number of bits belonging to the detection configuration register
whose result is shown in the DVC output. The additional FA block (DCR). The FC block is responsible for driving OVC (an MCD
is necessary to define, according to the current operation, the primary output), from 4 possible sources: (i) AVC, (ii) DVC,
input values (I2,I1,I0) for the first basic condition detector. (iii) AVC AND DVC and (iv) AVC OR DVC. The source is selected
Likewise, the additional FB block is necessary to compute the through signals VS1 and VS0, i.e. 2-bits belonging to the DCR. OVC
DVC logic value according to the current operation and the output is valid when inputs COMP2 and RTI are true. These two signals
values of the last basic condition detector. A simplified repre- act as an enable input. COMP2 is true at logic level ‘‘1’’ when the
sentation of the DCDR is illustrated in Fig. 7b. IEEE1149.4 instruction register (IR) is loaded with the optional
A similar yet simplified register associated with an ADC is used instructions EXTEST2, PROBE2 or INTEST2 (described ahead), while
to detect analog conditions. The comparison operation takes place RTI is true at logic level ‘‘1’’ when the TAP controller is on the Run-
in the pure digital domain, as illustrated in Fig. 8, with the ADC Test/Idle state. Table 3 resumes the operation of the FC block.
input connected to one line (AB2) of the internal analog test OVC can either be an internal signal used for breakpoint
bus—a part of the IEEE1149.4 infrastructure. The analog condition operations, when the necessary mechanisms for stopping the
detector register (ACDR) is an optional register, permitted by the circuit operations are present, or a dedicated output pin used to
IEEE1149.4 std., internally built with DBM-alike blocks without flag an event to the outside world, as already illustrated in Fig. 5.
the second multiplexer (i.e. it does not have primary outputs), as DCR corresponds to an 8-bit optional register added to the
it only receives information from the ADC. registers structure accessible through the IEEE1149.4 infrastruc-
The operation type implemented by the analog condition ture. Fig. 9 illustrates its internal contents, where the purpose of
detector register (ACDR) and the DCDR is defined by inputs each group of bits was already described in the previous
(C2A,C1A,C0A) and (C2D,C1D,C0D), respectively, fed by an equal paragraph.
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Fig. 7. DCDR structure and simplified representation.

Fig. 8. MCD structure.

Table 3 The DCDR is formed by the DBMs already present in the circuit,
Truth table for the OVC signal. making this register a part of the BSR. The same does not apply to
the ACDR. However, it should be possible to shift in the Limit_A
RTI COMP2 VS1 VS0 OVC
vectors to both registers, during the same shift sequence, and then
0 X X X 0 store them at the respective update stages. The same should be
X 0 X X 0 also possible for the Limit_B vector. The register structure
1 1 0 0 DVC presented in Fig. 10 enables this possibility by serially connecting
1 1 0 1 AVC
1 1 1 0 DVC OR AVC
the boundary scan and the analog condition detector registers (i.e.
1 1 1 1 DVC AND AVC BSR+ACDR), when the data multiplexer input 2 is selected.
Selecting input 1 enables accessing the DCR for debug configura-
tion purposes, while the two remaining inputs (3 and 0) serve the
mandatory boundary scan and bypass registers. Notice that DCDR
is not represented as a discrete register as it is part of the
mandatory BSR.
In order to operate the functionally provided by the MCD, it is
necessary to add a number of new optional instructions to the
IEEE1149.4 infrastructure. A first optional instruction, named
SELCON, is required to place the DCR into the test data input
(TDI)—test data output (TDO) path, i.e. to select input 0 of the
Fig. 9. The DCR description. data mux illustrated in Fig. 10. A second optional instruction,
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Fig. 10. Registers structure supporting the MCD.

Table 4
Characteristics associated with the proposed optional instructions.

Optional instruction Selected data mux input UpdateDR signal disabled Behaviour of the remaining
IEEE1149.4 infrastructure

PROBE2 2 Yes ¼PROBE

INTEST2 2 Yes ¼INTEST
EXTEST2 2 Yes ¼EXTEST
S/P2 2 No ¼S/P
SELCON 0 – ¼BYPASS

named SAMPLE/PRELOAD2 (or S/P2, in an abbreviated form) selects selected mission circuit should also allow demonstrating the use
input 2 of the same data mux, to allow storing the Limit_A vector of both analog and mixed-signal condition detection operations.
on the U stages of DCDR and ACDR. A third optional instruction, Developing a circuit in hardware with such characteristics would
named PROBE2, has multiple purposes: (1) it selects input 2 of the be quite time consuming, as the number of IEEE1149.4-compatible
data mux to allow storing the Limit_B vector on the C/S stages of devices is reduced and, furthermore, do not support the proposed
DCDR and ACDR; (2) it disables the UpdateDR signal to avoid ABM variants. The alternative of implementing a compatible circuit,
corrupting the previously stored Limit_A, when the TAP controller using discrete components, is also quite cumbersome and time
passes through the Update-DR state; (3) it allows selecting the consuming as already demonstrated through the example described
current analog node under debug feeding the ADC input, i.e. in a in [42], referring to a simple functional circuit composed of a digital
similar operating mode provided by the mandatory PROBE inverting buffer and an operational amplifier with unitary gain,
instruction, it connects the AB2 switch of the ABM associated surrounded by the mandatory IEEE1149.4 infrastructure. In order to
with the analog node selected for debug purposes and routes the validate the proposed debug model, a substantially more complex
signal through the internal test bus line with the same name circuit is required, thus favouring the use (in a first approach) of a
(AB2) to the input of the ADC associated with the ACDR. Similar to simulation environment. We decided for OrCAD v10.3, supported by
the PROBE mandatory instruction, the PROBE2 optional instruction Cadence, which includes a PSpice simulator. The main character-
allows using the internal analog test bus in a non-intrusive mode istics of the mission circuit designed for validation purposes are:
during the mission circuit normal operation mode. Another two
optional instructions, named INTEST2 and EXTEST2, allow using ! Includes at least two mixed-signal macro blocks, enabling the
the MCD when the IEEE1149.4 infrastructure is placed in the association of an ABM to an internal analog node.
internal and external test modes, respectively. When the present ! Enables detection operations on analog nodes and/or digital
instruction is PROBE2, INTEST2 or EXTEST2, the remaining buses.
elements of the IEEE1149.4 infrastructure retain their operational
conditions, defined for the mandatory instructions PROBE, INTEST
and EXTEST, respectively. Table 4 summarizes some character- As illustrated by Fig. 11, the selected macro-blocks composing the
istics of the proposed optional instructions. mission circuit are a 4:1 analog mux and a 12-bits ADC (named
The following section will now describe the sequence of ADC1). ADCs and analog multiplexers/switches are quite common in
IEEE1149.4 operations necessary for using the MCD and the G- MS circuits, with the association of ADC plus analog mux, in
ABM to implement part of the debug model presented in Section 2. particular, being frequently found in circuits comprising a micro-
controller.
The complete target circuit includes the mission circuit plus an
5. Validating the proposed solution through simulation IEEE1149.4 infrastructure with the proposed extensions, i.e. the
ABM variants described in Section 3, and the MCD described in
To validate the proposed debug model it is necessary to have a Section 4. The main characteristics of the target circuit are:
mission circuit surrounded by an IEEE1149.4 infrastructure
comprising the previously defined extensions, i.e. the MCD and ! The digital pins have DBMs associated with.
the non-canonical ABM topologies that allow (i) controlling the ! The analog input pins have ABMs associated with a topology
mission circuit inputs in an independent mode, and (ii) accessing corresponding to the one illustrated by Fig. 2b (identified as
internal analog nodes for control/observation purposes. The variant ABM-1).
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Fig. 11. Mixed-signal target circuit used for verification purposes.

! The internal analog node corresponding to the interconnection respectively (corresponding to the analog mux inputs S1–S4). The
between the analog mux output and the functional ADC input associated ABMs should be in the transparent mode.
contains an ABM whose topology includes the SB1, SD and ! The digital control inputs (EN,A1,A0) of the analog mux should
SB22 conceptual switches of the proposed G-ABM (see Fig. 3). be controlled through the pins holding the same name. The
This topology is named ABM-4 and allows full control/ associated DBMs should thus be in the transparent mode. In
observation of the analog node through the internal test bus the provided example, input S1 is driving the analog mux
AB1/2 lines. output D, which implies (EN,A1,A0)¼(1,0,0).
! The IEEE1149.4 std. imposes DBMs for the functional ADC ! ABM-4 should be in the non-intrusive observation mode (i.e.
outputs. These DBMs are reused in the DCDR. switches SD and SB22 closed, and SB1 open), allowing the
! The MCD and the associated ADC (named as ADC2) are part of signal present at the analog mux output D to be routed to the
the internal debug and test infrastructure and allow detecting ADC2 input, through AB2.
analog conditions (defined by the ACDR). ! OVC should be at logic level high (‘‘1’’) whenever the internal
! ADC1 and ADC2 are equal and present a transfer function analog signal present at the interconnection between the analog
where the analog input range [ # 10 V; +10 V] is converted into mux output and the functional ADC input is higher than +6 V OR
a digital word in the [000h; FFFh] interval. the digital output pins of the mission circuit (corresponding to the
ADC1 data bus) exhibit a vector value lower than 66Bh.
To validate part of the proposed debug model we follow an
To select this debug operation, we first define the DCR contents,
example where the MCD is used with the ‘‘ 4 Limit_A’’ and ‘‘ o
i.e. the values uploaded into (C2D,C1D,C0), (C2A,C1A,C0A) and
Limit_A’’ operations, for detecting an analog and a digital
(VS1,VS0). The first two sub-vectors are defined according to Table 1
condition, respectively, during the circuit normal operation. The
and the last one according to Table 3. In the present example, we
circuit is placed in the following normal operating conditions:
select the ‘‘oLimit_A’’ operation for the digital part, which
corresponds to (C2D,C1D,C0)¼(0 1 1); the ‘‘4Limit_A’’ operation for
! Four different analog signals (V1–V4), simulating four different the analog part, which corresponds to (C2A,C1A,C0A)¼(0,1,0); and
analog sources, are applied to the circuit functional inputs E1–E4, OVC as a logic OR between AVC and DCV, which corresponds to
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Table 5 %limit_B/mask, an all 1’s vector is shifted into

ADC1 and ADC2 conversion values. the Digital and
%Analog Parts.
ADC (analog) input ADC (digital) Comments
value (V) output value TAP controller’Run-Test/Idle;

# 10 000h Lowest value Simulating the described circuit in the OrCAD simulation
#2 66Bh Digital condition value environment requires the definition of the input stimuli, namely
0 800h (GND) for the TAP input signals (TCK, TMS and TDI). To speed up the
+6 CD7h Analog condition value simulation process, we developed an in-house application, named
+ 10 FFFh Highest value
BSOrcad, which automatically generates the input stimuli for the
3 digital input signals, from a test program written with commands/
data similar to those specified by the serial vector format. The
output of the BSOrcad application is a file ‘‘ofilename4.stl’’
directly interpreted by the PSpice simulator. Fig. 12 illustrates the
(VS1,VS0)¼(1,0). This results in shifting in the (C2D,C1D,C0,C2A, simulation results for the example described earlier.
C1A,C0A,VS1,VS0)¼(0110 0100 01)¼ 6Ah vector into DCR, using the The names appearing at the upper left corner of Fig. 12,
SELCON optional instruction. Next, we must select the values correspond to the following signals (by order of appearance, i.e.
corresponding to the analog Limit_A and to the digital Limit_A. The top-down):
first corresponds to the digital conversion of the indicated upper limit
voltage (+6 V), i.e. (110011010101)¼CD7h, while the second is
already a digital word, i.e. (011001101011)¼66Bh. These two analog
! TCK (test clock), TMS (test mode select), TDI and TDO
values / digital words are represented in Table 5 for the sake of clarity.
! TAP controller state (coded according to the suggestions of the
IEEE1149.1 std.)
The two digital words are shifted into DCDR and ACDR using
the optional S/P2 instruction. The ‘‘ o Limit_A’’ and ‘‘ 4 Limit_A’’
! IR contents
comparison operations do not require a Limit_B nor a mask, so we
! DCR contents
may shift an all 1’s vector to the C/S stages of those two condition
! AVC signal
detector registers, using the PROBE2 optional instruction. The
! DVC signal
detection process starts the moment the TAP controller enters the
! OVC signal
Run-Test/Idle state. The following paragraph lists the pseudo-code
! Analog signal present at AB2 (IEEE1149.4)
with the sequence of steps necessary to configure the IEEE1149.4
infrastructure and the MCD with the previously identified A careful analysis of Fig. 12 reveals the TAP controller to be in
parameters. the Shift-IR (Ah) and Shift-DR (2h) states for longer periods, as it is
in these states that vectors are serially shifted into/out of the
Instruction Register’SELCON; IEEE1149.4 infrastructure. The last TAP controller state (from
%Select position 0 in the Data MUX (see Fig.10); E3.4 ms onwards) corresponds to Run-Test/Idle (Ch), where the
Detection Configuration Register MCD will be active (see Table 3), given the instruction loaded into
(C2D,C1D,C0D,C2A,C1A,C0A,VS1,VS0)’(6Ah); the IR (PROBE2, i.e. 06h). The IR is loaded with BYPASS (FFh), on
%Shift in the vector that selects the analog and power-up, and then loaded with SELCON (08h), SAMPLE/PRELOAD2
%digital conditions types, and selects the analog (05h), and, finally, with PROBE2 (06h). The DCR is loaded with 0h,
OR the on power-up, and then with 6Ah, according to the explanation
%digital detections to be outputted at the OVC pin; provided in the previous paragraphs. After shifting in the vector
Instruction register’SAMPLE/PRELOAD2; corresponding to the PROBE2 instruction (06h), more precisely on
%Select position 2 in the Data MUX (see Fig. 10); the Update-IR state (at the TCK falling edge), the AB2 line starts to
SR +Analog Condition Detector Register’(YYYy66B follow the voltage present at the ABM-4 input. Notice that, in the
CD7h); example provided, AB2 monitors the analog value present at the
%Shift in the vector that selects the analog node analog functional input of ADC1 (part of the mission circuit) while
%under analysis (YYY) and the Limit_A for the DCDR is loaded with the condition to be detected on the ADC1
Digital (BSR) and digital output bus. This combination allows us to verify the
%Analog Condition Detector Registers; the digital detection limits ( oLimit_A , 4Limit_A) of both analog and digital
%value (that corresponds to -2 V on the analog parts, in relation to the analog voltage present at AB2. The ACDR
value) output (i.e. AVC) is at logic ‘‘1’’ whenever the voltage at AB2 is
%is shifted into the Digital Part; the analog value higher than + 6 V, while the DCDR output (i.e. DVC) is at logic ‘‘1’’
%that corresponds to + 6 V is shifted into the whenever the contents of the ADC1 digital output bus is lower
Analog part; than 66Bh, i.e. whenever the voltage at AB2 is lower than # 2 V.
Instruction Register’PROBE2; OVC is at logic ‘‘1’’ when the following conditions are true at
%Select position 2 in the Data MUX (see Fig. 10); the same time: (i) the result of AVC OR DVC is true; (ii) the
BSR +Analog Condition Detector Register’(YYYyFFF current instruction is PROBE2; and (iii) the TAP controller is on
FFFh); Run-Test/Idle. The example given illustrates the MCD being used in
%Signal UpdateDR disabled in the Analog and a debug operation while the mission circuit is on its normal
Digital operation mode. This was accomplished with the PROBE2 optional
%Detection Registers; instruction.
%Shift in the vector that selects the analog node The INTEST2 optional instruction allows supporting debug
under operations while the target circuit is on the internal test operation
%analysis (YYY) and the Limit_B for the Digital and mode, as described in [43]. In this mode, the state of the digital
%Analog Condition Detector Registers. As the inputs of the mission circuit is defined by the contents present on
%selected operations (oLimit_A,4Limit_A) do the U stage of the associated DBMs (on control mode), while the
not depend of ABMs may either be on the transparent or control mode, although
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228 M.C. Felgueiras et al. / Microelectronics Journal 42 (2011) 218–232

Fig. 12. Detecting an AMS condition during the target circuit normal operation.

the latter requires them to support the resources described on analog part, so we select (VS1,VS0)¼(0,1). The DCR contents will
Section 3 (see also footnotes 2 and 3). thus be (C2D,C1D,C0D,C2A,C1A,C0A,VS1,VS0) ¼(0,0,0,1,1,0,0,1)¼
The following example illustrates how the EXTEST2 instruction 19h. The following paragraph lists the pseudo-code with the
can be used to verify if a resistor value is within its tolerance sequence of steps necessary to configure the IEEE1149.4 infra-
window,4 i.e. it demonstrates the use of the MCD during the structure and the MCD with the previously identified parameters.
external test mode. In the example provided, a resistor connected
Instruction Register’SELCON;
between the E1 pin and GND is verified. In a broad sense, it could
%Select position 0 in the Data MUX (see Fig. 10);
be the case of verifying an extended interconnection between two
Detection Configuration
IEEE1149.4-compatible ICs, or verifying the value of a resistor
Register(C2D,C1D,C0D,C2A,C1A,C0A,VS1,VS0)’(19h);
necessary for configuration purposes, e.g. a configurable IP analog
%Shift in the vector that selects the analog and
filter used in an SOC.
digital condition
The verification sequence includes the following steps:
%types, and selects only the analog detection to be
outputted at OVC;
! A known current is injected into Rx, via AT1/AB1. Instruction Register’SAMPLE/PRELOAD2;
! The voltage drop at Rx is applied to the MCD analog input, via AB2. %Select position 2 in the Data MUX (see Fig. 10);
! MCD detects if the voltage present at AB2 is within the voltage BSR +Analog Condition Detector Register’(YYYyFFF
limits corresponding to the resistor tolerance range.
B9Ah);
%Shift in the vector that selects the analog node
Fig. 13 illustrates (in bold) the current path from the AT1 pin to %under analysis (YYY) and the Limit_A for the
the E1 pin (routed via AB1) and the voltage path from the E1 pin Digital (BSR) and
to the MCD analog input (routed via AB2). %Analog Condition Detector Registers;
In this example, the IEEE1149.4 infrastructure is configured in %for the digital part an all 1’s vector is shifted in;
such a way that: ABM-1(1) has SB1 and SB2 closed and the %for the analog part is shifted in the vector B9Ah
remaining switches open; ABM-1(2), ABM-1(3) and ABM-1(4) that
have all switches open; ABM-4 has SD closed and the remaining %corresponds to +4.50 V;
switches open; the TBIC has switches S5 and S6 closed and the Instruction Register’PROBE2;
remaining ones open. The resistor value is 47 75% kO and the %Select position 2 in the Data MUX (see Fig. 10);
injected current is 100 mA, which implies a voltage drop in BSR +Analog Condition Detector Register’(YYYyFFF
between 4.98 and 4.50 V (corresponding to the BFBh and B9Ah BFBh);
codes, respectively). We select the ‘‘A[A, B]’’ operation for the %Signal UpdateDR disabled in the Analog and Digital
analog part, which corresponds to (C2A,C1A,C0A) ¼(1,1,0), while %Detection Registers;
the operation for the digital part is irrelevant, as it will not be used %Shift in the vector that selects the analog node
in this verification process, so we select a default value, i.e. %under analysis (YYY) and the Limit_B for the
(C2D,C1D,C0D)¼(0,0,0). The MCD result does not depend on the Digital (BSR) and
%Analog Condition Detector Registers;
4
Not previously published—see introductory note. %for the digital part an all 1’s vector is shifted in;
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M.C. Felgueiras et al. / Microelectronics Journal 42 (2011) 218–232 229

Fig. 13. Verifying a resistor value during an external circuit test.

%for the analog part is shifted in vector BFBh that (08h), S/P2 (05h) and EXTEST2 (04h) instruction codes. The DCR,
%corresponds to +4.98 V; presenting by default the 0h value, is loaded with a 19h pattern,
TAP controller’Run-Test/Idle; as intended. On Update-IR, after EXTEST2 (04h) has been shifted
into the IR, the AB2 line starts to exhibit the analog voltage
The simulation results are depicted in Fig. 14, where the names
present at the ABM-4 input. The C/S and U stages of the ACDR are
appearing at the upper left corner correspond to the following loaded with BFBh and B9Ah, respectively. The digital output bus
signals (by order of appearance, i.e. top-down):
of ADC2 (belonging to the MCD) presents the BC6h pattern when
the current instruction becomes EXTEST2 (04h), where this digital
! TCK, TMS, TDI and TDO pattern corresponds an analog value of 4.72 V, resulting from the
! TAP controller state voltage drop at the resistor under verification. A quick inspection
! IR contents on the product given by the injected current times the resistor
! DCR contents range (Ohm’ law with 100 $ 10 # 6 A [44650, 49350]O ¼[4.47,
! Contents of the ACDR C/S stage 4.94] V) indicates a resistor value within the tolerance range. OVC
! Contents of the ACDR U stage is at logic ‘‘1’’ when the following conditions are true at the same
! Digital output bus of the ADC2 pertaining to the MCD time: (i) the resistor voltage drop is within the specified analog
! OVC signal limits; (ii) the current instruction is PROBE2; and (iii) the TAP
! Analog signal present at the AB2 line, part of the internal controller is on Run-Test/Idle.
analog test bus The examples described the advantages associated with the use
of the MCD for: (i) detecting a mixed condition during the
Fig. 14 reveals how the TAP controller exhibits a sequence of mission circuit normal operation mode; (ii) detecting an analog
states quite similar to the one occurring on the previous example. condition during the internal test operation mode; and, (iii)
The IR is again loaded, on power-up, with the BYPASS instruction detecting an analog condition during the external test mode. The
code (FFh), and then, by chronological order, with the SELCON following section will now analyze the limitations and the
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Fig. 14. Verifying a resistor value (within its tolerance range) during an external test sequence.

cost (overhead) associated with the proposed built-in debug Table 6

mechanism. The complexity of some IEEE1149.4 internal blocks expressed in terms of G2.

IEEE1149.4 blocks Complexity N(G2)

6. Disadvantages/overhead 8-bits instruction register 296

Data mux 4
The major limitations associated with the MCD are due to the Bypass register 17
Instruction decoder 62
introduced overhead and its functional restrictions. The first
DBM 41
results from the inclusion of this block and the resources required ABM (digital part only) 165
by it (e.g. additional ABMs or ABM variants), which may be
quantified in terms of an extra pin and the extra silicon area. The
last will now be addressed in detail.
Since the silicon area required by each element is technology- equivalent complexity of this IEEE1149.1 infrastructure is given by5
dependent, the analysis will consider the circuit complexity. In NðG2Þ ¼ 556þ 41NDBM
respect to the digital part, the following assumptions are
made: where NDBM represents the number of DBMs included in the
infrastructure. For instance, the equivalent complexity of an
! All circuits can be decomposed into elementary two-input IEEE1149.1 infrastructure for an IC with 100 I/O pins is N(G2) ¼4656
logic gates (G2). elementary two-input logic gates. In respect to an IEEE1149.4
! All elementary two-input logic gates (G2) are equally complex. infrastructure, the digital part can also be expressed in G2 terms,
while the analog part may be expressed in terms of switches and
Table 6 resumes the complexity of some digital blocks comparators. The equivalent complexity will thus be given by
constituting the mandatory IEEE1149.4 infrastructure, based on NðG2,SWITCHES,COMPARATORSÞ ¼ ð746 þ 165NABM þ41NDBM ,10
these two assumptions. þ 6NABM ,2 þ NABM Þ
Besides a digital part, the IEEE1149.4 infrastructure also
includes analog switches and comparators, not mentioning the where NABM represents the number of ABMs included in the
ADC2 when the MCD is present. The silicon area required by these infrastructure. In this sense, the equivalent complexity of an
three component types is also technology-dependent while the IEEE1149.4 infrastructure with 100 DBMs and 5 ABMs, will be of
analog nature impairs them to be decomposed, so we decided to N(G2,SWITCHES,COMPARATORS) ¼(5671,40,7). Adding an MCD to the
keep them apart. To allow a better understanding of the overhead infrastructure (and not considering the ADC2 at the present time)
associated with our solution, we will first characterize the will lead to an equivalent complexity of
complexity of an IEEE1149.1 infrastructure, follow to the NðG2,SWITCHES,COMPARATORSÞ ¼ ð1091 þ 165NABM þ 41NDBM þ119NDREG
characterization of the expansion to an IEEE1149.4 infrastructure, þ 115NAREG ,10 þ 6NABM ,2 þNABM Þ
and then consider the inclusion of the proposed MCD.
where NDREG and NAREG represent the number of bits in the DCDR and
A test infrastructure has two parts: one fixed and another that
in the ACDR, respectively. Considering the existence of the ADC2, the
depends on the number of DBMs and ABMs. The fixed part includes
the following non-replicated blocks: the TAP controller, the IR (with 8
bits, in our case), the instruction decoder, the Bypass register, etc. The 5
These values were extracted from the model used in our simulation case.
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Table 7
Infrastructure complexity.

1149.1 1149.4 1149.4+ MCD

Circuit characteristics # of digital I/O 100 100 92

# of analog I/O – 5 5
# bits of the DCDR – – 8
# bits of the ACDR – – 8

Infrastructure complexity # of equivalent G2 gates 4650 5671 7650

# switches – 40 40
# comparators – 7 7
# bits of the ADC2 – – 8

number of elementary two-input logic gates needed to implement it, The resources of the IEEE1149.4 infrastructure were extended at
which depend on its number of bits (NAREG), should be added to the the ABM level so as to support basic debug operations (defined in
previous result. Let us consider an IEEE1149.4 infrastructure with an Section 3). A further step could be done at the TBIC level, namely to
MCD, NABM ¼5, NDBM ¼92, NDREG ¼8 and NAREG ¼ 8, which is similar to allow reusing the analog test bus (AB1/2) as an internal mechanism
the one used in the two provided examples (Section 5). In the present for selecting the analog node under debug, and route it to the MCD or
case, we only consider 92 out of the initial 100 DBMs, as 8 are now another internal debug mechanism. These two analog lines must
considered as part of the DCDR. The infrastructure plus the MCD has either be connected to the AT1/2 pins or to the internal VCLAMP
thus an equivalent complexity of N(G2,SWITCHES,COMPARATORS) voltage, as there is no configuration (for the mandatory test
¼(7560,40,7). Table 7 resumes the equivalent complexity of the instructions defined in the IEEE1149.4 std.) allowing its use for debug
three infrastructure stages considered. operations such as the previously referred one.
The previous examples allow concluding that the MCD represents In respect to the advanced debug operations, the most natural
an overhead of 33%, in relation to the digital part of the IEEE1149.4 direction follows two lines: (i) improve the MCD functionality
infrastructure. In respect to the analog part, the number of switches (e.g. reduce its time latency); and (ii) develop new debug mechanisms
and comparators remains the same, although one should consider the supporting the execution of real time analysis operations, which
overhead associated with the ADC2 (with 8-bits, in our example). necessarily imply the memorization of circuit states (in the MS
Another important limitation of the MCD derives from its domain) until, before, or in between user-defined circuit conditions.
operation inside the IEEE1149.4 infrastructure. As earlier ex- Other open issues include the verification of both the integrity
plained, the DCDR re-uses all or some of the DBMs associated with and impact of components supporting the proposed infrastructure
the device functional digital pins, according to the designer’s extensions. As a matter of fact, the PCBs that contain one or more
debug needs. While the IC is on its normal operation mode, the IEEE1149.1-compatible ICs normally undergo a BST integrity test
DBMs may be placed in the transparent mode and thus may be before using this test infrastructure for testing the board
used for storing the Limit_A and the Limit_B. When the IC is interconnections. This integrity test can target the TDI–TDO,
placed on test mode, the DBM outputs are controlled through the TMS and TCK interconnections [44], or include the internal test
IEEE1149.4 infrastructure. However, the INTEST2 and EXTEST2 logic as well [45]. An integrity test for the mandatory IEEE1149.4
optional instructions assume the U stage of the DBMs integrating infrastructure has already been described in [46], and should now
the DCDR to contain the Limit_A, which will thus be applied at the be extended to include the proposed extensions and the MCD. The
DBM outputs. This situation is not critical as the values typically impact of the IEEE1149.4 infrastructure during parametric tests
used in debug operations are related to the circuit normal was already analyzed in [47,48,49], although this should now be
operation and thus will not present a particular hazard to the repeated taking into account the proposed extensions.
devices externally connected to the pins associated with the Another aspect concerns the verification of the proposed exten-
DBMs in question. Nevertheless, a DCDR supporting, at the same sions in silicon. As previously explained we chose to simulate the
time, the storage of a Limit_A and the control of the DBM outputs proposed mechanisms due to advantages such as versatility and the
would require 3 memory elements, thus slightly increasing the higher level of controllability/observability of the circuit nodes, in the
associated overhead. This limitation does not apply to the ACDR, time domain. These advantages are however impaired by the large
as this is an independent register added to the IEEE1149.4 simulation times. The validation involved a large number of PSpice
mandatory group of test data registers. models, for the OrCAD simulation environment, distributed in a
A final limitation of the MCD concerns its response time that design scheme with 39 pages (or sheets) and 8 hierarchical levels. The
depends on (i) the conversion time of the ADC-type selected, and total simulation time, relating to the 1st example provided (Fig. 12),
(ii) the structure of the condition detector registers. In fact, the was of 1 $ 103 s, in the following conditions: fTCK ¼50 kHz; circuit
serial nature of the condition evaluation process (derived from the simulated time¼6 $ 10 # 3 s; characteristics of the machine
concatenation of a series of elementary 1-bit condition detectors) used¼Pentium IV, 2.66 GHz, 1 GB RAM, Windows XP. This gives a
imposes a total detection time that corresponds to the sum of the relation of approximately 1:150 $ 103 in terms of real time to
individual detection time periods, which depend on the circuit simulated time, which is an obvious disadvantage of this sort of
implementation technology used. validation approach.
The proposed debug mechanisms reuse the IEEE1149.4 infra-
structure in several aspects, mainly because it is, at present, the only
7. Conclusion and future directions standard test infrastructure for MS circuits. Yet, it is important to
consider new infrastructures, e.g. the IEEE P1687 (IJTAG), which
The present work proposes the reuse of the IEEE1149.4 directly targets the ‘‘development of a methodology for access to
infrastructure for supporting debug operations. However, some embedded test and debug features, (but not the features themselves)
improvements are still possible, especially concerning the effec- via the IEEE 1149.1 TAP’’, as taken from [50]. A broader solution could
tiveness and the efficiency of the proposed solution. also be devised in terms of an embedded macroblock, eventually in
 Author's personal copy

232 M.C. Felgueiras et al. / Microelectronics Journal 42 (2011) 218–232

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