The 68000

Hardware and Software

Macmillan Computer Science Series

Consulting Editor
Professor F. H. Sumner, University of Manchester

S. T. Allworth, Introduction to Real-time Software Design

Ian O. Angell, A Practical Introduction to Computer Graphics
G. M. Birtwistle, Discrete Event Modelling on Simula
T.B.Boffey, Graph Theory in Operations Research
Richard Bornat, Understanding and Writing Compilers
J. K. Buckle, The ICL 2900 Series
J. K. Buckle, Software Configuration Management
J. C. Cluley, Interfacing to Microprocessors
Robert Cole, Computer Communications
Derek Coleman, A Structured Programming Approach to Data*
Andrew J. T. Colin, Fundamentals of Computer Science
Andrew J. T. Colin, Programming and Problem-solving in Algol 68*
S. M. Deen, Fundamentals ofData Base Systems*
P. M. Dew and K. R. James, Introduction to Numerical Computation in Pascal
K. C. E. Gee, Introduction to Local Area Computer Networks
J. B. Gosling, Design ofArithmetic Units for Digital Computers
David Hopkin and Barbara Moss, Automata*
Roger Hutty, Fortran for Students
Roger Hutty, Z80 Assembly Language Programming for Students
Roland N.Ibbett, The Architecture ofHigh Performance Computers
Patrick Jaulent, The 68000 Hardware and Software
H. Kopetz, Software Reliability
E. V. Krishnamurthy, Introductory Theory oj Computer Science
Graham Lee, From Hardware to Software: an introduction to computers
A. M. Lister, Fundamentals of Operating Systems, third edition*
G. P. McKeown and V. J. Rayward-Smith, Mathematics for Computing
Brian Meek, Fortran, PL/l and the Algols
Derrick Morris, An Introduction to System Programming - Based on the
PDPll
Derrick Morris and Roland N.Ibbett, The MUS Computer System
C. Queinnec, LISP
John Race, Case Studies in Systems Analysis
L. E. Scales, Introduction to Non-Linear Optimization
Colin J. Theaker and Graham R. Brookes, A Practical Course on Operating
Systems
M. J. Usher, Information Theory for Information Technologists
B. S. Walker, Understanding Microprocessors
Peter J. L. Wallis, Portable Programming
I. R. Wilson and A. M. Addyman, A Practical Introduction to Pascal - with
BS6192, second edition
*The titles marked with an asterisk were prepared during the Consulting Editorship of Professor J. S. Rohl,
University of Western Australia.
 The 68000
Hardware and Software

Patrick Jaulent
Microprocessor System Training Engineer
Microprocess
Puteaux, France

M
MACMILLAN
 © Editions EYROLLES, Paris 1983

Authorised English Language edition

(with additions and revisions) of
Le Microprocesseur 68000 et sa programmation
by Patrick Jaulent, first published 1983 by
Editions EYROLLES, 61 boulevard Saint-Germain,
75005 Paris

Translated by M. J. Stewart

© English Language edition, Macmillan Publishers Ltd, 1985

All rights reserved. No reproduction, copy or transmission

of this publication may be made without written permission.
No paragraph of this publication may be reproduced, copied
or transmitted save with written permission or in accordance
with the provisions of the Copyright Act 1956 (as amended).
Any person who does any unauthorised act in relation to
this publication may be liable to criminal prosecution and
civil claims for damages.

First published 1985

Published by
Higher and Further Education Division
MACMILLAN PUBLISHERS LTD
Houndmills, Basingstoke, Hampshire RG212XS
and London
Companies and representatives
throughout the world

British Library Cataloguing in Publication Data

Jaulent, Patrick
The 68000 hardware and software.-(Macmillan
computer science series)
1. Motorola 68000 (Microprocessor)
I. Title
00 1.64'04 QA76.8.M67

ISBN 978-0-333-38574-6 ISBN 978-1-349-07763-2 (eBook)

DOI 10.1007/978-1-349-07763-2
A mes parents - Rene et Antoinette
Contents

Acknowledgements ix

1 Pin Assignment of the MC 68000 and MC 68010 1

Technical History 1
Pin Assignment of the MC 68000 and the MC 68010 1
Bus Arbitration Control 5
Interrupts 5
System Control 5
6800 Peripheral Commands 7

2 Internal Organisation of the 68000 9

Status Register (SR) 10
Supervisor Mode S = 1 11
User Mode S = 0 13
Data Registers 14
Address Registers (AO-A6) 15
Stack Pointer (SP) 17

3 Bus Operation 18
Introduction 18
Data Transfer 18
Rerun Cycle 27
Bus Allocation Arbitration 29
Halt and Single Step Operation 32
Interaction with Synchronous Circuits (6800 family) 35

4 Exception Procedures 38
Exceptions 38
Technical File 58

5 Addressing Modes of MC 68000, MC 68008 and MC 68010 61

Types of Address 61
Definition 61

vii
viii Contents

6 68000 Instruction Set 82

Details and Programming 82
DBcc Instructions 95
Scc Instruction 101
BSET, BCLR, BCHG, BTST Instructions 104
LSL, LSR, ROL, ROR, ROXL, ROXR, ASL, ASR
Instructions 110
MULU and MULS Instructions 113
ABCD and SBCD Instructions 115
DIVU and DIVS Instructions 119
CHK Instruction 121
MOVEM Instruction 126
MOVEP Instruction 129
LINK and UNLINK Instructions 133
TAS (test and Set) Instruction 145

7 Programming Exercises 150

1 Exceptions 150
Hardware Used 150
Study of the Listing 150
2 Dynamic Memory Test 162

Appendix 1 Memory Reference Instructions 183

Appendix 2 Special Memory Reference Instructions 184
Appendix 3 Shift and Rotate Instructions 187
Appendix 4 Program Control Instructions 188
Appendix 5 PAL Devices 191
Acknowledgements

Both the author and the publishers are grateful to

Motorola Inc., Chicago, USA and to Monolithic Memories
Inc., Santa Clara, USA for permission to reproduce data
and diagrams from their publications, through the kind
assistance of their United Kingdom offices.
Special thanks are also due to Richard Mitchell for
his help in the preparation of the English language
edition of this book.

®
PAD (Programmable Array Logic) is a registered trade
mark of Monolithic Memories Inc.

ix
1 Pin Assignment of the MC 68000
and MC 68010

TECHNICAL HISTORY

The 16-bit MC 68000 microprocessor is the result of the

MACSS project (Motorola Advanced Computer System on
Silicon), which was begun in 1976 with the objective of
developing a monolithic microprocessor whose
performance would be based on the two main criteria of
simplicity and orthogonality (that is, the internal
registers would be general purpose with regard to
addressing modes and instructions).
From the software point of view, the aim was to
simplify programming by drawing upon the best of the
modern programming techniques that enable the use of
high-level languages, such as FORTRAN, Pascal, COBOL
and Ada.
The package would also need to be able to function
in a multiprocessor configuration, while remaining
hardware compatible with the 6800 family; this
requirement imposed serious constraints at the design
stage.
The HMOS technology used for its production was
required to reduce by a factor of 2 to 3 the area of an
elementary cell, and divide by 4 the associated quality
factor (that is, the result of the product of the
consumption times the speed), which in turn would give
a consumption of 1 picojoule per cell at 8 MHz.
The first samples were offered to industry in 1979
with the majority of these aims having been realised.

PIN ASSIGNMENT OF THE MC 68000 AND THE MC 68010

Data Bus (00-015) (Tristate logic)

These 16 bidirectional lines, which are not
multiplexed, can transfer two types of data
16-bit word, or
8-bit byte, via the lower line 00-07, or via the
upper line 08-015.
It was necessary to be able to transfer 8-bit data
in order to be hardware compatible with the 6800
family. Note also that on a vectored interrupt the
lower line (00-07) is used to transfer a vectored
number.
2 The 68000 Hardware and Software

Address Bus (Al-A23) (Tristate logic)

The non-multiplexed address bus allows direct
addressing of 224 combinations; that is, 16 777 216
bytes or 8 388 608 words. We should note that the 68000
does not have an AO output address line whose role
would be to select an even address (AO = 0) or an odd
address (AO = 1) for a byte data item.
Such a single line would in fact be insufficient to
satisfy the following three combinations
1. Selection of an exclusively even address for a
word data item.
2. Selection of an odd address for a byte data
item.
3. Selection of an even address for a byte data
item.

Upper Data Strobe UDS (Tristate logic)

Lower Data Strobe LDS (Tristate logic)
These two signals _work in conjunction with the
Read/Write line (R/W) and control the different lines
for word or byte read/write operations. Table 1.1 shows
how they work.

04
03 -- -- 1
2
64
63. ----- ----
05
06
02
-- - 3 62 07
01
-- -- 4 61
-- : 08

AS - ---
DO 5 60 09

UOS
6
7
59
58
-
.-
.-
010
011
lOS 8 57 - 012
R/W
OTACK
9
10
56
55
-
..:-
-
:
013
014
~
B'GA"C"K
11
12
54
53 - - 015
GNO
SR 13 52 A23
68000
Vee 14 and 51 A22
ClK 15 68010 50 A21
GNO 16 49
- -:..
Vee
HALT 17 48 A20
- -
~
RESET 18 47 A19
VMA 19 46 A18
E 20 45 A17
VPA 21 44 A16
BERR 22 43 A15
IPl2 23 42 A14
iPL1 24 41 A13
iP[Q 25 40 A12
FC2 26 39 A11
FC1 27 38 A10
FCO 28 37 A9
A1 29 36 A8
A2 30 35 A7
A3 31 34 A6
A4 32 33 A5

Figure 1.1
 Pin Assignment of the MC 68000 and MC 68010 3

Table 1.1
AO R/W LOS UOS Lower Upper Operation Address
line line
(00-07) (08-015)

1 0 0 1 En Dis write Byte Odd

1 1 0 1 En Dis Read Byte Odd
0 0 1 0 Dis En Write Byte Even
0 1 1 0 Dis En Read Byte Even
0 0 0 0 En En Write Word Even
0 1 0 0 En En Read Word Even

Read/Write R/W (Tristate logic)

This signal determines the direction of the transfer on
the data bus; t~at is, a read cycle (R/W = 1) or a
write cycle (R/W = 0).
Note the use of the line over the W in R/W. Here
it indicates that when the voltage is low, the data bus
is to be used for a write cycle. This convention is
also used for all the other lines.

Address Strobe AS (Tristate logic)

The pulse along this line to the external hardware
signals that the address currently present on the
address bus is electrically stable.
This signal is for example required by dynamic RAM
~tems. Some examples are RAS Row Address Strobe,
MUX Multiplexors (type 74LS157 or PAL), and CAS
Column Address Strobe.

Data Transfer Acknowledge DTACK

When this input line is asserted (DTACK = 0) by a
memory or peripheral device, the processor is informed
that a data transfer is acknowledged.
Recognition of the DTACK signal at low state
during a read cycle indicates that the data transmitted
on the data bus is latched, or that it has been
received during a write cycle. This feature, resulting
from the asynchronous operation of the 68000, is of
particular value for the synchronisation of slow memory
or peripheral devices.

Processor Status: Function Codes FCa, FCl, FC2

(Tristate logic)
These three fixed output lines are set ~y the processor
at the beginning of a bus cycle and indicate that
status of the processor to the external hardware.
In particular, they show whether the processor is
operating in supervisor mode (FC2 = 1) or in user mode
(FC2 = 0), whether the information being executed is
4 The 68000 Hardware and Software

"data" type or "program" type, or whether it has

acknowledged an interrupt (table 1.2) .
Table 1.2
FC2 FCI FCO Status Mode

0 0 0 Reserved User
0 0 1 Data User
0 1 0 Program User
0 1 1 Reserved User
1 0 0 Reserved Supervisor
1 0 1 Data Supervisor
1 1 0 Program Supervisor
1 1 1 Interrupt Supervisor
These lines therefore constitute an additional
security for the system, while also making it possible
to increase the addressing capacity of the 68000 from
16 megabytes to 64 megabytes by using the noted
reserved combinations.
The timing diagram shown in figure~.2 compares the
electrical relationships between the AS signals, FCO,
FCl, FC2 and the address bus.

SO S2 S4 S6 so
CLOCK

A1-A23~ >-C
\ /
AS

FCO-FC2 J C
74 LS138

Reserved Y7 A FCO
User program Y6 8 FC1
Supervisor data YS C FC2
Reserved Y4
Reserved Y3
Supervisor program Y2 G1 +SV
Supervisor data Y1 G2A AS
Interrupt acknowledge YO G28
-

Figure 1.2
 Pin Assignment of the MC 68000 and MC 68010 5

BUS ARBITRATION CONTROL

The three lines that ensure arbitration of the bus are

described below.

Bus Request BR
This input, at low state, informs the processor that an
external device requires the bus (for example, the DDMA
68440, DMAC 68450 or SBC 68430).

Bus Grant BG
While authorising the calling circuit to take control
of the bus, the 68000 alerts its surrounding circuitry
that it will surrender the bus at the end of the
current bus cycle.

Bus Grant Acknowledge BGACK

The input confirms to the processor that the calling
circuit has taken control of the bus. This line can
only be enabled by the caller if the following four
conditions are satisfied.

1. BG asserted (BG = o)
2. AS invalid (AS = 1 )
3. DTACK invalid (DTACK 1)
4. BGACK invalid (BGACK = 1 )

INTERRUPTS

Interrupt Request Interrupt Priority Level

IPL2, IPLl, IPLO
The logical state of lines IPL2, IPLI and
IPLO indicates to the processor the level of the
wait~interrupt request. IPLO represents the LSB
and IPL2 the MSB.
Level 7 codes the highest level priority while level
o indicates that there is no waiting interrupt request.
If the logical state on these lines is greater than
the level of the interrupt mask set by the programmer
in the status register, the processor accepts the
interrupt request.
These lines must remain stable until the processor
sets FCO to FC2 to 1 and the address lines A4-A23 to
high.

SYSTEM CONTROL

Bus Error : BERR

This input is controlled by external hardware, for
6 The 68000 Hardware and Software

example by a memory management unit (MMU). It informs

the processor that there is a hardware error in course
of execution of the bus cycle.

Example
Absence of the DTACK signal during a reading or
writing operation in working memory after a time delay
fixed by the design~
Enabling of the BERR input leads either to a
sequential rerouting, called a trap, or to a rerun
cycle.

Reset : Bidirectional Line

Reset on input : Initialisation of the 68000
When this line, which is set to input at power up, is
held for 100 ms at the low state by means of the
HALT line, the stack system and the program counter
are loaded. This is the initialisation phase of the
68000.

Reset on output
Execution by the processor of the RESET instruction
sets the reset line to the low state for 124 clock
cycles. Handling this instruction does not affect the
internal registers of the processor.
For example, this instruction is used to initialise
a system or to program a peripheral circuit (PIA,
timer, etc).

HALT : Bidirectional Line

HALT on input
1. Initialisation of the 68000
2. Halting the processor
1. On input the HALT line follows the state of the
RESET line (on input) throughout the entire
initialisati~hase.
2. When the HALT input is asserted, the processor
terminates its bus cycle, then sets the three status
lines at high impedance before moving to stop.

HALT on output
An example is the display of a double bus error. This
follows a double error on the bus (for example, a
hardware fault).
If during the initialisation phase (RESET and
HALT on input at low state) a hardware or software
anomaly occurs, the 68000 takes this to be catastrophic
for the remainder of the program. In such a case it
places itself at the halt state and alerts the outside
world via the HALT output line.
 Pin Assignment of the MC 68000 and MC 68010 7

Only an action on the RESET and HALT pins will

cause the 68000 to leave the HALT condition.

6800 PERIPHERAL COMMANDS

The three signals defined below allow a dialogue

between an asynchronous processor like the Me 68000 and
the synchronous peripherals of the 6800 family.

Valid Peripheral Address : VPA

1. When a 6800 family peripheral device wishes to
converse with the 68000, the request circuit enables
the VPA signal (VPA = 0) in order to alert the
(asynchronous) processor that it should now transfer
data according to the clock E. This is the
synchronisation phase.
2. If VPA is at the low state during the
interrupt acknowledge phase, the 68000 will identify
the interrupt as corning from a 6800 peripheral device.
From then on, the processor will move to
autovectorisation by distribut-ing__ a_ vector number
according to the state of lines IPL2 to IPLO
(see chapter 4 on interrupts).

Enable E
This periodic signal, which is generated from a
floating clock internal to the 68000, represents the
time reference for all exchanges with the synchronous
circuits of the 6800 family.
The period of signal E is equal to 10 periods of the
signal fed to the input clock of the 68000, and has the
form of 6 low states and 4 high states, as shown in
figure 1.3.

CLOCK

I I I

i
I

! 3 4 : 5

Figure 1.3

Valid Memory Address : VMA

On receiving the VPA signal (VPA = 0) the 68000
synchronises itself before asserting th~address sent
on the address bus, by setting the VMA output to
zero, when the clock E is at the low state (two cycles
before E moves to the high state).
8 The 68000 Hardware and Software

The VMA signal is used in the logical equation

which ensures selection of the 6800 peripheral circuits
(chip select).

Clock : eLK
The 68000 is able to produce the different signals
required to allow it to function (for example, the E
clock of the 6800 family), beginning from the clock
signal fed to the 68000 eLK input.
The TTL compatible signal must be perfectly stable
and adhere to the manufacturer/s specifications as set
out in table 1.3.

Table 1.3

4 MHz 6 MHz 8 MHz 10 MHz 12.5 MHz

68000L4 68000L6 68000L8 68000LIO 68000L12
Min Max Min Max Min Max Min Max Min Max

Freq 2 4 2 6 2 8 2 10 2 12.5 MHz

Prd 250 500 167 500 125 500 100 500 80 250 ns
pr -ve 115 250 75 250 55 250 45 250 35 125 ns
pr +ve 115 250 75 250 55 250 45 250 35 125 ns

CLOCK

Max transfer ti me = 10 ns

Figure 1.4
2 Internal Organisation of the 68000

As shown in fi gure 2 .1, th e MC 6 8000 c ontain s the

following .

8 32 -bit data registers ( DO-D7)

7 32 -bit address registers (AO -A6 )
1 32 -bit user stack pointer A7(or USP}
1 32 -bit supervisor stack pointer A7 '(orSSP)
1 16 -bit status register (SR)
1 24 -bit program counter (PC)

DO

I BYTE

I I
~ WO:RD ??~ , registers
Data

I (Dn)

t~ LONG YJO RD •!
I
I,07
31 15 0
I I~ WORD ~ I AO

I
@ LONG:WORD ~l
Data
registers
(An)

L..- --'- ---' I A6

Ei - -- -J'--- - --- - - - - - ------=-I

~-_-_-_-_-_-_-----------_-"-°lr p~~~~;rs
_
31 23
.\ (USp · SSP)
0 A'7
Program
~ _ _ _ _ . coun ter (PC)
o
15 87
I Status register
L...--=--=-_L~-
:=-:_::--...... (SR )
Supervisor User byte
byte (CCR)

Fig ure 2 . 1 Pr o g r ammer ' s mode l (6 80 0 0 a nd 6 8008)

9
10 The 68000 Hardware and Software

STATUS REGISTER (SR)

It is no coincidence that our description of the 68000

programming model begins with a examination of the
status register, since it is, as we shall see, the real
heart of the microprocessor.
As figure 2.2 shows, the 16 bits of the status
register, form the user and supervisor bytes.

15 13 10 9 8 7 o

Supervisor byte User byte

Figure 2.2

The 68000's method of operation is determined by the

logical state of bit S, which fixes the processor in
supervisor mode when S = 1 and in user mode when S = O.
The availability of these modes facilitates the setting
up of the operating system and makes multitasking and
multi-user operation possible. In this case, memory
management and logical protection will need to be
carried out by a type MC68451 memory management unit
(see figure 2.3b), or by an electronic equivalent.

ADDRESS ENABLE

SUPERVISOR
DATA
SUPERVISOR MEMORY

FeO SUPERVISOR
Fe1 PROGRAM
MEMORY
Fe2
68000
USER
DATA
ASt----- MEMORY

USER
PROGRAM
ADDRESS BUS MEMORY

Figure 2.3a Principles of memory organisation

(without MMU)
 Internal Organisation of the 68000 11

." , I T T
r-=--
"'...

"0
no l' !"
' to 1 I ' l Ol
I
RJ W

.,
DOO'':l
' CJ
lOS
I ~; U'05 iii
U,·

"11
1..!j11 A8 13
f '.LS'""
?
~ 1-1--
'- S r<
.1111

f' T
~
<
~
AI A1 ., " I~~A OO I" ........... .

m
P." I'''-J ''
'JIl ta u:: 1- Of Ar- ~

~?i
... ·'V iAUi1
=:
1-
~t SE , ~ I'vO!)
CS '-I A '; GO" UllJ~
8!n
."

~
Bf AR
T I-irr .
vcs

"S
G~,
m

.....-. -.,
d ~A!U :;)1 4(, 1,

= -
riUl1 R/W'
5TiCi iO ~r
~.w
AI' 13 ~ ...C
t..:,. AS l o h"e rn
PA Ot) l !.
~ 0Titi""
., « DC
~
ii» ::: A 1 S~
uOS
I; uo W;;;;
tm lOS
IlffiT ~
rO' CS

~-
.. m f--
,Pl O ~
'Pl' .,~, ~ ~ C0 1
1",- 'CJ
i
IPlJ
'------
Al AI

bB
~

5.s '..,.,
h OK...
JlESfT
(
Fig u r e 2 .3b Memor y org ani sa t i o n wi th MMU

SUPERVISOR MODE S = I

Al so c a l l e d th e se c u r i ty s ystem, the super visor mode

(S = 1 ) allow s th e p r og r a mmer acce ss to all resourc es,
bo t h so ft wa r e and ha r dware. For examp le , he ca n choose
fr o m any of th e f o l l owi ng
1. Use all the 6 8000 inst ructi on s
2 . Address th e d ata, program, su per visor and user
memor y locations
3. Ac ce s s the compl ete status r egister (supervisor
and us er b ytes)
4 . I f r equir ed, se le c t the super visor stac k (SSP)
and u se r s t ack ( USP ) poi n te r s (se e s ection 2.4).

Th e supervis or is a set of p r o grams that allows the

user program to be initialised and then chained with
other us er programs, all without the operator having to
take an y acti on .
Fi g u r e 2 . 4 shows the superviso r b yte that can onl y
be acc ess ed b y th e p rog r a mmer when i n s u perv isor mode.
12 The 68000 Hardware and Software

15 8

~ ISR
.........---~

L Interrupt mask

1
- - - - - - - - - Status supervisor
- - - - - - - - - - - T R A C E Mode

Figure 2.4

Trace Mode
After each instruction the processor tests internally
whether bit T of the status register is enabled
(T = 1).
When T = 1, a program can be traced, instruction by
instruction. It is the software equivalent to the
single step operation carried out in 8-bit
microprocessors. The trace function can be used to
debug a program, whether in supervisor or user mode.

Processor Status
S 1 fixes the processor in supervisor mode
S = 0 fixes the processor in user mode

Interrupt Mask
The 68000 has seven interrupt levels that can be
programmed by bits 12, II and 10, as shown by the table
in figure 2.5.
These three bits fix the interrupt mask, and also
the priority level of the interrupt currently being
handled.

Level 12 11 10
7 1 1 1 . - - Highest priority level
(NM I type interrupt)
6 1 1 0
5 1 0 1
Increasing 4 1 0 0
priorities
3 0 1 1

2 0 1 0

1 0 0 1 4- Lowest priority level

0 0 0 0 ..- No priority (no request)

Figure 2.5
 Internal Organisation of the 68000 13

Priority occurs in the increasing order, so that

level 1 represents the lowest priority (level 0
corresponds to no priority) and level 7 the highest,
being equivalent to a non-maskable interrupt.
In order to understand how the interrupt is handled,
let us assume that the interrupt mask is at level 5
(the logical state of bits 12, II and 10 represent the
mask) .
Any interrupt request less than or equal to the mask
(1 to 5 inclusive) is ignored, whereas a higher level
request (6 or 7) will be accepted by the processor.
Note, though, that level 7 is non-maskable.

USER MODE S = 0

The user .rode (S = 0) is the lowest priority mode. This

means that a program execute~ in this mode can only
access the data and the user program memories.
Those instructions that are able to change the
functioning mode of the processor are called
privileged.
On executing a privileged instruction the 68000 also
causes a trap which is called a privilege violation. It
is therefore impossible, except in a manner controlled
by the central unit, for a program executing in user
mode to be able to change the functioning mode of the
processor or address a data or supervisor program area.
The latter would still require a memory management unit
(MMU) circuit.

Flag Identification
As figure 2.6 shows, only the first five bits of the
user byte are of importance for the programmer.

Supervisor byte User byte

15 8 7 o
Status
register

---Zero
~---- Negative

- - - - - - Extension

Figure 2.6
14 The 68000 Hardware and Software

These flags, which are found in the majority of

8-bit microprocessors, inform the programmer of the
status of the microprocessor after an arithmetical or
logical instruction has been carried out.
For example, flag X is required by the processor
when carrying out decimal addition and subtraction.

Arithmetic processing

Instruction source Logical state of flags

after instruction execution

MOVE.B #$FF,02 N 1; Z = 0; V set at 1;

C set at 0
AOOI.B #$01,02 N O;Z=l;V 0; C = 1

Logical processing
The instruction LSL.W #1,04 causes a logical shift one
position to the left.
Figure 2.7 shows the flags requested by the
instruction.

31 15 o
04 rUNAFFECTEDBYTHE-~-------""" ~O
L.. _ _ .l!'J"§..T.!!~.JJQf'J ........ ---,

Figure 2.7

DATA REGISTERS

Figure 2.8 illustrates how the eight data registers

accept operands, whether of 8, 16 or 32 bits.

31 1615 8· 7 o
DO
I to
07
11 BYTE = 8 bits
• II

~ 1 WORD = 16 bits-----..
,. 1 LONG WORD = 32 bits •

Figure 2.8

When a data register is used for a process

(instruction) as the source or the destination, only
the bits specified by the size are involved; the other
bits are not affected.
 Internal Organisation of the 68000 15

UNAFFECTED

--
CLR .B 02

It Destination

Size (Byte)

- - - - - - Mnemonic

Figure 2.9

The size is specified in the instruction source by

the letters B for Byte (8 bits), W for Word (16 bits),
and L for Long Word (32 bits).
Example
CLR .B 02 resets bits 0-7 of 02
CLR .W 02 resets bits 0-15 of 02
CLR .L 02 resets bits 0-31 of 02

ADDRESS REGISTERS (AO-A6)

The seven address registers (AO-A6) handle operands of

16 or 32 bits. In fact, they do not accept 8-bit byte
type operands.
If an address register An is used as destination,
the whole register is affected, even if the size
specified by the instruction is a word type.

Example

MOVEA.W # $8000, AS
Destination register
Hexadecimal operand
l6-bit word size
Mnemonic

Since the operand is negative (bit 15 = 1), the

32-bit sign extension sets register AS to the value
$FFFF8000 as shown in figure 2.10.
sign bit = 1, operand is negative
31 1615 I o

F F F F 8 o o o
Figure 2.10
16 The 68000 Hardware and Software
DATA
DATA HIGH
AS
ADDRESS
LOW

DO .18 '2
D1 17 74lS245 3
D2 16 4
D3 15 5
D4 14 6
D5 13 7
11 8
D6 12
D7 19 9

D8 D8
D9 14ls245 I
I
D10

~ ---.......-...............-.1
I
D11
D12 ....-----~ HALT
I
D13 I
I
D14 I
D15 D15

R/W
AO 18 2 A1
A1 16 74lS244 4 :68000
A2 14
6 I
I
A3
A4
12
7
~
~
8
~
13
..----...,...t--. : I
I ...10----- VPA

5 15 :
DTACK
A5 3 17 :
A6 9
A7 19 11 ~8 BERR
R/W

A8 A9
A9 74lS244 I
I
A10 I FCO
I
A11 t -. .- - - -...~t--. ..I FC1
A12 I
FC2
I
A13 I
I
A14 I
I
A15 19 A16

E
BLOCK 1 A16 19 1 A17
BLOCK 2 VMA
14ls244 A17 18 2
BLOCK 3 A18 17 3
BLOCK 4 A 19 16 4 I--"~ __
BLOCK 5 A20 PAL 5
I5
BLOCK 6 A21 ~10 L86
BLOCK 7 10 H8 A22
13 7 A23
BLOCK 8
19 12 MAKPAGE

AS
MODE
CLK IPL IPL 1 iPI2
Figure 2.11 Shows the interface between the 68000 and
MAKBUS. The 74LS244/5 devices buffer the 68000 signals,
and the PAL10L8 acts as memory management unit (see
also Appendix 5). Note that the availability of the
MODE signal allows two possible configurations, such as
MAKBUS and MAKBUS+. (Copyright Microprocess)
 Internal Organisation of the 68000 17

Problem
What is the content of register AS after the processor
has executed the instruction MOVEA.W #$2AOO,AS? Can you
explain your answer?

STACK POINTER (SP)

All the rules explained in the previous section apply

equally to the stack pointers.
The CPU automatically uses address register A7 as
stack pointer (SP) when subprograms are called, such as
for exception handling or implicitly for certain
instructions (RTS, PEA, or RTD, for example).
The system stack pointer can be one of the following
1. The supervisor stack (SSP) when bit S of the
status register has the value 1;
2. The user stack pointer (USP) where S = O.
By convention, the user stack pointer (USP) is
designated A7, while the supervisor stack pointer (SSP)
is A7/.
Note that this chapter is equally valid for the
8-bit MC 68008.
3 Bus Operation

INTRODUCTION

What follows is intended to show future designers of

applications based on the Me 68000 how its bus
functions during such operations as the following

data transfer
rerun cycle
bus allocation arbitration
halt or single-step operation
dialogue with synchronous circuits.

DATA TRANSFER

Figure 3.1 illustrates the different command and

control signals that are requested during data transfer
operations.

1 Read Cycle
During a read cycle the processor receives an item of
data from memory or peripheral circuits. The 68000
always reads a byte type data item using an internal
bit AO, in order to determine which line the data item
should follow.
If AO = 1 and the LOS signal is asserted, the
data item can be read on the lower line 00-07, to an
odd address.
If AO = 0 and the UOS signal is asserted, the
data item can be read on the upper line 08-015, to an
even address.
On the other hand, when the instruction code
indicates reading of a word (or a lo~word)L-!he 68000
processor simultaneously enables LOS and UOS,
while AO = 0, since in this case the specified address
can only be even.
The reader is urged to study closely the timings for
reading a word, as illustrated in figures 3.2 and 3.3,
referring where necessary to table 3.1 for further
details.

18
 Bus Operation 19

4.7krl

+5V

VPA

OTACK

SYS
BERR
R/W

68000

FCD FCD

FC1 FC1

FC2 FC2

LOS LOS

>
LO
+ OS

UOS UOS

E E

VMA VMA
R/W

v
MAKBUS®

Figure 3.1 In this circuit the PAL16L8 buffers

microprocessor and bus signals. It also provides the
control for multiprocessor configurations. (Copyright
Microprocess)
20 The 68000 Hardware and Software

Period

A1-
A23
AS--+--+-,""",

ODS- - + - - + - - -

00-07
----+--+---~

08-015

Figure 3.2 Read bus cycle for a word

Period

elK

UOS
--......--+-_.

AtW

Figure 3.3 Slow read bus cycle for a word

 Bus Operation 21

Table 3.1 Reading a Word Within the Bus Cycle

State a (SO) Address lines AI-A23, the read/write

line (R/W) and the processor status
outputs FCO, FCI and FC2, are all high.

State 1 (Sl) The processor places the address on its

bus AI-A23 and reports its electronic
status externally, by means of lines
FCO-FC2.

State 2 (S2) Output AS is enabled from the

beginning of S2, which allows a decoding
circuit to use this signal to latch the
address
-- sent
- -on the bus.
UDS and LDS are also asserted
during S2.

State 3 (S3/4) Wait for signal DTACK.

1. If DTACK arrives during S3, it

will be recognised by the processor when
S4 is high.
2. If DTACK is not present (for
example, on slow read), the processor
sets wait states until the arrival of
DTACK (see figure 3.3).

State 5 (S5) Inactive in our example.

State 6 (S6) The data are recognised and latched in

the input register (DBIN) of the
processor.

State 7 (S7) Signals AS, UDS and LDS are

disabled causing the signal DTACK
to be set high by an external electronic
source.
During the following state (80) or, at
the end of 87, lines FCO to FC2, the
address bus, the data bus and the R/W
line are disabled.
22 The 68000 Hardware and Software

2 Write Cycle
For a write cycle, the MC 68000 processor places the
data on the bus, to be sent to an addressable area
(memories or peripherals).
In a manner similar to the read operation, the data
written by the processor is byte type. We therefore do
not need to go into the conditions that lead to its
being sent on the lower or upper line. Of course, if
the operation code specifies a word or long word data
item, the two lines are enabled by means of LOS and
UDS signals (with AO = 0), as shown in table 3.2.
Figure 3.4 shows the timing of a write cycle.

Table 3.2 Writing a Word Within the Bus Cycle

State 0 (SO) The address bus is high (~1-A23).

The read/write line (R/W)is at read
(end of previous cycle).
The processor status lines (FCO, FCl,
FC2) are enabled.

State 1 (Sl) The current address is placed on the bus

(AI-A23).

State 2 (S2) Sampling of the address is asserted

(AS = 0), line R/W is positioned at
write while the data bus is disabled.

State 3 (S3) The data is placed on the bus (DO-DIS)

by the processor.

State 4 (S4) Outputs UDS and LOS

are asserted.
The data is latched.
The processor recognises DTACK.

State 5 (S5) Confirmation that the write bus cycle is

terminated as DTACK is present (in
the opposite case, the processor
introduces state waits).

State 6 (S6) Inactive in our example.

State 7 (S7) Outputs AS, UDS and LOS are

deactivated, bringing about an
incrementation of the DTACK signal
via an external electronic source.
 Bus Operation 23

Period

eLK

A1·A23
AS
---+--~

oss- - - - + - - - + - + - ' - \ ,

00-07

08-015

Figure 3.4 Timing of a write cycle

LS164
1/4 LS03
UDS
elR A
LDS
CK
OA
as Clc aD B
CKIJP

1/2 LSD3
Jumper --.
•••

CSRQM Other sources

Figure 3.5a Traditional method of producing DTACK signal

24 The 68000 Hardware and Software

Memory
Address _ _---,
selection
PAU
PROM
Control
2

CK.uP CK
QA

OB Multiplexer DTACK
AS CLR Oc

00

Figure 3.5b Producing DTACK signal using PROM and/or PAL

technologies

3 Relationship Between DTACK and the Data Bus

If you want a system to function at the maximum
permitted speed, using RAM memory locations, the
relationships between DTACK and the data bus are
important.

We recall that
1. DTACK, when recognised by the processor
during a read cycle, indicates that the data is latched
and that the bus cycle is terminated.
2. DTACK, when recognised during a write cycle,
indicates that the bus cycle is terminated.
Most systems use a timer (counter) to detect a
nonexistent addressable area (removed or damaged memory
locations). If no DTACK signal has been received
when the timer reaches a timeout value, a bus error
signal is generated (see next section).
 Bus Operation 25

RAM SaMSEL
15 14
SELECT [1 [2 [3 [4 Hi Fi2 R3 R4
ROM 58167
16 18
SELECT 10 x 4.7k.Q
H4
17 8

H3
12
H2
13 6
H1
19
DTACK
l4
PAL 4

16L8 l3
3
l2

l1

10
N C")
~ ~ ~

r
C/) C/) C/)

20
9 r
I
I
r-o r-o-i
L ...I I
L
I
L
+

21 20 19 18 17 16 15 14 6
PAL 12L 10_ 20 L 10
DS 23 22 9 10 11 13 1

+5V---+--"""--

Figure 3.6 The PAL12LlO controls the decoding of the 8

memory packages on the card. It can be reprogrammed to
be used with memory packages of a different size. The
PAL16L8 controls the memory DTACK signal(s), both on
the CPU-M card and external to it. (Copyright
Microprocess)
26 The 68000 Hardware and Software

I:i:

I~

I~

II

15

1:3

I~

I:J

Figure 3.7 Part of figure 3.6. (Copyright Microprocess)

 Bus Operation 27

RERUN CYCLE

If during execution of a bus cycle an external circuit

activates lines BERR and HALT (BERR = 0 and HALT = 0),
the processor is alerted that the current bus cycle will
not be correctly completed or terminated, and that it
must initiate the rerun cycle procedure.

Figure 3.8 shows the timing of a rerun cycle whose

different stages, set out in the flowchart of figure
3.7, are described below.
1. Inputs BERR and HALT are asserted during a bus
cycle.
2. The MC 68000 processor terminates its bus cycle
before placing the address and data lines at high.
While the HALT line is held at low by an external
circuit, the processor is halted.

. - Beginning of rerun cycle

~ASO 51 S2S3 S455 S857

ClK L.JL.rL
A1·A23
AS
LOS et UOS
RJW
DmK
00-015
FCo-2 --J, ---f I-- +-- ~-------J"'--

BEAR
HALT
-+--I. Reading of word _~-- Processor at HALT-- - - Rerun
cycle

Figure 3.8 Timing diagram of rerun cycle

(Courtesy of Motorola)

Rerun Condition
If the aborted bus cycle is not indivisible (TAS
instruction read/modify/write cycle) and, if the
BERR line is again positioned at high, a rerun
cycle can be envisaged. __
3. As soon as the HALT line is disabled by the
external circuitry (HALT = 1), the 68000 moves to the
preceding rerun cycle using the address and data
transmitted by their respective buses which have
previously been set to high.
28 The 68000 Hardware and Software

~=o
and
HALT on start up = 0

Address and data

lines set to
high impedance

Figure 3.9 Rerun cycle

-0-
L:r
MC 68000 MC 6809

DATA

Figure 3.10 Simplified multiprocessor system

 Bus Operation 29

Example
In the multiprocessor system shown in figure 3.10, the
MC 6809 microprocessor uses RAM when the MC 68000
processor wishes to access it (CS RAM 68000 enabled).
While waiting for the memory to be available to the
68000, the former executes n rerun cycles.

BUS ALLOCATION ARBITRATION

1 Bus Request
When an external unit wishes to take control of the
bus, whether in a multiprocessor context by means of
the BAM 68452 bus arbitration module or for a direct
memory access via a DMA controller, it make~ its
request of the MC 68000 with the enabling signal BR
(Bus Request).
The 68000 then confirms that it has received the
signal by replying with ~G (Bus Grant). The
acknowledgement, that is, BG at low, occurs~etween
1.5 and 3.5 clock periods after the request (BR
at low), which will lead us quite naturally to propose
several consequences.

2 Agreement to Transfer Bus Control

The transfer of the bus to the requesting circuit only
becomes effective if the following four conditions are
satisfied: the AS output of the 68000 is high, thus
confirming the end of the current bus cycle; the
DTACK input is high, indicating that no
addressable circuit (peripherals, memories, etc) is
communicating with the processor; the BGACK input
is high, indicating that the bus is not being
controlled by a main bus control circuit; BR remains
low.
If these four conditions are fulfilled, at the end
of the current bus cycle the 68000 sets the address,
data and exchange control lines to the high impedance
state, and awaits confirmation of bus control from the
requesting circuit (BGACK at low).

3 Recognition of Bus Control by Requesting Circuit

The requesting circuit confirms that it has assumed
control of the bus by enabling the BGA~ignal,
and this remains so for as long as BGACK is at
low. It therefore becomes superfluous for the BR
output to ~emain low, and the 68000 accordingly
repositions BG at the high impedance state.
 30 The 68000 Hardware and Software

4 Methods of Operation
We shall examine three examples of requests that might
occur in practice.

Bus request during bus cycle

If the BR input is enabled after AS is at low, the
68000 acknowled~s receipt of the bus control request
by asserting BG (at low) 1.5 clock periods later.
This i~the optimum.
If B~is asserted before AS, that is, during SO
or Sl (AS is asserted during S2), the 68000 decides
that it has not advanced sufficiently far in its bus
cycle to be able to respond as before, namely 1.5
cycles after the request. As a consequence,
confirmation that the 68000 has received a bus r~uest
(BR at low) will be made 1 clock period after AS
has been set at low (see figure 3.11).

elK
SO S2 S4 56 so
BR
BG
BGACK ---~-I-:,L.~::;:;:$t=~---

A1-A23

AS

uos --.1 ,---

lOS Jr------ '---__ .-.-J ,---

FCOFC2===x ...-.---------....., C
R/W ---.J
OTACK --f /11//

+
00 o 15-------L_.ltmpMl!UtIID----------;-----L_-.mmm
Word read cycle ~ Busesunder DMA control Processor has resumed bus control

Figure 3.11 Timing of various signals when bus request

arrives during execution of a bus cycle

CLK
so 52 54 56 so 52 54 56 SO
BR----_

BG----~:::;:~=~-\-

BGACi<
A 1A23 - - - - - (

AS
Uos-----\ r----------~ r_
COS-----\ r ~ r_
FCOFC2=:Y ) ( 'C
R/W

OTACK ~~@IoWoIl~ /huuWl ~ r-

--------«("-_~-............. MW
~ ~.- 4. ~ Busesunder DMA control .~_. Processor has resumed bus control
00-015

Word read bus cycle

Figure 3.12 Timing of various signals when the bus

request arrives at the beginning of a bus cycle
 Bus Operation 31

Bus request at beginning of bus cycle

If BR is asserted at the end of a bus cycle (S6 or
during S6 or S7) and is therefore present at the
beginning__of the next bus cycle, the 68000 will
position BG at low after AS is enabled by the
processor (see figure 3.12).

Bus~equest when not in use

If BR is asserted when the 68000 is not using the bus
(that is, when the 68000 is working internally), the
processor~ill confirm receipt of the bus request by
setting BG at low 2.5 periods after the request.
Also, the bus control will only be effective~ further
1 period later, that is, 3.5 periods after BR is set
at low (see figure 3.13).
0.5
CLK~
so 52 54 56 so 52 54

BGA:~------~tL.;Ll
_S_~_0~t5~~~§43_~,--_0---J4_---JI _
A1 A23 --{== -=______ ( _
AS~'-_ _---J/ ~
U05 ~ I------'-----------~
L05~ / ~
FCOFC2:X (-----
R/W - _ _~ ___J

OTACK---_......
~ 11III '-
00-015

Word read bus cycle -+-

~(;:::::=;ei!~-----------------~=
Bus inactive I ~ __ Buses under
~
DMA control ---..I.- Processor has resumed
bus control

Figure 3.13 Timing of various signals when bus request

arrives while bus is inactive

Bus Control Circuits

There are at least three DMA controllers in the 68000
family (to which new circuits are continually being
added). These are as follows

SBC 68430 (1 channel) from Philips/Signetics

DDMAC 68440 (2 channels) from Motorola
D~ffi 68450 (4 channels) from Hitachi

Motorola have also produced a bus arbitration module

BAM 68452 that is capable of handlin~ight bus
reguests via the device bus request lines DBRO to
DBR7, where DBR7 carries the highest priority request
and DBRO the lowest. This system of priority is only
invoked if two or more requests arrive at the 68452
simultaneously.
32 The 68000 Hardware and Software

These eight inputs have assigned to them eight

device bus grant outputs, DBGO to DBG7, whose role is
to advise the requesting circuit tha!-the request has
been received by the 68000 via the BR output of the
68452. Once this~been done, the requesting circuit
positions the BGACK line connected to the BAM 68452
and to the 68000 (see figure 3.14).

DBAn

BA

Figure 3.14 Communication between requesting circuit

and processor via bus arbitration circuit

HALT AND SINGLE STEP OPERATION

1 Functions of the Bidirectional HALT Line

1.1 On input
Keeping the RESET and HALT lines at low causes a
processor RESET (initialisation phase of the 68000) or
return to a system function following a double error
bus.
If an external circuit activates the HALT line
during handling of ~ bus cycle, the processor
terminates its cycle (AS = 1 at the end of the cycle)
before being stopped on the next bus cycle to be
executed. This next cycle places the address and data
lines at the high impedance state.
 Bus Operation 33

___ During~he__entire _halt period the control lines

ODS, LDS~ AS and R/W are inactive while the bus
arbitration lines, namely BR, BG and BGACK are
available.
The halt or single step mode allows the instruction
executing program to be debugged, bus cycle by bus
cycle. This function is complementary to the trace mode
which authorises the processor to execute the program
instruction ~nstruction.
Once the HALT line (on input) is again at high, two
clock periods (Tl and T2) are necessary before the
processor can resume the remainder of the program (see
figure 3.15).
____I f an external circuit enables inputs BERR and
HALT (BERR and HALT at low), the processor terminates
its bus cycle before proceeding, subject to certain
conditions (non-indivisible cycle and HALT line reset
at high), to the rerun of the preceding cycle.

f
Beginning
of bus cycle f
End of bus cycle;
address and data
buses set to high
impedance T1 T2 I
r Beginning of
next bus cycle

ClK 50515253545556 57 ~~"""~50 515253'5455 5657

A1·A23

lDS/UDS__
AS
~=======--+-+- ---l -+--_-=======~+--_
Riw

DTACK-=;;;;;~~~~~~~~====1::==:±==~~~~2~=
00-015
~~==~-----t------j======:::t=============+-===
FCO-2

+- - -
HALT
~ - Read - - Halt - - - Read - ~

Figure 3.15 Timing diagram to show processor HALT

(Courtesy of Motorola)

1.2 On output
When the HALT line is asserted on output (HALT at low),
the outside world is alerted that the processor is
halted, following~rdware of software event. Only an
action on the RESET pin will cause it to leave this
state.
ADDRESS BUS
DATA BUS
IRQ ACIA1
I
~HA8 18 IRQ3 IRQ4
9 E ~
10 R/W
8 ACIA1
7643 ." -- .'~ +5V VMA RXD
PROM MAKPAGE CTS
decoder • I. .. MYRAM

v
I-IAl t:ttl : MYROM
:;x: • 10 I I I

M
:;x:H1 15 ~
A6 Cb
2 16 2
3 21 3
4 22 4 ~
5 18 5 8
6 PA L
I : ~~~~RAM 6
718 L4 A11- 7 ~
...,
SEL10
8 1
L~,)A:'-_----------=LD=S~~· 81
9 ~
Q)
10 ~
11 12 AS.. ' Q)
13 23 +5V :'::3
Q..
Al 8 14 17
~
56 F !
p -
I
OMil _ 56pF RTS
Q)
DOl 6850 ~
\ TXD ~
t ACIA2
RXD
CTS

~
.::,t,
,.... D7
~

DO-D7

Figure 3.16 Use of programmable array logic devices for input/output

decoding. (Copyright Microprocess)
 Bus Operation 35

INTERACTION WITH SYNCHRONOUS CIRCUITS (6800 FAMILY)

Interfacing with 6800 Family

1.1 Review
Although synchronous, the 6800 family is hardware
compatible with the MC 68000, something that was not
easily achieved, as the reader may imagine.
The solution adopted by Motorola of providing on the
MC 68000 the means for the exchange of important
signals with the MC 6800 is probably the most
satisfactory.
Three lines from the MC 68000 ensure interfacing
with the peripheral circuits of the 6800 family

clock E (Enable)
validation of a peripheral address
(VPA : Valid Peripheral Address)
validation of an addressed position
(VMA : Valid Memory Address).

The clock signal E, which is equal to one-tenth of

that fed to the clock input of the MC 68000, has a
cyclic relationship of 60/40 (six periods of input
clock at low and four clock periods at high). Note that
this cyclic relationship for example avoids the need
for the 68000 to have to resynchronise itself after
each movement of bytes when handling such instructions
as MOVEP.W (MOVEP.L). This feature allows two
successive VPAs for consecutive E periods.
It quickly occurs to the user that certain 6800
applications may require a clock frequency greater than
that available at the output E of the MC 68000
(E = 1/10 of the frequency on the CLK input of the MC
68000), such as for example the advanced communications
controller circuit, ADLC MC 6854, which in order to
effect a high speed data transfer, most usually
requires a clock frequency of 2 MHz.
In this case, the user will have to solve the
problem by hardware means; for example, by
"refabricating" the clock E.

1.2 Exchange Protocol (MC 68000/MC 6800)

We assume that the 6800 peripheral interacts with the
68000 processor by means of the lower line 00-07,
enabled by LOS 0 (or via the upper line 08-015,
enabled by UDS 0).

State 0 : SO
line R/W is at read (preceding cycle)
address lines are at high
lines FCO-FC2 show the processor status.
36 The 68000 Hardware and Software

State 1 Sl
address bus is freed from the high
impedance state
the processor places the current address
on lines Al-A23.

State 2 S2
the 68000 address strobe AS is
asserted, indicating that there is a
valid address on the bus.

Write Read
Line R/W Output LOS
is set to low, enabling
write (R/W 0) channel 00-07
(or UOS for
channel 08-015)

State 3 : S3 State 3 S3
The processor presents
the data item on channel 00-07,
then one half clock cycle
later, asserts LOS
(LOS = 0) confirming
the validity of
the data on 00-07.
(Alternatively, on 08-015 by
asserting UOS.)

At this point, the processor waits for the VPA

signal at low level, by inserting waits W. In fact, the
VPA input informs the MC 68000 that the current
address belongs to a 6800 family circuit or to a memory
field reserved for the MC 6800. When the 68000
recognises the VPA signal on the low state of E, it
is aware that a synchronous peripheral wishes to
interact at the E clock rate after synchronisation. The
VMA output, which is used for decoding 6800
peripheral circuits (selection or deselection), is
asserted by the 68000 (VMA = 0), two clock periods
before the E signal moves to high.

Write Read
States 5 and 6 States 5 and 6
(55 and S6) (S5 and S6)
The data item is The processor
latched when clock carries out a read
E moves from at the high state
high to low. of signal E.
 Bus Operation 37

State 7 S7
Output LOS (or UOS) is disabled
by the 6~00.
Outputs AS and VMA are set high,
which authorises the ~OO peripheral
circuit to disable VPA(VPA = 1).
Note that OTACK must on no account
be enabled at the same time as VPA.
~~~wwwwwwwwwwwwwww~~

ClK

A1·A23 }{~ }C

\ I
DlACK

Data Out ---{\... -.J>-

Data In ------------('---_--J>-
FCo-FC2 ~~ x=
E
_ _ _I ,'--_ _---J! L-
VPA
\L- ~r_

\\--_ _---JI
Figure 3.17 "Worst" timing exchange with a synchronous
peripheral (6800 family)
505254 W W W W W W56 5052

A1.A2~'__ ~>--< _
AS~ ~
DTACK
-------------------------
Data o_u_t--~'_ ____J)>----

Data In----------------~(\_ ___.J»)----

Y.=================X==
FCD-FC2

E \~
,'------
,'--
--JI
-..J!
VMA - - - - - - - - - - - . \ \ - ---J/
Figure 3.18 "Best" timing with a synchronous peripheral
(6800 family)
4 Exception Procedures

EXCEPTIONS

1 Overview
The name trap or exception is given to a change in
routeing of the program which is generally the result
of internal (software) or external (hardware) events.
Each trap or exception has a byte associated with it
that represents a vector number which, when multiplied
by four, gives the offset of the corresponding vector.
The 68000 microprocessor contains 255 vectors in
memory, arranged in an exception table 512 words in
length (1024 bytes), from address $000000 to address
$0003FF. See table 4.1.
Each exception vector is 32 bits long, except for
the initialisation vector which is coded in 64 bits.
It should also be noted that all the vectors in the
exception table are located in the data supervisor
memory area, except for the initialisation vector which
resides in the program supervisor memory area, thus
providing greater security. Table 4.1 shows how the
exception table is organised.
Before embarking on a detailed study of the
different types of exception, it is valuable to have a
knowledge of the general procedure followed by the
processor when handling an exception. This may be
summarised as follows
1. A temporary copy of the status register is made
in an internal register of the 68000.
2. Bit S (8 = 1) is asserted, thus placing the
processor in supervisor mode. All exceptions will
therefore be handled in supervisor mode.
3. Trace bit (T = 0) of the status register is
disabled.
4. The vector number is obtained.
5. The program counter and the previously copied
status register are saved to the supervisor stack.
(Additional information is stored in the case of
address error or bus error exceptions.)
6. The table is consulted for the start address of
the exception program.
We shall see that only exceptions caused by an
external event do not more or less exactly follow this
procedure.

38
 Exception Procedures 39

Table 4.1 Exception Vector Assignment

Vector Addresses Assignment
Nos. Dec Hex Space

o o 000 SP Reset supervisor stack

4 004 SP Reset program counter
2 8 008 SO Bus error
3 12 ooe SO Address error
4 16 010 SO Illegal instructions
5 20 014 SO Division by zero
6 24 018 SO CHK instruction
7 28 Ole SO TRAPV instruction
8 32 020 SO Privilege violation
9 36 024 SO Trace
10 40 028 SO Line 1010 emulator
11 44 02e SO Line 1111 emulator
12 48 030 SO Unassigned, reserved
13 52 034 SO Unassigned, reserved
14 56 038 SO Unassigned, reserved
15 60 03e SO Uninitialised
interrupt vector
16-23 64 04e SO Unassigned, reserved
95 05F Unassigned, reserved
24 96 060 SO Spurious interrupt
25 100 064 SO Level 1 interrupt
autovector
26 104 068 SO Level 2 interrupt
autovector
27 108 06e SO Level 3 interrupt
autovector
28 112 070 SO Level 4 interrupt
autovector
29 116 074 SO Level 5 interrupt
autovector
30 120 078 SO Level 6 interrupt
autovector
31 124 07e SO Level 7 interrupt
autovector
32-47 128 080 SO TRAP instruction
vectors
191 OBF SO TRAP instruction
vectors
48-63 192 OCO SO Unassigned, reserved
255 OFF Unassigned, reserved
64-255 256 100 SO User interrupt
vectors
1023 3FF
Note: SP Supervisor Program (FC2 = FCI = 1, FCO = 0)
SO Supervisor Data (FC2 = FCO = 1, FCI = 0)
40 The 68000 Hardware and Software

68000
Exception
processing

Figure 4.1

2 Internal Exceptions
Internal exceptions or traps occur in the following
instances
l.when certain instructions are being carried out
2. when there is a programming error
3. when the trace bit of the status register is
asserted.
This new concept confirms the software bias of the
MC 68000 and the considerable importance that the
manufacturer has attached to ensuring the security of
the system.

Handling Certain Instructions

a) Division by zero : Vector number 5
Division by zero is a typical example of the trap set
by the MC 68000 for the programmer when executing the
instructions OIVS and OIVU where the divisor is zero.
When this occurs, the processor generates internally
the vector number 5 (corresponding to trap division by
zero) which when multiplied by four gives the address
of the vector associated with the trap. The address,
which is found in the exception table (5 x 4 = $14),
will need to be loaded by the programmer with the start
address of the division by zero program.
 Exception Procedures 41

Of course, in practice it is up to the programmer to

write a subroutine, for example to recalculate the
divisor more accurately, send an error message or
simply halt execution of the program.

b) TRAP CHK : Vector number 6

The CHK instruction allows one to test whether the
operand contained in a data register lies between two
values. If this is the case, the program continues: if
not, the program is rerouted in the exception table to
address $18 (6 x 4 = 24 = $18), in order to recover
the start address of the exception program CHK.

c) TRAPV : Vector number 7

If the condition V = 1 is satisfied on execution of the
instruction TRAPV, the program is branched to the
associated vector to find the address of the trap
exception procedure in the event of overflow.
This "exceptional" instruction is completely
tailored to ensure that the 68000 has satisfactorily
carried out the division required by the OIVU or OIVS
instructions (see chapter 6). In fact, if the processor
suspects that overflow will occur, it does not carry
out the division but sets V to 1.

d) TRAPs available to the user: Vector numbers 32 to 47

There are 16 TRAP instructions, called TRAP #0, TRAP #1
to TRAP #15, which provide the programmer with the
facility to reroute at will a program sequence to a
resource systems type of exception procedure (for
example, breakpoints).

Program Error
There are three types of exception or trap resulting
from a programming error.

a) Address error : Vector number 3

Unfortunately, when the 68000 processor detects an

address anomaly (for example, writing a word to an odd
address), it is too late to halt execution of the
instruction, as the 68010 would. Figure 4.2 shows that
the signals UOS and LOS are asserted by the 68000 (not
by the 68010), which will execute the procedure before
being rerouted to the trap, address error, but after
executing the following microprogram
1. copy the status register (SR) in an internal
register of the 68000
2. enable the supervisor mode by S 1
3. disable the trace mode by T = O.
42 The 68000 Hardware and Software

CLK
A1.A23--{ H ~
AS
\ 1\ ~ L-
UOS
/68010 ~
.
I
. L
\ .. '
'------- --- __1.... 68000
LOS , ~

\ / ____________J! L
.J \ ~ L-
•
RIW
/'
_________1J- 680~0
~

'-
OTACK
III '~\

OO.015----e .-H )~----'~"""" ---------(c=

r.- Read word
at even address
-+- toWrite word -+- Detect ~ Save to
odd address error supervisor stack1

Figure 4.2 Timing of an address error

Since the 68000 processor has not been able to
execute the current instruction, the contents of the
program counter (PC) are incremented by between two and
ten bytes in relation to the address of the first word
of the instruction, before being saved to the
supervisor stack. This particular feature may cause
problems for the programmer when it comes to
determining in the exception program what the main
program return address should be (see figure 6.6).
The following have to be saved
1. the status register previously copied in the
internal register of the 68000 to the supervisor
stack.
2. the instruction register containing the op-code
of the aborted instruction.
3. the current value of the address transmitted on
lines Al to A23 - also saved to the supervisor stack.
Finally, the manufacturer offers the user a super
status word consisting of information that indicates
1. the status of the processor at the moment of the
error by means of lines FCO to FC2;
2. whether the processor was at read or write;
3. whether the processor was handling an exception
or not.
Although inadequate, compared with the 26 words
stored by the 68010 in the same circumstances, the
above information does allow the situation to be
analysed quite precisely.

b) Privilege violation : Vector number 8

If the processor tries to execute a supervisor resource
in user mode, the program is rerouted to a trap called
"privilege violation".
 Exception Procedures 43

In fact, as we have already noted, all functions are

accessible to the programmer in supervisor mode,
whereas in user mode the resources capable of modifying
the system state are said to be privileged.
This concept of hierarchical levels, which exists
already on some minicomputers, provides the system with
a degree of security never achieved with 8-bit
processors. For example, resource systems are protected
in a multi-user configuration, such as the OS9 68K from
Microware and Motorola.
The privileged instructions are

STOP AND. v-1 # da ta , SR

RESET EOR.W # data,SR
RTE OR.~'J # data,SR
MOVE.W Source,SR MOVE.L An,USP
MOVE.L USP,An

c) Illegal instructions : Vector number 4

Unimplemented instructions

code 1010 vector number 10

code 1111 vector number 11

An instruction is said to be invalid if the 4-bit

MSB of the instruction word is not recognised by the
processor. If such a combination is decoded by the
instruction decoder register of the CPU, an invalid
instruction trap is produced.
Three op-codes, $4AFA, $4AFB and $4AFC, lead to an
illegal procedure. The first two ($4AFA and $4AFB) are
reserved by Motorola for the system; the third $4AFC
can be used by the programmer to force the 68000 into
an illegal instruction trap.
Instructions whose binary combination of bits 15 to
12 corresponds to code $A(lOlO) and $F(llll) are not
implemented on the 68000, 68008 and 68010. However,
they are assigned an emulation vector which allows the
operating system to detect certain program err~rs or to
emulate instructions unimplemented by the manufacturer
but developed by the user.
Note that the new 16/32-bit MC 68020 microprocessor
recognises the binary combination 1111(F), which allows
it to use the MC 68881 floating point co-processor. The
MC 68020 has additional instructions (such as MOVE F,
MOVE SB, PACK and UNPK), some of which manipulate
strings of ASCII characters.

Assertion of Trace Bit (T = 1) : Vector number 9

After executing each instruction the processor tests
internally the logical state of the status register
44 The 68000 Hardware and Software

trace bit T. If this is asserted (T = 1), the processor

obtains the start address of the trace program from the
exception table. If on the other hand bit T is negated
(T = 0), the processor moves on to execute the next
instruction (see programming example in chapter 7).

4 External Exceptions
External exceptions can be generated by the following.
1. On start, keeping both the RESET and HALT lines
low for 100 ms, this being the initialisation phase: or
again low for 10 clock cycles in order to exit the
68000 from the HALT state following a double bus error.
2. A bus error detected by an external device or by
a MC 68451 MMU circuit, which asserts the input BERR of
the 68000 processor low, following a hardware anomaly
during execution of an instruction (protected segment
on write).
3. An interrupt request made to the processor by
means of lines IPLO, IPLI and IPL2.

100 milliseconds
RESET!C »l~ _
l '
H'AIT
l ~1
BUS 1
CYCLE ~

2 3 4 5 6
1. Internal start up time.
2. Load 16 high order bits of the supervisor stack
pointer.
3. Load 16 low order bits of the supervisor stack
pointer with the contents of addresses $000002 and
$000003.
4. Load 16 high order bits of program counter with the
contents of addresses $000004 and $000005.
5. Load 16 low order bits of program counter with the
contents of addresses $000006 and $000007.
6. Fetch first instruction.

Figure 4.3 Sequence of operations on RESET

(Courtesy of Motorola)
 Exception Procedures 45

I RESET and HALT I

Figure 4.4 RESET and HALT circuit.

(Copyright Microprocess)
46 The 68000 Hardware and Software

Initialisation exception or reset : Vector number 0

When requested by an external source, initialisation of
the processor is carried out by holding low for 100 InS
the bidirectional lines RESET and HALT that are fixed
on entry (see figure 4.3).
Initialisation consists of the following sequences
a) Bit S of the status register is asserted (S = 1),
thus placing the processor in supervisor mode.
b) Bit T (trace) of the status register is negated
(T = 0), disabling the trace function.
c) The interrupt mask (12, II, 10) is set at level
7, that is, 12 = 1, II = 1 and 10 = 1.
d) Since the vector number is generated internally,
the processor loads the supervisor stack pointer with
the contents of addresses $000000 and $0000003 and the
program counter with the contents of addresses $0000004
and $0000007. We now understand why the initialisation
vector is coded in 64 bits. The processor then executes
the instructions located at the address initially
loaded in the pc.
If an anomaly occurs during recovery of the
initialisation (reset) vector, the processor reacts as
though there is a catastrophic error, called a double
bus error, by placing itself at the halt state, so
inhibiting all program execution.
Control of the system can only be regained by action
on the RESET and HALT line lasting 10 clock cycles.

Bus error : Vector number 2

A bus error may occur for example when the processor
tries to access a nonexistent or protected work area,
such as missing or faulty peripheral devices or
protected RAM memories.
When an external electronic circuit recognises a bus
error, it pulls the BERR line low, thus alerting the
processor that there is/ a hardware anomaly during
execution of the instruction. The timing diagram of
figure 4.5 shows the different stages that lead the
68000 to handle the bus error exception. As in the case
of the address error exception, this operation is
preceded by saving on the supervisor stack any
information that may help the user to identify the
hardware error. Figures 4.6 and 4.7 show how the bus
error is handled by the processor and how the
information is stored in the supervisor stack.
If an anomaly occurs during handling of the bus
error exception, the processor goes to halt, which
stops the exception handling. This is known as a double
bus error.
Once again, system control can only be regained by
action on the reset and halt lines.
 Exception Procedures 47

'----
\
No response Bus error I Bus error
~ Read ~ (card missing - ~ recovery vector
detection
operation perhaps) after saving to
supervisor stack

Figure 4.5 Timing of a bus error

(Courtesy of Motorola)

Normal exception sequence

internal copy of SR
.............- - - - - 1 S bit enabled
T bit disabled

Start address of
exception handling
program fetched

Program counter
loaded with exception
handling address.
Exception program
executed

Figure 4.6 Bus error handling

48 The 68000 Hardware and Software

15 2 o
Supervisor stack
pointer after
exception

High order of address on bus

Low order of address on bus

Address
error and Instruction register Increasing
bus error addresses

Status register

Groups High order of program counter

1 and 2

Low order of program counter

_ Supervisor stack
pointer at moment
of except ion

Figure 4.7 Information saved to the supervisor stack

when a bus error or an address error occurs

Definition of Status Super Word

Function code: logical status of lines FC2, FC1, FCO
(see figure 1.2)

I/N o instruction in course of execution

1 exception in course of execution
(this was not an instruction)

R/W o the processor was at write

1 the processor was at read

Interrupts
The 68000 microprocessor possesses 192 usable vectors
for peripherals that can provide a vector number (for
example, MFP 68901, PI/T 68230, etc) and 7 autovectors
allocated to 6800 family circuits (ACIA 6850, Timer
6840 and PIA 6821) that do not generate a vector
number.
Seven levels of priority, fixed by the programming
of the interrupt mask (see status register), can be
assigned to these 199 vectors, as shown in the
following table.
 Exception Procedures 49

Level 12 II 10

7 1 1 1 Highest priority
6 1 1 o
5 1 o 1
4 1 o o
3 o 1 1
2 o 1 o
1 o o 1 Lowest priority
o o o o No priority (no
interrupt request)

The levels of interrupt are numbered 1 to 7 (level 0

indicating that there is no interrupt request), with
level 1 being the lowest priority and level 7 the
highest.

Interrupt recognition
When an interrupt request reaches the processor, it is
first made to wait, before being interpreted by the
processor at the end of the instruction cycle. (See
figure 4.7 for timing diagram.)
If the interrupt level present on lines IPLO, IPLI
and IPL2 is less than or equal to the interrupt
mask, the processor executes the next instruction and
ignores the request. However, if the request level is
greater than that of the mask, the processor proceeds
to the interrupt recognition described below. Note that
level 7 priority is a special case; it cannot be
inhibited by the interrupt mask. Level 7 interrupt thus'
provides a non-maskable interrupt capability.

1. The contents of the status register (SR) are

copied into an internal (non-programmable) register of
the 68000.
2. Bit S of the status register is asserted (S = 1),
thus placing the 68000 in supervisor mode.
3. Bit T of the SR is negated (T = 0), disabling the
trace function.
____
4 . The interrupt level present on lines IPLO to
IPL2 is recopied into the status register. Because
of this, the processor will only be able to be
interrupted by an interrupt level greater than the one
currently being handled.
5. - Address
---
lines Al to A3 reflect the status of
----
lines IPLO to IPL2, so that an external decodirg
logic can determine which interrupt request is
currently being recognised.
The remaining lines of the address bus (A4-A23) and
the outputs FCO, FCI and FC2 are set to 1.
50 The 68000 Hardware and Software

~
~_----::::::==========~--\'-----
,""' ..Jr---\\- _
(
Vector number ~,,_ _~
--------(~---->---<----
------........ '<'------~
IPLO-2 \ - - - - - -.... ~---------_-I SR and
I Bus cycle of I 14 Interrupt acknowledge .1_ high PC .1
• an instruction • (Vector number acquisition) saved to
supervisor stack

Figure 4.8 Interrupt from 68000 peripherals

(Courtesy of Motorola)

Problem
Does the interrupt recognised by the processor corne
from a 6800 peripheral (figure 4.8) or from a 68000
peripheral (figure 4.9)?

fPCO
fl5IT
fP[2

' ....1 _ - - - - - - - - - - - - - - - 1 RtW

._--------------tE
I_----.----------t~
T+SV ~

Me 68000

00-07
(or 08-015)

Figure 4.9

6a. 6800 peripheral

The VPA line (valid peripheral address) at low
alerts the 68000 processor that a 6800 peripheral (PIA,
ACIA) requires its attention and that, in order to work
with it, it must synchronise itself with the clock
 Exception Procedures 51

AU TQ VECT O R O P!:RATlON n ....N G DI AG RAM

PAL16R4
* •• • •••• • ~~S 2

R/W-~::::~~=========::"'-
OUCl(
06-0 1S, -~->-+------------

OO.01C~~~~~====~=~=::::;C
FCO· 2 )
FC'

,
IPl O· 2 FCO

VP'~~~~~~~~;==
Viii \
__ ----l
/":

t- MAl+ - - AUTO't"EcTOR OPERATION - - - -l

HOR
CYC LE

Figure 4.10 Autovect orisation using pro grammable array

logic
(Court es y o f Monolithic Memorie s)

[i5S_~~~~====================:!....-~
Rm
OTACK~
0 8-015 ---eJ~---------------­
00-07 ~>----------------
X 'I 'C
__
FCO·2

IPLO·2 ~\..--;:::===~ ----;===~

E l.-
VPA =======----..\ I\...
VMA \ /
!.....L. Normal ~
~ c yCle- -- Auto-vectorisat ion - - -~

Figure 4.11 Timing of interrupts from 6800 peripherals

(Courtes y of Motorola)

signal E , which is equivalent to the 02 of the 6800. On

enabling VMA ( valid memor y address), the 68000
addresses the peripheral and indicates that it is read y
to i n t e r a c t in s ynchronisation with clock E ( the 68000
is s ynchronised) .
6800 peripherals do not g enerate ve c t o r numbers. The
52 The 68000 Hardware and Software

RESET

t
t t MC 68000
Exception table

R/W PC
PIIT
68230
DB $000000 -Initiafisation
--Buserror
ddress
error

07 ------411
$000 100 .......
User
PIRQ $000 3 FF interrupt
vector
TOUT

T+5V
DTACK

RS1RS5 ~

jrthcK7ddress
FCO
_ decoding FC1
CS and FC2
lACK LOS

Address bus

Figure 4.12
68000 therefore uses the autovectorisation procedure
that allows it to access the 7 autovectors of the
exception table (numbers 25 1 0 to 31).
The vector number is determined from the priority
-- --
level established by lines IPL2 to IPLO, remembering
that these lines are enabled at low state.
Example
Interrupt mask: 12 = 1; II = 0; IQ =_1_
Interrupt request: IPL2 = 1; IPLI = 1; IPLO 0
The 68000 "internally" supplies the vector number 30
that corresponds to level 6 (vector address = 30 x 4
10
= 120 = $78).
10
6b. 68000 peripheral
When the decoding logic recognises the interrupting
circuit, it places a vector number on lines 00-07 of
the data bus (LOS = UOS = 0) and sends the DTACK signal
to confirm the transfer of a data item.

When the 68000 recognises OTACK (OTACK = 0) during a

read cycle (R/W = 1), the data are latched and the
read bus cycle is terminated, changing UOS and
LOS to high, and disabling OTACK.
 Exception Procedures 53

Interrupt Controller Logic Diagram

External Vector Generation
PAL20L10

CLK
Fi> ~_@) -------i"
"D2

A2 '--- -r;-J .. 01
I-----~ .. DlACK
i ]- - - - -- __ IPL2 A1 I- - - - - - - ..
~ DD

FC2
1------_~ t P L l

FC1 ~--,,_. r'

1- - - - - - ..
~ I PlO
FCD

FC'

45.---- 0...;'-' FCD

-,-
F~ure 3

so S1 52 53 94 S5 56 97
CLK

Al - 23 - ---1-:-"7--:'1

--.J } I
~ i..
_16_

RiW_---1+_-l

- ---1+---/''I--------i - - - - - - - I
~
FCO- 2

I
~·=tt=~------~tt======= !-
r; r--
I
0 0- 7

+ -:-:-::---::'1
OTACK _ _
_1'9~~ I

WR IT E M A CH INE CYC L E INTERRU PT ACKNOWLEDGE CYCLE

1 CLOCK PERIOD (80 ns) 8 CLOCK HIGH TO R /W HIGH (60 ns) 15 DATA VALID TO OS LOW ( 15 ns )
2 CLOCK LOW TO ADDR ESS (SS ns) 9 CLOCK HIGH TO RiW LOW (60 ns) 16 C LOCK HIGH TO AS , os LOW (55 ns)
3 CLOCK HI GH TO ADDR ESS Hi-Z (60 ns) 10 CLOCK HIGH TO Fe VALID (55 ns ) 17 PA L's INPUT TO Hi -Z (25 ns)
4 CLOCK HIGH TO AS LOW (55 n.) 11 CLOCK HIGH TO OATA Hi·Z (60 ns) 18 PAL 's INPUT TO Hi -Z (25 n51
5 C LOCK lOW TO AS HIGH (50 ns) 12 AS HIGH TO ClACK HIGH (70 ns) 19 PAL 's INPUT TO Hi -Z (25 n51
6 C LOCK HIGH TO oslOW (55 n s) 13 PAL·s CLOCK TO OUT (25 ns )
7 C LOCK LOW TO osHIG H (50 ns) 14 MI NIMUM seTUP TIME ( 20 ns)

Figur e 4 .1 3 Interrupt vec t o r i sa t i o n using programmable

arra y logic (Courtes y of Monolithic Memories)

Example
Suppose that th e peripheral circuit PI /T 68230 (see
s ection 4 .2) positions the ve c tor number 64 in base 10
(equi valent to 40 in base 16). Figure 4.11 show s that
the address pointed to, equal to $40 x 4 = $100, is
ind eed the v e c t o r corresponding to the number 64 ,
10
54 The 68000 Hardware and Software

Problem
What happens if during interrupt recognition no
peripheral (whether 6800 or 68000) replies by
maintaining at low the signals VPA (for the 6800
family) and OTACK (for the 68000)?

Answer
The explanations given so far would lead one to assume
that the BERR line (bus error exception) would
terminate the acquisition of the vector number. Now,
the the program is rerouted by the 68000 towards the
spurious interrupt vector number 24 1 0.

7. Saving the program counter to the supervisor

stack.
8. Saving the status register, previously copied in
an internal 68000 register, to the supervisor stack.
9. Retrieval of the begin address of the interrupt
program in the specified vector.
10. Execution of the interrupt program which, like
every exception program, will have to terminate with
the instruction RTE (Return from Exception).

Uninitialised Interrupt Vectors : Vector number 15 1 0

Some 68000 peripherals have both vectored and
autovectored interrupts; an example is the Pl/T Me
68230 circuit (see section 4.2).
This circuit has two interrupt vector registers; one
is assigned to the ports (PIVR) and the other to the
timer (TIVR).
On interrupt vectorisation, the vector number placed
on lines 00-07 by the PI/T 68230 is the operand
previously loaded into these registers by the
programmer.

Example
Suppose that the PI/T 68230 circuit generates a
vectored interrupt after time out (that is, at the
timer level), and that the timer interrupt vector
register (TIVR) has not been initialised. In this case,
and in common with most of the 68000 peripherals that
have interrupt vector registers, the MC 68230
peripheral dispatches the uninitialised interrupt
vector or vector number 15 1 0($OF).
In fact, this number is automatically loaded into
the interrupt vector registers (PIVR and TIVR) when
there is a reset on the peripheral circuit. As a
result, it is possible to recover in a uniform way from
a programming error (by having the same number for all
circuits).
 Exception Procedures 55

68000 EXT A/S INTACK

+5V

3 1 12 10 20
BG 6
BR 13 PAL 16 R4
BGACK 4
18 11 14 19

iPL1
IPLO IPL2

+5V +5V

T
MAKBUS®

Figure 4.14 Shows interrupt priority control and bus

arbitration in a multiprocessor environment. (Copyright
Microprocess)

5 Recognition and Exception Priority

Overview
Exceptions are classified by groups according to the
following two criteria (see table 4.2).
1. Recognition of the exception by the 68000
processor.
2. The consequential effects of the exception on the
program or the system.
Thus a bus error type of exception recognised during
a clock cycle (1) with consequences that we know, is
not of the same importance for the system as a division
by zero type of exception recognised during an
instruction cycle (3). This concept inevitably leads
one to think in terms of group priority and of
hierarchy within the group.
56 The 68000 Hardware and Software

ADDRESS BUS

DATA BUS
RS1
I
I
I
I
I
I PORTA
RS5

DO
I
I
I
I
I
I H1
I
I H2
I
I
H3
I H4
I
07

68230

AS PORT B

FCO
FC1
FC2
IRQACK OUT
IIRQACK IN

V322P
0 - - - - - - 1 TOUT
PORTC

ClK

USER

Figure 4.15 Interrupt device interface. The PAL16R4

allows priority encoding on 7 input signals II to 17
(II highest, 17 lowest). The PAL16L8 decodes lines FCO,
FCl, FC2 and AO, AI, A2 so that vectors can be
generated in phase with the interrupt acknowledgement.
(Copyright Microprocess)

Group 0
Group 0 consists of three exceptions - initialisation,
bus error and address error - which are recognised by
the 68000 at the end of a clock cycle. These occupy the
position of highest priority group. In addition, if
during the handling of an address error exception the
BERR (bus error) line is set to low, the processor
abandons handling the address error exception in order
to execute the bus error exception. Thus, even at the
heart of group 0 a hierarchy of exceptions is
established. As a result, the initialisation exception
 Exception Procedures 57

possesses the highest priority, while the lowest

priority is assigned to the address error exception.

Table 4.2 Priorities and Exception Groups

Group Group Exceptions Hierarchy Recognition

1
o Reset End of
Bus error clock cycle
Address error
1 Trace
interrupts
Illegal End of
instructions instruction
Privilege cycle
violation
2 TRAP # 0 to
TRAP # 15 During an
TRAPV CHK instruction
DIVU,DIVS cycle
(if zero d i v , )

! Increasing priority
I No priority
Group 1
Of lesser priority than group 0, the exceptions that
make up group 1 include those recognised at the end of
an instruction cycle (3), like tracing and interrupts,
together with those recognised at the end of a bus
cycle (2), namely illegal instructions and privilege
violations.
The different nature of the exceptions that go to
make up group 1 explains the natural hierarchy between
them, as can be seen from the following.

Tracing ------------~~~ Highest priority

Interrupts
Illegal instructions
(including invalid instructions - not implemented - as
well as codes $4AFA, $4AFB and $4AFC)
Privilege violation ... Lowest priori ty

Group 2
Group 2 has the lowest group priority. It consists of
instructions that eventually lead to a trap (exception)
like CHK and TRAPV.
Given that a single instruction cannot be executed
at once, and that recognition takes place during an
instruction cycle (3), no hierarchy is established
between the instructions of group 2. Table 4.2
summarises the three groups.
58 The 68000 Hardware and Software

Definitions

(1) Clock cycle

Clock period fed to the CLK input of the MC 68000.
(T = 125 ns for a frequency of 8 MHz and 100 ns for a
frequency of 10 MHz.)

(2) Bus cycle

Time sequence required to complete the following cycles

byte read or write

word read or write
read, modify or write (TAS instruction)

(3) Instruction cycle

Time sequence necessary to execute a 68000 instruction.

Exception Periods

Address error 50 (4/7)

Bus error 50 (4/7)
Interrupt 44 (5/3)*
Illegal instructions 34 (4/3)

Privileged instructions 34 (4/3)

Trace 34 (4/3)

*It is accepted that the interrupt recognition cycle

lasts four external clock periods. The numbers in
brackets after the period numbers are the numbers of
read and write bus cycles used in order to execute the
exception.

Example
Bus error 50 periods made up
of 4 read bus
cycles and 7 write
bus cycles.

TECHNICAL FILE

Parallel Interface/Timer MC 68230

The PI/T MC 68230 peripheral circuit is constructed
using HMOS technology and comes in a 48-pin plastic or
ceramic package. It is compatible with the MC 68000, MC
6809E and MC 6809.
A Motorola design, this circuit allows one to expand
considerably on both the hardware (number of circuits,
PIA, timer) and the software of applications as varied
as interfacing parallel printers, time measurement,
burglar alarms, and so on.
 Exception Procedures 59

Its asynchronous data bus 00-07 allows it to operate

at speeds (clock frequencies) greater or less than its
own, using bus master circuits such as the MC 68450
direct memory access controller.

DO-D7 PAQ-7

RS1·RS5 PBQ-7

RiW H1
H2
~
H3
MC68230 H4
PIIT
RESET PC71TIACK·
PC6/PIACK·
PC5/PIRO·
ClK PC4/DMAREO·
PC3lTour·
VCC
PC2ITIN·
GND PC1
PCO
* dual function lines

Figure 4.16 MC 68230 pin assignment

Pin Assignment
The MC 68230 has an asynchronous data bus (00-07), a
read/writ~ne (R/W)and a transfer recognition
output (OTACK). There are five register selection
lines (RSI-RS5) and one circuit selection line (CS).
There are two concatenable ports (PAO-PA7 and PBO-PB7),
a dual function port (PCO-PC7) consisting of the timer,
input, output and interrupt lines (TIN, TOUT and
TIACK~d the port interrupt lines (PlACK and PIRQ).
Finally, there is the direct memory access (OMAREQ) and
initialisation (RESET) line.
The PI/T MC 68230 has three 8-bit ports (A,B,C),
four handshake lines (HI-H4), a 24-bit timer and
vectored or autovectored interrupts. Note that the port
functions are independent of the timer functions.

The 25 registers that are programmable by the data

bus fix four operation modes at the port level.

8-bit unidirectional operation

l6-bit unidirectional operation (ports A,
PAO-PA7, and B, PBO-PB7, can be concatenated
to make a l6-bit port)
8-bit bidirectional operation
l6-bit bidirectional operation

Each port a has double buffer, consisting of two

8-bit static latches which, for example, allow the
60 The 68000 Hardware and Software

throughput to be increased for applications such as the

output of characters to a printer.
The direction of the port lines is fixed a) by
program in unidirectional mode (8 and 16), and b) by
pin HI in bidirectional mode (8 and 16).
Some of the lines of port C (PC2 to PC7) can be
individually programmed to fulfil the following roles

input timer (PC2/TIN)

Timer output timer (PC3/TOUT)
inter~recognition timer
(PC7/TIACK)

autovectored interrupt request

(PC5/PIRQ)
Ports port interrupt recognition
(PC6/PIACK)
direct memory acces request
(PC4/0MAREQ)

The PI/T 68230 timer, depending on how its control

register is programmed, allows a) interrupts to be
generated periodically, b) an interrupt to be generated
after a programmable delay, c) time elapsed to be
measured, and so on. To achieve this it has three
8-bit counter registers, each also assigned to three
8-bit preloading registers.
The timer uses as its time reference the PI/T clock
or an external clock fed to the timer input (TIN) with
the possibility of dividing the latter by 32 (five
prescale bits).

Table 4.3 68000/68008/68010/68020 Peripherals

(Motorola,Mostek,Philips,Signetics,Hitachi,Rockwell)

IPC 68120/1 DPLL 68459

BIM 68153 MPCC-2 68561
VME 68172 DUSCC 68562
VMS 68173 SIO 68564
VME 68174 LANCE 68590
Pl/T 68230 MPCC 68652
DDMA 68440 PGC1 68653
DMAC 68450 EPC1 68661
MMU 68451 DUART 68681
BAM 68452 FPCP 68881
lMDC 68454 MFP 68901
5 Addressing Modes of MC 68000,
MC 68008 and MC 6801 0

TYPES OF ADDRESS

The 68000 has 14 addressing modes grouped into the

following six categories.

Address Register Direct

Address Register Indirect
Absolute Address
Immediate Address
Relative Program Counter Address
Implicit Address

DEFINITION

Addressing mode is the name given to the different ways

that an instruction can access an address in order to
carry out an operation on it.

1 Address Register Direct

The direct addressing mode comprises two types

direct data register address EA On

(EA = Effective Address)
direct address register address EA An

Data Register Direct Address EA Dn

Example 5.1
MOVE.W DO,$lFFE

Source ---11 LOestination

Effective address Effective
address

61
62 The 68000 Hardware and Software

MP 68000 Workspace

1234 $ 1 FFE (and $ 1 FFF)

Source Destination
Role of the instruction
The instruction MOVE.W DO,$lFFE (or MOVE DO,$lFFE)
gives the order to the processor to transfer the 16 low
order bits of the data register DO to the destination
location $lFFE (and $lFFF).
Details
The size specified by the instruction can be

8-bit byte (MOVE.B DO,$lFFE)

16-bit word (MOVE.W DO,$lFFE)
32-bit long word (MOVE.L DO,$lFFE)

If however the size is a word or a long word, the

destination address can only be even. Only a byte size
allows the programmer to choose an even or an odd
address.

Address Register Direct Address : EA = An

a) The source is specified by the address register
Example 5.2
MOVE . ~v A2, $ 4 °°°
MP 68000 Workspace

1234 $ 4000 (and $ 4001)

Source Destination
 Addressing Modes of MC 68000, MC 68008 and MC 68010 63

Role of the instruction

The instruction MOVE.W A2,$4000 directs the CPU to
transfer the LSB word of the address register A2 (bits
o to 15) to the destination location $4000.
Details
The size specified by the instruction can be

8-bit byte (MOVE.B A2,$4000)

l6-bit word (MOVE.W A2,$4000)
32-bit long word (MOVE.L A2,$4000)

The removal of the contents of an address register

does not affect the condition code register (CCR).

b) The address register specifies the destination

Example 5.3
MOVEA.W $5000,A2

Source ~ \\-----Destination

MP 68000 Workspace

31 16 15 0
I FFFF I 8000 8000
t---- --....-t $ 5000 (and $ 5001)
t A2
I
32· bit
extension

Destination Source

Role of the instruction

The instruction MOVEA.W$5000,A2 (or MOVEA $5000,A2)
transfers the contents of the source address $5000 to
the destination location, that is, address register A2.

Details
The size specified by the instruction can be word or
long word.
When a register An is used as destination, the
transfer of an operand to it leads systematically to a
32-bit sign extension.
64 The 68000 Hardware and Software

Demonstration

) 2000
2000
*.

"' ~ :::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::-.:

: F~~ P C::: OO(),~()O .. OBOO ~~:::O S 000 C::: SP ::: 00000600

DO::: 00000000 D" ::: 00000000 I);~?:::: OOO()OOOO 0]::: OO()O()()OO
[).i;::: O()()OOOOO ()~=j::: 00000000 01;)::: OO()()OO()() D?::: OOOOO()OO
i~O::: 00000000 A'1::: 00000000 I~~~?:::: 00000000 I f~]::: OO()()OOOO
~~'I"":l:::: OOOOO()()O A~;j::: OOOOOOO() (.\6::: O()()()()()OO A7::: O()()()0600

~:.;OOO I]OOO··..I':lOOol storing data at address $5000

C:.,OOO liOOO--
• (.',? OO()(l()()()() _. FFFFFFFF
~ R PC::: OOOi,OO U 0000 ~):::O S 000 C::: sp::: OOoOO~:'O()
DO::: OOOOOOO() I)" :::: 00000000 D~.~::: OOO()OOOO DJ::: OOOO()()Of)
[).i:t : :: OO()()OnOO os- OOOOO()OO Db::: O()()(lO(lOO O?::: OO()OOOOO
(.'0::: 00000000 {~'I:: ()Ot')f)()OOO I(.'~-:?::: FFFFFFFF I i~::3::: OO(){)DOOO
(.,.. .;::: O()OOO()()() ~:l~:j::: OOO()()()()() A6::: OOOOO()()() A7::: OO()()()6()()

~~ooo; T .> "1

~:- lR(-\C PC::: ()O~.~()O/t tt I,F7"1 f;:::O~) 000 C::: ~)p::: OO()()()600
DO:: O()O()()()OO 1)'1:: ()OOJ]Of)O{) D~~::: OO()()()()()() IY3::: O{)OOI]()()()
D.ii::: OOOOO()OO O~):::: OO()()()()()() Ol:/:: OO()()()()()() D7::: OOOOOO()()
(-'0::: 00000000 ('~'I::: ()OOO()()()O I(.'~?::: ()()004000 I f~:3::: O()()()ODOO
~;\.i1::: OO()()()O()() ~~~)::: OOO()()()()O Ab::: O()()()O()()() {l7::: OOO()060()

'i(.

~: {~FTEf.~ EXECUTION::
~, :::::::::::::::::::::::::::::::::::::::::::::::::::::::::

~:,;OOO '1000-· eooo }

~:.;OOO 8000·..· storing data at address $5000
• f~2 :: 0000',000 .. contents of A2 before program execution
i(.

:t(. B[FORE [>::ECUTION::

-l(. :::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::

*2000;T }"1
TRAC PC= 002004 « ';£-:7'" S:::O ...C') ()OC) C::: SF'::: ()()()()()l>() 0
DO::: OO()()()O()() D'I::: 00000000 D~~::: ()()()() ()()()() 1)3::: ()()()(){)()()O
D.I-t:: O()()()()()()() os- O()()()()()O() D6:::: ()()()()()()()() D7::: ()()()()()()()()
t~()::: {)()OOOOOO A"I::: O()()()()O()O I
f'~":?::: FFFFBOOol A:3::: OO()(){)OOO
(.'14= ()()()()()()()() A~j:::: ()()()()()()()() (-l6:::: O()()()()O()() ~~7::: ()()()()O60()

* AFTER EXECUTION::
~,
* ::::::::::::::::::::::::::::::::::::::::::::::::::::::
*
 Addressing Modes of MC 68000, MC 68008 and MC 68010 65

2 Address Register Indirect

There are six types of indirect address mode, as set
out below.

Address Register Indirect

Address Register Indirect with Postincrement
Address Register Indirect with Predecrement
Address Register Indirect with Displacement
Address Register Indirect with Displacement
and Short Index
Address Register Indirect with Displacement
and Long Index

Address Register Indirect

EA = (An)

Example 5.4
MOVE (Al) ,01

Source _-_I \----Destination

MP 68000 Workspace

ABeD $ 2000
(and $ 2001)
0000 2000
A1

Role of the instruction

The instruction MOVE (Al),Dl or MOVE.W (Al),Dl informs
the CPU that the operand to be transferred to the
destination register 01 is located at the address
pointed to by the source register AI.

Details
The size specified by the instruction can be byte, word
or long word. However, if the size is word or long
word, the address register indirect must point to an
exclusively even address. If this rule is not
respected, an exception rerouteing called an illegal
address will occur.
Generally speaking, these details will apply
whatever the type of indirect address.
66 The 68000 Hardware and Software

Address Register Indirect with Postincrement

EA = (An)+

5L
Example 5.5
MOVE.W

Instruction source
Size
J (A5\) + , $

_.--------Source
Destination

MP 68000 Workspace

Before
00002000 I ABCD
t--------4
$ 5000 (and $ 5001)
AS

After
0000 2002 I Source ~----f
ABCD $ 2000 (and $ 2001)
AS

Role of the instruction

The instruction MOVE.W (A5)+,$5000 (or MOVE (A5)+,
$5000) transfers the contents of the address specified
by the address register AS to the destination location
$5000. Address register AS is then incremented by two.
Details
The address register used as indirection must without
fail point to an even address, when the size specified
by the instruction is word or long word. On the other
hand, if the size is byte, the address pointed to can
be even or odd.
When requested with postincrement, the content of
the address register is incremented by one, two or
four, depending on whether the size specified is byte,
word or long word. If the address register is the stack
pointer and the size is byte, the increment of the
stack pointer is two and not one.

Address Register Indirect with Predecrement

EA = -(An)

Example 5.6

--1 ! ,
MOVE.W -(A5),$5000

Instruction source
Size ..
L Destination
Source
 Addressing Modes of MC 68000, MC 68008 and MC 68010 67

MP 68000 Workspace

I nitial status of A5
31 1615 0
I 0000 I 2002 I 1234
t------4
$ 5000
(and $ 5001 )
A5

Before processing
I 0000 2000 1234
A5

Role of the instruction

Once the effective address is obtained, and after the
address register AS is decremented by two, the contents
of the address pointed to by AS is transferred to the
destination location.

Details
The size specified by the instruction can be byte, word
or long word. If the address register used as
indirection is the stack pointer, and if the size is
byte, the register An is always decremented by two in
order to keep the size to word.

Address Register Indirect with Displacement

EA = (An) + dl6

Example 5.7
MOVE.L $5000(AI),D5

16-bit signed
displacement
~
Source
Register (An)

Destination

Role of the instruction

The instruction MOVE.L $5000(AI),D5 loads the 32 bits
of destination register D5 with the contents of the
effective address, whose value is equal to the sum of
the contents of address register Al and the signed
16-bit displacement $5000.
68 The 68000 Hardware and Software

MP 68000 Workspace

31 16 15 0
11234156781
05

1 2
34
56
0000 2000 78
A1

Destination Source

Calculation of effective address (EA)

Al ~ 0000 2000
+
16-bit signed ---.- 0000 5000
displacement
with 32-bit
extension
0000 7000
Details
For a word or long word operation, the effective
address must be even. However, for a byte size the
effective address can be even or odd.

Address Register Indirect with a-bit Signed

Displacement and Short Index

EA = (An) + (Xi.W) + d8

Example 5.8
MOVE.W $08 (A2,D3.W), DO

---I
l l
Instruction ----l l

Size

8-bit signed
displacement

Register An

Register xi

Index size

Destination
 Addressing Modes of MC 68000, MC 68008 and MC 68010 69

MP68000 Workspace

Destination

unaffected
31 1615 0
I 0000 I 3000 I
03
~ ..--A_B ~ $ 4008
31 1615 0 Source l..--C_D ~ $ 4009
I 0000 1000 I
A2

* I N~)TI~UCT ION = r~O'·,.IE. ~'" $OB (f~';!, D::~:. ~,J) DO : OP CODE ;

'! ~<-}O:-};.) 300B
'* :::::::::::::::::::::::::::::::::::
*
2 000 :~',7B-- ::~:o::~;! ~:;OO()·_· 30()~~ ';E7"I-- } loading of program
;~O()O :-}O:-};.~-- 30()E}·· 4£-:7'1·-
~:

:t: BEFORE E):ECUTION~

~. :::::::::::::::::::::::::::::::::::::::::::::::::::::::
~ p p C:::: O()~~()O'; 4. i.E?··1 S:::O s O()C) C::: ~:;p::: O()()O(){)()O
1150:: D(j(j(jDOOol I)'" ::: 00000000 D:~?::: OOO()()I]()() IIx§::: OO()OD(JOO I
0.11 : :: O()O()()()()() [)~:.i:::: O()()()()()()() D6::: ()()O()()()()() D7::: 0001]0000
(.~O:;: OO()()()()()I] (.~.,;;: O()O()()()()() IH;~~::: ,··1- F' f· BOOO I t~::3::: OOO{)()()OO
{I.I,::: OO()()OOOO (.'I~j::: O()O()()()()() A6:-.:: ()()()()OO()() tl7 ::: O()()()060()

. D3 ()()()()OO()()·- :3000..- contents of D3

• f~~~ FFFFBO()() ·-·1()OO~contents of A2
> ~.

PC::: OO~~O()4 ',[7'1 S::::() S 000 Sp::: ()()()()() so()

••
f':::

IDO::: OO()()()()()() I D'I::: O()()()()O()() D2::: O()O()OO()() 10:]::: ()O()()~3()OO I

1).<;:: O()()OOOOO [)~):::: o ()()()()o()() D6:::: O()()O()()()() D7::: ()()()()O()()O
{~O::: 00000000 I~'I :::: O()()()OO()O I~)~?::: OOO()'·' DOD I iY3::: O()()()()DO()
~~\"1::: OOO()()O()() (~~:j:::: O()()OO()()() (~6::: O()()()()OO() {~7::: OO()OOt.iOO

) 4:.

I~ nOB O()~~{~~- {'IBCD ~~---- contents of source address

~

2000~ T )'1
il:· rR~:,C PC:;: O()~.~()O" •• i,E?"'1 ~):::O~) 000 1"::.: • N. •• ~)p::: O()()OO{.()()
DO:= C;!)OO(.'BCD D" ::: ()()OOOOI]O D~?:::: OI]O()()OOO 1)::3::: 0()OO~3()()D
[).<i::: OO()()OOOO [)~.;::: OOO()()()OO Dl,::: OOO()()O()O [) 7 ::: OOO()OO()O
{~() :: I]() () () I]()()0 (.\"1 ::: () oo()() 0 0 () A:~~ ::: 0 ()()()"1 ()()() (.) ::3 ::: I] () () () DOD0
f~·IL~:-.:: 00000000 (~~:;::: OOOOOO()O ~~ ~.) :::: ()()()()OO ()() rl 7 :::: 00000600

~------Destination

~:. ~'~ F TFr·;: E XECU r I ON:

':> ~. ::::::::::::::::::::::::::::::::::::::::::::::::::::::

Role of the instruction

The instruction ~10VE.W $08(A2,D3),DO .i n st r uc t s the
processor to transfer the contents of the effective
address (source) to the destination register DO.
70 The 68000 Hardware and Software

Calculation of effective address

EA = (An) + (Xi.W) + 8-bit sign-extended
displacement
where
An represents an address register
Xi determines the index register which can be a data
register or an address register
xi.w means that when the size if the index register is
word, there is 32-bit signed extension when EA is
calculated.

The source effective address is therefore

Address register (An) 1000

+
Index register (Xi.W) 0000 3000
with extension
+
8-bit sign-extended (d8 ) 0000 0008
displacement
EA 0000 4008

Details
See address register indirect with displacement.

Address Register Indirect with 8-bit

Signed Displacement and Long Index

EA = (An) + (Xi.L) + d8

Example 5.9

MOVE.W $08 (A2,D3.L),DO

Instruction ~
Size

8-bit signed
displacement

Register An

Register xi

Index size

Destination
 Addressing Modes of MC 68000, MC 68008 and MC 68010 71

MP 68000 Workspace

unaffected
31 1615 0
I 0001 I 0000 I
03
61
31 1615 0 00
0000 I 2000 I
A2

Destination Source

~.

..
i(.

~
I t-t::;TPUCTION::
::::::::::::::::::::::::::::::::::::::::
~;O'-.JE.l·1 "OB(A~?:oD:~.L) :rOO

~?OOO 0',f-\0···30::-::;.:: OAOB·- ::~~~OB 0'1 ;,~()···,(:'E7·1 }

;.~OOO "30:~~,~-" 3HOO··.. ',E7"\-- loading of program
4:
*. BEFOPE E:~<ECUTION
4:. :::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::

~ p PC::: OOO"t()() 4t ',BOC) S::() S 000 C::: Sf-':: ()O()006()O

I DO::: O()OODOOO I D'" ::: O()O()()O()() ,):~~:: ()()()()()()()O ID~3::: o{joo(j(j(jo I
[),(t::: ()()() 0 oDOC) D ~:.i:::: ()() OO() D() 0 {)6 ::: O()()() () O()(} [) 7::: ()(}()O ()O ()O
I~O::: OO()()()()()() ?\., :::: ()O()()()OD() IA:~~::: OOO(j(j(jO() I A~3:: ()()()()()C)()()
f.),(,:: OOO()()()()C) I'~.:;::: ()()O()()()()() A6::: O()()()()()(}O (:-,7::: O()()()O{)O(}

.D3 O()()()O()(}O ·-'1 DOOO ....--loading of D3 ------------t

• ~i;.~ ()()()()O()OO -- O~.~()()O .--loading of A2- - - -
''1FOOH
* 6'100'·' contents of source
;R PC::: OOD'tO() «',B()O B:::() S O()() C:::
DO:: OO()(){)()()O D'" ::: ()()()O()()O() D~?::: ()()()()()()()()
[),(t::: ()(}()()()(}(}() os- ()O()()()()O() D6::: ()()()()()()()O
AD:: O()()()()()()() A"'::: ()OOO()()()O ( , ..':... ,
t,,,,;::: 0 o()()()()()() A~,:;::: ()()()()()()OO Ab:::: ()(}()()()()()()

20()(), T >'1
~. lR AC P c:= O()~,~()()'; tt 'tE7 '1 S:::() S O()() C::: Sp:::: O()()()06()()
DO::: ()()()()6'" 00 D'1::: (){)OOOOOO ()OO()()()()()
D:~?::: D~~::: O()()··, DO()O
D.lt ::: O()OO()()()() os- (}()()()()()()() Db::: ()O()()()O()() D7::: ()()()()()()()()

L
A()::: ()()()()()()()() A'I::: O{)()()OO()() (.\:~~::: O()()()~?O()() A~3::: ()()(){)O(JO()
M= 00000000 A5= 00000000 Ab=' O()OOOOOO A7= 00000600
the contents of DO.W have been loaded with the contents of addresses
: AFTER EXECUTION $1F008 and $1F009
* :::::::::::::::::::::::::::::::::::::::::::::::::::::
*

Role of the instruction

The instruction MOVE.W $08(A2,03.L),00 instructs the
CPU to transfer the contents of the effective address
(source) to the destination register DO.
72 The 68000 Hardware and Software

Calculation of effective address

EA = (An) + (Xi.L) + 8-bit sign-extended displacement

which gives

Address register (An) xxxx 2000

+
Index register (Xi.L) 0001 0000
+
8-bit sign-extended 0000 0008
displacement -----
EA = 0001 F008

Note that this addressing mode is equivalent to the

record type in Pascal, since it allows addressing by
base limit.

Absolute Address
There are two types of absolute address

absolute short address EA l6-bit address

absolute long address EA 24-bit address

Absolute Short Address: EA = l6-bit address

Example 5.10

MOVE.W $2000,$5000
or

\
MOVE $2000,$5000

Source __________~t Destination

MP 68000 Workspace

Destination 12
AS

12
Source
AS

Role of the instruction

The instruction MOVE.W $2000,$5000 tells the CPU to
transfer the contents of the source address ($2000 and
$2001) to the destination address ($5000 and $5001).
 Addressing Modes of MC 68000, MC 68008 and MC 68010 73

This instruction is especially interesting since it

allows a movement from memory to memory without passing
through a working register of the control unit.

Details
The size specified by the instruction can be

8-bit byte with EA = even or odd

l6-bit word with EA = exclusively even
32-bit long word with EA = exclusively even

Absolute Long Address : EA = 24-bit address

Example 5.11

! ,'----------:~~~~~~
NOT.B $F400l

Instruction - - - - - - - -
Si ze f__ ve

MP 68000 Workspace

......,. ~ $ OF 4001

...... ..... Before instruction After instruction

Role of the instruction

The instruction NOT.B $OF4001 carries out a one's

complement on the contents of the effective address
$OF400l.
This type of address allows access to a memory
position beyond 64K.

Details
The size specified by the instruction must be

byte for an even or odd effective address

word for an even effective address
long word for an even effective address.
74 The 68000 Hardware and Software

4 Immediate Address
The immediate address mode allows an operand (data
item), whether 8, 16 or 32 bits, to be sent to one of
the following
data register
address register
memory location

Immediate Address with Address Register Destination

Example 5.12

MOVEA.W #$2000,A5
or
MOVEA #2000,A5

I I
31 16 15 0

I 0000 2000 AS

3~
extension # $ 2000
J
The above instruction loads address register AS with
the immediate value #$2000.

Details
1. There is always a 32-bit extension when the
destination is an address register (for a 16-bit source
or da ta item).
2. The size specified by the instruction can only be
word or long word. Byte is forbidden.

Example 5.13

1. MOVE #$8000,A5

1- Sign bit is
negative

31 16 15 0

I FFFF
I 8000
I
/
32-bit extension # $ 8oo0 J
 Addressing Modes of MC 68000, MC 68008 and MC 68010 75

2.MOVE.B #$80,A5 This is forbidden.

Immediate Address with Data Register Destination

Example 5.14

MOVE.B #$6A,02

Oper and ---l t

Destination ~

I I I
31 16 15 87 0

XXXX XX 6A 02

~)
# $ 6A

The instruction MOVE #$6A,02 loads data register 02

with operand #$6A. (Note that the # indicates the
mode. )

Details
1. The size specified by the instruction can be

Byte MOVE.B #$80,02

Word MOVE #$8000,02
Long word MOVE.L #$FFFFFFFF,02

2. There is no bit extension when the size stipulates a

byte or a word.

Immediate Rapid Address with Data Register Destination

(MOVEQ instruction only)

Example 5.15

MOVEQ #$6A,04

This l6-bit instruction loads destination register

04 with operand #$6A.

0000

)
32-bit signed
extension
76 The 68000 Hardware and Software

Details of MOVEQ
1. The destination is always a data register.
2. The size can only be byte.
3. There is 32-bit sign extension (the only occurrence
of sign extension on a data register).

Special note
The instructions AOOQ and SUBQ specify a 3-bit operand
whose different combinations code values lying between
1 and 8 inclusive.
000 represents value 8; 001 value 1; 010 value 2,
and so on, with III representing value 7.

Simulation

Case 1 : Positive operand

786A MOVEQ #$6A,04

~,

~ r N~rn~UCT I ON:: MO~."F(~ *t <;l;i!':.(', D',

'!

~, ::::::::::::::::::::::::::::::::::::
~.

;~O()() 30:~~,~"- -:l::;:b(" }

;~ooo ?H6r,··· loading of program
:11:

~ BEF()PE EXECUTION
'* ::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
~:

PC:;: oo~~ ()()" *. '.E 7 '1 ~~ :::: () S ()()() C::; SP ::: OO()()()600
DO::: ()()()Of,~>"'1 ()O D"::: O()()()()()()O D;.~::: ()()OO()()OO D~3::: O()()"J DOOO
I Doli:: OO()()()()()() I [)~:;::: ouoooono Dt,::: OOOO()(}(}(} [) 7::: ()()()(}()(}()()
(~o::: ()()O()()()OO I~~'" :::O{)OOO()()() A:2::: ()()()():;~()()() (.':3::: O()()()OOOO
{i.fi:::: ()O()()()()OO {:\~5::: ()()()()()()(}() A6::: O()()()()()()() ~~ 7 ::: ()()()()06()()

;.~O()() ; T ) '1
-:0:. TRAe PC::: 0 () ~.~ 0 () ~~ ..'tE 7 '1 s :::o s ()()() C::: sp::: O()()()060()
D()::: ()()()()(~d 00 D"'::
O()()O()O()() D~~::: ()()()()()()O() D~3:: 000'1 DODO
I[)"',:"_-: O()()()()()f.:.F\ I [)~;::: ()()()()()()()() DtJ::: ()()()()()()()O [) 7 ::; 00000000
(.)() ::: ()0 () () (1() o o A'" = o()ooo0 () o o()
A :-:~ :::: 00 ()0 ~~ 0 (-\:3::: O()(){)OOOO
t.iJ::: ()()()()()()()() A~:i:::: ()()OO()()O() A6:::: OO()()O()()O (.\7::: ()O()()Ot,()()

> :11:

> * AFTER EXECUTION

~. :::::::::::::::::::::::::::::::::::::::::::::::::

) *

Case 2 Negative operand

7880 MOVEQ #$80,04

 Addressing Modes of MC 68000, MC 68008 and MC 68010 77

oJ:
* IN~:)TRUCTION:; MOl~JE(~ "~;,fiO ,Dol;
* ~::::::::::::::::::::::::::::::::::::::

*
2()()() 7El6Ao--7BElO 4E7 1-- } loading 0
of program

** BEFOF<E EXECUT ION

~. ::::::::::::::::::::::::::::::::::::::::::::::::::::::::::

> ~.
PC::: () 0 ~~ o()~? 4t Lt E 7 ." S:::() S ()() () C::: SF' :::: O()O()()6()()
DO::: nO()06" no I)'.'::: nnoooooo I):~~:::: O()()(){)()()O D]::: ()()()'1 DODO
I[).fi::: I
AD:::
{jLot:::
()()()()()()t)A
on()()I]()()O
OO()()()()()()
f'", : : ()()()()()()()()
[)~:j::

A~,i::::
()()()()()()()()

O()()()()O()()
[)l'):::
A~~:::
(~6::::
()()()()()()()()
()()()();:~()()O
()()()()()()()()
[) 7:::
A:3:::
O()()O()()O()
()()()()O()()()
A7 ::: OO()()()6()()

) ;,) noo 1 T >'1

.~: lR ~~c PC::: O()~~()()~,~ .. ',E7'1 S::::() S O()() C:: • N. • • sp:::: ()O()OOt,()()
DO:: OO()()6 ", ()O I)'" == O()()()()OO() D:~~ :::: ()()()()()()()() 'Y3::: ()()()"II)() ()O
11)'(1:: F FF F FF BO I [)~:,i:::: O()()()()()()O D6:::: ()()()()()()()() [) 7::: ()()()()()()()()
(~():::: ()()()()()()()f.) A'1::: ()()()()()O()() (.~~7?::: n()()()~?()()() A:3== ()()()()OOO()
{i4::: O()()()()()()O A~):::: O()()()()()()() At.::: O()()()()()()() A7:: OOO()()C)()()

** AFTEI~ EXECUT ION

) * :::::::::::::::::::::::::::::::::::::::::::::::::::::
) ~:'

Immediate Address with Memory Location Destination

Example

ADDI.B #$80,$4000

The above instruction tells the processor to add

operand #$80 to the contents of destination address
$4000, then store the result in destination address
$4000.

Example 5.16

#$80 + 1 2 0 ........1 $4000 -> A 0 $4000

5 Address Relative to Program Counter

This address mode consists of two types

program counter with displacement

program counter with index

Basis
The value contained in the program counter (PC) is used
to calculate the effective address for instruction
handling, with the knowledge that the PC value is equal
to the current instruction address +2.
All instructions using relative program counter
addressing must be written in a section of program
called RORG. This special feature allows position
independent programs to be written.
78 The 68000 Hardware and Software

Program Counter Address with Displacement

Example
In the following we shall examine some program
instructions defined in a RORG section.

/)() 00OO2()OO I~ ORG $;'~Of)O

E~() 000-1 ['lIB OUlME.S [QLJ 1;'1l:"17EJ

90 DOO()OO" B VECrCHK EQU $"'8
'100 O(JO-l [~~rE MONIT E.QlI 1)'1 E~)I-'F
"'10 OOOO{)OO5 NUMOER E~U S

-1~~) oozoon I.FFAOOI)A LE:A ~ :Bc~., SF'

"f Ita 00200'. 4'1 FA()()-l [ LEA rt~APCHK , AD
-1 ~:-,() onaoon ;~'1 COOO'18 MOVCA.L AD 7 VEe', CHK
-lbO oo:·?OOC 4:~FA()()CE LEA fABLE, A"
'170 O()~~O-1 () 7~~O5 MOVl::G .. NuMBER, D'l
'180 OO~?O'12 ()C~j')OOlJF LOOP Cf,lP I. W tt$OlJor·· , ( A" J .+
'1<;'0 O()~~O'16 57C9FFT r~ DBLG D'l,LOOP
:'=~()O OO:,:~()-l A It3B C{)O{)~) CHK "NUHBI:R, I)"
;."10 O()~~O-l E I.EF9000-1 E ~~F E Jl-1F' MOI-lI'l
2:~{) ~

~_~:10 ()O()();!(J~~ I, ll~~ ~PCH'< EQU .)(.

;~/tO O(J20~/, I,BE·7 /.O'.O MOl..JFM.l D"1 / A'l

7 -. ( Sp )

zso OO:,:~O~~(3 4'1 FAnOOE LFA NESSA(J[ , ()O

;.'60 ()();.~02C I,EB (lOOO"1 F'178 J~:;I~ OUTrH:.~~
270 (J()::~() 3 :-~ 4C()f:'O:?U;~) MOVLi'1. L ( GP ) ->- r [)., / A '1
;.~HO OO~~{)~16 1.1·.:l:J 1·:lF: Lt or n
I~~
:-?'JO .)(

~~OO ()O~?()38 ;.~C.I r1ESSAGE DC.L: '..·'(,)I..UE NO

~3 '1() On:;~I)/i~-2 0-', DI.= .8 Oft
~;~~O 00-;;'>06 1, OOOO()07H D~~ .1. 3U
]:)() o()()() :,~ 0 D I ~ :~.l"'J~ )( E(~U
*
~J40 oozouc (\O(IO()()(){~ 1 (~BLt:· DS.lr.. 1
:350 ENL'

1. The instruction LEA TRAPCHK,AO located at address

$2004, gives the order to the processor to load
register AO with the effective address specified by the
label TRAPCHK which is positioned at address $2024
(LEA = Load Effective Address).

Calculation of effective address

Formula EA (PC) + d 16

l ! ~
v..
giving
2024 (2004 + 2) + 00 1 E

TRAPCHK
/ Program
!
Label address counter +2 displacement
shown by op-code
(2024 - 20006 = 00 1 E)
 Addressing Modes of MC 68000, MC 68008 and MC 68010 79

Table 5.1 Summary of Addressing Modes

Mode Notation Operation

Data register On EA = On
direct

Address register An EA An
direct

Address register (An) EA (An)

indirect

Address register EA = (An) then

indirect with (An)+ An := An + 1,2 or 4
postincrement depending on size
of 1,2 or 4

Address register An := An - 1,2 or 4

indirect with -(An) depending on size,
predecrement then EA = (An)
of 1,2 or 4

Address register (An) + d16 EA = (An) + 16-bit

indirect with sign extended
displacement displacement

Address register EA =(An) + (Xi.w)

indirect with (An,Xi) + d8 with 8-bit
displacement/index sign extended
displacement

Address register EA = (An) + (Xi.L)

indirect with (An,Xi.L) d8 with 8-bit
displacement sign extended
and long index displacement

Absolute short Addr 16 EA = (addr 16)

address

Absolute long Addr 24 EA (addr 24)

address

Immediate address # data data item

Relative program
counter address raddr 16 EA (PC) + d 16
with displacement

Relative program
counter address raddr 8 (Xi) EA (PC) + (Xi) + d 8
with displacement
and index

Implicit address EA SR,USP,SP,PC

80 The 68000 Hardware and Software

2. The instruction LEA TABLE, Al located at address

$200C suggests the same handling as before, that is,
loading address register Al with the effective address
defined by the label TABLE.

Calculation of the effective address

Formula EA (PC) + d 16

~ ~ +
-:
20DC (200C + 2) + 00 CE
-,
TABLE
Label address
Program
•
counter +2
Relative
displacement
shown by op-code
(20 DC - 200 E)

Program Counter Address with Index

The basis of operation is the same as for program
counter with displacement except that for calculation
of the effective address an index register has to be
taken into account.

Formula
EA = (PC) + (Xi.W) + d8
or

»> -,
EA = (PC) + (Xi.L) + d8

Current value
t
Index register, 8-bit signed
of PC + 2 a 16 or 32-bit displacement
data or address
register

Implicit Address
Table 5.2 lists the instructions that make implicit
reference to the following

program counter (JMP, BRA)

user stack pointer (MOVE USP)
supervisor stack pointer (TRAP, DIV)
status register (RTE, RTR).
 Addressing Modes of MC 68000, MC 68008 and MC 68010 81

Table 5.2
Instruction Implied registers

Branch conditional (Bcc),

branch always (BRA) PC
Branch to subroutine (BSR) PC, SP
Check register against
bounds (CHK) SSP, SR
Test condition, decrement
and branch (DBcc) PC
Signed division (DIVS) SSP, SR
Unsigned division (DIVU) SSP, SR
Jump (JMP) PC
Jump to subroutine (JSR) PC, SP
Link and allocate (LINK) SP
Move condition codes (MOVE CCR) SR
Move status register (MOVE SR) SR
Move user stack
pointer (MOVE USP) USP
Push effective address (PEA) SP
Return from excEption (RTE) PC, SP, SR
Return and restore
condition codes (RTR) PC, SP, SR
Return from subroutine (RTS) PC, SP
Trap (TRAP) SSP, SR
Trap on overflow (TRAPV) SSP, SR
Unlink (UNLK) SP

Each 68000 instruction can be broken down into

several microinstructions. An example is given below.

MOVE.W -(An),-(Am)

Microinstruction 1 Calcu ates source

effective address
(An-2), since word is
the size specified.
Retrieval of the op-code
of next instruction to be
executed (Prefetch)

Microinstruction 2

Microinstruction 3
6 68000 I nstruction Set

DETAILS AND PROGRAMMING

Motorola deliberately restricted the instruction set of

the 16-bit MC 68000 (~nd 68008) microprocessors to 56
instructions that offer extreme flexibility. (Note that
the newer 16/32-bit MC 68010 has 57 types of
instruction.)
Even if this number appears small (although
programmers will probably not complain), some
instructions offer several thousand combinations
because of the different address modes available and
the type of data that they can manipulate.
The five basic data types are

bit
BCD digit (4 bits)
byte (8 bits)
word (16 bits)
long word (32 bits)

The 68000 instructions operate on byte, word and/or

long word, which in assembly language need to be
specified by .B, .W and .L. If the size is word, the
suffix .W is assumed by default.

Example
MOVE.B Source, destination
MOVE.W Source, destination
or MOVE Source, destination
MOVE.L Source, destination

82
 68000 Instruction Set 83

The operation code (op-code) of all the 68000

instructions is fixed in 16 bits (word), but an
extension is required when the specified address mode
uses constants, absolute addresses or displacements.
As a consequence, a 68000 instruction can be coded
in from one to five words (2 to 10 bytes).
We have arbitrarily classified the 56 instructions
into three categories: me~ory reference and special,
arithmetical and logical, and program control
instructions (see also appendixes 1 to 8).
In what follows we shall not be studying in detail
all 56 of the 68000 instructions; we shall confine our
examination to those that do not have an approximate
8-bit equivalent. The reader is advised to study the
three types of flowchart shown in figure 6.1, as well
as the 68000 assembler directives listed in tables 6.1
and 6.2, in order to be able to follow the discussion
of this chapter without difficulty.

Iteration with test Iteration with test

before action after action

In pseudo-code In pseudo-code

I
WHILE CONDITION TRUE
ACTION
REPEAT
I ACTION
UNTIL condition TRUE
END
Selection

In pseudo-code
IF condition TRUE THEN
IACTIONl
ELSE
IACTION2
END

Figure 6.1
84 The 68000 Hardware and Software

Table 6.1 68000 Assembler Directives

Directives Examples Role

ORG ORG $4000 Origin in absolute

short of program
ORG.L ORG.L $40000 Origin in absolute
long of program
RORG RORG 0 Relative origin
RORG $1000 of program

BASE EQU $1000

EQU PIACA EQU BASE + 1 Symbol equivalence up
LF EQU $OA to 32 bits maximum

SET BASE SET BASE-l Temporarily fixes the

value of a symbol

DC.B TEXT DC.B "HELLO" Byte constants stored at

LFCR DC.B $OA,$OD successive addresses

DC.W WRITE DC.W $FOOO,TAB Word constants stored at

DISPLAY DC.W-3000,SET successive addresses

DC.L VAUE DC.L $ABCDFFFF Long word constants stored

LINE DC.L VALUE +3 at successive addresses

DS.B STACK DS.B 20 Reserve memory (bytes)

DS.W BUFFER DS.W 2 Reserve memory (words)
DS.L TEXT DS.L 3 Reserve memory (long words)
END END End of assembly directive
MACRO CALCULATE MACRO Definition of Macro
CALl,CAL2 instruction
ENDM ENDM End of Macro

Table 6.2 68000 Assembler Directives

Directives Examples Role

LLEN LLEN 120 Fixes number of characters

per line (here 120)
PLEN PLEN 40 Fixes number of lines
per page (here 40)
NOOBJ NOOBJ No object output

IFEQ MULTI EQUO Conditional assembly

IFEQ MULTI Assembles if equal to 0
 68000 Instruction Set 85

IFNE MULT2 EQUI Conditional assembly

IFNE MULT2 Assembles if different

ENDC ENDC End of conditional assembly

SPC SPC 6 Line space
TTL TTL MP 68000 Program title. Source
with 60 characters max.

Memory Reference and Special Instructions

Table 6.3 lists these instructions.

Loading Instructions
LEA and PEA cause a pointer to be initialised (LEA
Src,An means An := effective address) and saved to the
stack (PEA Src means Src = effective address -) -(SP)).
These two instructions, which share the same
addressing modes, are to some extent complementary.

Table 6.3 Memory Reference and Special Instructions

Mnemonic Operand Size Notes Description

LEA Src,An L 1 Load An with Src

PEA Src L Save Src -) -(SP)
MOVE Src,Dst L,W,B Copy Src -) Dst
MOVEP On,Src L, ~v 2 Store Sn -) Dst
MOVEP Dst,Dn L,W 2 Load On with Dst
MOVEM Regs,Dst L,W 3,4 Store Regs - ) Dst
MOVEM Src,Regs L,W 1,3,5 Load Src -) Regs

BSET Numb,Dst B,L 7,8 Tests Numb and sets

BCLR Numb,Dst B,L 7,8 Tests Numb and
clears
BCRG Numb,Dst B,L 7,8 Tests Numb and
changes
BTST Numb,Dst B,L 7,8 Tests Numb in Dst

CMPM Src,Dst L,W,B 9 Dst-Src; CCR set

CMP Src,Dst L,W,B 10 Dst-Src; CCRset
CMPI Src,Dst L,W,B 10 Dst-Src; CCR set
CHK Src,Dn W 7 If On < o or On )
Src - ) TRAP
TAS Ost B 7 If Dst MSB 0 then
MSB = 1
CLR Dst L,W,B 11 Clears Dst
TST Dst L,W,B 11 Z and N set
according to Ost
86 The 68000 Hardware and Software

Special instructions

SWAP Dn L Exchanges word MSB

with word LSB
EXT Dn L,W Extends sign
EXG Xn,Xm L Exchanges Xn with Xm

Src Source W Word

Dst Destination B Byte
Numb Bit number Dn Data registers
Regs Registers Xn Data or address registers
L Long word Xm Data or address registers

(1) Src can only use addressing modes

(An),d(An),d(An,Xi),ABS.W,ABS.L,d(PC),d(PC,Xi)
(2) Src and Dst can only use addressing mode d(An)
(3) AO-A5/DI-D5 is equivalent to
AO/Al/A2/A3/A4/A5/Dl/D2/D3/D4/D5
AO/A3/A6/Dl-D3 is equivalent to AO/A3/A6/Dl/D2/D3
(4) Dst can use the following addressing modes
(An),-(An),d(An),d(An,Xi),ABS.W,ABS.L
(5) Src can use the following addressing modes
(An),(An)+,d(An),d(An,Xi),ABS.W,ABS.L,d(PC),d(PC,Xi)
(6) Src and Dst use addressing modes Dn and -(An)
(7) Src and Dst cannot be An registers
(8) Numb can be an operand between 1 and 8 or the
contents of Dn register in 32 bits
(9) Src and Dst can only be (An)+
(10) For CMP, Dst can only be a Dn register.
Memory/memory comparison only possible with (9). For
CMPI, Src can only be an operand
(11) Src and Dst cannot be An registers.

The MOVE instruction, which is the most flexible of

the 56, can be selected in 12 288 different ways. It
would be wrong to conclude from this that the structure
of the 68000 is general purpose, but it should be noted
that the following movements are possible with this
instruction: memory to memory, memory to register,
register to memory, operand to memory.
The MOVEP instruction is particularly suitable for
programming peripheral circuits that occupy an
alternate memory field, or are in other words
addressable either via the lower line (odd address) or
via the upper jline (even address).
The two versions of the MOVEM instruction (load and
store) are designed to move, in a predetermined order,
a list of address or data registers from or to a block
of memory.
 68000 Instruction Set 87

Bit Manipulation Instructions

The second group of table 6.3 comprises four bit
manipulation instructions. For example, a bit can be
tested, then set to 1 (BSET) or to 0 (BCLR); it can
also be changed (BCRG), or simply tested to establish
its state (BTST). The bit number can be specified as
static and immediate (modulo 8), or dynamically by the
contents of a Dn register (modulo 32).

Comparison Instructions
The first two instructions of the third group are
concerned with comparisons. This is one area where the
instructions set could be criticised. In fact, the
memory to memory comparison (CMPM) is only possible
with a source and destination having the addressing
mode (An)+. As for the CMP instruction, the source can
only be a Dn register. Finally, CMPI compares the
destination with the source specified as immediate.
(CMPI # Immediate, Dst.)
The CHK instruction compares the word LSB of a
register Dn with a bounded value, where the lower bound
is 0 and the upper bound is a 16-bit signed operand. If
the word LSB does not belong to the interval, the
processor is rerouted to the exception procedure
TRAPCHK whose vector number is $6.
The TAS (test and set) instruction allows management
of a resource that can be shared by several processors,
since during a single bus cycle it executes the
reading, testing and finally modifying of a destination
byte (memory or register) called a semaphore.
The next two instructions, CLR and TST, present
little difficulty, save for the fact that the
destination cannot be an An register.

Special Instructions
The fourth and last group in this category only affect
An and On registers. The instruction SWAP exchanges
bits 0-15 of a Dn register with bits 16-31. EXT carries
out a signed l6-bit or 32-bit extension in a Dn
register.
The last of the special instructions, EXG, instructs
the 68000 to exchange the 32 bits of a source register
with the 32 bits of a destination register (register =
An and/or Dn ) ,

Arithmetic and Logical Instructions

There are 34 arithmetic and logical instructions. They
can be divided into four types: addition, subtraction
and complementation; multiplication and division;
logical instructions; shifts and rotations. Table 6.4
lists the various instructions in this category.
88 The 68000 Hardware and Software

Table 6.4 Arithmetic and Logical Instructions,

Shifts and Rotations
Mnemon Operand Size Notes Description

ADDI Imm,Dst B,W,L 1 Dest + operand -> Dst

SUBI Imm,Dst B,W,L 1 Dest - operand -> Dst
ADDQ Imm,Dst B,W,L 1 Dest + operand -> Dst
SUBQ Imm,Dst B,W,L 1 Dest - operand -> Dst
ADD Src,Dst B,W,L 1 Dest + source -> Dst
SUB Src,Dst B,W,L 1 Dest - source -> Dst
ADDA An,Src W,L 1 An + source -> An
SUBA An,Src W,L 1 An - source -> An
ADDX Src,Dst B,W,L 2 Dest + srce + X -> Dst
SUBX Src,Dst B,W,L 2 Dest - srce - X -> Dst
ABCD Src,Dst B 2 Dst(lO) + srce(lO) + X
-> Dst
SBCD Src,Dst B 2 Dst(lO) - srce(lO) - X
-> Dst
NBCD Dst B 3 O-Dst(lO) - X -> Dst
NEG Dst B,W,L 3 Two '"s complement of Dst
NEGX Dst B,W,L 3 Two's complement with X
of Dst
NOT Dst B,W,L 3 One '"s complement of Dst

MULU Src,Dn W 3 Dn source -> Dn

*
MULS Src,Dn W 3 Dn source -> Dn
*
DIVU Src,Dn W 3 32 bits Dn/16 Src ->
DnCRST:QUT]
DIVS Src,Dn W 3 32 bits DN/16 Src ->
DnCRST:QUT]

Logical Instructions

AND Src,Dst B,W,L 1 Dst; . Src -> Dst

ANDI Imm,Dst B,W,L 1 Dst Imm -> Dst
OR Src,Dst B,W,L 1 Dst + Src -> Dst
ORI Imm,Dst B,W,L 1 Dst + Imm -> Dst
EaR Src,Dst B,W,L 3 Dst + Src -> Dst
EaRl Imm,Dst B,W,L 3 Dst + Imm -> Dst

Shifts and Rotations

ASL CntDst B,W,L Arithmetic shift left

ASR CntDst B,W,L Arithmetic shift right
LSL CntDst B,W,L Logical shift left
LSR CntDst B,W,L Logical shift right
ROL CntDst B,W,L Rotate left
ROR CntDst B,W,L Rotate right
ROXL Cn t.Ds t. B,W,L Rotate left with extend
ROXR CntDst B,W,L Rotate right with extend
 68000 Instruction Set 89

Src source An address register

Dst destination On data register
Imm immediate
CntDst = counter (including destination when specified)
(1) Memory to memory operations are not possible
(2) Src can only use addressing modes Dn,-(An)
(3) Src and Dst cannot be an An register.

Addition, Subtraction and Complement

The first four instructions, ADDI, SUBI, ADDQ, SUBQ,
carry out the addition (or more correctly,
incrementation, as such instructions do not exist), and
the subtraction (decrementation) between the
destination and the source, coded as immediate. If the
immediate operand lies between I and 8 inclusive, it
will be preferable to choose the instructions ADDQ and
SUBQ which are more efficient in code and execution
time, as can be seen from the following

ADDI.B #3,$4000 is coded in 6 bytes and requires 21

clock cycles;

ADDQ.B #3,$4000 is coded in 4 bytes, with an execution

time of 17 cycles.

Note that a good assembler will, if you are not too

rigorous in your requirements, look after coding the
instruction as it should. The ADD and SUB instructions
add and subtract in binary the source and destination
before storing the result in the destination. When the
destination is a On register, we have available in the
source all the addressing modes. On the other hand,
when the source is a On register, the addressing modes
making reference to the program counter are not
allowed. The next two instructions, ADDA and SUBA, only
concern the An registers as destination.
The ADDX and SUBX instructions allow
multiple-precision calculations to be carried out,
where source and destination can only use the
addressing modes On and -(An); this appears quite
logical, in view of the method of calculation (low bit
to high bit, or predecrement mode).
It is also possible to write directly in BCD (which
eliminates the well-known DAA of the 6800 and 6809).
Here the 68000 has three instructions available: ABCD
(addition in BCD); SBCD (subtraction in BCD); and NBCD
(complement in BCD).
The remaining instructions in group (1) instruct the
68000 to two's complement (NEG), and with bit extension
(NEGX), or to one's complement (NOT).
90 The 68000 Hardware and Software

Multiplication and Division

The four instructions of group (2) multiply (MULU and
MULS) and divide (OIVU and OIVS) unsigned and signed
binary numbers.
MULU and MULS multiply the 16 bits of a On register
(bits 0-15) by the 16 bits of the source that may use
all addressing modes except An. The 32 bits of the
result are saved in On.
OIVU and OIVS divide the 32 bits of a On register by
the 16 bits of the source, with again all addressing
modes except An available, before saving the 16 bits of
the remainder in the word MSB of On (bits 31-16) and
the 16 bits of the quotient in the word LSB of On (bits
15-0).
Two conditions may prevent the 68000 from carrying
out division.
a) if the divisor is zero, the processor is rerouted
to the exception procedure "zero division", the vector
number of which is $5.
b) if the result exceeds the 32 bits of On
(remainder and quotient in 16 bits), causing overflow
(V := 1). In such a case no internal provision has been
made to cope with the situation (as has been done for
division by zero). It is therefore up to the programmer
to verify if overflow has occurred, by testing flag V,
and to take any necessary action.
Note that neither source nor destination operands
are altered if such anomalies occur.

Logical Instructions
The next group (3), the logical instructions, will be
well known to programmers. It includes AND and ANOI
which carry out a logical AND of the source and the
destination, with the result being stored in the
destination.
We have however noted that memory to memory
operations are not possible and that, for EaR and EaRl
(exclusive OR), the source can only be a On register or
an immediate operand.

Shift and Rotate Instructions

These form the last group (4) of the arithmetic and
logical instructions. Here the operand CntOst can be
written #Cnt,Ost, where #Cnt codes as immediate an
operand between 1 and 8. This operand specifies the
number of shifts or rotations to be made in the
destination (which can only be a On register).
CntOst can also be written Om,Ost, where Om is a On
register that codes the number of shifts or rotations
to be made in Ost. Up to 63 operations (modulo 64) are
possible.
 68000 Instruction Set 91

CntDst can also be written as Dst, where Dst

represents a memory address. The number of shifts and
rotations is always 1, so it is superfluous to specify
the source. Note that the memory size can only be word.

Program Control
The most significant advances have been made within the
category of the program control instructions. Table 6.5
lists the various instructions involved.

Table 6.5 Program Control Instructions

Mnemon Operand Size Notes Description

Unconditional sequence break and no operation

NOP / / 1 No operation
JMP Address / I Unconditional jump to
address
BRA Displ. / 3 Branch always

Call and return subroutines and block memory allocation

JSR Address / 1 Jump to a subroutine

BSR Displ. / 3 Branch to a subroutine
RTS / / / Return from subroutine
RTR / / Return with CCR restored
LINK An,imm,dpl/ 2 Link with the stack
UNLK An / / Unlink from stack

Condition operation

Bcc Displ. / 3,4 Branch conditionally

DBcc Dn,dpl / 3,4 Test, decrement, branch
Scc Dst B 4,5 If cc is true then $FF -)
else 0 -) Dst

Handling on CCR and SR registers

MOVE Src,CCR W 6,7 Copy Src in CCR

OR Src,CCR B 8 Inclusive OR between CCR
and Src
ORI Imm,CCR B 8 Inclusive OR between CCR
and operand
AND Src,CCR B 8 Logical AND between CCR
and Src
ANDI Imm,CCR B 8 Logical AND between CCR
and operand
EORl Imm,CCR B 8 Exclusive OR between CCR
and operand
MOVE SR,Dst W 5 Copy SR in Dst
92 The 68000 Hardware and Software

Privileged instructions

OR Src,SR W 8,9 Inclusive OR between SR

and Src
ORI Imm,SR W 8,9 Inclusive OR between SR
and operand
AND Src,SR W 8,9 Logical AND between SR
and Src
ANDI Imm,SR W 8,9 Logical AND between SR
and operand
EORI Imm,SR W 8,9 Exclusive OR between SR
and operand
MOVE An,USP L 9 Copy An in USP
MOVE USP,An L 9 Copy USP in An
RTE / / 9 Return from exception
RESET / / 9 Set Reset line low
STOP Imm W 9 Load SR with Imm,
then stop

Logical traps

TRAP Vectnum / 19 Logical exception

TRAPV / / Exception if V = 1

Notes
(1) The address is specified in absolute: all
addressing modes allowed except
Immediate,Dn,An,(An)+,-(An).
(2) Displacement lies between $8000 (-32 768) and $7FFF
(+32 767).
(3) Displacement is 16 bits signed (32K).
(4) See table 6.5 for condition codes.
(5) Destination can use all addressing modes except
Immediate,An,d(PC),d(PC,XI).
(6) Source may use all addressing modes except An.
(7) Only word size is allowed even if destination is
byte (in which case CCR is loaded with the source LSB).
(8) The data on immediate is a function of the
instruction specified size.
(9) Privileged instructions can only be handled in
supervisor mode.
(10) The vector lies between 0 and 15.

The first group (1) is typical of the instructions

sets of the majority of microprocessors (6800/6809,
8080/8085, 6502).
The first two instructions of the next group (2)
allow calls to be made to a subroutine - absolute with
JSR and relative with BSR.
 68000 Instruction Set 93

The instructions RTS and RTR instruct the 68000 to

return to the calling program. The difference between
these two instructions lies in the execution. In the
case of RTS, restoration of the return address,
previously stored in the stack, is made when the
subroutine is called. with RTR, the CCR is restored
first, then the return address to the calling program.
Note that in the case of RTR only the return address is
saved on the stack when the subroutine is called.
The LINK instruction automatically allocates a
working area (block of RAM) to the calling program, to
be used for example for passing parameters or storing
local data. As for UNLK, its role is to free this
working area.
These two high-level instructions are completely
suited to the writing of reentrant programs, that is,
those programs or subroutines that work on a block of
memory belonging to the calling program.
The instructions in the thir? group (3) concern
conditional operations, where the logical condition is
specified by the instruction mnemonic in the cc
(condition code) form.
The Bcc type of instruction will already be familiar
to assembly language programmers of Motorola
microprocessors. Note that with Bcc displacement the
68000 executes a conditional branch if the cc condition
is true. The relative displacement is coded in one or
two bytes.
The OBcc type of instruction has no equivalent in
8-bit microprocessors, at least in the Motorola range.
This conditional branch instruction, also called a
looping primitive, operates in relation to the
following three parameters
the conditional branch condition specified by
cc (for example, OBEQ, OBNE, OBMI)
the loop counter On
the relative signed 16-bit displacement.
The Scc type instructs the CPU to set the
destination byte (On or memory registers) at $FF if the
cc condition is true and at $00 if it is false.
The fourth group of instructions concerns those that
have the condition code register CCR as destination,
that is, the user byte of the status register SR.
The fifth group is very important, as the following
discussion will reveal. In fact, all the instructions
in this group are called privileged instructions; that
is, they can only be executed in supervisor mode
(S := 1). If one of these instructions is executed is
user mode (S := 0), a privilege violation occurs: the
68000 is rerouted in the exception table to address $20
(vector number 8*4 = 32 or $20) in order to recover
94 The 68000 Hardware and Software

the start address of the exception program.

Note that all the instructions capable of modifying
the status of the processor (loading SR) are
privileged.
The RTE instruction allows return from an exception
procedure to a normal procedure.
The RESET instruction, which is also privileged,
instructs the 68000 to hold the RESET line (here an
output) at low for 124 clock cycles, this being for
example the time required to initialise a peripheral
circuit (PIA 6821, PTM 6840, PI/T 68230).
The 68000 instructions set has 16 logical traps (the
6809 has 3: SWI, SWI2 and SWI3) which, when one of them
is executed, cause the 68000 processor to branch to an
exception procedure. Each trap has its own vector
number and therefore its own exception vector.

Examples

TRAP #0 has the number 32 and the address

10
32 *4 128 $80.
10 10

TRAP #15 has the number 47 and the address

10
47 *4 191 $BF.
10 10

On the other hand, the TRAPV instruction is the

logical trap that is available to the programmer if the
status flag V is at 1 when this instruction is
executed. This instruction is especially useful, for
example, in the case of OIVS and OIVU. In fact, if the
68000 finds that it cannot carry out such an operation
because of lack of space, it sets the status flag to 1
to inform the programmer that overflow has occurred.

Example
OIVU 01,00 := $FFFFFFFF
TRAPV 01 $XXXX0002
BRA*
The 68000 carries out the signed or unsigned
division of the 32 bits of the destination (DO in the
above example) by the 16 low order bits of the source
(01) .
The 32 bits of the result available in the
destination are distributed as follows: the remainder
in 16 bits (bits 16-31 of the destination); the
quotient in 16 bits (bits 0-15 of the destination).
If the result exceeds this format, the 68000 does
not carry out the operation, but sets V to 1, without
 68000 Instruction Set 95

altering the destination and source registers.

The same principle applies with the TRAPV
instruction, but in this case the program is rerouted
to the exception table at address $lC which corresponds
to vector number 7.

DBee INSTRUCTIONS
Role of DBee
Instruction OBcc On,d16 is a looping primitive with
three parameters: the condition specified by cc, the
loop counter represented by a data register On, and the
relative 16-bit displacement.
Execution of this instruction by the CPU causes the
following sequence of events
1. Condition cc is tested (cc can be one of the 16
conditions listed in table 6.6). If the condition is
true, instruction OBcc is terminated and the processor
executes the rest of the program.

Table 6.6 Conditions (ee) Used with Instructions

DBee, Sec, Bee
Mnemonic cc conditions Logical equation

T (not Bcc) True 1

F (not Bcc) False a
HI High C + Z a
LS Low or same C + Z 1
CC Carry clear C a
CS Carry set C 1
NE Not equal Z a
EQ Equal Z 1
Vc* Overflow clear V a
VS* Overflow set V 1
PL Plus N a
MI Minus N 1
GE* Greater or equal N EB V = a
LT* Less than N EB V = 1
GT* Greater than Z EB (N EB V) a
LE* Less or equal Z EB (N EB V) 1
*Used in two's complement mode

2. If condition cc is false, the LSB word of

register On is decremented by one.
3. If the decrementation of register On has brought
about the result -1, instruction DBcc is terminated and
the processor executes the remainder of the program.
If the result is the opposite, the contents of the
PC are added to the relative 16-bit displacement so
that the branch address can be determined.
96 The 68000 Hardware and Software

Expression of Instruction DBcc

In assembler

OBcc On,d16

OBcc instruction mnemonic (conditional branch)

On register On, loop counter
d 16 l6-bit signed displacement

Flowchart and Pseudo-code

1
No Yes I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
'-------------
End
-------------- J

In pseudo-code
IF cc FALSE THEN
On := On -1
IF On<> - 1 THEN
PC := PC + l6-bit displacement
END
ELSE
NOP

END

Figure 6.2
 68000 Instruction Set 97

Examples
1. The assembler programs in listings 6.1a and 6.1b
instruct the Me 68000 to print out n times the message
"The 68000 microprocessor is wonderful".
The value n stored in byte $2054 before execution of
the program represents the contents of the loop counter
register of the primitive DBLT D2,LOOP.
The different simulations prove that the test on the
loop counter is carried out on value -1.

Listing 6.1a

20
*******************************'*****'*****'**'*****'*'*'***'******'***********
30
40
'* THREE PARAMETER LOOPING PRIMITIVE
* DBCC INSTRUCTION
50
*
60
* '*
70
*******'*******'************************************'**********'**********
90 000'1F9E9 ACIA EQU $"1F9E9 = ADDRESS ACIA 6850 EUROMA~; 68000

-1"10 00002000 RORG $2000

t 30 002000 4FFAOOAE LEA.L STACK.SP INI TIALISE SSP

'140 002004 41F9000-1F9E9 LEA.L ACIA,AO INITIALISE AD ADDRESS ACIA
-150
-160 00200A -143AOD48
* MOVE.B COUNTER~D2 LOAD COUNTER LOOPING
"170
"180 00200E 6-10A
'*
LOOP BSR.S PCRLF
-190 002010 6'128 BSR.S TEXT
200 002012 SnCAFFFA DBlT D2,LOOP
2-10 0020-16 4E4"1 TRAP #'1 RETURN TO EUROMAK 68000 MONITOR
220 0020-18 0000 DC.W 0
230
240 OG20lA 2FOO
'PCRLF
* MOVE.L DO,-(SP) SAVE ALTERED REGISTER
250 00201 C 700A MOVEQ #$oA,DO DO.B := ASCII LINE FEED
260 0020tE 6-108 BSR.S OUT OUTPUT LF
270 002020 700[1 MOVEQ #$OD,DO DO.B := ASCII CARRIAGE RETURN
280 002022 6-104 BSR.S OUT ; OUTPUT CR
290 002024 2a-1F MOVE.L (SP"J+. DO ; RESTORE REGISTER
300 002026 4E75 RTS
3"10
320 002028 2FOl
*
OUT MOVE.L D-l.-(SP.l ; SAVE ALTERED REGISTER
330 OG202A 12'1 (I OUT'! MOVE.B (AD} .D'! ; ACIA READY
340 00202C 020-10002 ANDl.B #2.[l·1
350 002030 67F 8 BEQ.S OUTl ; NO WAIT
360 002032 -11400002 MOVE.B DO.2(AOi Ok TRANSMIT
370 002036 221F MOVE.L (SP}+.(i-l ; RESTORE REGISTER
380 002038 4E75 RTS
390
400 00203A 48E78040 TEXT ~10VEM.L DO,: A'1 •- i SP) SAVE ALTERED REGISTERS
410 00203E 43FAOO-1S LEA.L TEXT-1,Al A-l:= Ql START ADDRESS TEXT
420 002042 10'19 LOOP2 MOVE.B iA'1.i+.[iO DO WHILE DO :> EOT
430 002044 OCOOOO04 CMPI.B #EOT .DO
440 002048 6704 BEQ.S ENDTRANS I i* TRANS~l1T CHAR i/
450 00204A 6'1 DC BSR.S OUT
98 The 68000 Hardware and Software

460 OO204C 6OF4 BRA.S LOOP2 ; ENDOO

470 00204E 4COF0201 ENDTRANS MOVEM.L (SP)+,OO/A1 ; RESTORE REGISTERS
480 002052 4E75 RTS
490 *
500 002054 00000OO1 COUNTER OS. B
5'10 002055 20 TEXT1 DC.B THE 68000 HICROPROCESSOR IS WONDERFUL I

520 002087 04 DC.B EOT

530 00000oo4 EOT EQU 4
540 002088 00000028 [tS.L 10
550 0000208O STACK EQU *
560 END

'*
'* S 1. MULATION PROGRf.,M
~. ::::::::::::::::::::::::::::::::::::::::::::::::::::::

*
> ;?()~:j'1. B
* 00205't > O~?
* ()O~~05!5 )
200CHG
THE 6ElO()() MICROPROCESSOR IS ~JONDERFUI..
THE 680(){) MICROPROCESSOR IS WONDERFUL
THE 6El()()() MICROPROCESSOR IS WONDERFUl..
> *
> * WHY· ??
') -t(.

;?O~:.i4. B
.:* O()~?05't
* ()O~?055
) -;.,()OO; o
THE 6E}()()() MICROPROCESSOR IS ~JONOEI~FUL
THE b80{)() MICROPROCESSOR IS I"JONDERFUL
THE 68()(lO MICROPROCESSOR IS ~JONDERFUL.
THE 680{)() MICROPROCESSOR IS I"JONDERFUL

20
*****************************'*******'*********'****************'******
30 * *
40 * THREE PARAMETER LOOPING PRIMITIVE (EXERCISE 2 ) *
50 * *
60 * TWO STRINGS ARE COf1PARED TO SEE IF THEY ARE THE SAME *
70 * *
80
*************************1*********************************************
** Al = POINTS TO THE BEGINNING OF
100
'110 THE FIRST STRING
'120 * A2 = POINTS TO THE BEGINNING OF THE SECONO STRING
130 * 02 = NUMBER OF CHARCTERS
140 OOO'lE178 OUTMES EQU $'1[178 ; PRINT TEXT STRING OF CHARS

00002000 ORG $2000

180 002000 4FF8200C LEA.L STACK,SP INITIALISE STACK POINTER SSP

190 002004 43F8202A LEA.L TEXT"t ,A"! INITIALISE POINTER STRING'!
200 002008 45F8205E LEA.L TEXT2,A2 INITIALISE POINTER STRIN62
210
220 00200C 2209
* MOVE.L Ai ,[J"t [J"!:=A"l
230 OO2OOE 240A MOVE.L A2,D2 02:=fi2.
240 002010 9481 SUB.L 0"1,02 02:=02-0"1 1* COUNTER CHARS *1
250
*
 68000 Instruction Set 99

260 002012 B509 LOOP CMPM.B (A'1) +, (A2)+ DO WHILE MEM[A2]=MEM[A1]

270 002014 56CAFFFC D8NE D2,LOOP ~ 1* CORRECT *1
280 ENDDO
290 002018 b604
* BNE.S ERROR IF Z=O THEN ERROR
300 00201 A 4E 4'1 RETURN TRAP #'1 ENDIF
3'10 00201 C 0000 OC.W 0

330 0020'IE 4'IF82092 ERROR LEA.L TEXTERROR, AD AO:= i TEXT STRING

340 002022 4EB9OOO1E"178 JSR OUTMES PRINT TEXT STRING
350 002028 60FO BRA.S RETURN

370 00202A 20 TEXT1 DC.8 THE 68000 HI CROPROCESSEUR IS WONOERFUL I

380 002050 04 nc.e 4

390 00205E 20 TEXT2 nc.e THE 68000 HI CROPROCESSEUR IS WONDERFUL !

400 002091 04 OC.B 4

410 002092 20 TEXTERROR ec.e I STRINGS CHARS NO EQUAL , ERROR I

420 002083 04 OC.B 4

430 0020B4 00000028 DS.L '10
440 000020DC STACK EQU
450 END
*

f***** TOTAL ERRORS 0-- 0

SYMBOL TABLE - APPROXIMATELY 504 SYMBOL ENTRIES LEFT

ERROR oo201E LOOP 002012 OUTMES O1E'178 RETURN 00201A

STACK 00200C TEXT-1 00202A TEXT2 oo205E TEXTERRO 002092

2. The program example shown in listing 6.2 is not

directed exclusively at the loop primitive, but also
gives a brief reminder of address register indirect
with index.

Listing 6.2

20
30
**********************************************************************
40
** EXAMPLE OF USE OF "INDIRECT AORESSING" WITH INDEX **
50 * AE = d+An+Xn *
60 * FINDING THE LARGEST OPERAND IN THE TABLE (size Long Word) *
70 * Program Written in Position Independent Code *
80
90
* *
**********************************************************************
110 00002000 ORG S2000

'130 002000 43F83000 lEA.L S3000,A1 ;INITIAllSE POINTER I

140 002004 2049 MOVE.L A'I,AD ;INITIALISE POINTER J
150 002006 2610 MOVE.L (AO) ,03 ; D3:= MEt1[JJ
160 002008 7009 MOVEQ 110-1,00 ; 00:=9 1* lOOP COUNTER *1
170 oo20OA 4281 CLR.L D1 ; [I'1.L:= 0
180 00200C 588'1 lOOP AODQ.l 14,0'1 ; REPEAT
190 00200E 86811800 CMP.L 0(A'1 ,D'1.l) ,03 ; ~ [t1.L:=O'I.l+4
200 002012 6C04 BGE.S GREAT ; ~ IF 03 :>= MEM[A'I+01 •lJ THEN
 100 The 68000 Hardware and Software

2-10 002014 2631-1800 MOVE.L O(A-1 .oi.u ,03 i I i/

220 0020t8 S-lCBFFF2 GREAT DBRA DO,LOOP I ELSE
230 0020"1 C 4E41 TRAP #'1 : 03:= MEM[Al, D'1.LJ
240 00201 E 0000 DC.W o ENDIF
250 END UNTIL DO=-t

if**** TOTAL ERRORS 0-- 0

SYMBOl TABLE - APPROXIMATELY 5'10 SYMBOL ENTRIES LEFT

GREAT 002018 LOOP 00200e

Simulation
~:'

'~ ~: S I Mtll. ~~ T ION F}F;~ ()Ol:'~ r,M :

) ~: ::: :::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
i1:.
3000.1,.
~* OO:~O{)O 00000000
* OO:3001.t BBBaaBBB
* ()()~30()B FFFFFFFF
':* OO]()O(
:* OO]()-IO EFEEF.:EFE
* OOJO·llj.
* n0:30'IB
:* ()i) :] f)-I C
:.. 00::30:?O
:.. 00::30:~~":t
~* OOJO:?B \

.'
;.)('1'1(":;1)
~?()OO; Fi
~(- . . J~)TP F,'C::: OO~?O--I C tt '1£:','1 f;:::O S 000 c::: sp::: 00000(,00

PC::: ()() ? ()'1C U ,:~ [' ,; ,., S:::0 S 00 () C:: ~)p::: O()OO()600
DO=: OOOOF F FF D'I::: ()OOO()()~?B D~?:::: O()O()OO()() D~3:::: 77777777
[)L,::: OO()()OOCl() [)~:j::: ()()O()O()()O Dt}::: OO()()()O()() [)i' ::: OOO()OO()()
i~():::: O()()O:3()()() (~"I::: OO{)O:3()()() (.\;':~::: Oo()n()()oo A:;3::: O()()()l)DOO
~~~(;:::: ()OOO()OOO ~~~:;::: ()OOOOOO() ~~t,::: O()()()()()()O (~7:: 00000600

> *
:> *
]000.1.,
:cf OO~3()()O
~ 00::300 l t
* OO]()OB
~cf ()O~3()OC 00000000
* OO]()-" I] (., {ll~~\~~\r'(lr\~~\
* ()()]()'14 6 c':·(,',t!.'.,{,c",66
:do OO]()'IB 7777?'700
* OO:J()'I C
* no]o~~~O EEEEF:EEE
* () ():3() ~':? ,:j. 7FFFFFFF
* O()::3();~~B

") ?O-1 C; I)
2000;13
-G~ I,JSTP P C::: O()~.~O·1 C U ':'1:'.';'1 S:::O~) DOO C::: sp::: OO()()0600
DO::: OOOOFFFF D-I:: ()O()()()O~?B D:~?::: OOO()()()OO D3:::: lFFFFFFF
D,(1:: OOO()()()()() os- OOOOOO(}O [){:.:::: OO()O(}()(}() D7::: OO()O()O(JO
(~o::: OO()O:)OOO ~'-I ::: ()OO()~JOOO A~~::: OO()OO{)OO A]::: O()O()ODOO
f~Ll:: OOO()()O()() ~~~:;:::: OOOOOO()() (.,6::: OOOOO()()O (-\7::: ()()()()0600
 68000 Instruction Set 101

Sec INSTRUCTION

1 Role of Sec
Instruction Scc dst tests one of the 16 cc conditions
summarised in table 6.6.
The destination byte is positioned at $FF if the
condition specified by cc is true, and at 00 if cc is
false.
This instruction is generally used to position a
boolean variable after evaluating an expression, where
the true variable is coded $FF and the false variable
is coded 00 (see the example in listing 6.3).

2 Syntax of Sec

....;
In assembler

Scc dst

Instructi~
mnemonic effective address

Flowchart and Pseudo-code

IF cc TRUE THEN
I destination .= $FF
ELSE
f destination .= 00 End
ENDIF

Figure 6.3
102 The 68000 Hardware and Software

Listing 6.3

30
40
**********************************************************************
50
* USE Sec INSTRUCTION
*
60
* *
70
* *
80
* PROGRAM TO DETECT ·16 BIT PALINDROMES
90
*
... (USING MACROS)
*
100
1"10
* *
**********************************************************************
-130
*
140 ** ALGORITHM :
-150 * ---------
160
"170
*
-180
** BTST [1"1. (AD) ~ ~ BTST DO. (AD)
-190
200
* v v
2-10
* ++++++++++++++++
220
*
230
* :- 0
*
240
*
260 *
270 ** MACROS
280 * ------
300 TEXT MACRO
3-10 \a HOVEM.L OO-D7/AO-A6,-(A7)
320 LEA STRING\i,AO
330 JSR OUTMES
340 MOVEM.L (A7)+,DD-[l7/AO-A6
350 RTS
360 ENDM

380 oo01E-178 OUTMES EQU $1[178 • OUTPUT STRING OF CHARS (EURO~;AK 68(00)

400 00002000 ORG $2000

420 002000 4FF82194 LEA.L STACK,A7 ; INITIALISE STACK POINTER SSP

430 002004 41F82074 LEA.L TABLE,AO ; INITIALISE AOORESS PALINDROMES
440 002008 61-10 BSR.S SEARCH
450 *
460 00200A 4A3B2194 TST.B FLAG
470 OO200E 6706 BEQ.S CORRT ; IF FLAG <)0 THEN ERROR
480 002010 613A BSR.S IiOOi ;
490 002012 4E4'1 ENOPROG TRAP 11 ; RETURN EUROMAK 68000
500 002014 0000 OC.W 0
510
520 002016 6'148
*CORRT BSR.S ;;002
530 002018 6OF8 BRA.S ENOPR06
 68000 Instruction Set 103

550 D020iA 48E7FOOO SEARCH MOVEM.L DO-D3.- i A7)

560 00201E S-lF820194 SF FLAG : FLAG := FALSE
570 002022 4202 CLR.B D:2
580 002024 4203 CLR.B D3
590 002026 4200 CLR.B DO ; INITIAL RIGHT HAND BIT NUMBER
600 002028 720F MOVEQ #°15 4 [;°1 ; INITlAL LEFT HAND 81T NUMBER
6-10 00202A 0-110 LOOP BT5T DO. i.AD) ; TEST RIGHT HAND BIT
620 00202C 57C2 SEQ 02
630 00202E OJI0 BTS, [1°1, (AO} ; TEST LEFT HAND B1 T
640 002030 57C3 SEQ 03
650 002032 8602 CMP.B D2,D3 IF BITS ARE EQUAL THEN
660 002034 660C BNE.S EXIT ~ 1* MOVE TO NEXT BIT *1
670 002036 5240 ADDQ ~t-1, DO ELSE
680 002038 534·1 SUBQ ~U .D-l ~ /* EXIT *1
690 00203A OCooo008 CMPI.B #8,DO EN(iIF
700 00203E bbEA BNE.S LOOP
7"10 002040 6004 BRA.S EXIT"! IF END TEST THEN EXITt
720 002042 50F82t 94 EXIT 5T FLAG FLAG := TRUE
730 002046 4CDFOOOF EXIT"! MOVEM.L (A7)+.DO-£i3
740 00204A 4E75 RTS
750
*
760
770
* TEXT "1
770 00204C 48E7FFFE .j001 MOVEM.L DO-D7 jAO-A6~-(A7)
770 002050 4"1F82076 LEA STRING"i ,AO
770 002054 4EB9000·1Et 78 JSR OuTMES
770 00205A 4CDF7FFF MOVEM. L (A7.1 +4 00-07 JAO-A6
770 00205E 4E75 RTS

..*
780
790
800 TEXT 2
800 002060 48E7FFFE ~(I02 MOVEM.L DO-D7/AO-A6.-(A7)
800 002064 41F820A3 LEA STRING2,AO
800 002068 4EB9000-tE178 JSR OUTMES
800 00206E 4C(~7FFF MOVEM. L (A7) +, DO-D7.1 AO-A.~
800 002072 4E75 RTS

820 002074 00000002 TABLE DS.w

840 002076 OA STRING·l DC.B iA,$D

850 00207B 20 DC.B THE WORD IS NOT A PALINDROME
B60 0020AO OA ec.s iA,$(i,4
870 0020A3 OA STRING2 OC.8 SA,i[l
BBO 0020AS 20 DC.B THE WORD IS A PALINDROME i

890 0020C8 OA DC.B

910 0020CC 000000C8 DS.L 50

920 00002'194 STACK EQ0
930 002194 00000001 FLAG DS.B
940 END

****** TOTAL ERRORS 0-- 0

SYMBOl TABLE - APPROXIMATELY 493 SYMBOL ENTRIES LEFT

104 The 68000 Hardware and Software

Simulation

~.

) *

.
"> *iI: S IMUL("TION PRO G RAM
-i(.

") 1/..

'

~'>07Li. t,.J
:.. {)O~?()7,ct AFF~:.i
·)f OO:;~Ol,~
;';000;13
fHF "'lORD r s NOT (" PAI,..INDI~OME
;~07L;. 1,01
:.. O()~?()7 "t F FFF
* ()O~?07lJ )
20()O ~ o
THE "'lORD IS A PALIN[)I~OME

) ;.~07Lt. W
* 00207 it (" ~:,i~;;~~
:tf. ()O:~~()7 6 ;~
> 2000;G
THE ""ORD IS A PALINDr~OME

) 207't.l·J
* () I] ~? () ? it (ol~:j f~~:.;
* ()O:~?O? 6
2000;(1
THE WORD IS A PALINDROME

BSET, BCLR, BCHG, BTST INSTRUCTIONS

The Me 68000 has four test instructions that allow it

to work at the bit level.
These instructions operate on long words in the data
registers, but on bytes in the addresses.
Unfortunately, there were not sufficient op-code
combinations available to provide other options.
The bit concerned in the test, which we shall call
numb, can be specified statically as immediate, or
dynamically by data registers whose contents are the
bit to be tested.
If the source or the destination is a data register,
the size is a long word and the bit tested lies between
o and 31 (modulo 32).
If the size is byte, the destination can only be a
memory location and the bit tested lies between 0 and 7
(modulo 8).
 68000 Instruction Set 105

1 Syntax of the Instructions

In assembler

BSET numb , dst

BCLR numb , dst
BCHG numb , dst
BTST numb , dst

Instructio_n ~!
mnerno n i c
Ldestination
Number of
bit tested
-------_-----.1

Flowchart and Pseudo-code

BSET numb, dst

Test a bit and set

Example : Test a bit at 0

IF numb = 0 THEN
I
ELSE
Z -= 1

I Z
ENDIF
-= 0

numb -= 1

Figure 6.4
106 The 68000 Hardware and Software

BCLR numb, dst

Test a bit and clear

Example : Test a bit at 1

IF numb 1 THEN
I
ELSE
Z .= 0

I
ENDIF
z := 1

numb := 0

Figure 6.5

BTST numb, dst

Test a bit

Example : Test a bit at 0

IF numb = 0 THEN
I
ELSE
Z .= 1

I Z
ENDIF
.= 0

Figure 6.6
 68000 Instruction Set 107

BeHG numb, dst

Test a bit and change

Example : Test a bit at 0

I
IF numb = 0 THEN
.=
num~ .= 1
1

Inum~ .=
ELSE
:= 0
0
ENDIF

Figure 6.7

2 Program Examples
The program shown in listing 6.4 causes the number of
Is and as contained in a long word to be displayed.

Listing 6.4

20
30
**********************************************************************
40 PROGRAM TO DISPLAY A LONG WORr, IN BINARY
*
50
*
60
**********************************************************************
80 00O'lF9E9 AeIA EQU SlF9E9 ADDRESS ACIA EUROMAK 68000 SYSTEM

100 00002000 ORG $2000

110 002000 4FF82068 LEA.L STACK,SP INITIALISE STACh POINTER SYST.
120 002004 40F9000'1 F9E9 LEA.L AClh~A6 INITIALISE A6 ADDRESS ACIA 6850
130
140 00200A 7COA
* MOVEQ #$OA~(i6 LINE FEED
-150 00200C 6136 aSR.S TSTACIA , OUTPUT LINE FEED
-160 00200E 7COD MOVEQ #$OD,D6 CARRIAGE RETURN
-170 0020-10 6132 BSR.S TSTACIA OUTPUT CARRIAGE RETURN
l80
190 0020-i 2 20382050 MOVE.L \. LWORD) , 00 LOAD LONG WORD
200 002016 6102 BSR.S COUNTBIT
2"10 0020'18 4E41 TRAP #'1 RETURN TO EUROMAK 68000 SYSTEM
220 *
 108 The 68000 Hardware and Software

230 00201 A 2F02 eOUNTBIT MOVE.L D2,-(SP) ; SAVE ALTERED REGISTER

240 0020'IC 74'IF MOVEQ #31,02 ; 02:=31 .1* COUNTER BIT *1
250 0020·1E 0500 TEST BTST .L D2,DO ; REPEAT
260 002020 6704 BEQ.S BITO ~ IF BIT D2 <> 0 THEN
270 002022 sioc BSR.S DISPLAY'i I
~ 1* DISPLAYED "1 *1
280 002024 6002 BRA.S SUIT ~ ELSE
290 002026 6'1'12 BITO BSR.S DISPLAYO I
~ i* DISPLAYED 0 *1
300 002028 5·1CAFFF4 SUIT DBRA D2, TEST ; ~ ENDIF
3'10 00202C 241F MOVE.L (SP)+,D2 ; UNTIL [12=-'1
320 00202E 4E75 RTS RESTORE REGISTER
330
340 002030 2F06
*DISPLAY'1 MOVE. L [)6,-(SP) ; SAVE ALTERED REGISTER
350 002032 7e3'1 MOVEQ #$3"1,06 : 06.B:= !·r
360 002034 6·10E BSR.S TSTACIA
370 002036 2C'lF MOVE.L (SP)+.D6 : RESTORE REGISTER
380 002038 4E75 RTS
39J
400 00203A 2F06
*OISPLAYO MOVE.L D6.-(SP) : SAVE ALTERED REGISTER
4'10 00203C 7C30 MOVEQ #$30,06 ; Db.B:= fOI
420 00203E 6'104 BSR.S TSTACIA
430 002040 2C'1F MOVE.L (SP)+,Db ; RESTORE REGISTER
440 002042 4E75 RTS RETURN
450
460 002044 08·16000'1
*TSTACIA BTST .8 #'1, (A6) ; ACIA READY ?
470 002048 67FA BEQ.S TSTACIA ; NO BRANCH TSTACIA
480 00204A 10460002 MOVE. 8 06,2(A6) ; YES TRANSMIT CHAR
490 oo204E 4E75 RTS

5·10 002050 00000004 LWORD OS.L ; RESERVE 1 LONG WORD

520 002054 00000014 OS.L ; RESERVE 5 LONG WORD FOR THE STACK
530
540 00002068 STACK EQU
550 END
'*

****** TOTAL ERRORS 0-- 0

Simulation

'*
~: S IMUI...(~T ION pr~OGR~~,M
it: :::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::=

> *-
> *-
* ~~O~:jO. L.::: 1... ONG ~IOPD

~.~ () ~:,; 0 ..I..

.:* OO;?050 > (.iO~:,O{lOf.·IO
:d- t"'O?()~.:5lt >
~?OOO; C'
.., I] 1ClOO(l()'10'" 00000'" 0'1 OOO()('1'1 0'1 00000

*;!o~)o .. I..
:If OO:?()~50 FFFFFFFF
()():~~ os I.t
*
~?OOO; G
 68000 Instruction Set 109

'1'1'1"1'1 '1'1'1'1'1'1'1'1'1'1'1"1'1'1'1"1'1'1'1'1'1'1'1'1'1'1'1
*
*
;?O~;,;(). L..
* 0020~jO 00000000
* (){):~?O!5/'t

*2000;G
OOOOO()(}O()()()()OOOO(}O()O()()O()()(l()()()()()()

The program shown in listing 6.5 counts the number of

Is in a long word.

Listing 6.5

20
*'***************'**********'*****************'****************************
**' PROGRAM TO COUNT THE NtJIBER OF -1 " IN A LONG WORD *
30
40 ..
. .
/I

50
60
***********************************************************************
80
90
** FUNCTION REGISTERS
'100 * -----------------
'1'10 * [lO.B = COUNT BIT
'120 * O'l.B = COUNT LOOP
'130 * 02.L = LONG WORD
'140
150 00002000
*' ORG 52000

"170 002000 4FF82048 LEA.L STACK,SP INlTIALISE STACK POINTER SSP

180 002004 2438202E MOVE.L (LWOR[J) ,02 02:= (LWOR[i)
'190 002008 6104 BSR.S TSTO
200 00200A 4E41 TRAP ~H RETURN TO EUROf1AK 68000 SYSTEM
2'10 00200C 0000 DC.W o
230 00200E 48E7COOO TSTO MOVEM.L 00-01.-(SP) SAVE ALTERED REGISTERS
240 0020'12 4200 CLR.B DO 00.8 := 0 1* COUNT BIT 11'1" *i
250 002014 72'1F MOVEQ #31,0-1 01.B :=3'1
260 0020'16 4A82 LOOP'! TST •L 02 DO WHI LE 02 -: : > 0
270 00201 B 670A BEQ. S ENOPROGRAM
280 0020'1 A 0382 BCLR.L 0'1,02 I IF NUMB BIT <.:> [I THEN
290 0020'1 C 6702 BEQ.S LOOP I ~ Z:=0 ; NUMB BIT:=0; DD:=[lO+'1
300 0020'1E 5200 A[J[JQ.B tt-l,[JO ELSE
3"10 002020 5'1 C9FFF4 LOOP [lBRA 0'1 ,LOOP'! ~ Z:='1 ; NUMB BIT:=0
320 002024 '1'1 C02032 EN[JPROGRAM MOVE. B DO, NUMB I ENOIF
330 002028 4CDF0003 MOVEM.L (SP)+,[JO-D1 ENO[)()
340 00202C 4E75 RTS

360 00202E 00000004 LWORD DS.L '1

370 002032 00000002 NUMB DS.W -1
380 002034 000000'14 DS.L 5
390
400
00002048 STACK EQU
END
*
110 The 68000 Hardware and Software

****** TOTAL ERRORS [1-- [I

SYMBOL TABLE - APPROXIMATELY 50S SYMBOL ENTRIES LEFT

ENOPROGR 002024 LOOP 002020 LOOP"! OO~J}16 LW.ORD 00202E

NUMB 002032 STACK 002048 TSTO 00200E

.: ~; I MUl..(.,T ION P'~~OCi,~~(.,r·1:

,.: :::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::'*
} ....
;?O;?E. L
* ()O~?()?E 00000007
* OO~~()~3;~~
.:
* ..lUST B EFOr~E pr~~OGr~~~M EXECUTION
4: ••• -- .•• - .•••.• - •....•• - ..•..• -- - -- - ----
") *
') 203~.) 0300···
~.~O];.~ 0:300···0000
;~OOO; G
~:.

:) .:. (~FTER E)::ECUT ION

> it:·
~: .iusr BEFORE f-'ROGR(.,M EXECUTION
* _.. _ - - __ -.. - _ .
i(-

;~O;!E .t
-:tf· ()()~?O~~~E FFFFFFFF
* OO::'?O::3:;?
*~~ 0 :];~ oaoo-
;?OOO1: Fi
1I::

..:
~. AFTER E X[CUTION
-_ ...... -...... _.. _ _ ..._....._..
;.~ oaz 2 ooo .
) *
> ~~();?E. L
* O():':.~()2E FFFFFFFF
* ()O~?():]:;?
20()();G
;?():~;:~ '1 F (l().•.
oJ(-

> ~:.

?O;~E FFFF .... onoo F FFE·· O()()()

i(.

?():·1~.~ '1 F DO-·

~?()O(); G
....
* AFTER EXECUTION
~: -.-.-.--- - - .
;.)O:~~~ oooo-

LSL, LSR, ROL, ROR, ROXL, ROXR, ASL, ASR INSTRUCTIONS

1 Role of the Instructions

Rotate and shift operations are carried out on byte,
word or long word from bits 1 to 8 in static or from
 68000 Instruction Set 111

bits 1 to 63 in dynamic (when the destination is a On

register). On the other hand, if the destination
location is a memory position, operations on it can
only be carried out on one bit.

2 Syntax of the Instructions

Static : #Cnt,On

ASR.W #cnt,On

ASR.W instruction mnemonic, Arithmetic Shift Right

#cnt shift count (1 to 8 maximum)
On destination register

31 1615 o
On

t
Sign bit
retained

Figure 6.8

Example
ROL.W #8,On

Before
31 16 15
,----------~.
87 0
]
~
Dcarry

After
31 1615 87 0

1...- - - - - - - - - ]

l
ri-.

Figure 6.9
112 The 68000 Hardware and Software

Dynamic Dm,Dn
The total number of rotations or elementary shifts of
the content of Dn is specified by the 6 low order bits
of register Dm (modulo 64).

31 5 4 3 2 1 0

20
21
_ _ _ 22
'---- 23
'---- 24
_______ 25

Figure 6.10

Example
The maximum number of rotations or shifts is equal to

N = 1 + 2 + 4 + 8 + 16 + 32 63

Programming

MOVEQ #$08,Dm load number of operations

to be carried out
(for our example 8 - 2

LSR.W Dm,Dn 8 logical shifts right in Dn

Memory Position
If the destination location (dst) is an address, all
memory addressing modes are authorised, except for
immediate (# Op, dst), relative and relative indexed.
However, the word is the only authorised size.

Example
ROXR.W dst

ROXR.W instruction mnemonic, rotate operand extended

right
dst destination effective address

The instruction ROXR.W dst causes a rotation of one

bit to the right.
 68000 Instruction Set 113

Memory

15 0
.,

[
Figure 6.11

MULU AND MULS INSTRUCTIONS

Program Example
The program shown in listing 6.6 carries out a BCD -)
binary conversion and displays the result (see
simulation).

Listing 6.6

30
40
************************************************************************
50
**' U SIN G "M U L U and M U L S 1 N S T RUe T ION S ...
1\

60
70 * WRITTEN BY: PATRICK JAULENT
*
80 * MACMILLAN EDITION
90
* *
100
no ************************************************************************
-120 ** BCD --) BINARY CONVERSION
"i30 * ===========================
140 '* RESULT DISPLAY IN BINARY

-160 000-lF9E9 ADDRACIA EQU $lF9E9 :ACIA 6850 SYSTEM EUROMAK 68000

180 00002000 ORG $2000

200 002000 4FFB2"156 LEA.L STACK.SP :INITIALISE STACK SSP

2'10 002004 4BF90001F9E9 LEA.L ADDRACIA. AS ; AS .L:= ADDRESS ACIA 6850
220 00200A 3F3820BC MOVE.W NUMBERBCD •- (SP)
230 00200E 610A BSR.S CONVERSION
240 0020-10 321F MOVE.W (SP)+,D"l RESTORE RESULT
250 0020-12 6-15E BSR.S PCRLF
260 0020-14 6-134 BSR.S DISPLAYED
270 0020-16 4E4-1 TRAP #'1
280 0020-18 0000 DC.W o
114 The 68000 Hardware and Software

300
310
*** BCD --) BINARY CONVERSION
320 * -------------------------
330 * ALGORITHM:
340 * =========
350 *
360 * RESULT= Di'1*10"'0 + Oi2*'10..··1 + Oi3*10"'2 + Oi4*'10"'3
370 *
390 00201A 48E778OO CONVERSION MOVEM.L 01-04,-(SP) SAVE ALTEREO REGISTERS
400 0020-1E 322F0014 MOVE.W 20(SP) ,0'1 LOAD NUMBER BCD
410 002022 4283 CLR.L 03 03.L:=0
420 002024 4284 CLR.L 04 04.L:=O
430 002026 7401 MOVEQ '1,02 INITIALIZATION MULTIPLICAND
440 002028 OC422710 LOOP CMPI.W #'10000,02 DO WHILE 02 < #$'1000
450 00202C 6C12 BGE.S EXIT
460 oo202E 3801 MOVE.W 0'1,04 ! D4.W:=0·1
470 002030 0244000F ANOI.W #fF, 04 ~ i* MASQ OIGIT LOW *1
480 002034 C8C2 MULU D2,[)4 ! D4.W*D2.W:=D4.L
490 002036 0644 ADD.W 04,03 ! D3.W+04.W:=D3
500 002038 E849 LSR.W #4,0'1 ~ 1* SHIFT NYBBLE TO HIGH *i
510 00203A C4FCOOOA MULU #'10,02 ! 02.W*·10:=02.L
520 oo203E 60E8 BRA.S LOOP ENODO
530 002040 3F430014 EXIT MOVE.W D3,20(SP) STORE RESULT
540 002044 4COF001E MOVEI'1.L (SP)+,D1-D4 RESTORE REGISTERS
550 002048 4E75 RTS
570 *
580 ** OUTPUT BINARY RESULT
590 * ===================
610 00204A 48E7FOOO DISPLAYED MOVEM.L DO-03,-(SP) SAVE ALTEREO REGISTERS
620 oo204E 7403 MOVEQ #4-'1 ,02 NYBBLE NUMBER
630 002050 7603 RBIN"! MOVEQ #4-'1 ,03 BITS BUMBER
640 002052 7020 MOVEQ #$20,00 ASCII SPACE
650 002054 6-12A BSR. S OUT CH'1 OUTPUT CHAR.
660 002056 "103C0030 RBIN2 MOVE.B #'0' ,00 ASCII 0
670 002D5A E349 LSL.W #'1,0-1
680 00205C 6404 BCC.S RBIN3 IF BIT =0 THEN
690 00205E '103COOJl MOVE.B #'1' ,DO ~ 1* 0 ,DISPLAYEO *1
700 002062 61-1 C RBIN3 BSR.S DUTCH'! ELSE
710 002064 51CBFFFO £lBRA 03,RBIN2 ! 1* '1 ,DISPLAYED *i
7~~ 002068 51CAFFE6 OBRA D2, RBIN'! ENOIF
730 00206C 4CDFOOOF MOVEM.L (SP)+, 00-03 RESTORE REGISTERS
740 002070 4E75 RTS

760
770
***OUTPUT LINE FEEO & CARRIAGE RETURN
780 * ==================================

800 002072 2FOO PCRLF MOVE.L DO,-(SP)

8-10 002074 700A MOVEQ #WA, eo
820 002076 6108 BSR •S OUTCHI
830 002078 700[) MOVEQ #$O[J,DO
840 00207A 6104 BSR.S OUTCH'1
850 00207C 201F MOVE.L (SP)+,DO
860 00207E 4E75 RTS
 68000 Instruction Set 115

880
890
*'*'* SUBROUTINE TRANSMIT CHARACTER
900 *' =============================
920 002080 08'15000'1 OUTCHl 8TST B #'1, (AS)
I TEST ACIA TRANSMIT READY ?
930 002084 67FA BEQ.S OUTCH"!
940 002086 '1B400002 MOVEIB DD.2(A5) OK I TRANSMIT CHAR.
950 00208A 4E75 RTS

970 00208C 00000002 NUMBERBCD DSIW "1

980 00208E 000000C8 D51L 50
990 00002'1 S6 STACK EQU *
'1000 END

*..*11* TOTAL ERRORS 0-- 0

SYMBOL TABLE - APPROXIMATELY 500 SYMBOL ENTRIES LEFT

ADDRACIA 0'lF9E9 CONVERSI 0020'1A DISPLAYE 00204A EXIT 002040

LOOP 002028 NUMBERBC 00208(: OUT CH'I 002080 PCRLF 002072
RBIN'! 002050 RBIN2 002056 RBIN3 002062 STACh 002156

~:

.: S IMULf,TION PI~~OC:;f<AM
*. ::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
.:
.:. 20BE .l·J :: NUMBEP E~C[)
.: •..-_ _ _--- .
> i(-

;~()B[. l·'
:cf DO:·~OBE > DO"tO
!If ()O:~?()90 >
~~OO() ~ G
1]000 0000 0000 '1 ()'1 0

*~'>OBE.l·J
!If DO~~ OBE > 0'1 CI()
:If ()()~?090
;,~OOO; Ci
OJOO 0000 0110 0100
> *.

*~.~()BE • l·J
!If ()O~~()BE > '1000
!If ()O:~~090
> ~~()OO; c:;
0']1]0 00'1'1 '1'1'1 () '1() 0 o

> *
*.

ABCD AND SBCD INSTRUCTIONS

1 Role of ABCD and SBCD

The instructions ABCD and SBCD carry out the addition
and the subtraction of operands using binary coded
decimal arithmetic. Both operations are byte only.
116 The 68000 Hardware and Software

As a consequence, the MC 68000 has no need of the

well known decimal adjustment instruction DAA that
8-bit microprocessors like the MC 6800 and MC 6809
possess.
These instructions (ABCD and SBCD) add and subtract
the source operand to/from the destination operand,
taking account of the extend bit, and store the result
in the destination location.

2 Syntax of ABCD and SBCD

The ABCD and SBCD instructions use only two addressing
modes, as follows.

Data Register Direct, where the source operand and the

destination operand are respectively contained in a
register Dn.
Example
ABCD Dn, Dnl
SBCD Dn, Dnl

Source - - - - - - - - - - - - , , ....- - - - - Des tina tion

Predecrement Register Indirect addressing where the

source and destination operands are stored in the the
addresses to by the registers An.

Example
ABCD - (An), -(AnI)
SBCD - (An), -(AnI)

Source 1 \\----Destination

Choice of Address Mode Explained

Motorola's choice of the addressing mode with
predecrementation is justified by the type of
calculation involved.

~ Direction of calculation
,DIGIT MSB I I DIGIT LSB , Number 1
+ (ou-)
,DIGIT MSB , I DIGIT LSB I Number 2

,DIGIT MSB, I DIGIT LSB , Result

======C> Direction of read of result

Figure 6.12
 68000 Instruction Set 117

In fact, decimal arithmetic calculation requires

numbers (operands) to be handled as shown in the figure
below; that is, from the least significant digit (LSB)
towards the most significant digit (MSB).
The predecrement address mode carries out the
calculation of the LSB digits (stored in the MSB
addresses) towards the MSB digits (stored in the LSB
addresses), thus facilitating the reading of the result
into memory.

(Destination ) + (Source ) + (X) -) Destination

7
oAdd resses 0 Add resse: 0
Increasing
LSB LSB
DIGIT MS -.-J ~ DIGIT MS~-.-J ~ DIGIT MS addresses
(visualisation
of result)

+
I
Decreasing ddresse Addresses
addresses DIGIT LS /MjSB, DIGIT LSB ",M~B,t-D-IG-I-T-L-S--tB
(calculation) T ,.
1---==-_--i~·(An) ~·(An1)

Figure 6.13 The instruction ABCD -(An), -(AnI).

How it functions.

Program Example
The program of listing 6.7 demonstrates the use of the
ABCD instruction.

Listing 6.7

20
30
**********************************************************************
40
* USE ABC [I INS T RUe T ION
*
50
* II II
*
60
** WRITTEN BY: PATRICK JAULENT *
*
70 * EDITION : MACMILLAN *
80
****************************************H****************************
"100
-liD
** ADD THE SOURCE OPERAND TO THE OESTINATION OPERAND ALONG WITH THE
120 * EXTEND BIT (X), ANO STORE RESULT IN THE DESTINATION •
"130
·140 00002000
* OR6 $2000

160 002000 41F82024 LEA.L [)fSTINATION, AD ; INITIALISE POINTER DEST.

170 002004 43F8201E LEA.L SOURCE,A1 ; INITIALISE SOURCE POINTER.
 118 The 68000 Hardware and Software

'180
190 002008 7204
* MOVEQ 15-1,0'1 : NUt1BER OPERATION
200 00200A 023COOOF ANDI.B "OF ,CCR X:=o
210 00200E C'109 LOOP ABCD -(A'1) ,-(AD)
220 002010 51C9fFFC ClBRA 0'1 ,LOOP
230 002014 4E4'1 TRAP #'1
240 0020'16 0000 DC.W 0

260 002018 00000006 DS.B 6

270 ‫סס‬oo20"1 E SOURCE EQU *
280 00201E o00ooo06 DS.B 6
290 ‫סס‬oo2024 DESTINATION EQU *
300 EN[)

****** TOTAL ERRORS 0-- 0

SYMBOL TABLE - APPROXIMATELY 509 SYMBOL ENTRIES LEFT

DESTINAT 002024 LOOP 00200E SOURCE 002iJIE

Simulation
~:

~. S IMU!..(",l ION pr..~OGR(",M;

'* ::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
of(.

~. ()F~)TIN~~l ION::
'* ._.4 •.•. ".•"__ .' •. __ ._

~.)O·1 F .I:~
* OO;;?'O'IF 9B
.)f- O():~~O~~O '1()
* ()O;~?n;~~" '1 ~:i
* O();,:~()2~~ ~)O
:cf ()O~?()::? ::3 ) '1 0
·:tf OO:~?O:;~ it

*
*. SOURCE::
,~(. .. -- _.... _.._-
..:
.:> 20'19. B
* O()~?O'I ~.;I o;~
:If O()~?()·" A ~~ 0
:4- ()()~.?()., B {, 0
* ()():~~O·' C '10
OO;?O·, D HO
OO:~?O'I E
'*
2000; 13
-1(.

* RESULT > D(-:~~)TI~U~\TION

* __ _ --- __ .
*
20'1 F ) OO~.~()·1 E vono- 4076,·, 0090,·,

'*
* O[SINATION:
* :::::::::::::::::::::::::::::::::::
'*
?O'1F .B
()O~?O"'F 00
 68000 Insuuction Set 119

* O()~~()::~O 99
* OO~~():,:?·' 99
.:tf- 0020~~2 99
* O()~~()~~ ~3 99
* ()():':~o~~ 4
> ~
> * SORCE
~ SOURCE:
* __ . -
~

;.)()·19. B
* O()20·19 ()()
* 0020" A 99
* ()O:,:~()·' B 99
* ()o:~o·, C 99
* ()O~~()" f) 99
* ()()~~()·t E
)*
> *.
> 20()();G
> *
) * RESULT ) [)E~~TIN(-\TrON
> * -._._---_._-_.-..__._--.-_._-_..- _ .
} 20·1F > ()()~~()·1 F. 900·1-- 9999-" 9998···

DIVU and DIVS INSTRUCTIONS

1 Role of DIVU and DIVS

The orvu and orvs instructions tell the Me 68000 to
divide the 32 bits of a data register (destination) by
the 16 bits of one of the following

an operand orvu #16,d On

orvs #16,d On

a memory position Drvu saddr,d Dn

OIVS saddr,d On

the low order bits of orvu sOn,d On

a register On OIVS sOn,d Dn
2 How the Instruction is Executed
(Destination) : (Source) -) Destination

31 16 15 0 15 0

Dividend MSB Dividend LSB

I Divisor (Source)
I
16 15 0
Remainder Quotient
(destination) (destination)

L After operation, result available in ...

Figure 6.14
120 The 68000 Hardware and Software

See also the program in listing 6.8.

Details
Both source and destination cannot be an address
register.
Any zero division causes a trap.
If overflow occurs the 68000 does not carry out the
division (the registers are not modified) but sets V to
1.

Listing 6.8

***************************************************************~

) **
>
., [) I I..J U f~' ND () I I) S .. I N ~) T r~ U C T ION S *
*
~ *
) ****************************************************************
*
~: p ,~~ ('JGR (,,~'1::
..: ::::::::::::::::::::::

* $ B()C>1 [) II·~JU [)'1, DO

$"':~E?t. ..
Tr;~ ~,pI ..J

$/1E 7 '1 NOP

1){,OFE B '~f., -.:.
? 000 00 ?~.~.- BOC>1
O()20()~? 06D2-- i.E? l;. loading of program
~~OO/:. OOBE-· .liE7·1
;?006 09'1'1--60FE
> -.:.
:~ ~:

* FI f·~ST SI MI..lt..~Yr ION::

* _._-_ __ _-_ -_ _ --
-.:.
':> ~.

> ~:

. DO :: OOO()()()(lO -'OOOOFFFF Di vidend

• [)'1 ::. OO()()OOOO .- OO()OOOO~.~ Divisor
;p PC::: OO()';()O tt OO~:;() S:::O S OO() c::: SP ::: ()(}()()06()()
DO:::: O()()OFFFF 1)"1::: ()O()()()()()~~ D;~?::: ()()()O()()()() D ~3 ::: o()() ()() 000
[).It : : O()()()()O()() [)~)::: ()()()O()()O() [)6::: ()()()()0 ()()() o7 ::: ()()()()()()()()
(.~()::: OO()()OO()() A'1::: ()()()()()()()() A~~:: {)()()()()()()() ~'~3::: ()(){)()()()()O
f:'.It : : 0 () () () () o()() A ~:.i ::: () o()()()0 () o At.:::: ()()()()()()()O A7 ::: ()()()()() tJ() o

it: BFFOR E EXECUT :ro~

it: •.••• ---- - - .

2000; G Quotient
:P: ABR r PC::: ()()~~()()6 tt bOFE s-u s ()()C) c:::: sp:.-.: 0()()()()6()()
I)()::: ()()()"17FFF I)'" ::: ()()OO()()()~~ I) ~~ ::: () () () o()()()() 1):3:: ()()()O()(){)O
().Ii = O()()()()()()() [)~:;::: O()()()()()()() DtJ::: ()()()()()()()() ()? ::: ()()()()()()()()
A()::c ()()()()()O()() A "I::: ()()()()()()()() A~,~::: ()()()()()()()() (.'~3:= ()()()()()()OO
{V;:: ()()()()()()()() A~:;:::: ()()()()()()()() A6:::: ()()()()()(}()() A 7 ::: ()() () () 0 tJ00

Remainder
** AFTER EXECUTION
*
 68000 Instruction Set 121

~.

* SECOND S IMUlJ:~TION=
~( _ - --..- -'" _..

• D'" ::: OOOO()()()~~ .- 00000000 Di vi sor

• DO :: OOO"17FFF -- ()OCII=t:.~;.~;!;! Dividend
;R PC::: 0 () ~! ()() 6 •• 6 ()F E s :::() S ()() () C::: sp::: O()()()()b()()
D()::: ()()()() ~~:'2 2~? 0 ..,:-.: ()I] o()o()()() D~~? ::: ()()()() o()()() OJ::: ()()()(){)()()()
D,(:~:::: 0 OO()()O()() [)~:.i:::: O()O()()O()() Dt,::: O()()()()()()() [)7 :::: ()()()()()()()()
A o:: : ()()()()()()()o A"'::: oI.)() () n()() 0 f.' ~~ ::: ()()()()()()()() ~':3::: ()()()()()()()()
~'~I '1:: ()0 ()()()()()0 (-\ ~;j ::: () () 0 ()()()()() t, 6 :::: ()()()()()o()() ~~ 7 ::: O() () () () 6 0 ()

> it:
* BEFORE E)(ECUTION=
* _._- - _ _ .
'>
*
;~O()O;[i
~: [) I . . .1... E'~~ r~! 0000 OOO()()()O() 0000
REG = P C::: •• fiE? 6
()O~.~(}()~.~ ~>:::() S ()()O C::: •• Z.. SF'::: ()()()()()6()()
DO::: D'" ::: O()()()()()()()
()()I.)();:?:~~:':~~~ D~?::: ()()()I]()()()() D~3::: ()()()()()()()()
I).t,::: ()()()(]()()()() Dt}:::: O()()()()()O() D6::: O()O()()()()() [) 7 :::: ()()()()()()()()
(-,()::: O()()()()()I.)O (-\., ::: ()()()O()()()() ~,;~?:::: {)()()()()()()() A::3::: OO()()()OOO
{,.It:: ()()()()()()()() ~~ ~j::: ()()()()()O()() (,,6 :::: ()()()() D()()O A 7 :::: ()()()()06()()

> *
* [) II....'J:~n:ON H '( ZERO !!!
* .--._ __ _--
) *
* T1-.1 II:'~() s I MUl..~~ TION::
* _.- __ .
*• [)'1 ::: OOO()O()()() ··OOOO()()O.. .i Di visor
• DO :: OOO();?~~;,.~;..~ .. FFFFFFFF Di vi dend
~.

OOC); C)
;~
~(. TR'J.. ERR! O()()O ()()()()()()()() ()()()() V := 1
r~EG:: PC::: ooaon- tt'tE7"1 S:::() S O()() C::: • N.V. SP::: ooooueno
DO::: FFFFFFFF f)"I::: noouooc- D;~~::: (){)()(){)()O() IX3::: ()()()()()()OO
D4== O()()()()()()() os- ()()()O()()()() Dt,::: O()()()()()OO D7== ()()()()()()()()
A{):: {)()()()()()()() A"I :::: ()()()()()()()() (:\;~~::: ()O()()()()()() A~3::: O()()()()O()()
r., "J::= ()0 () () () () () () ~~ ~:i :::: ()()()()()()()() A 6 :::: () () () () () () () () A 7 ::: () () () () () 6 () ()

> ~
i(. .., ~I: ::·1 J F Ot..'ERFI...OloJ
-Jt; •• -..-- •• -••• ---.-.-- ..... -•• -....-- ••.•---..
~:

CHK INSTRUCTION

1 Role of CHK
The CHK instruction compares the 16 low order bits of a
data register with a bounded value.
By definition, the lower bound is zero and the upper
bound is a 16-bit number.

~----lssssssssssssss1ss~ Interval

~ ] TRAP

Lower bound (L)

/ \
Upper bound (H)

Figure 6.15
122 The 68000 Hardware and Software

The trap operates when the value that is examined,

which is contained in a register On, does not belong to
the interval.
It should be noted that for the CHK instruction the
inequalities are always strict.

2 Syntax of CUR
In assembler
CHK <ea>, On

Effective address -----' '-----Data register

In pseudo-code
IF On < L THEN
I TRAP CHK
ELSE
IF On > H THEN
, TRAP CHK
ELSE
I
Execution of next instruction
ENOIF
ENOIF

Application Exercises
1. Write in 68000 assembly language a program to search
for a value called entry in a table. If this entry
($OOOF for our example) is not found in the table
arbitrarily fixed at five words - the program will need
to be rerouted into the TRAP CHK, with the aim of
displaying the message "Value not found in table". On
the other hand, if the entry is present, the system
returns to the control of the monitor.
The algorithm used to search for the entry will need
to be established in pseudo-code and the program
written in position independent code.

Suggested solution

*Pseudo-code

/*STACK INITIALISATION*/
/*VECTOR CHK INITIALISATION*/
/*TABLE ADDRESS INITIALISATION*/
NUMBER : = 5
READ 1 VALUE IN TABLE
IF VALUE <> ENTRY THEN
NUMBER : = NUMBER - 1
IF NUMBER <> -1 THEN
, REPEAT
ELSE
 68000 Instruction Set 123

DISPLAY "VALUE NOT FOUND IN TABLE"

I
ELSE
ENDIF

I/*RETURN MONITOR*/
ENDIF

Listing 6.9

20
************************'********************'************************
** SEARCH A TABLE OF 5 WORDS FOR SPECIFIC OPERAND (#$DDOF) *
30
40
50 * IF NOT FOUND THEN "TRAP CHK" *
60 * THE PROGRAM IS WRITTEN IN A "RORG" SECTION *
70 * *
80
*****'*'***'*********************'****************'*******************
'100 oo01E178 OUTMES EQU ; SUBROUTINE PRINT STRING OF CHARS
'1'10 00000018 VECTORCHK EQU ; ADDRESS VECTOR TRAP CHI<
120 00000005 NUMBER EQU ; SIZE TABLE

'140 00002000 RORG $2000

160 002000 4FFA013E LEA.L STACK,SP ; INITIALISE POINTER SSP

'170 002004 41 FAOO1 C LEA.L TRAPCHK,AO ; AD:= ADORESS PROGRAM EXCEPTION CHK
180 002008 21C80018 MOVE.L AD, VECTORCHK ; INITIALISE EXCEPTION VECTOR CHK
'190 00200C 43FA0028 LEA.L TABLE,A'l ; INITIALISE ADDRESS TABLE
200 002010 7204 MOVEQ #NUMBER-l ,0'1 ; INITIALISE SIZE TABLE
2'10 0020'12 OCS9000F LOOP CMPI.W #$ODDF, (A'l)+ ; DO WHILE MEM[A'1 J <> I$F AND D'l <-'1
220 00~~16 57C9FFFA [)BEQ D'l,LOOP • ~ iREAO MEMEA'IJ; Al :=A'l+2
230 00201 A 43BCOOOS CHK INUMBER. D'l ; ENDDO
240 0020'1E 4E4"1 TRAP tt"l ; IF D"l <0 THEN "TRAP CHK"
250 002020 0000 DC.W o
270 00002022 TRAPCHK EQU ,
280 002022 48E7FFFE MOVEM. L DO-D7/AD-A6, - (SP)
290 002026 41FA0018 LEA TEXT .AO • INITIALISE AD BEGIN STRING OF CHARS
300 OG202A 4EB9000'1E178 JSR OUlMES
310 002030 4C(~7FFF MOVEM.L (SP)+, DO-D7 iAO-A6
320 002034 4E73 RTE

340 002036 OOOOOOOA TABLE DS.W ; STORAGE BLOCK FOR 5 WORDS

350 002040 20 TEXT DC. B THE OPERAND IS NOT FOUND IN TABLE ~ ~ ~ I

360 002074 OA DC. B $OA, $00,4

370 002078 000000C8 OS.L SO
380 00002'140 STACK EQU *
390 END

'***'* TOTAl ERRORS 0-- 0

SYMBOL TABLE - APPROXIMATELY 504 SYMBOL ENTRIES LEFT

LOOP 0020'12 NUMBER 000005 OUTMES 0'lE'178 STACk 002'140

TABLE 002036 TEXT 002040 TRAPCHK 002022 VECTORCH OOOO·IE.
124 The 68000 Hardware and Software

Simulation

**- S I ~1 U L. ~:, T ION P R o G ~~ AM:

* ::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
*iI: ;~ 0::-=:1.') • l·J IN;? OitO • l·J :: ~:) TOF~ AGE HL O[:I( F OR ~; WORos
i(. .-.-.-.- ~- -- -- -. _.•_- _. _..•.• _. _._._ ..•• -- -- _. _._ .. _. ---- -- --.- --- .. - .. - •• _-- ._-- •.. -- _•• - --'-' -- -- -_.- -_.-

'*
;~O:]f.:'.l·1
.)f OO~?():36 0000
-:tf ()()~?O~3B 6666
* O()~~f)::3f~ EHlElH
* OO~?()]C () nDn
:* O():~?O::3E 999~.)
.:11: OO~?040 > OOOF
* ()() ~? 0 I.. :~?
;'>OO();!3 THE OPER(-\ND IS NOT FOUND IN TABLE !!!

?O::-::o!:•• lol
.:11: O()~?()3,:':, 0000
:11: O()~?O:3B (it!.·;.b6
)(0 ()()~?()~3~~ BBHB
.:. ()0 :-:? () ::3C EEEE
':'(0 ()()~-?()]E OOOf~
:.. OO~?()40
;.~OO(); (oJ
:> ~

*
i(.
CORF~ECT
_._- •. '.00.00_.,_,

2. The program that follows is especially interesting

since it allows the following expression to be tested

- INi ~ number ~ + ~N!

Listing 6.10

20
************************************************'*'**'*'*'***'*'**************
30
*
40 * EXCEPTION: CHK INSTRUCTION
*
50
'*' -I NI =<: NUMBER =<: +INI '*'
60
*
70
*' *
80
***********************************************************************
-100 ooo1E'178 OUTMES EQU ; MONITOR SUBROUTINE PRINT CHAR
1'10 00000018 VECTORCHK EQU VECTOR TRAP CHK

'130 00002000 ORG $2000

'150 002000 4FF820E6 LEA.L STACK.SP INITIALIZE STACK POINTER SSP

160 002004 21FCOOOO2034
00'18 MOVE.L #TRAPCHK, VECTORCHK INITIALIZE CH~; INSTRUCTION
'170
'180 00200e 3"1 FC-1 0002048
* MOVE.W #$'1000.H : LIMIT H
 68000 Instruction Set 125

190 002012 3"1FCEOO0204A MOVE.W #-$2000,L ; LIMIT L

200 0020·18 3038204C MOVE.W NUMBER, DO ; LOAD NUMBER FOR CHECK
2"10
220 0020'1 C 9078204A
* SUB.W L~DO : DO:=DO-L
230 002020 3238204A MOVE.W L,D"! : Dl:=L
240 002024 93782048 SUB.W D'l,H : H:=H-D1
250 i

260 * ----------[--------]----------
270 * L=-$2000 NUMBER H=$'1000
280 i
290 002028 41B82048 CHK H,DO IF DO < -$2000 THEN
300 00202C 0078204A AOO.W L,OO ~ i* TRAP CHK *i
310 002030 4E41 TRAP #·1 ELSE IF DO> $·1000 THEN
320 002032 0000 DC.W 0 ~ 1* TRAP CHK */
ENOIF
330
340
* ENDIF
*
350
3bO 00002034
*
TRAPCHK EQU *
370 002034 48E7FFFE MOVEM.L 00-07/AO-Ab,-(SP) ; SAVE ALTERED REGISTERS
380 002038 4·1F8204E LEA.L TEXT,AD ; AD:= a TEXT
390 00203C 4E89OOO1E178 JSR OUTMES
400 002042 4COF7FFF MOVEM.L (SP)+,OO-(J7 iAO-Ab ; RESTORE REGISTERS
410 002046 4E73 RTE

** RESERVE
420
430
440 * -------
450 002048 000‫סס‬oo2 H DS.W : ADDRESS LIMIT H
460 00204A 00000002 L DS.W ; ADDRESS LIMIT L
470 00204C 00000002 NUMBER DS.W ; NUMBER FOR CONTROL

490 00204£ OA TEXT DC.B $OA,$OD

500 002050 20 OC.B TRAP CHK
5'10 00206A OA OC.B $OA,$Q[),04
520 00206E 00000078 DS.L 30
530 000020E6 STACK EQU *
540 END

**f*** TOTAL ERRORS 0-- 0

Simulation

> it S IMUI.~f~TION PI~OGRAM~

.... ::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
~.

..
11: ~?O'1C .u ::: NUi'1BEr~ FOI~ CONlf.-~OI..

~!()"C .loJ
* OO:-:?O'tC ·1000
* OO:-:?04E
:> ~~OOO; Ci

-!(

;,~Oi",C Ilil
* O() ~-:?O 4C ) ·10()-1
* on~-:~()'tE >
;~()OO; G
Tr~AP CHI(
126 The 68000 Hardware and Software

..'*
:.

;?()'1C • ~.J
00:20 -c ) E O()C)
* OO:;?Ol.tE
> '*
~~OO() ;G
~.

204C.W
* ()()20'tC DFFF
* ()O~~()4E
>
>
*
;.~()O(); (.)
TRAP CI-II(

*
*
;~()LtC • W
* O()~~?()4C FFFF
* O{)~~04E >
~~ OOCl; (~

MOVEM INSTRUCTION

I Role of MOVEM
The different versions of the MOVEM instruction
transfer, according to a predetermined order, a list of
address and/or data registers to or from a block of
memory.
The second word of the instruction (the first always
being the op-code) is established from a l6-bit order
table, in which each register occupies one bit, so that
any combination of the 16 registers can be specified by
the instruction.

2 Syntax of MOVEM
Whatever type of transfer is involved, whether
registers to memory or memory to registers, the size
specified by the instruction is word, which is the
default size, or long word.

1. We take as a first example the transfer of a list of

registers to a block of memory (see figure 6.16).

MOVEM.W Al/A5/D2/D4,$1000

MOVEM.W instruction mnemonic and size (word)

Al/A5/D2/D4 list of registers whose 16 LSB bits are
transferred to the memory block.
$1000 destination effective address
automatically incremented by two if the
size is word (or by 4 if it is long word)
 68000 Instruction Set 127

Memory
15
Me 68000
~o
1(J~~ 02 - 15 0

--...
~ 02 I
1_t>~2 04 .- 15 0
nA I
1t>04 A1 ,. 15 0
A1 I
A5 15 0
1~;8 ~ A5 I
1f)f)A

~
Order table

Increasing addresses
<
Figure 6.16 MOVEM.W A1/A5/D2/D4,$lOOO
Memory
31
o 68000

SP
after ~
execution
t-----... ~

SP
before
execution

Order table
Memory to registers transfer only

<----------------
Figure 6.17 MOVEM.L AO-A2/DO-D2,-(SP)

2. Our second example is the transfer of a list of

registers to a memory block (stack) in predecrement
mode (see figure 6.17).

MOVEM.L instruction mnemonic and size (long word)

AO-A2/DO-D2 the 32 bits of each register in the list
are transferred to the stack.
-(SP) stack pointer requested in predecrement
mode
128 The 68000 Hardware and Software

Listing 6.11

20 **********************************************************************
30
40 USE IN~;TRUCTI0N
50
60 **********************************************************************

80
90 * COpy N BYTES FROM ONE LOCATION TO ANOTHER LET L (LENGTH) BE
"100 * 2048 (2 K BYTES)
1·10 * EXEMPLE: 2048/32=64 LOOPS
120 it' -------

·130 *
·140 * AD =POINTS TO THE SOURCE BLOCK
·150 * Al =POINTS TO THE DESTINATION BLOCK
'160 * DO =NUMBER OF 32 BYTES TO MOVE
·170
·180 00002000
* RORG $2000

200 002000 4·1FAFFFE LEA. L SOURCE-32, AD ;POINTER TO SOURCE

2·10 002004 43FA'1 0·1 A LEA.L DESTINATION,A·1 ;POINTER TO DESTINATION
220 002008 303C0800 MOVE. W #64*32, DO ;COUNT BYTES TO XFER
230 *
24D 00200e 4CF004FEOOOO LOOP MOVEM.L D(AO. DO.W) ,D"l -D7 !A2 = REPEAT
250 0020·12 48E17F20 MOVEM.L D·l-D7.1A2.-(A"l) *
• I MOVE DATA IN*,i
260 0020·16 04400020 SUBI.W #32.DO ; ~ 1* SEND DATA OUT *1
270 0020·1A 66FO BNE.S LOOP • ~ [;0:=DO-32
280 00201 C 4E41 TRAP #·1 ;UNTIL DO=D
290 0020-1E 0000 DC.W 0

310 00002020 SOURCE EQU *

320 002020 00000800 DS.B 64*32
330 002820 00000800 DS.B 64*32
340 00003020 DESTINATION EQU *
350 END

'***'* TOTAL ERRORS 0-- 0

SYMBOL TABLE - APPROXIMATELY 509 SYMBOL ENTRIES LEFT

OESTINAT 003020 LOOP 00200C SOURCE 002020

3. Our third example is the transfer of a memory block

to a list of registers in postincrement mode (see
figure 6.18).

MOVEM.L (SP)+,DO-D7/AO-A6

MOVEM.L instruction mnemonic and size (long word)

(SP)+ stack pointer used in postincrement mode
DO-D7/AO-A6: list of registers loaded with the contents
of addresses pointed to by SP*.
 68000 Instruction Set 129

*Note that the intervals of a list of registers are

indicated by dashes and the different register names by
the slash symbol. For example,
AO-AJ/DO-D4 means AO, AI, A2, A3 and DO, Dl, D2, D3, D4
AO/A4/DO/D6 means AO, A4 and DO, 06.

Memory Me 68000
31 ~~
»31 0
SP
before ~ 00
~ Of)
execution 01
01

02
02

1
03 03

04 04
Increasing 05
05 addresses
06 06

07 07
31 0
A0 A0
A1 A1
A2 A2
A3 A3
A4 'f

--
A4
A5

--- .....,
AS
SP A6
--
A6
after ......

~
execution
SPI I

Increasing addresses
<------------------4

Figure 6.18 MOVEM.L(SP)+,00-07/AO-A6

MOVEP INSTRUCTION

The MOVEP instruction facilitates access to the

peripheral devices that occupy alternate bytes in a
memory area.

1 Some Reminders about Addressing

When the Me 68000 processor wishes to interact with an
8-bit memory location, it uses the internal bit AO to
select the even address (AO =~ or odd address
(AO = 1) and the outputs LDS and UDS to enable
the lines, whether lower 00-D7 (LOS = 0) or upper
D8-D15 (UDS = 0).
130 The 68000 Hardware and Software

2 Role of MOVEP
The MOVEP instruction allows one to prcgram the 8-bit
peripheral circuits of the MC 6800 (PIA 6821, PTM 6840)
or MC 68000 (PI/T 68230) via the lower line (DO-D7) if
the peripheral address is odd, or via the upper line
(D8-DlS) if the address is even.

3 Syntax of MOVEP
In assembler

MOVEP.W d16(An),Dn Read from

MOVEP.L d16(An),Dn peripheral

MOVEP.W Dn,d16(An) Write to

MOVEP.L Dn,d16(An) peripheral

4 Programming Examples

Without using MOVEP

Let us assume that we wish to program the PIA 6821
circuit according to the model shown in figure 6.19,
assuming that this circuit occupies odd addresses (4)
that are programmable via the lower line.

VPA~-----

A3-A23

68000

Figure 6.19 Programming: ports A and B on output;

interrupt on CAl authorised; access to ORA and ORB.
 68000 Instruction Set 131

Even Odd
addresses addresses
15
0

>< DORA
ORA $ 1DFF1

>< $ 1DFF3

>< CRA $ 1DFF5

>< CRB $ 1DFF7

Figure 6.20 Memory positioning of peripheral

Program *Equivalences*

PIADOA EQU $lDFFl Direction/data registers

of port A
PIADOB EQU PIADOA +2 Direction/data registers
of port B
PIACRA EQU PIADOA +4 Control register of port A
PIACRB EQU PIADOA +6 Control register of port B

*Program*

MOVE.B #$FF,PIADOA Port A on output

MOVE.B #$FF',PIADOB Port B on output
MOVE.E #$05,PIACRA Interrupt authorised
on CAl, access to ORA
MOVE.B #$04,PIACRB Access to ORB

The above is exactly the same method of programming

as with the MC 6800.

Using MOVEP

Program *Equivalence*

PIADOA EQU $lDFFl Base address of peripheral

circuit
MOVE.L # PIADOA,A6 Base initialisation
address
MOVE.L #$FFFF0504,Dl Loading of command long
word of PIA
MOVEP.L Dl,0(A6) Transfer of contents of 01
to alternate byte memory

After each byte transfer, the address specified by

A6 is incremented by two (register A6 is not modified).
132 The 68000 Hardware and Software

Programming Exercise
Let us suppose that we want to write in 68000 source
language the initialisation program of N peripheral PIA
6821 circuits. The operands (32 bits) belonging to each
peripheral circuit are stored in a table, whose begin
address is MEMTABLE.

Even Odd
addresses addresses

~ Peripheral

PIA@
~----+------·n

MEMTABLE ~

• Set memory of
® 6821 peripherals

*Table of
operand storage

Figure 6.21

Program
MOVEQ # N,DO Initialisation of number
of peripherals
LEA MEMTABLE,AO Loading AO with
MEMTABLE address
LEA PERIPHERAL,Al Loading Al with
peripheral address
BRA IN Adjustment of
primitive DBF
 68000 Instruction Set 133

LOOP MOVE.L (AO)+,Dl Loading of programming

long word (AO) + 4 -) AO
MOVEP.L Dl,O(Al) Transfer of operand to
8-bit peripheral
ADDQ.L #8,Al Incrementation of
table pointer
IN DBF DO,LOOP
END

LINK AND UNLK INSTRUCTIONS

1 Role of LINK and UNLK

These high level instructions allow automatic
allocation of an area of memory used for the storage of
local variables or for the passing of parameters
between two programs.
These instructions simplify the writing of reentrant
subroutines that work on areas of memory that belong to
the calling program, or shareable subroutines that can
be shared by several users.

2 Syntax of LINK and UNLK

LINK (with stack)

Assembler notation

LINK An, # displacement

LINK instruction mnemonic

An represents the block pointer
(frame pointer FP). Only
address registers AO-A6
can be used as FP, as A7
represents the stack pointer.
# displacement signed l6-bit displacement
(-32768 ~ d ~ + 32767)

The value of the displacement included in the LINK

instruction is used to decrement the stack pointer so
that it frees a memory location when it is required for
storing local variables or parameters. These variables
need to stored in relation to the frame pointer.
134 The 68000 Hardware and Software

Method of Operation

Stack

1111

Figure 6.22

1. Saving of the contents of FP to the stack.

2. Creation of a new FP with the contents of SP.
3. Reserving of a work area fixed by the addition of SP
with displacement.
UNL(IN)K (disconnection of stack)
Assembler notation

UNLK An

UNLK instruction mnemonic

An represents the frame pointer
(block pointer)

Method of Operation

31 0
FP ® Stack
~SP

Figure 6.23

1. The stack pointer (SP) is loaded with the contents

of the frame pointer (FP).
2. Register FP is loaded with the contents of the
address pointed to by SP.
 68000 Instruction Set 135

Example
Reserving an area of memory between the main program
and the stack pointer

LEA $ 2000,SP Initialisation of stack pointer

LEA $ 2002,A6 Initialisation of frame pointer

LINK A6,#-4 Reserves two words in common zone

NOP
NOP
JSR INPUTBCO Call subroutine
INPUTBCO (1st number)
JSR INPUTBCO Call subroutine
INPUTBCO (2nd number)
MOVE.W (A6)+,OS (A6) -) OS ; (A6) + 2 -) A6
MULU (A6)+,OS (A6) x (OS) -) ; (A6) + 2 -) A6
UNLK A6

Rest of main program

INPUTBCO *Capture of ASCII character from keyboard

*Conformity test
*Conversion of ASCII character to binary
(OS contains the binary number)
MOVE.W OS,-(A6)
RTS
We shall now examine the above program in detail.
The two instructions LEA $2000,SP and LEA $2002,A6
load the stack pointer SP with $00002000 and the frame
pointer FP with $00002002.
The instruction LINK A6,#-4 causes the following
operations to occur.
1. The "old" FP value (the 32 bits of A6) are saved
to the stack.
Workspace
15
Q

Increasing
addresses
31 0
SP (A7) I 0000 2000 I~
FP (A6) I I ~ J-------e
I-----~
0000 2002

Figure 6.24 (Part)

136 The 68000 Hardware and Software

Workspace
15
o

Reserved
Reserved
31 0
New FP (A6) I 0000 1 FFC I~ 0000
t--------4
2002

Figure 6.24 (Continued)

2. A new FP is created with the contents of the

stack pointer SP (remember that SP has been decremented
by 4 during the previous operation).
3. A location is reserved in the stack to store two
words (4 bytes).
The NOP (no operation) instructions are there to
represent the programming of the peripheral circuit
(Pl/T 68230 or AClA 6850) connected to a keyboard
which, for the purposes of this example, we have not
considered it necessary to write.
JSR INPUTBCD, after the return address has been
saved to the stack, causes the CPU to jump to the
subroutine INPUTBCD.

PC high
PC low
Reserved
Reserved
I
FP (A6) 0000 1 FFC I ~ ...--------4
0000

2002

Figure 6.25
 68000 Instruction Set 137

The subroutine INPUTBCD, whose different sequences

have been omitted intentionally, instructs the MC 68000
to
a) fetch an ASCII character from the keyboard and
carry out a conformity test on the character obtained;
b) convert this character into binary (05 contains
the binary number);
c) store the first number fetched in the reserved
area of memory, this operation being carried by the
instruction MOVE 05, -(A6), before returning to the
calling program via RTS.
Workspace
15

PC high
PC low
SP
after I 0000 1 FF8 I ~ Reserved 31 16 15 0
FP I
(A6) .. 0000 1 FFA ,
after I~ 1st number -------- ~~~~~~]1st numberl 05
F'P (A6) L_Q.C!.02_!.!:.':9_J ~ -0000 MOVE.W 05, -(A6)
before 2002

Figure 6.26

Instruction JSR INPUTBCO causes the processor to

make a new call to the subroutine INPUTBCO, with the
aim of storing the second number in reserve.
Instruction RTS returns control to the calling
program (SP after RTS points to the second number
fetched) .

16
o

PC high
PC low
2nd number
BCD
1st number
BCD
0000
2002

Figure 6.27
138 The 68000 Hardware and Software

Instruction MOVE.W (A6)+,05 loads the LSB word of

the data register 05 with the contents of the address
pointed to by register A6(A6 = FP)i A6 is then
incremented by two in order to complete the addressing
with postincrement.

FP (A6) ~1 . ~ 31 0
before L_~_!_~E~__ J ~n------~----t
2nd number
BCD ~ 1- 0000 1 FF8 ISP
FP (A6) I 0000 1 FFA I ~ 1st number
BCD
after u--;;...;;;"o;.......--..
0000
2002

unaffected

Figure 6.28

The next instruction MULU (A6) +,05 carries out the

unsigned multiplication of the 16 bits pointed to by A6
with the 16 low order bits of register 05. The 32-bit
result is available in 05. The content of A6 is then
incremented by two (postincrement), which positions FP
at address $OOOOIFFC.

15
o
2nd number
BCD
1st number
BCD
0000

2002

31

Figure 6.29

Instruction UNLK A6 causes the following

1. Loading of SP with the contents of FP.
2. Loading of FP with the contents of the address
pointed to by SP (SP is incremented by 4 after this
opera tion ) .
 68000 Instruction Set 139

E
FP
i
31 0
0000 1 FFC ~ 0000
--~ 0000 L2002 IFP (A6)
CP-.------------. 2002
t------f After instruction
• 00001 FFC :
... _------------~
SP
CD
31 0
I 0000 2000 I
SP
After instruction

Figure 6.30

The following example illustrates the value of the

LINK and UNLK instructions in the writing of a
subroutine that can be called by several users.

,otiedulre 8

I}/
~~/--....

§o/ \
~O/
(j~,/;:- /
;/ s
., 1
LINK SP # d1~ t: JSR
LEA src, SP
LEAsrc, FP
I~I Procedure B

I
I
I 8 / ATE
I
I ~ / @
I ~ I
I
I ~
&. I
Return I
I I g
Interru~ I .~
I I ~
g'"
~I
I
I
I
\
Re't\'S
"
~.:<.<::-
I I ,
I
I I I
I
I
I I
I U~LK /
I RTS /
I
I @
JMP return

Figure 6'.31
140 The 68000 Hardware and Software

Simulation (see figure 6.32)

Program (A) calls the interruptable procedure (B) by

means of instruction JSR PROCEDURE B.
The first instru~tion of procedure (B), namely LINK
FP,#dI6, reserves for calling program (A) its own
working storage area.
While executing procedure (B), the processor is
interrupted by an external device (hard or soft
processor). After recognising the interrupt, the 68000
saves the program counter and the status register to
the supervisor stack, before executing the exception
program (C) which itself calls procedure (B) (JSR
PROCEDUREB).

15
0

SP~
Memory block \
allocated to
program (C)

FP~ MSB of FP
LSB of FP
( LINK FP, # d16

~
Address of return
JSR Procedure 8
to program (C)
Status J
PC high Save on
interrupt
PC low

Memory block
allocated to J
program (A)
t LINK FP, #d16
MSB of FP
LSB of FP )
Address of return
to program (A) ~ JS R Procedure B

SP~

FP~

Figure 6.32

In a manner similar to the first call of procedure

(B), the calling program (C) is provided with its own
workspace.
 68000 Instruction Set 141

After it has executed procedure (B), the Me 68000

repositions the frame pointer at the state prior to the
interrupt by executing the instruction UNLK FP.
Instruction RTS orders the processor to return to
the exception program which has to terminate with the
instruction RTE, in order to ensure return to procedure
(B) for the program to continue. Of course, the
workspace currently defined by the frame pointer
belongs to program (A).
Instruction UNLK FP resets register FP to its
initialisation value, before executing RTS which allows
it to return to program (A).

Example of the use of LINK and UNLK

Listing 6.12

30
***************************************..*....********..****..******..***..****
40 * ..
50 * USE 0 F ilL INK and U N L K INS T RUe T ION S * I!

60
70
*
80 ******************************************************************'*******
UNSIGNED DIVISION:
90 *' ------------------
'100 * THE SIMPLEST BINARY DIVISION ALGORITHM IS ALSO BASED ON THE TECHNIQUE
"1'10 * WE LEARNED IN GRAMMAR SCHOOL.
'i20
'130 ** DIVISION: 64/32 = 32 BITS REMAINDER
'140 * = 32 BITS QUOTIENT
150 * ALGORITHM PSEUDOCODE
II II

"160 * =====================
"170
'180 * PROCEDURE DIVISION 64 BITS
'190 * I

200 .. ~ STATUS :=0

2'10 * DOlL :=MSB DIVIDEND
220 * D"lIL :=LSB DIVIDEN[)
230 *~ IF DOlL >= DIVISOR THEN
240 .. ~

250 * i* WRITE : II DIVIDE OVERFLOW " *1

260 * 1* WRITE : II DIVIDE BY 0 *1
270 *~ STATUS :='1
280 *~
290 *~ ELSE
300 *~ I COUNTER: =32
3"10 * DO WHILE COUNT <>- 0
320
330
*
* [r1.L:= D·1.l*2
340 * DO.L:= DO.l*2 WITH X
350 *
360 *~ IF C='l THEN
370
380
** [i"l.L:=Dt .l+"!
390 .. DO.L:=DOIL-DIVISOR
400 * I ELSE
142 The 68000 Hardware and Software

4'10 * i I

420 * IF [lO.L >= DIVISOR THEN

430 *~ I I

440 *' i I ! O'1.L:=[l·1.L.d

450 *' i I I I OO.L:=DO.L-DIVISOR
460 * I : I

470 *' ~ I I ENOIF

480 *' ~ I ENDIF
490 I ,

500
*' COUNTER:=COUNTER-'l
*' I

ENODO
510
520
*'*' I ,

530
540
* I REMAINDER :=OO.L
QUOTIENT :=(il.L
550 *' ~
560 *~ ENOIF
570 *' ENDPROCEOLIRE
580
*'

600 ..
6'10 *' MACRO
620 .. -----
630 SHIFT64 MACRO
640 \!i LSL.L #'1, \1
650 ROXL.L 1H.\2
660 ENDM
b70
680 **' IN£iEX TABLE
690 * -----------
700
7'10 00000000
*
OLOFP EQU o .OLD FRAME POINTER
720 FFFFFFFE COUNTER EQU OLDFP-2 : COUNTER
730 00000008 OVSR EQU OLOFP+8 .OIVISOR <INPUT)
740 OOOOOOOC MSBDVD EQU OlDFP+'12 :MSa DIVIDEND <INPUT)
750 000000'10 LSBOVD EQU OLOFP+'16 ;LSB DIVIOEND €.INPUT)
760 00000018 STATUS EQU OLDFP+24 ; STATUS
770 OOOOOO"lA REMD EQU OLDFP+26 ; REMAINDER t.OUTPUT.i
780 OOOOOO'lE QUOT EQlI OL[fP+30 ;QUOTIENT (OUTPUI i
790 000"1E'178 OUTMES EQU $'1E'178 : OUTPUi STRING OF CHARS

8'10
820 *' D'1.L = LSB DIVIDEND
830 * DO.L = MSB DIVIDEND
840 * M.L = FRAME POINTER
850 *' A7.L = STACK POINTER
860

880 00002000 RORG $2000

900 002000 4FFAO'i 96 LEA. L 8TACK •A7 INITIALISE POINTER SSP

9'10 002004 OFFCFFFFFFF2 AOO.L #-14.A7 RESERVE SPACE FOR OUTPUT PARAMT
920 *
930 00200A 2F3AOOB2 M01JE.L LSBDlvlliEND.-(A7)
940 00200E 2F3A007 Ii MOVE.L MSBOIVl[iEND, -(A7)
950 002012 2F3A007E MOVE.L DIVlSOR.-(AT;
960 0020'16 6'122 BSR.S DIVISION PROCEOURE DIVISION
970
 68000 Instruction Set 143

980 002018 4A5F TST.W (A7)+ IF STATUS o 0 THEN

990 00201 A btrl0 BNE.S ERROR ! 1* WRITE ERROR 1.1
1000 0020-1C 4-1FAOO7C LEA.L MEMREMAINOER, AD
-10'10002020 209F MOVE.L (A7)+,(AQ)
1020 002022 4'lFAOO72 LEA.L MEMQUOTIENT ,AD
-1030 002026 209F MOVE.L (A7)+,(AO)
"1040 002028 4E41 RETURN TRAP
_1 RETURN EUROMAK 68000
"1050 oo202A 0000 OC.W o
1~0 *
'1070 00202C 4-1FAD070 ERROR LEA. L STRINGERROR, AO
1080 002030 4EB9000-1E"178 JSR OU,MES
'1090 oo203b 508F ADOQ.L #B,A7
'1100 00:;:1)38 60EE BRA. S RETURN
tUO
-H20 ** PROCEOURE DIVISION
-1130 * ==================
1'150 00203A 4E56FFFE DIVISION LINK A6,#-2
1-160 00203E 426EOOl8 CLR.W STATUS(Ab)
'1'170
'1180 002042 202EOOOC
* MOVE.L MSBDVD (A6) , DO ; DO.L:=MSB DIVIDEND
1'190 002046 222EOO'10 MOVE.L LSBDVO (A6) ,01 ; D'1.L:=LSB DIVIDEND
1200 00204A BOAEOOO8 CMP.L OVSR(A6), DO
12'10 00204E 6506 scs.s OK
1220 002050 526EOO'18 ADOQ.W #1,STATUS(A6) ; STATUS:='1
'1230 002054 6026 BRA.S EXIT
'1240
'1250 002056 307C0020FFFE OK
* MOVE.W #32,COUNTER (A6)

'1270 SHIFT64 [;-1. DO

-1270 00205 C E3B9 aDOl LSL.L ~t-1, [l'l
-1270 00205E E390 ROXL.L #'1,[10

1290 002060 6506 scs.s INeRt

-1300 002062 BOAEOOOB CMP.L DVSR (A6)• [1(1
-1310 002066 6506 scs.s LOOP-!
'1320 002068 5201 INCR'l ADOQ.B ~t-1 ,D1
-1330 00206A 90AEOO08 SUB.L DVSR(A6), DO
1340 00206E S36EFFFE LOOP"! SUBQ.W #"1, COUNTER(A6)
'1350 002072 bEE8 BuT .S aDO·1
"1360
'137D
1380 002074 2[J4000'l A
* MOVE.L DO, REMD(A6)
'1390 002078 2D4'100'lE MOVE.L Dl,QUOT(A6)
'1400 002D7e 4E5E EXIT UNLK A6
'1410
-1420 oo207E 2F5700-10
* MOVE.L (Ai), '16(A7)
-1430 002082 DFFCOOOOOO-1 0 ADD.L #·16,A7
-1440 002088 4E75 RTS

'1460 00208A 00000004 MSBDIVI[;END DS.L '1

·1470 oo208E 00D00004 LSBDIVIDEND DS.L -1
'1480 002092 00000004 DIVISOR DS.L
-1490 002096 00000004 MEMQUOT 1ENT [IS. L -1
-1500 00209A 00000004 MEMREMA 1NDER DS. '_ 1
"1520 00209E OA STRINGERROR OLe· $OA.$OD
-1530 0020AO 20 DC.8 DIVISION BY C OR QUGTIENT TOO BIG ~ ~
144 The 68000 Hardware and Software

'154D 0020CD OA DC.B $OA~ $OD ~4

"1550 002000 000000C8 DS.L 50
'1560 00002-198 STACh EQU
"1570 END

****** TOTAL ERRORS 0-- 0

SYMBOL TABLE - APPROXIMATELY 486 SYMBOL ENTRIES LEFT

Simulation

i1:
> *- S I ~~ UL.. ~~\ T ION () I I...J I ~:; I ON
*- ::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
:> '*
) ~. L :::: MSB [) P)IDEND
?OB~:,.
'> '* .L::: LSB DJ:I..JIDEND
;!.Oe~E
:,; 2 09~.~. l..:::: 0 I I) I ~:;Ol~~
* ;'>096. L:::: QUOT TENT
~li: 20':';'(.\. l..::: F~ Et'1{1l:N()EI~~
~;

>- ~:.

.i.
~'>OB~~
:-.. 0020B1-":j 00000000
:'tf ()O~?OBE FFFFFFFF
* ()()~?()9~~~ O()O()OOO~~
* ()():~?()96 ClOOOOOOO
:rf O()~~?()9f; o (lO()OI]OO
:~ ()()~?()9E

> ~.~OOO; G
> ~.
> i1: [) I f.)PI..~~ y R E~~UI... T
'* .
*
P RNT.1.. BEG> ;,iOB(.\ END> ;?09A
* O()~?()BO O(l100FFe oononoi I] .ttE7~)()O()() O()()OFFFF
.-:. O()~~()9() FFFFO()()() O()()~.~7FFF FFFFOOOO OO()'10(-\(l[)
> ~.

~. 0 I '..JI S ION B Y () !!
it: :::::::::::::::::::::::::::::::::::::::::::::::::::::::::
i1:.
;.>OH(-\.l..
.:et- O()~?()B{~ 00000000
·)fo ()()~?()BE A t'::\I~~\~~'I~~\(.I~:\{.'
* O()~-~()O:;~:;? ) 00000000
:* ()O~.~09I,S
> ;.~OO(); G
DIVISION BY 0 OR QUOTIENT TOO BIG !!

'*
.;:.
'* QUOTlENT TOO BIG !!
*- :::::::::::::::::::::::::::::::::::::::::::::::r~ :::

;~OHA .t.
:If- O()~?08~~ '1 0000000
* ()()~~OBE OOOO()()()O
~~ (J o:~~ ()<? ~~ oOOO()()();.~
* (){):~~()(?6
> ;?OOO; G
DIVISION BY 0 or~ QUOTIENT TOO BIG ,!
 68000 Instruction Set 145

*
*.
?OB(.l.L
OO~~()8~~ o()00 000 ..,
OO;":~()(3[ ()00()0 00 o
O():~~()9:;~ OO()OO()O~.~
* O()~~O~?I,S
;~OOO:: C";
Pf·~NT .1.. BEG) ~,~OBA END >~?091~~\
* ()()~~?OBO DO" ODFFe O()()()()O·, () 4El~)O()O() 000" 0000
.-: O()~.)OC)() OO()()(J()()O O()O?B()()() O(l()()()()()() O()()()()AOl)
-9:

TAS (Test and Set) INSTRUCTION

1 General Aspects of Semaphores

Definition
When several processors (hard or soft) use one and the
same resource (printer, working memory, etc), we shall
speak of a shareable resource. It is vital, in order to
ensure synchronisation between the processors and the
resource, to assign a semaphore register (register or
memory byte) to the resource. (For example, the
peripheral circuit 6809/68000 IPC MC 68121 has six
semaphore registers.)
A semaphore register is made up of one or more flags
allocated to the same resource which inform the
programmer about the availability of the resource (SEM
bit) and about the arbitration between several
processors (bit ownership in the case of the Me 68121).
Generally, when the SEM bit is at 1 it indicates
that the resource assigned to this semaphore is
occupied, while SEM bit at 0 shows that it is
available.

Method of Operation
The method of operation is very simple. If in a
multiprocessor environment a particular processor
wishes to use a shareable resource, it must first
establish that it is free, by reading the semaphore
register; it then modifies the SEM bit to reserve the
resource for itself (that is, if it is available) and
writes the SEM bit in the semaphore register.
When the processor has finished using the resource,
it makes it available again by resetting the SEM bit to
o.
Example
Two processors, PI and P2, share the same resource (a
peripheral connected to a printer) within a multi-
processor system.
146 The 68000 Hardware and Software

Let us assume that processor PI wishes to access the

shareable resource first;in order to do this it reads
the semaphore register allocated to this resource and
tests the SEM bit.

Processor Pl Processor P2

Read

Yes Yes

f SEM bit set to 1 SEM bit set to 1

Modify

~
t
Write

SEMbit--.

Semaphore register

Figure 6.33
(Note that in the case of the TAS instruction branch
Ll, L2 does not exist. If the resource is occupied
(SEM = 1) the processor continues with the program.)

Bit SEM set to 0 indicates that the the resource is

available, as processor PI finds.
Processor P2 can only assume control of the bus
after it has set SEM to 1 (SEM = 1 indicating that the
resource is occupied).
 68000 Instruction Set 147

When processor P2 also wishes to access the

resource, it reads the semaphore register and, after a
test, confirms that the resource is available. Next,
processor P2 sets the SEM bit to 1 in the semaphore
register, thus surrendering the resource that it was
occupying.
However, before using the resource, processor PI
reassumes control of the bus. Processor PI continues
execution of its program by setting SEM to 1 (we should
not forget that the bus transfer took place before SEM
was set to 1), before storing it in the semaphore
register. The resource has therefore also been reserved
by Pl.
What would happen if the resource was a peripheral
like the MC 68230 connected to a printer?
One can envisage catastrophic results. To conclude,
this method can only be used if the read/modify/write
cycle cannot be interrupted, or in other words it is
indivisible.

2 Definition of TAS (Test and Set)

The TAS carries out the following during a single bus
cycle
reads the destination byte
modifies the condition codes (Z and N)
writes a 1 in bit 7 of the destination byte (the
other bits are unaffected).

3 Syntax of TAS
In assembler

TAS dst

Instruction
mnemonic ---------------
t , Oestination
address

Flowchart and Pseudo-code

Question
What is the difference between the instruction BSET
#7,dst and the instruction TAS dst?

Answer
These two instructions require the CPU to read the
destination (memory byte), modify its value and write a
1 in bit 7 of the destination.
However, instruction TAS dst must be used if two
processors share the same resource (dst represents the
semaphore of the resource). During execution of
148 The 68000 Hardware and Software

instruction TAS dst by the CPU, the processor inhibits

the data bus so that another processor cannot access
dst before the two read and write bus cycles have been
completed (see timing diagram of figure 6.35). This
prevents two processors from reading dst simultaneously
and finding the destination MSB at zero, before one of
the processors had set it to 1.

Yes

Indivisible
cycle

SEM: = 1

IF dst = 0 THEN
z := 1
I
ELSE
N := 0

IF SEM = 0
N .= 0
ELSE
N .= 1
ENDIF
ENDIF

Figure 6.34
 68000 Instruction Set 149

50 51 52 53 54 55 56 57 58 59510511 512513514S15S16S17S18S19
CLK

A1·A23

AS
---\
\_------------------
/ --- \_---
,-
UDS or LDS
R/W
OTACIe \ /,---------..,.,
\
,-
D8-D5
-i-s-« ) ( }-
Or DO-D7

I=CO·2 =x x:
~---- --------- Indivisible cycle ----------~

Figure 6.35 Read/modify/write timing diagram

(Courtesy of Motorola)

Time

68000 68000

WHILE SEM <>0 REPEAT WHILE SEM <>0 REPEAT

/*READ SEMAPHORE*/ /*READ SEMAPHORE*/
FTQ FTQ
SEM := 1 SEM := 1

L
Semaphore

Shareable memory
Figure 6.36 Synchronisation of two 68000 processors
sharing one memory
 7 Programming Exercises

This final chapter contains two longer programs that

show how to obtain the best performance from the 68000.
The first program deals with exceptions; the second is
a dynamic memory test.

1 EXCEPTIONS

The program that follows makes use of different

hardware exceptions, such as interrupts generated from
a peripheral circuit of the 6800 family (PIA 6821), a
bus error caused on purpose in order to examine the
different sequences of event, the trace mode and if the
conditions are satisfied the trapping of a spurious
interrupt.
Although this exercise is educational, the
programmer should find that it causes him to think
about the group priorities of the different exceptions
(see the program tests).

HARDWARE USED

1. A 68000 Euromak development system

2. A hard copy printer
3. A simulator connected on a PIA interface card, with
call switches.

STUDY OF THE LISTING

30 1**1**********I*IIIII***IIII****II*I***I**II*****I***I*fH***f***fHfll
40 * I
50 I EXCEPTIONS I
60 I ----------------- *
70 * - BUS ERROR f
80 * - TRACE MODE I
90 * - INTERRUPT AlJTOVECTOR I
100 * - SPURIOUS INTERRUPT I
110 I I
120 I (SYSTE" b8000 EUROMAK "I CROPROCESS f
130 I I
140 fffff****ffffl**ffffffHfff*ffffH****fHffffffffHfffffffflflfl*ffff**
160
170
*II EXCEPTION VECTOR
180 I

200 00000OO8 BUSERROR EQU 214 ;BUS ERROR VECTOR

2·10 00000024 TRACEr10D EQU 914 ;TRACE I'IODE
220 0000006O SPURIOUS EQU 24*4 ;SPURIOUS INTERRUPT
230 000000b8 AUTOLEV2 EQU 26*4 ;LEVEl 2 INTERRUPT AUTO-VECTOR
150
 Programming Exercises 151

240 0OOOOO7C AUTOlEV7 EQU 31*4 ;LEVEL 7 INTERRUPT AUTO-VECTOR

250 O(XHDE01 ADORPIA EQU $'1 [tEO-I ;PIA 682-1 ADDRESS
260 ooo'1E178 OUTMESS EQU $"1E'178 ;OUTPUT STRING OF CHARCS

280 OOOO~1)OO RORG $2000 ;POSITION INDEPENDENT CO(~

300 002000 4FFA025C RETURN LEA.L STACK,SP ;INITIALISE STACK POINTER

3'10
'*
320 002004 4DFA0054 LEA.L INITPIA,A6
330 002008 2"1 CEOOb8 MOVE.L A6,AUTOlEV2 ; INITIALISE LEVEL 2 AUTO-VECTOR
340
350 00200e 4fJFA0066
* LEA.L ABORT ,Ab
360 002010 21CE007C MOVE.L A6. AUTOLEV7 ; INITIALISE LEVEL 7 AUTO-VECTOR
370
380 0020-14 40FAOO9A
* LEA.L HAROERROR ,A6
390 0020'18 21 CE0008 MOVE.L A6, BUSERROR ; INITIALISE BUS ERROR VECTOR
400
4-10 0020-1C 4DFAOObA LEA.L NONVPA.A6
420 002020 21C£0060 MOVE.L Ab,SPURlOUS ; INITIALISE SPURIOUS VECTOR
430
440 002024 4OFA0076
* LEA.L TRACING,A6
450 002028 21CE0024 MOVE.L Ab. TRACEMOD ; INITIALISE TRACE MOOE
470
480
'*
** ADDRESSING PIA 682"1
490
*' -------------------
500
*'
5'10
520
*
*'
**********'*******'************************
..
530 *' * $-1 [;EO-l $"1OE03 $-1 OED; ~ $-1 DE07 ~
I I

540
*' *'
550 * *========================================
560
* *
570 * * (lORA DORB
I eRA CRB
580 * *' OR OR
590 '* * ORA I ORB
600 * *
610
630
* ******'**'******'*******'************'*'*******
640 ** INITIALISE PIA 682"1
650 '* -------------------
660 *
670 00202C 40F90001DEOl LEA. L ADDRFIA. A6 ;INITIALISE ADDRESS PIA
b80 002032 223CFFFFOS04 MOVE. L t$FFFFOS04. [;"1 ;A s B SIDE ALL OUTPUTS
690 002038 03CEOOOO MOVEP.L (j'LOfA6) ~ INTERRUPT CAUSED BY CAl
700 00203(: 46FC2100 MOVE. w #$2'1 DO ~ SR ;ENABLE INTERRUPTS
7"10
720 002040 323C8000
*LOOP MOVE. w #$8000. [:'1
730 002044 038Eoooo LOOP'1 MOVEP.W O-LtVA6 i ;WRI TE ORA and ORB
740 002048 6-1000088 BSR DELAY
750 00204C E2SQ ROR.W .-1,0'1 ; ROTAiE RIGHT
"760 00204E 64F" BCC.S LOOP-!

780 ..
790 *'* ENABLE TPACE MODE (.T:=l) .LOAD STATUS REGISTER AND STOP
800 * -------------------------------------------------------
fHO '* A TRACE EXCEPTION WILL OCCUR IF THE TRACE STATE ]S ON WHEN THE STOP
820 '* INSTRUCTION IS EXECUTED.
 152 The 68000 Hardware and Software

830 I IF AN INTERRUPT REQUEST ARRIVES WHOSE PRIORITY IS HIGHER THAN THE

840 I CURRENT PROCESSOR PRIORITY ,AN INTERRUPT EXCEPTION OCCURS ,OTHERWISE
850 I THE INTERRUPT REQUEST HAS NO EFFECT.
860 * IF THE BIT OF THE IrtEDIATE DATA CORRESPONDING TO THE S BIT IS OFF.
870 I EXECUTION Of THE INSTRUCTION WILL CAUSE A PRIVILEGE VIOLATION
880 I EXTERNAL RESET WILL ALWAYS INITIATE RESET EXCEPTION.
890 I
900 I

920 002050 46FCA100 HOVE.W tsA100.SR ;T:=1.S:=1.MASK LEVEL "1

930 002054 4E722000 STOP "2000
940 002058 6OE6 BRA.S LOOP

960 I
970 ff PROGRAM EXCEPTION CAUSEn BY LEVEL 2 INTERRUPT (CA1 OF PIA (821)
980 * ==============================================================

1000 00205A 48E7FFFE INITPIA t1OVEM.L DO-[}7/AQ-A6,-(SP) ;SAVE REGISTERS

1010 oo205E 41FAOO8O LEA.L STRING-! ,AD •INITIALISE POINTER AD
1020 002062 4EB90001E178 JSR OUH1ESS ;SUBROUTINE MONITOR
·1030 002068 12390001 DEDi MOVE. B AOORPIA. [J'l ; DISABLE INTERRUPT PIA
1040 OO206E 4CDF7FFF HOVEM.L (SP)+,DO-07/AO-A6 ;RESTORE REGISTERS
1050 002072 4E73 RTE
·1060
1070
*f* PROGRAM EXCEPTION CAUSE[) BY LEVEL 7 INTERRUPT
·10BO * ============================================

1·100 002074 48E7FFFE ABORT MOVEM. L OD-n7/ AO-A6, - (SP)

1110 002078 41FAOO8F LEA.L STRING2,AO
1120 00207C 4EB90001E178 JSR OUTMESS
1130 002082 4C[~7FFF I'tOVEM.L (SP) +,00-071 AO-A6
1140 002086 4E73 RTE

1160
'1·170
*
1* PROGRAM EXCEPTION CAUSED BY SPURIOUS INTERRUPT
1180 * ===========================================
"1'190 I IF DURING THE INTERRUPT ACKNOWLEDGE CYCLE ,THE PIA NO OEVICES
1200 I RESPOND BY ASSERTING VPA, THE PROCESSOR 68000 FETCHES THE SPURIOUS
1210 I INTERRUPT VECTOR.

1230 002088 48E7FFFE NONVPA MOVEM.L [~-07!AO-Ab,-(SP)

1240 OO~~8C 41FAOO9A lEA.L STRIN63,AO
1250 002090 4EB90001E178 JSR OUTMESS
1260 002096 4COF7FFF MOVEM.L (SP)+. 00-07/AO-A6
1270 00209A 4E73 RTE

1;'JqO
1300
**1 TRACE MOOE CAUSED IF THE T BIT IS ASSERTED AT THE BEGINNING OF THE
13"10 * =================================================================:
1320 * EXECUTION OF AN INSTRUCTION.
'1330 * ============================
 Programming Exercises 153

1350 00209C 48E7FFFE TRACING MOVEM.L [;0-[l7/AO-A6,-(SP)

1360 0020AO 41FA00A6 LEA. L STRING4, AD
1370 0020A4 4EB90001E178 JSR OUTMESS
1380 0020AA 4C[f7FFF MOVEM. L (SP) +,00-[0/ AO-Ab
1390 0020AE 4E73 RTE

14'10
1420
*** BUS ERROR CAUSED BY "HARDWARE PROBLEMS"
1430 * ======================================

1450 002080 48E7FFFE HAROERROR MOVEM.L OO-D7 iAO-A6,-(SP)

l4bO 002084 41FAOOB8 LEA.L STRINGS ,AO
1470 002088 4EB90001E178 JSR OUTMESS
1480 0020BE 4CDF7FFF MOVEM.L (SP)+, DO-07/AO-A6
1490
1500 0020C2 47FAFF3C
* LEA. L RETURN 'I A3 ;A3:= a RETURN
15-10 0020Cb 4FEFOOOE LEA.L $E(SP.I,SF
1520
1530
*** PEA INSTRUCTION
1540 * ==============
1550 * THE EFFECTIVE A[)ORESS IS COt1PUTEO AND PUSHED ONTO THE STACK
15bO * A LONO WORn AO[lRESS IS PUSHED ONTO THE STACK.
1580 0020CA 4853 PEA (A3)
1590 0020CC 4FEFFFFE LEA.L -2(SP) ,SP
1600 002000 4E73 RTE

1620
1630
**f DELAY
'1640 * =====
-1 bbO 002002 3F04 OELAY MOVE.W D4,-(SP)
1670 002004 383C61A8 MOVE.W i25000~D4
1680 oo20D8 51CCFFFE DELAY"! OBRA D4, DELAVl
-1690 0020DC 38-1F MOVE.W (SP"i+. [;4
1700 0020DE 4E75 RTS

-1720 oo20EO OA STRING-1 De.B $A,$[i

-1730 0020E2 20 OC.B LEVEL 1 INTERRUPT (PIA CAl:;
1740 002-106 OA ec.e $A,$[l,4
1750 002109 OA STRING2 OC.B $A,$[)
-1760 002-1OB 20 DC.B LEVEL 7 INTERRUPT !

-1770 002'125 OA OC.B $A,$O,4

"1780 002-128 OA STRING3 De.B $A,$D
"1790 002-12A ~1J ec.s SPURIOUS INTERRUPT !

'1800 002'145 OA De.B $A, $[;,4

-18'10 002148 OA STRING4 DC.S $A,$D
-1820 00214A 20 De.B TRACE MOOE •• TRACE MODE ••
'1830 002"16B OA OC.B $A,$(i,4
-1840 002-16E OA STRINGS OC.B $A,$D
'1850 002-170 20 OC.B BUS ERROR •••• BUS ERROR ••••
'1860 002'193 OA oC.B SA,$[),4
 154 The 68000 Hardware and Software

'1870 002°196 OOOOOOC8 DS.L 50

1880 000022SE STACk EQU *
1890 END

****** TOTAL ERRORS ij-- 0

SYMBOL TABLE - APPROXIMATELY 489 SyMBOL ENTRIES LEr=T

ABORT 002074 AOlit<PIA D-t DEOl AUTOlEV2 000066 AUTOLEV7 00007C

BUSERROR 000008 DELAY 0020(:2 DELAY"! 0020[;8 HARDERRO 0020BO
INITPIA 0020SA LOOP 002040 LOOP1 002044 NON\,ij:{."t G020B.S
OUTMESS O"lEl78 RETURN 002000 SPURIOUS 000060 STACK 0((::~~'5E
STRING"! 0020EO STRING2 002"109 STRIN63 002'128 SlR.iii!G4 002"148
STRINGS oo2"16E TRACEMOD 000024 TRACING [l0209(

1 Stack and Exception Table Initialisation Module

The instruction LEA.L STACK,SP loads the effective
address identified by the stack label into the SP
register.
The following instructions all have the same
function, namely to store the start address of the
exception program in the corresponding vector.

Example
LEA.L HARDERROR,A6 loads register A6 with the address
indicated by HARDERROR ($20BO) while the storing of the
contents of A6 in the BUSERROR address is ensured by
the instruction MOVE.L A6,BUSERROR. The label BUSERROR
has been previously defined in the list of
equivalences, being the address resulting from the
following multiplication

2*4 $8

Number in base lO~ ~ Address of bus

of bus error vector error vector

2 Initialisation of PIA 6821 Circuit Module

The reader will certainly have noticed the address
table of the 6821 which shows the memory allocation of
the PIA.
Instruction LEA.L INITPIA,A6 load the effective
address $lDFFI into register A6.
The next two instructions, MOVE.L #$FFFF0504,DI and
MOVEP.L Dl,0(A6) (already studied in the section on
MOVEP) tell the processor to store, in alternate bytes
and starting from address $IDFPl, the long word
contained in register Dl.
 Programming Exercises 155

The PIA 6821 is therefore programmed as follows

ports A and B on output (bit 2 of CRA and CRB

is at 0, after a RESET)
interrupts are authorised on CAl
access to the data registers of the PIA (ORA and
ORB) via bit 2 of CRA and CRB at 1.
The next instructions present no difficulty and
these will be translated by an algorithm that will need
to take account of the delay subroutine.

Statement of algorithm
BEGIN
FOR Dl altering from $8000 to $0000 by right shift 1

PIA := Dl
/*Under / DELAY PROGRAM*/
D4 : = 25000
REPEAT
I D4: = D4 - 1
UNTIL D4 = 0
ENDFOR
END

3 Enable Trace Mode and Halt Program Module

The privileged instruction MOVE.W #$AIOO,SR sets the
trace T and supervisor S bits of the SR to 1; it also
positions the interrupt mask at level 1.
Instruction STOP #$2000, which is also privileged
(this explains why bit S is confirmed to be at 1 by the
previous instruction), transfers the operand $2000 to
the status register before halting execution of the
program at the next instruction BRA LOOP.
Execution of the program can only be resumed after
one of the following three interrupts has been handled:
reinitialisation, interrupt or trace.
A trace exception occurs if bit T is asserted before
execution of the STOP instruction by the processor,
which is the case here (MOVE.W #$AIOO,SR).
Note too that it is possible to modify the mask
level by the STOP instruction (see the fourth program
test) .
We shall not examine each exception program in
detail, but will conclude with a study of the bus error
module.
 156 The 68000 Hardware and Software

First program run

> 20()();G
TI;~ACf MODE •• TRACE MODE.. Execution of trace procedure

TRAI,~E MODE •• TRACE MODE ••

l.EVEL "1 INTE'~RlIPT (PIA C~~'1) PIA interrupt (level 2)

LEVEl,. ., INTERRUPT (P If~ CA'-')

l.EVEl. '1 INTERRUP T (P IA CA'1)
TRACE MODE •• TRACE MODE ••

l.E"'El. '1 INTERRUPT (PIA CA'1 )

LElJEL INTEI~I~IJPT (PIA CA'I)

LEVEL '1 INTEI~RUPT <PIA CA'1 )

LEVEL '1 I NTE'~'<UP T (P.[ ~~ CA" ) Level 2 interrupt interrupted

t.F.:lJEL.. 7 I NTEr~RlJF' T by level 7 interrupt

TRACE MODE: •• TI~ACE MODE ••

LEVEL 7 INTE:I~I~lJPT

l.EVEL. 7 INlERr~lJPT

L.EVEL '1 INTERI~I.JPT (PIA C~~'I )

L.EVEL 7 rNTE'~RLJPT

LEVEL '1 INTE'~I~UPT (PLA CA'" )

I. El"JFl. 7 JNTE'~I~LJPl'

l..E',.IEL '1 INTEI~'~UPT (PIA CA'" )

LEI..IEl 7 INTERRUPT

TI~ACE
L.E'VE L. '1 I NT E I~ R UP T ( P 1: A C{~'1 )

LEVEL '1 INTEI'~RUP T (P IA CA"')

MODE •• T'~ACE MODE
l.EVEL 7 INTERRUPT

L.EVEL ? INTERRUPT

l.El,IEt. r INTERI~UPl
l.EVEl. '1 INTER'~UPT (PIA CA'" )

LEVEL INTERRUPT (PIA C{~'1 )

LE"'EL INTE".RRLJPT (PIA CA'1 )

LEVEl.
LEVEL 7 INTERRUPT
'1 INTERI~UPT (p tA CA")

LEVEL. 7 INlERr~UPT
 Programming Exercises 157

Second program run

> ~? OOC) ; G Simulation of a crash ( the PIA
TRACE MODE•• TRACE MODE•• card will be deselected during
program execution, then reselected)
r'~~'CE MODE•• TRACE MODE••

TRACE MODE•• TRACE MODE••

1.•EVEl. ., INTEI~I~UPT (PIA CA'1 ) PIA interrupt level 2

'('RACE MODE•• TI~ACE MODE••

LEVEl.. l INTEI~'~ UPT Abort interrupt level 7

Tr~ACE MOOE•• TRACE MODE••

T'~ACE MODE•• TRACE MODE••

TRACE MODF •• TRACE MODE••

BUS EI~'~OR •••• BUS EI~I~OR •••• PIA card deselected

BUS ERROR •••• BUS F.Rr~OI~ ••••

Crash
BU!) ERI~OR •••• BUB EI~I~OI~ •• II •

BUS FRROR •••• BUS ERROR ••••

BUS EI~I~OI~ •••• BUS E'~ROI~ •• II •

BUS ERROR •••• BUS ERROR ••••

BUS EI~ROR •••• BUB EI~'~OI~ ••••

TI~ACE MODE•• TRACE MODE•• PIA card reselected Restore

TI~ACE MODE•• T'~ ACE MODE••

L.EVEL. '1 INTEr~RUPT (PIA CA"I)

T'~ACr-: MODE•• T'~ f'CE MODE••

LEVEL. '1 INTEI~RUPT (PIA CA'l )

TRACr·: MODE•• TI~ACE MODE••

LEVEL 7 INTERRUPT

TRACE MODE•• TI~ACE MODE••

l.EVEL 7 INTERRUPT

LEVEL 7 INTERI?UPT

TRACE MOOE•• TRACE MODE••

LEVEL l I NTEI~ I~ UPT

LEVEl... 7 INTEI~RUPT

LEVEL 7 INTERRUPT

LEVEl... 7 INTERRUPT
158 The 68000 Hardware and Software

Third program run

?()OO~G Card is not selected
[),US ERROf,,~ •••• BUS EI~ROR ••••

BUS EI~I~OI~ •••• BUS EI~'~OI~ .....

BUS EI~ROR •••• BUS EI~ROr~ ••••

BU~3 E'~'~OI~ •••• BUB EI~I~OR .....

BUS FRROr~ •••• EJUS ERROR ••••

BUS EI?I~O'~ •••• BUS E'~'~OI~ .....

BUS EI~I~Or~ •••• BUS ERROR ••••

BU~) EI~I~OI~ •••• BUS E'~R O'~ .....

BUS ERROR •••• BUS ERROR ••••

BUS E'~'?OR •••• BUS E'~I?OR .....

BUS EI~ROR •••• BUS EI~ROR ••••

LElJEI.. 7 INTE'~I~UPT

BUS ERI~OR •••• BUS EI~ROI~ ••••

BUB EI~I~OI~ •••• BUS ERI~Ol~ ••••

BUS ERI~OR •••• BUS ERROR ••••

BUS EI?ROI~ •••• BUS ERI~OR •• II •

BUS [IH~OR •••• BUS ERROR ••••

13lJ~3 EI~ROR •••• BUS EI?ROI? .....

BUS EI~ROR •••• BUS ERROR ••••

BUS EI~I~OI~ •••• BUS EI~R,)R •• It •

Fourth program run

;~()OO; G Interrupt from PIA, but
TI~ACE MODE •• Tr~ACE MODE •• the 68000 does not
recognise VPA at low
TRACE MODE •• TRACE MODE •• during the interrupt
recognition phase
TRACE MODE•• TRACE MODE ••
TI~ACE MODE•• TI~ACE MODE••

TI~ACE MODE •• TRACE MODE••

BPUI~ IOUB '{NTEI?I~UPT

SPURIOUS INTERRUPT
SPUI~ rous INTERRUPT
~~PUR rous INTERRUPT
~~PUI~ IOUS INTEI~I~UP T
 Programming Exercises 159

~~PUR J OU~) INTERRUPT

BPUJ~ lOU~, TNTERI~UPT

SPUR IOU~) I NTF:r~I~lJP T

~3PUl~ IOUS (NTEt~RUpr

~~PlJR J OUS INTERRUPT

BPUI~ IOUS INTEl~RUPT

SPUI~ IOUS I NTE'~ RlJP T

~-:)P URI OU~) INTERJ~UPT

~)PlJR lOUS INTER

4 Bus Error Module

The contents of the supervisor stack after the bus
error and before the first instruction of the exception
program are shown in figure 7.1 (see also demonstration
listing) .

Stack
15
o

SPafter ~ Super status word $2250

MSB address on bus $ 2252

LSBaddress on bus $ 2254

Instruction register $ 2256 Decreasing

addresses
Status $ 2258

PC high $ 225A

PC low $ 225C
SPbefore~ $ 225E

Figure 7.1

The reader will recall that, as in the case of an

address error (see chapter 4 on exceptions), when a bus
error occurs the contents of the PC saved on the stack
may have been incremented by 2 to 10 bytes in relation
to the address where the error has occurred (the above
is no longer true with the MC 68020 and MC 68010).
 160 The 68000 Hardware and Software

The instruction MOVEM.L DO-D7/AO-A6, -(SP) saves the

context to the supervisor stack (remembering that all
exceptions are handled in supervisor mode).
LEA.L STRING5,AO loads register AO with the start
address of the characters string

"BUS ERROR ... BUS ERROR"

Instruction JSR OUTMES calls the monitor subroutine,

characters output.
We then come to instruction MOVEM.L (SP)+,
DO-D7/AO-A6 which restores the context previously saved
to the stack. After this instruction the stack pointer
SP points to the super status word (see figure 7.1).
What happens if after instruction MOVEM.L (SP)+,
DO-D7/AO-A6 the 68000 processor is ordered by RTE to
return to the main program?
Certainly, if one were to believe figure 7.1 the
super status word would be loaded into register SR, and
the address sent along the bus at the moment of the
error to the PC. The reader can imagine the problems
that this would cause.
We shall leave it to the reader to continue study of
the bus error exception program which, to judge from
the foregoing, must be very carefully examined. In the
following demonstration the program has been rerun from
address $2000 in order facilitate comparison with the
listing.

;>()BCl; I) Stop point

;>000; G Run command
TRACE MOOE .• TRACE MOOE ..
TRACE MODE .• TRACE MODE •.
L.El.'F I.. '1 I NlERRUP T (P I A CA·1)
LEl)El. ,., INTEI?I~UPT (P IA CA";'

TRACE MOOE •. lRA

LEVEL '1 INTE'~I~UP r (P I A CA")
CE l-10DE ••

LEVEL 7 INTERRUPT
TRACE MODE •• TRACE MODE .•
TRACE MOOE .• TRACE MODE ..
Deselection of PIA card
* VSTP PC= 0020BO " 48E7 8=0 S 000

> ;R p c= OO~.)()B 0 «',BE7 S::() S ()()() c::: sp:: ()OO()~?~.~~;()

DO::: ()()()()(){)()() O··'e: FFFF()()(30 D~~::: ()()()()()()()() D3= O()()OOO()()
D'1= O()()OO()()() [)~:;== ()()()()()()()() 06=: ()OOO()O()() [)7=: O()O()()()OO
A():: ()()()()O()()() A··, == ()()()()()()()() f'~~= ()()O()()()()() A:3= ()()()O()()()()
A.I,= O()OOO()()O A~i:: O()()()OO()() Ai):: ()OO'10E()·1 A7= O()OO()600
 Programming Exercises 161

) *
*
;.~ zso 0 ~~B~';'-' Super status word
> 000'-'-·
(){)~~2~'5~,:~
> ()O~?~~~:;I, [)[-:O'1-- address on bus
> OO~?:;~!)6 03BE-- instruction code
> OO;.~~~58 ;~()()O··' status register (SR)
> r){):,:~2~'5t:' oooo- contents of program counter (PC)
()o~? ~~ ~'; C ;?() I, l, ...
> {)()::Z~?!5E 4'100-·

~: ffU'iC PC:: O()~?()B't tt I"1FA ~)::O C'

... ) OO() C::: SP:: ()O()()~?~~,·, It
D()::: l,)()()()()()OO D'I= FFFFO()BO IX?::: ()()()()()()()O 1)::3= ()()()()O(){)O
[).Io}:: O()OO()()()() D~:;:::: ()()(l()()()O() D6= ()()()()()()(l() D7::: ()()O(l()()()()
A()::: O()()()()lJOO A'1::: ()()()()()()()O A:,:~::: ()()()()()()()0 ~'~3:: ()()(){)O()()()
A.i1:: O()O()()()()() A~j::: OO()O()()()() A6:: ()()()'1 DEO'" A7= ()()O()()~,()()

,..
~- AFT[I~ I NSlRUCTION: MOVEM. L [)O--[)71(-\O·-A~) '1-- (BP)
.... ::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
~

~! ()C~.~ ; I.•'
;p
BUS ERROR•••• BUS Er~ROR ••••

* VSTP PC:: OO:,:?()C~~ .. '.7FA S:::D B ()OD C:: •• Z.. BP:: ()()O{)2~~~"5()
DO::: ()OO()()()()() [)'l::: FFFFO()8() O~?::: O()()()()()()() [):~::: ()()()()()()()()
D4= (JO()()()()OO D~)::: O()()()f)()()O D(S== ()(){)()()()()() D7:: ()()O()(X)()()
(o,()::: ()()()()O()()() A'1::: ()()()()()()(l(l A~,~::: ()()()()(l()()() A:~= ()()()()()()()()
A4= O()()()()O(){) AS::: ()()()()()l)()() A6::: ()(){)'1 DE()'I A7 = O()()(){)!.>()()

** AFTER I N~>TRUCTJ:ON= MOt..JEM.l.. (SP)+, [)(l·-[)7 /AO-·Ab

* ::::::::::::::::::::::::::::::::::::::::::::::::::::::::
) tEo
> ~;
./
* TRAC PC= 0020C6 "4FEF 8:::0 S 000 C= •• Z•• SP= OOO()2250
DO= ()(){)f)()()()() D'I:: FFFFD080 D2::: ()OO(){)()()O 1):3= ()O{){)OOO()
D4= ()()O()()()()() [)~:j::: ()()()()(J()()O 06:-.:: O()()(lO()()() 07::: OO()()OO()()
A()::: O()()()O()()() A·1:-.:: ()()()()()()()() A~~== ()()()()()()O() A~3== ()()002000
~~/,= ()()OOOO()() A~~::: OOO()()()()() A6::: ()()()'1 [)E()'" A7:: O()()()()6()()

> ~
i(-* AFTER INSTRUCTION l.E(".l.. RETURN 'I A:·)
'* :::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
)
*/
~:. TR~~C PC::: ()()~~(}CA n ',E)~j:~ 8::::0 S ClO() C::: •• Z. • SP::: O()()()~.~~~~jE
DO::: O()()O()(){)() D":: FFFF()OBO D~~::: O{)O()(){)()O D3== ()()(){)OO()()
[).i,:: O()OOOO()() ()~)::: O()()()OO()O Db::: OO()()()()()() D7::: OO()()()()OO
AO::: O{)()f){)()()() A'1::: OO()()()()()O A2::: ()()()()(){){)() A~3::: ()D{)O~?OOO
~~",::: OOOOO(JOO At;::: O()()()()()()() At,::: ()()()'1DE()'1 A7::: O()()()()60()

**-t~F TEr~ I NST~~ UeT I ON l. E (.\.l.. ~,E ( ~)P ) SF' 7

*- ::::::::::::::::::::::::::::::::::::::::::::::::::::::

RAe
" 4FEF
~:. PC::: ()O~?OCC 8:::() C'
",) OO() c:;: . . l .. sp:::: ()()()()~~~~~;A
DO::: ()l)()()()()()() D'I:::: FFFFOO8() D~~::: ()(){)()()O()O 1)~3:: OO{)()O()()()
[)/t::: OO()()()()()() O~:;:: ()()()()()()OO D6::: (}O()()O()()() D7:: O()()()()()OO
AD::: ()O{){)(){)O() A"I= OOO()()()()() A2::: ()(){)O()()()() A:3:: 0000:-2000
A4= O()()(}()O(}() A~5= ()()()()()()()() A6:: O()()'1D[O'1 A7== ()O()()()~)OO
 162 The 68000 Hardware and Software

'*
> * AFTER I NST RUCT J: ON :: P [f" (~~:~ )
~. :::::::::::::::::::::::::::::::::::::::::::::::::::::

> *
> '*
) '*
> /
~l: TR AC P C::: O()~~ODO tt 'tE7:~ S:::O S OOC) C::: •• Z. • SP::: ()()()()2~~~5B
DO::: O()()OOOOO I)"':: FFFF()()BO D~~::: ()O()OO()()O D3= O()()OOOOO
[).It : : OOO()OOO() [)~)::: ()()()()()()(lO D6:::: O()()()OO()O D7:::: O()()O()()()O
A()::: O()()Of.)()()O A'1::: ()OO{)O{){)() A:~~::: O()OO{)OOO A~3::: O()OO~~O()()
~~l,(;:: O()()()(l()(lO A~:'::: OO()()OO()(l A6::: OOO'1DEO'1 A7:::: ()()O()()6()O

** AFTER IN~)Tr~UCTION:: I...Er-l.1... ··;.~(SP) 7SP

* :=:::::::::::::::::::::::::::::::::::::::::::::::::::::::

*.I Start of program

~: TR'~C PC= 00200() «46FC S=O S 000 C~ .NZ •• SP~ O()00225E
DO:::: noonooon D'I:: FFFFO{)80 D~~:: (){)OOOO()() D~3:: O{)O(){)()OO
D.lt : : O()(J()()()()O [)~:;:: OOOOO(lO() [)6::: OO()()()()()O [) 7 = ()OOOOO()O
AD::: ()O()()()()()D A'1:: O{)(){)()()()() A~~::: O()()()()OO() A~3=O()()O;;?O()()
(".1,= OO()()OO()() A~~:: OOOOOOO() At}::: ()()()'1DEO'" A7= OO()()06()()

** AFTEr,: INSTRUCTION: RTE

'* :::::::::::::::::::::::::::::::::::::::::::::::::::::::
.I
~: TRAC PC::: ()O~~OO/, tt I,FFA 8=0 S'1""1 C::: ~)p::: OOOO~~25E:
DO::: ooooonoo I)":: FFFFOOBO D::~= ()f){)OO{)O() IX3::: 00000000
D.I,.= OO()OOOOO 05= O()O()()OO() Db:: ()()OOO()()() [)7= OO()OO()()()
A()::: O(){)O{)O{)() A1= O()O{)O()()O A2= 00000000 A~3 ::: o()()ozooo
(ol.l,= O()()()OO()O A~~::: O()()()OOO() A6= O()01DEO'1 A7= OOO()0600

2 DYNAMIC MEMORY TEST

30 ****************************************************************+*****
**' **
40
50 MEMORY TEST
60
70
*
*
80 * WRITTEN BY PATRICK JAULENT : MAY '1984
90 *' COPYRIGHT:,.,l CROPROCESS
100 *'
1"10 ******************+*********'***************'***************************
** ALGORITHM: THE PROGRAM IS COMPOSED OF S MOOULES THERE ARE:
'120
-130 I

'140 * =========
**' -1- TEST : WRITING AT THE SELECTED ADDRESS : THE OPERAND $00000000
"150
'160
170 * AND RE-READING. IF THE RE-READING [tOES NOT CORRESPOND
"180 * TO THE wRITING THEN "ERROR 1 11
•

190
200 ** -2- TEST : WALKING 1: wRITING AT THE SELECTED ADDRESS THE OPERAND
2'10 .. $80 TO THE OPERAND $00 BY ROTATING ON PLACE TO THE RIGHT.
220 *' IF THERE' 5 A FAILURE THEN ;1 ERROR 2 ",
230
*
 Programming Exercises 163

240 * -3- TEST : WRITING AT THE SELECTED ADDRESS THE OPERAND SFFFFFFFF
250 * THERE ARE 2 SEQUENCES:
2bO
270
*
280
* -'1- VERIFICATION IF THE REAOING CORRESPONDS TO

290
*
I
THE WRITING,IF THERE IS A FAILURE, THEN "ERROR 3".

300 I -2- VERIFICATION IF THE REST OF THE FIELD MEMORY 15

310 I UNCHANGEO IF NOT SO, THERE ARE "PROBLEMS" OF
320
330
*
I
REOUNDANCY THE "ERROR 411•

340 * -4- TEST: WALKING 0: WRITING AT THE SELECTED ADORESS THE OPERAND
350 I $7F TO THE OPERAND $00 BY ROTATING ON PLACE THE RIGHT.
360 * IF THERE IS A FAILURE THEN " ERROR 5 ".
370
380
*
I -5- TEST : THE LAST TEST USES THE SOFTWARE FEATURES OF THE
390 I lITAS" INSTRUCTION.
400 I DESCRIPTION:
4-10 * -----------
4~1i
430
* TEST AND SET THE BYTE OPERAND AODRESSED BY THE
* EFFECTIVE AOORESS FIELD. THE OPERATION IS
440
450
*
I
INDI VISIBLE.

470 ** FUNCTION REGISTERS

480 I ================
490 * AD = POINTS TO STRING OF THE CHARACTERS
500 * Ai = START ADDRESS
5"10 * A2 = END AOORESS
520 * A3 = USE FOR RETURN
530 * A4 = USE IN THE REOUNDANCY TEST
540 * AS = ADORESS ACIA 6850
550 * A7 = STACK POINTER
560
570 ** 00 = LISE SUBROUTINE TO TRANSMIT CHARACTERS
580 * [)ol = COUNTER LOOPING
590 * 02 = USE SliBROlIT INE IIWALKING II
600 * 03 = USE SUBROUTINE OUTHEX AND A[i[iRTST
6'10 * 05 = USE SUBROUTINE DELAY
620 * D6 = MOOULE IDENTIFIER
630 * 07 = USE SUBROUTINE DELAY
640 *

6bO
670
*
*1 EQUATES
b8D
690
* -------
START ;AOORESS PROGRAM COUNTER
0‫סס‬oo004 EQU '1*4
700 ‫ס‬0ooooo8 BUSERROR EQU 2*4 ;BUS ERROR VECTOR
1'10 OOOOOOOC AOOERROR EQU 3*4 ;ADDRESS ERROR VECTOR
720 0‫סס‬oo018 TRAPCHEK EQU 6*4 ; CHK INSTRUCTION
730 o00ooo60 SPURIOUS EQU 24*4 ;SPURIOUS INTERRUPT
740 00‫סס‬oo64 IRQACIA EQU 25*4 ;LEVEL 1 INTERRUPT AUTOVECTOR
750 00OOOO7C ABORTIT EQlI 3"1*4 ;LEVEL 7 INTERRUPT AUTOVECTOR
760 00O"lF9E9 A[)ORACIA EQU $"1F9E9 ;AOORES5 ACIA .~850

780 0000000[1 CR EQU $00 CARRIAGE RETURN

790 OOOOOOOA LF EQU $01\ LINE FEED
8[(1 00000004 EOT EQU $4 END OF TRANSMIT
 164 The 68000 Hardware and Software

8'10 00000020 SPC EQU $20 ;SPACE

820 00000oo8 BS EQU $8
830 00000007 BEL EQU $7 ; CONTROL-6 (BELL)

860
870
*** THE SYSTEM IS IN SUPERVISOR MOOE
880 ** IF THE SYSTEM IS IN USER MOOE THEN WRITE:
890
900
** LEA. L BEGIN, AD
9'10
**
H MOVE.L AO,$80 (TRAP #0)
TRAP 10
920
** OC.W 0
930
940
**
*
960 *
970 ** INITIALISE STACK POINTER (SSP) AN[) EXCEPTION VECTOR
980 '* =====================================================
990 00002000 RORG $2000 ;P.1. C PROGRAM

10"10 002000 4FFA08Ab BEGIN LEA.L STACK,A7 ; INITIALIZE SSP

1020 002004 4bFC2700 MOVE. W 1$2700, SR ;MASQ INTERRUPT LEVEL 7
'1030
1040
*
** IF THERE ARE lliLLEGAL INSTRUCTIONS II THE 68000 MICROPROCESSOR STOPS
'1050 * ----------------------------------------------------------------------

'1070 002008 97C8 SUB.L A3.A3 ,A3.L:=O

1080 00200A 47E80010 LEA '16(A3).A:5 ;A3.L:=$'10
"1090 oo200E 45FA02DC LEA.L STOPPING,A2 ;A2.L:= ~ STOPPING
'1'100 002012 26CA LOOP MOVE.L A2, (A3.i+ ;MEMCA3J :=A2 ;A3.L:=A3.L+4
1110 002014 B7FCOOOQ0020 CMPA.L #$20.A3 ;A3.L=$20 ?

'1120 00201 A bbF6 BNE.S LOOP

'1130 *
1140 *
1150 0020lC 45FA0352 LEA.L ERRORBUS.A2
1160 002020 21CAOOO8 MOVE.L A2.BUSERROR ; INITIALISE BUS ERROR VECTOR
'1170 002024 21 CAOOOC MOVE.L A2. AOOERROR ; INITIALISt A[tDRESS ERROR vECTOR
1180 *
1'190 002028 45FA020E LEA.L CHECK,A2
1200 00202C 21CAOfr18 MOVE.L A2.TRAPCHE~. ;INITIALISE CHK. INSTRUCTION
1210
1220 002030 45F A0318 LEA.L IRQ6850.A2
1230 00~~34 2"1CA0064 MOVE.L A2.1RQACIA ;INITIALISE LE\,iEL "1 AUTOVECTOR
1240 *
1~~0 002038 45FA0322 LEA.L SPURIOUSIRQ.A2
1260 00203C 21CAOObO MOVE.L A2 t SPURIOUS ; INI TIALlSE SPURIOUS INTERRUPT
1270 *
1280 002040 45FA0324 LEA.L LEVEL 7IRQ. A2
1290 002044 2'1 CAD07 C 110VE.L A2.ABORTIT ; INITIALISE LEVEL 7 AUTOVECTOR
1300 *
13-10 ** CALLING THE SUBROUTINES i:MODULESi
1320 * ==================================
1340 002048 6158 BSR.S INITACIA
'1350 00204A 6'174 BSR •S INPUTHEx,
1360
1370 00204C 6'100009£ BSR TEST'1
1380 002050 41FA067F LEA.L STRING"} ,AD
 Programming Exercises 165

1390 002054 6100023A BSR PDATA PRINT STRING"!

1400 002058 61 00025A BSR INPUT1 INPUT CHARACTER
1410 00205C 6100024A BSR DUTCH-! ECHO ON THE CONSOLE
-1420 002060 OCOOOO4E CMPI.B liN' ,00 IF INPUT CHAR.= 'N I THEN
-1430 002064 6736 BEQ.S ENOTEST ~ 1* END TESTS *1
1440 002066 6-152 BSR.S INITIRQ ELSE
1450 002068 4bFC2000 MOVE.W 1$2000,SR ~ 1* ENABLE INTERRUPT */
1460 00206C 610000A0 BSR TE5T2 ~ 1* TESTS *1
1470 OO~~70 41FAObC9 LEA.L STRING2,AO
1480 002074 6'10002'1 A BSR PDATA ENDIF
-1490 .
1500 002078 610000AA BSR TE5T3
'15-10 00207C 41FA06F4 LEA.L STRING3,AO
1520 002080 6100020E BSR POATA
-1530
1540 002084 6-100000C
* BSR TEST4
1550 002088 41FA071F LEA.L STRING4,AO
'1560 00208C 61000202 BSR PDATA
"1570
1580 002090 610000E4
* BSR TESTS
1590 002094 4-1FA0560 LEA.L STRING5,AO
1600 002098 o-10001F6 BSR POATA
-16'10
-1620 00209C 45F8oo04
*
ENDTEST LEA.L START ,A2
-1630 0020AO 4ED2 JMP (A2)
"1650
1660
*** ACIA 6850 INITIALISATION
'1670 * =======================
'1680 * CONTROL REGISTER = 03 I* MASTER RESET *1
1690 * CONTROL REGISTER = 15 1* 8 BIT8,'1 5TOP,OIVI8ION '16 *1
1700
*
1720 OO~~A2 4BF90001F9E9 INITACIA LEA.L ADDRACIA,A5
1730 0020AB -!ABCOOO3 MOVE.B 13, (AS) ; MASTER RESET
'1740 0020AC 3£3C1000 MOVE. W 1$1000,07
1750 OO~~BO S'lCFFFFE LooP'1 [tBRA 07,LOOP'! ; DELAY
1760 002084 '1 ABCOO15 MOVE. B #$-15, .: AS) ; 8 BITS ,1 STOP ,DIVISION -16
'1770 002088 4E75 RTS

** CONTROL REGISTER = 95
-1790
1800 1* ENABLE INTERRUPT GET CHARACTER *1
"18"10
1820 0020BA 1ABCOO95
*INITIRQ MOVE.B 1$95,(AS)
'1830 OO2OBE 4E75 RTS

1850
1860
*i* GET 5TART AND END A[)[)RESSES KEYBOARD
1870 * =====================================

"1890 D020CO 4'lFA0312 INPUTHEX LEA.L ADDRBEGIN,AO

1900 0020C4 611 C BSR.S ADDRF
'19'10 0020C6 0283FFFFFFFE AND1.L I$FFFFFFFE ~ D3 ; ODD ADDRESS SVP
1920 0020CC 2243 MOVE.L D3,A"l ; A·1: = 5T ART ADDRESS
"1930 *
1940 0020CE 4-1FA037F LEA. L ADDREND ~ AD
1950 002002 610£ BSR.S ADDRF
1'(60 0020D4 0283FFFFFFFE AND I . L I$FFFFFFFE ~ [;3 • ODO A[i(iRESS SVP
166 The 68000 Hardware and Software

-1970 00200A 2443 MOVE.L 03,A2 • A2 : = EN[; AOORESS

-1980
1990 OO200C 85C9 CMPA.L A-1,A2 ; IF A2.L =< A'1.L THEN
2000 oo200E 6FEO BLE. S INPUTHEX ; ~ 1* RETURN INPLlTHEx ./
20"10 002DEO 4E75 RTS ENDIF
2020
2030 0020E2 b-10001AC
*
AO[)RF BSR POATA ; PRINT TEXT STRING
2040 0020E6 61QO010A BSR INAO[) ; GETS ADORESSES
2050 0020EA 4E75 RTS

2070 *
2080 ** TEST -1 : WRI TE $00000000 AND READ IF ADORESS EQUALS $00000000
2090 *' ======================================================
2'100
2-1-10 ** MODIFIES REGISTERS: 0 -1 2 3 4 5 t. 7
2'120 * ------------------(1
2130 I A* *
2-140
2160 OO2OEC 48E700CO TEST'1 HOVEM.L AD-At, -(A7) ;SAVE AlTERED REGISTERS
2'170 0020fO 7C01 MOVEQ #'1,06 ; IDENTIFIER MOOULE -I
2-180 002Of2 B3CA LOOPTl CMPA.L A2,A1 ;00 WHILE A'I =< A2
2-190 0020F4 62'12 BHI.S ENOl1 ;'
2200 002OF6 429'1 CLR.L (A-I) ; ~ MEM[Al]: =$00000000
2210 002OF8 4A9'l TST.L (A-1) ; ~ IF MEM[A1] <) $00000000 THEN
2220 0020FA 6708 BEQ.S OKTST-l ; ~ ~ If: AO.L:= a TEXT ERROR-1 *1
2230 0020FC 41FA037-1 LEA. L ERRORl ,AD • ~ ~ II PRINT STRING-! Ii
2240 002100 61000144 BSR FAILURE ,.
.1 I

2250 002'104 5889 OKTST-i ADOQ.L #4.A'l ; ~ ENDIF

2260 002106 bOEA BRA. S LOOPTl
2270 002108 4CDF0300 ENDT'1 MOVEM.L (A7)+,AO-A'1 ;ENOOO
2280 0021 OC 4E75 RTS

2300 I
23-10 It TEST 2 : WALK ING ·1
2320 I =================
2330 I MODIFIES REGISTERS: 0 "1 2345 b7
2340 I ------------------(J *
2350 * AI
2300 * AO.l:= ADDRESS TEXT STRING2 INPUT PARAMETER PASSED
2370 * 02.B:=$80 INPUT PARAMETER PASSE[)
2380 I

2400 0021 OE 48£72080 TEST2 MOVEM.L D2iAO,-(A7) ;SAVE ALTERED REGISTERS

2410 002112 E30E LSl.B #1,06 ;IOENTIFIER MOOULE 2
2420 002114 4'lFA0397 LEA.L ERROR2,AO ;AO.L:= AO[)RESS TEXT ERROR 2
2430 002118 7480 MOVEQ h80,02 ;02.8:= "10000000
2440 00211A 61000082 BSR WALK ;CALLING WALK
2450 00211E 4COF0104 MOVEM.L (A7)+.02/AO ;RESTORE REGISTERS
2460 002122 4E75 RTS

2480 I
2490 1* TEST 3 :WRITE fFFFFFFFF AND READ
2500 * ===========================
2510 I MOOIFIES REGISTERS: 0 -1 2 3 4 5 b 7
~'520 * ------------------0
2530 I A**
2540
*
 Programming Exercises 167

2560 002124 48E700C8 TE5T3 MOVEM.L AO-A'lIA4,-(A7) SAVE ALTERED REGISTERS

2570 002-128 E30E LSl.B #1,Db IDENTIFIER MOOULE 3
2580 002-12A B3CA LOOPT3 CMPA.L A2,A"l 00 WHILE A2=<A1
2590 00212C 622E BH1.S EN031
2600 002-12E 2849 MOVE.L A'I,A4
26'10 002130 sese AD[tQ.L #4,A4 : I A4.L:=A1.L+4
2620 002'132 22BCFFFFFFFF MOVE. L #$FFFFFFFF, (A-I) ~ ~ MEM[A'1 ] :=$FFFFFFFF
2630 00~138 OC91FFFFFFFF CMPI. L #$FFFFFFFF, (A-I) ;~ IF MEM[A'I] -:::;. $FFFFFFFF THEN
2640 002-13E 6708 BEQ.S END3 ;~ ~ AO L:= ADDRESS TEXT ERROR 3
I

2650 002"140 41FA03AA LEA. L ERROR3O, AD

2660 002144 61000100 BSR FAILURE ;~ ~ il PRINT TEXT ERROR 3 II
2670 I ; I ENDIF
2680 002148 89CA END3 CMPA.L A2,A4 ; ~ DO WHILE A4=< A2
2690 002'14A 620C BHI.S EN032 ,-
.1 I

2700 00214C 4A94 TST.L (AA) ; ~ I IF f1EM(A4J o 0 THEN

27"10 oo214E 6704 BEQ.S OKT3 :~
2720 002"150 610000FE BSR TE5T11 ; I ~ / I ADORESS ERROR */
2730 I ; ~ ENDIF
I

2740 002"154 588C OKT3 AOOQ.L #4,A4 ; I I A4.L:=A4.L+4

2750 002'156 6OFO BRA.S EN03 ; ~ EN()[)O
2760 002'158 5889 EN032 AODQ.L #4,Al ; ~ A"1.L:=A"l.L+4
2770 00215A 60CE BRA.S LOOPT3 ;ENDOO
2780 *
2790 D02-15C 4CDF1300 ENOl1 MOVEH.L (A7)+,AO-A1iA4 ; RESTORE REGISTERS
2800 002"160 4E75 RTS

2820
2830
*
*1 TEST 4 : WALKING D
2840 * =================
2850 I
2860 I MODIFIES REGISTERS: 0 1 2 3 4 5 b 7
2870 I ---------------- 0 *
2880 I A*
2890
2900 I
* AO.L:= ADDRESS TEXT STRING4,INPUT PARAMETER PASSED
29'10 I 02.B:= 57F INPUT PARAMETER PASSEO
2920
*
2940 002162 48£72080 TEST4 HOVEM.L D2/AO,-(A7) ,SAVE ALTERED REGISTERS
2950 002160 E3CE LSl...B 11,D6 ;INDENTIFIER MOOllE 4
2960 002168 41FA03E2 LEA L
I ERROR4 ,AD ;AD. L:= ADDRESS TEXT ERROR 4
2970 00216C 747F MOVEQ 1$7F, D2 ; D2. B:=011 "l"U "1'1
2980 oo216E 612E BSR.S WALK ; CALLING SUBROUTINE WALK
2990 002170 4COF0104 MOVEH.L (A7)+,D2/AO ;RESTORE REGISTERS
3000 002174 4E75 RTS
30'10
3020
*
II TEST 5 : READ/WRITE (QUICK)
3030 I ========================
3040 I
3050 I MODIFIES REGISTERS: 0 1 2 3 4 5 b 7
3060 * ------------------0
3070 * AI *
3080 I

3100 002176 48E700CO TEST5 HOVEM.LAD-Ai, - (A7) ;SAVE ALTERED REGISTERS

3110 D0217A E30E LSL..B tt,06 ;IOENTIFIER MODULE S
3120 00217C B3CA LOOPT5 CHPA.L A2,A·t ;00 WHILE Ai =< A2
3130 00217E 62"18 BHI.S ENOS ,.
.1
 168 The 68000 Hardware and Software

3140 002-180 42'1 '1 CLR.B (AI) ~MEMEA'! J:=0

3'150 002"182 4AO-l TAS.B (A'I) ~R/M/W ; MEMEA'l J: =$80
3160 002'184 085'10007 BCHG.B #7,(AI) ~ MEMEA1 J: =$00
31 70 002-188 4A1-1 TST.8 (A-I) IF MEM[Al J <> $00 THEN
3-180 002-18A 6708 BEQ.S OKTS ~ 1* ERROR 5 *1
3'190 002'18C 4'1FA03FF lEA.l ERRORS, AO ~ AO.l:= A[)(JRESS TEXT ERS
3200 002190 610000B4 BSR FAILURE ~ 1* PRINT TEXT ERROR 5 */
32'10
3220 002-194 5289
*
OKT5 ADDQ. l ~t-1 ,Al
~ ENDIF
~ A'1.L:=A'1.l+'1
3230 002196 bOE4 BRA IS lOOPTS ENOOO
3240 002'198 4CDF0300 ENDS MOVEM.L (A7)+,AO-A'1 RESTORE REGISTERS
3250 002'19C 4£75 RTS
3260
3270
*** WALKING PROCEDURE
3280 * =================
3290
3300
** MODIFIES REGISTERS: 0 1 2 3 4 5 6 7
33'10 * ---------------- [) * * * *
3320
3330
* A**

3340
** 02.8:=$80 ,AOIL:= ADDRESS TEXT ERROR2
3350 * OR
3360 * 02IB:=$7F ,AO. L:= ADDRESS TEXT ERROR4
3370
*
3390 002'19E 48E7E8CO WALK MOVEM.L DO-D2/(i4/AO-Al,-(A7)
3400 0021A2 B3CA LWAlK CMPA.l A2,A'1 ;DO WHILE A-l=(A2
34-10 002-1M 622E BHI.S ENOW ;~
3420 002-1Ab 1811 MOVE.B (A'I) ,04 ; ~ SAVE HEM[A'1 J
3430 002-1 AB 7207 MOVEQ 18-1,D-I ; ~ 01.8:=07
3440 0021 AA '1282 LWALK-I HOVEIB D2, (A'1) : ~ FOR D2=N UNTIL 0 DO
3450 0021AC B4'1 '1 CMP.B (Al) ,02 ; ~ ~ MEM[AIJ :=D2.B
3460 0021 AE 67-1 A BEQIS OKTW ; ~ ~ IF HEM[A'! ] <::> [12 THEN
3470 0021 BO 2F08 HOVE.L AO,-(AT) ,..1 ~ SAVE AOIL
3480 oo21B2 61OO00DC BSR PDATA ,..1 ~ 1* PRINT TEXT ERROR *1
3490 0021B6 61000-140 BSR ADORTEST .1
~ 1* ADOR. TEST ODD/EVEN *
3500 0021 BA 204E HOVEIL A6,AO ,..1" ~ AO.l:= ADDR O[Jo/EVEN
35-10 002-1BC 6HlO0002 BSR PDATA .1
~ 1* PRINT ADDRESS *1
3520 OO21CO 2009 MOVE.L A'l,DO ,.".1 ~ 00:=00-07/08-[;15
3530 OO21C2 61000100 BSR OUTHEX .1 I
~ 1* PRINT DO.L *1
3540 002'1 C6 6l-12 BSR.S DELAY ,-".1 ! 1* OISPLAY DELAY *1
3550 002-1 C8 205F MOVE.L (A7)+,AO ,..1 ~ RESTORE AO.l
35bO .1 ~ ENDIF

3570 0021CA E2-1A

*
OKTW ROR.B 1-1,02 ".1
3580 002lCC 5-1C9FFOC HBRA 0'1,LWALK1 ;"~ ENDFOR
3590 D02-lDO 12C4 MOVE.B 04,(A1)+ ; ~ RESTORE MEM[A1J;A1.L:=+1
3600 002102 bOCE BRA.S lWALK ;ENDOO
3610 0021 D4 4C[}F0317 ENDW MOVEM.L (A7)+,[)0-D2/04iAO-A-I
3620 002-108 4E75 RTS

3640
3650
*** DELAY FOR DISPLAYING
3660 * ==================

** MODIFIES REGISTERS: 0 -1
3670
3b8D 234567
3690 * ------------------[) * *
3700 * A
37"10
*
 Programming Exercises 169

3730 002"1 DA 4BE70500 DELAY MOVEM.L D5/[i7,-(A7) SAVE ALTERED REGISTERS

3740 002"1 DE 7A04 MOVEQ #5-"1, DS
3750 002"1 EO 3E3CFFFF LPT2 MOVE.W #$FFFF .D7
3760 002'1E4 S'1CFFFFE LPT"l DBRA [l7,LPTl
3770 002'1 EB 5"1 COFFF 6 DBRA OS ,LPT2
3780 002'lEC 4CDFOOAO MOVEM.L (A7)+,DS![I7 RESTORE REGISTERS
3790 002-1 FO 4E75 RTS
3800 I

38'10 II GET ADORESS OF KEYBOARD

3820 '* =====================
3830 * D2.8:= ERROR FLAG
3840 * 0'1.8:= COUNTER CHAR
3850 I D3.L:= ADDRESS
3860 I MODIFIES REGISTERS: 0 "1 2 3 4 5 6 7
3870 '* ------------------
3880 I [I I '* *
3890 * A
3910 002-1F2 48E76000 INADD MOVEM.L (j"1-D2,-(A7) SAVE REGISTERS
3920 002'1F6 4283 CLR.L 03 03.L:=0
3930 002'IFB 7205 MOVEQ #6-1,D"1 INITIALISE COUNTER
3940 002-1FA 6"112 LOOPAD BSR.S INMEX
3950 002"1FC 4A02 TST .B 02
3960 002"1FE 6808 BtU.S ENDAO
3970 002200 E9BB LSL.L #4,[J3
3980 002202 0680 ADO.L [)0,O3
3990 002204 5-1 C9FFF4 DBRA D-l,LOOPAO
4000 00220B 4CDFoo06 ENDAO MOVEM.L (A7)+,D"1-02 ; RESTORE REGISTERS
4010 D0220C 4E75 RTS

4030 *
4040 ** GET ONE HEX CHARACTER
4050 * ========================
4060 * IF 0-9 OR A-F THEN CONVERTED BCD OTHERWISE [J2. B:=$80 AND RETURN
4070 *
4090 00220E 610000A4 INMEX BSR INPUT-I ;GET ON HEX
4100 0022"12 61000094 BSR OUTCH1 ;ECHO
4110 0022"16 OCOOOOOO CMPI.B #CR,DO ; IF CHAR=CR THEN
4"120 0022'1 A 6606 BNE.S SUITEMEX
4-130 0022-1 C 08C2ooo7 BSET .B #7,D2 ; ~ [l2.B:=$80
4-140 002220 60-14 BRA.S ENDt'1EX ; ~ RETURN TO INAD[)
;ELSE
4'150
4160 002222 04000030
*SUITEMEX SUBI. B i'D' ,00 ; ~ ASCII-)BCD CONVERSION
4170 002226 47FAFFE6 LEA.L INMEX,A3 ;! A3:= a RETURN IF TRAP CHK
4"180 00222A 4"1BC0016 CHK #$-16,00 ; ~ IF CHAR <0 OR :>9 THEN
4"190 ; ~ ~ 1* TRAP CHK */
* ; ~ ENDIF
4200
42-10 oo222E OCOOOOO9
* CMPI.B #9,00 ; ~ IF CHAR) 9 THEN
4220 002232 bF02 BLE.S ENDMEX */
;! ~ / '* AJUST
4230 002234 5FOO SUBQ.B #7,00 ; ~ ENOIF
4240 002236 4£75 ENDMEX RTS

4260
4270
*** TRAP CHK
4280
* --------
4300 002238 7007 CHECK MOVEQ #BEL,DO ; BIP ~ ~
 170 The 68000 Hardware and Software

4310 00223A 61bC BSR. S OUT CH1 OUTPUT CHAR

4320 00223C 7008 HOVEQ ISS, DO B.SPACE
4330 00223E 6lba BSR •S OUTCH1
4340 002240 2F4BOO02 MOVE.L A3,2(A7) STORE RETURN A[t[lRESS
4350 002244 4E73 RTE
4370
4380
* PRINT TEXT STRING PROCEDURE
**
4390 * ==========================
4400 *
4420 002246 6-148 FAILURE BSR. S P[JATA ; OUTPUT TEXT
4430 002248 2009 MOVE.L At,00 ; 00.L: = ADORESS ERROR
4440 00224A 6'178 BSR. S OUTHEX ; OUTPUT ADDRESS ERROR
4450 00224C (,.18C BSR.S OELAY ; OISPLAYEO OELAY
4460 00224E 4E75 RTS

4480
4490 II
* PRINT THE IILINE Il ADORESS ERROR
4500 * ==============================
45-10 I IF THERE IS A FAILURE ,THE SUBROUTINE EXECUTES AN "EXCLUSIVE OR" BETWEEN
4520 I THE TWO POINTERS (A4.L & A1.L). THE RESULT WILL BE A LOGICAL '1 IN EACH
4530 * BIT POSITION WHERE THERE WAS A FAILURE.
** MOOIFIES REGISTERS: 0 -1 2 3 4 5 6 7
4540
4550
4560 * ------------------0 * * * * *
4570 * A*
4580
*
4600 002250 48E74480 TEST3'l MOVEM.L [l-1/05iAO.-(A7) ;SAVE ALTERE[I REGISTERS
46-10 002254 2209 MOVE.L A1,0-1 ; D-I •L: = AOORESS ERROR
4620 002256 2Aoe MOVE.L A4,OS ; [15 •L: = ADDRESS ERROR
4630 002258 8385 EOR.L 0'1 ,OS ;D5.L(±)D-1.L :=OS.L
4640 00225A 41FA02CE LEA.L ERROR31 ,AD ;AO.L:= A[)DRESS TEXT ERROR
4650 00225E 6-130 BSR.S POATA ;PRINT TEXT
4660 002260 6106 BSR.S BINARYADOR •CALLING OUTPUT BINARY AOR
4670 002262 4C[lFO-122 MOVEM •L (A7) +, AD.I 0-11 [15 ; RESTORE REGISTERS
4680 002266 4E75 RTS
4690 I
4700 002268 48E7B400 BINARYADDR MOVEM.L DO/02-03!(i5.-(A7) ;SAVE ALTERED REGISTERS
47'10 00226C 7407 MOVEQ 18-'1. (12 •NUMBER NVBBLE
4720 oo226E 7603 RBIN-l MOVEQ #4-1•D3 :NUMBER BIT
4730 002270 610000CC BSR SPACE
4740 002274 103C0058 RBIN2 MOVE.B #f Xi .DO .DO.B:=$S8
4750 002278 E380 LSL. L #-1 •OS
4760 00227 A 6404 scc.s RBIN3 ; IF 81T=0 THEN
4770 00227C 103C0031 MOVE.B i!l! ,DO : ~ If : X' DISPLAYEli Ii
4780 002280 6126 RBIN3 BSR. S OUT CH"t : ELSE
4790 002282 5'1 CBFFFO OBRA [13. RBIN2 ; i l* : '1' DISPLAYED to
4800 002286 5'1 CAFFE6 [JBRA 02.RBIN-! ; ENDIF
48'10 00228A 4COF002D MOVEM.L (A7)+.DOi[J2-[J3iD5
4820 00228£ 4E75 RTS
4840
4850 ''*** PRINT TE~T STRING OF CHARACTERS
4860 I ==================================
4870
4880 '* MODIFIES REGISTERS: 0 '1 2 3 't s6 7
 Programming Exercises 171

4890 * ------------------0 *
4900 * AI

4920 002290 48£78080 PDATA MOVEM.L AQ/OO,-(A7) ;SAVE ALTERED REGISTERS

4930 002294 '1018 POATA1 HOVE.B (AQ)+,OO ; DO WHILE 00 <> EOT
4940 002~~6 OCOOOOO4 CMPI.8 IEOT, 00
4950 00229A 6704 SEQ.S ENDPD
4960 00229C 610A BSR. S OUT CHi ! 1* OUTPUT CHAR *1
4970 00229E bOF4 BRA.S POATA1 ;
4980 oo22AO 2C48 ENOPD MOVE.LAD, At, ; ENOnO
4990 0022A2 4CDF0101 MOVEM.L (A7)+,AO/DO
5000 0022Ab 4E75 RTS
5010 I

5020 ** TEST ACIA 6850 READY FOR TRANSMIT

5030 I =================================
5040
5050 0022A8 08-150001
*
OUTCH-! BTST.B ~H, (AS) ; DO WHILE TORE =0
5060 0022AC 67FA BEQ.S OUTCH'l ; ! 1* READ STATUS *1
5070 0022AE 18400002 HOVE.8 [JO,2(A5) ; ENDOO
5080 002282 4£75 RTS
5090 I
5100 ** INCHNP GETS DO CHAR (NO PARITY)
51"10 * ===============================
5120 I
5130 oo22B4 08150000 INPUT-1 8TST.8 #0, (AS) ; 00 WHILE RORF =0
5'140 0022B8 67FA BEQ.S INPUT-I ; ~ 1* REA[) STATUS *1
5'150 0022BA '102D0002 MOVE.B 2(AS) ,DO : ENDO
5160 00228E 0200007F AND!.B 1$7F, DO ; REAO CHAR AND MASQ
5170 OO22C2 4E75 RTS
5180 I
5190 1* OUTPUT IIFAILED ADORESS II ON THE CONSOLE
5200 I ======================================
52'10 * MODIFIES REGISTERS: 0 '1 2 3 4 5 6 7
5220 * ------------------[1 * * *
5230 * A
5240
5250 OO22C4 48E70000
*
OUTHEX MOVEM.L DO-O'l/D3,-(A7) ;SAVE AlTERE[) REGISTER
5260 OO22C8 7207 MOVEQ 18--1,0'1 ; COUNTER DIGIT=7
5270 0022CA 2600 MOVE.l 00,03 ;03.L:= ADDRESS ERROR
5280 0022CC E99B LOOPOUT ROL.L 14,03 ; REPEAT
5290 oo22CE 2003 MOVE.L 03,[JQ
5300 002200 0200000F AND1. B I$F, DO ~ MASQ
53'10 002204 06000030 A[)0!.8 II OJ , 00 ~ BCD - > ASCI I CONVER.
5320 002208 OC000039 CMP1. B # 9 DO
1
1
, ! CHECK FOR A-F
5330 0022DC 6302 BlS.S ASCIICH
5340 oo220E san ADDQ.B 17,00 ! AJST. FOR HEX A-F
5350 0022EO 61C6 ASCIICH BSR.S OUTCH'1 ~ OUTPUT CHAR.
5360 0022E2 51C9FFE8 [lBRA O'l,lOOPOUT ; UNTIL 0'1=-'1
5370 oo22E6 4COFOOOB MOVEM.L (A7)+,00-0'1 !D3 ; RESTORE REGISTERS
5380 0022EA 4E75 RTS
5400 I
54-10 ** STOPPING 68000 MICROPROCESSOR
5420 * ============================
5430

5450 0022EC 41FA02EO STOPPING lEA.L TEXTRST ,AD

5460 0022FO 6-19E BSR.S P[)ATA
5470 0022F2 4£722700 STOPPEO-l STOP 1$2700
 172 The 68000 Hardware and Software

54BO 0022F6 60FA BRA.S STOPPED-!

5500
55'10
* TEST : ADDRESS ERROR
**
5520 * ====================
5530
5540
** IF ADDRESS ODD (UDS) THEN DATA BUS IS [;8-015
5550 * IF ADDRESS EVEN(LOS) THEN DATA BUS IS DO-D7
5560
5570
** MODIFIES REGISTERS: 0 '1 2 3 4 5 6 7
55BO * ------------------0 * * *
5590 * A
5600
*
5620 0022FB 4BE70000 AODRTEST MOVEM.l 00-D·I/D3~-(A7) ;SAVE AliEREO REGISTERS
5630 0022FC "100'1 MOVE. B (J-1 ,00 ;SAVE ERROR POSITION
5640 0022FE 2609 MOVE.L A-1, D3 ; 03.l: = ADDRESS ON ERROR
5650 002300 08030000 8TST.8 #0,03 ; IF ADDRESS EVEN THEN
5660 002304 6628 BNE.S ODD
5670 002306 5040 AODQ #8,DO ; ~ II ADJUSTMENT D8-(l'15 */
56BO 002308 OCOOOO09 CMPI.8 19,DO ; ~ IF DIGIT >=9 THEN
5690 00230C 6F20 BlE.S O[)[; ;~
5700 00230E 0400FFFA SUBI.B #-6,00 ;~ ~ II DECIMAL AJUST II
57"10 0023-12 "1600 MOVE.B 00,03 ;~ ~ 03.8:=00.8
5720 0023-14 7201 MOVEQ 12-'1 ,01 ;~ ~ 0-1. B:=-1
5730 002316 E9'1B EVEN ROL.B 14,03 ;~ ~ REPEAT
5740 0023-18 2003 MOVE.l 03,00 ;~ ~ OO.l:=D3.l
5750 0023"1A 0200000F ANOI.8 #SF, DO ;~ ~ MASQ MSB OIGIT
5760 0023"1E 06000030 AODLB #'0' ,DO ;~ ~ BCD-)ASCII CONVERSION
5770 002322 6'184 BSR.S OUTCH'! ;~ ~ OUTPUT DIGIT
5780 002324 5'1C9FFFO OBRA 0'1 , EVEN ; ~ ~ UNTIl [J-l =--1
5790 002328 4COFooOB EXITAOR MOVEM.l (A7)+,[l0-O-1/03 ; ~ ENDIF
5800 OO232C 4E75 RTS ;~
58-10 00232E 6"10E ODD BSR. S SPACE ;ElSE
5820 002330 0200000F ANDI.S #fF,DO ; ~ 1* OUTPUT SPACE *1
5830 002334 06000030 ADDLB #'0 ' ,DO ; ~ II MASQ MSB 01G1T *1
5840 002338 6"100FFbE BSR OUTCHl ; ~ 1* BC[l=)ASCII CONV *i
5850 00233C bOEA BRA.S EXITAOR ; ~ 1* OUTPUT DIGIT *
58bO
* ;ENDIF
5880
5890
*** PRINT SPACE
5900 * =========
59-10 I MODIFY REGISTER: 00
5920
*
5940 00233E 2FOO SPACE MOVE.l DO,-(ATi ;SAVE 00
5950 002340 7020 MOVEQ ISPC,DO
5960 002342 6"100FF64 BSR OUTCH-l
5970 002346 20-1F MOVE.L (A7)+,DO ;RESTORE DO
5980 002348 4E75 RTS

*** ACIA 6850 INTERRUPT

6000
6010
6020 * ===================
6030
6040 00234A '10200002
*IRQ6850 MOVE.S 2(AS),DO
6050 00234E 41FA0303 LEA.L TEXTIRQ,AO
6060 002352 6100FF3C BSR PDATA
 Programming Exercises 173

6070 002356 4E722'100 STOP #$2'100 ; LEVEL '1 ACIA MASQ

6080 00235A 4E73 RTE

6'100
61"10
*** SPURIOUS INTERRUPT
6'120 * =================
6'130 *
6'140 00235 C 4'1 FA0320 SPURIOUSIRQ LEA.L TEXTSPURIOUS,AO
6150 002360 610OFF2E BSR PDATA
6'160 002364 4E13 RTE

6'180
6'190
* LEVEL 7 INTERRUPT
**
6200 * ================
62'10
*
6230 002366 41FA0344 LEVEL7IRQ LEA.L TEXTLEVEL7,AO
6240 oo236A 610OfF24 BSR PDATA
6250 oo236E 4E73 RTE

6270 .
6280 **
as ERROR AND ADDRESS ERROR PROCEDURE
6290 * ====================================
6300
63"10 ** CASE
6320
6330 I IF BUS ERROR OR ADDRESS
~ ERROR DURING TEST-l THEN EXECUTE TEST2
6340 I IF BUS ERROR OR ADDRESS
~ ERROR DURING TEST2 THEN EXECUTE TEST3
6350 * ! IF BUS ERROR OR AODRESS ERROR DURING TEST3 THEN EXECUTE TEST4
6360 .. ~ IF BUS ERROR OR ADORESS ERROR DURING TEST4 THEN EXECUTE TESTS
6370 .. ~ IF BUS ERROR OR ADDRESS ERROR DURING TESTS THEN END
6380 .. !
6390 .. OTHERWISE
6400 * ~ I" ERROR STOPPING 68000 MICROPROCESSOR II
64'10 .. I

6420 .. ENOCASE
6430
6440
*
6450 002370 4'1FA02B4
*ERRORBUS LEA.L TEXTBUS,AO
6460 002374 6100FF1A BSR POATA ;
6470 002378 202FOO02 MOVE.L 2(A7) ,DO ; RESTORE AODRESS ERROR
6480 00237C 610OFF46 BSR OUTHEX ; PRINT ADDRESS ERROR
6490 002380 6'100FE58 BSR DELAY ;DISPLAYED [JELAY
6500 002384 '1 C06 MOVE.B 06,06 ;REGISTER CCR POSITIONED
65'10 002386 6742 BEQ.S OTHERWISE ; ERROR STOPPED 68000
6520 002388 44C6 HOVE.B 06,CCR ;CCR:=06.B
6530 00238A 650C scs.s MODULE'! ;ERROR DURING TEST'!
6540 00238C 69'14 BVS.S MOOULE2 ;ERROR OURING TEST2
6550 oo238E 67"! C BEQ.S MODULE3 ;ERROR DURING TEST3
6560 002390 6B24 BMI.S MODULE4 ;ERROR DURING TEST4
6570 002392 602C BRA.S MODULES ;ERROR DURING TESTS
6580 002394 508F EXITBA AO[J.L 18,A7 ;NO GOOD BUT ~ ~ ~
6590 002396 4E73 RTE
6600 ..
6ifl0 002398 47FAFD74 MOOULE1 LEA. L TEST2, A3
6620 00239C 2F4BOOOA MOVE.L A3,10(A7) RETURN EXECUTE TEST 2
6630 0023AO 6OF2 BRA.S EXITBA
6640 ..
 174 The 68000 Hardware and Software

6650 0023A2 47FAFD80 MOOULE2 LEA.L TEST3,A3

6660 oo23A6 2F4BOOOA HOVE.L A3,'10(A7) RETURN EXECUTE TEST 3
6670 oo23AA 6OE8 BRA.S EXITBA
6b8O
6690 0023AC 47FAF084
*
MOOULE3 LEA.L TEST4,A3
6700 002380 2F4BOOOA MOVE.L A3,10(A7) ;RETURN EXECUTE TEST 4
6710 oo23B4 bODE BRA.S EXITBA
6720
6730 002386 47FAFDBE
*HOOULE4 LEA.L TEST5,A3 ;
6740 oo238A 2F48000A MOVE.L A3,.10(A7) ; RETURN EXECUTE TEST 5
6750 00238E 6004 BRA.S EXITBA
6760
6770 OO23CO 47FAFC[~
*
MOOll.E5 LEA.L ENOTEST ,A3 ;
6780 0023C4 2F4BOOOA HOVE.L A3,'10(A7) ;ENO TEST
6790 OO23C8 bOCA BRA.S EXITBA
6800
6810 0023CA 47FAFF20
*
OTHERWISE LEA. L STOPPING,A3 ;
6820 oo23CE 2f4BOOOA HOVE.L A3,10(:A7) ;ERROR STOPPING 68000
6830 002302 bOCO BRA.S EXITBA

** TEXTS
6850
6860
6870 * ====
6880
6890 002304 'IB
*AOORBEGIN DC. B $'lB,$45,$18,$b8
6900 002308 40 (lC.B 'MEMORY TESTS : (C) '1984 BY MICROPROCESS ,INC I
69-10 002405 1B nC.B ua, $69 ,LF,LF,LF,LF,CR
6920 00240C 50 DC.B I PRESS ANY KEY TO STOP PROGRAM .'
6930 00242D OA [lC.B LF,LF,LF,CR
6940 002431 20 DC.B BEG AOORESS ----:> '
6950 00244E 04 OC.8 EOT
6960 00244F OA ADDRENO DC.B LF,CR
6970 00245'1 20 £lC.B END ADDRESS ----:> I

6980 00246E 04 OC.B EOT

6990 0024bf OA ERROR"1 DC.B LF,LF,CR
,
7000 002472 20 DC.B IT" 5 IMPOSSIBLE TO WRITE "011
,
7010 002498 20 DC.8 IN ====>
7020 0024AC 04 OC.B EOT
7030 0024AO OA ERROR2 DC.B LF,CR
7040 oo24AF 20 oe.B IT"5 IMPOSSIBLE TO CARRY "'1 11 IN 0'
7050 002408 04 DC.B EOT
7060 002409 20 OC.B IN ====> !

7070 oo24EB 04 OC.B EOT

7080 oo24EC OA ERROR30 ec.s LF,CR
7090 oo24EE 20 (lC.B IT!JS IMPOSSIBLE TO WRITE Ill"
7100 002517 20 cc.s IN ====)
7110 002529 04 OC.B EOT
7'120 00252A OA ERRORJl OC.B LF,':R
7'130 00252C 20 ec.s AODRESS'I ERRORS ====> J

7140 002548 04 OC.B EOT

7'150 00254C OA ERROR4 (tC.B LF.CR
7160 00254E 20 OC.8 IT' '5 IMPOSSIBLE TO CARRY "O!! IN [;1
7170 002577 04 oc.s EOT
7180 002578 20 DC.B IN ====>
7'190 00258C 04 OC.8 EOT
7200 002580 OA ERRORS OC.B LF.CR
72'10 00258F 20 OC.B TIMING'i PROBLEMS
 Programming Exercises 175

7220 002586 20 DC.B IN ====) I

7230 (u~CD 04 DC.8 EOT
7240 0025CE OA TEXTRST OC.8 LF,CR
7250 002500 20 OC.8 PRESS ON RESET TO QUIT
7260 0025F5 04 OC.8 EOT
7270 0025F6 OA STRINGS DC.B LF ,LF,LF,LF,CR
7280 0025FB 20 OC.8 END MEMORY TESTS
7290 002622 OA DC.B LF ,LF,CR,EOT
7300 002626 OA TEXTBUS DC.B LF,CR
7310 002628 20 DC.B BUS ERROR OR ADDRESS ERROR
7320 002652 04 DC.B EOT
7330 002653 OA TEXTIRQ DC.B LF ,LF,CR
7340 002656 20 DC.B PRESS ON ABORT TO CONTINUE I
7350 002670 04 OC.B EOT
7360 00267E OA TEXTSPURIOUS DC.8 LF ,CR
7370 002680 20 OC.8 SPURIOUS INTERRUPT ~! ~
7380 oo26A9 OA DC.B LF,CR,EOT
7390 OO26AC OA TEXTLEVEL7 OC.B LF,CR
7400 0026AE 20 DC.B TESTS PROGRAM R~NING I
7410 oo26CF OA DC.B LF,EOT
7420 002601 OA STRIN61 DC.B LF ,LF, CR ,SP ,SP ,SP ,SP ,SP ,SP,SP ,SP
7430 oo26DC 20 DC.B E N [) oF T EST
7440 002705 OA DC.B LF ,LF,CR
7450 002708 20 OC.B 00 YOU WANT CONTINUE THE TEST? (YIN) I

7460 00273A 04 [IC.B EOT

7470 002738 OA STRING2 OC.B LF ,LF,CR,SP,SP,SP ,SP,SP,SP,SP ,SP
7480 002746 20 DC.B E N [t oF T EST 2
7490 00276F OA OC.8 LF ,LF,EDT
7500 002772 OA STRING3 OC.B LF ,LF, CR, SP ,SP, SP ,SP ,SP,SP,SP ,SP
7510 002770 20 OC.8 END oF T EST 3
7520 0027A6 OA DC.B LF ,LF.EOT
7530 0027A9 OA STRING4 DC.B LF ,LF,CR,SP,SP,SP ,SP ,SP,SP,SP ,SP
7540 002784 20 DC.B END oF T EST 4
7550 002700 OA DC.B LF ,LF.EOT
7500 D027ED ooooooca OS.L 50
7570 000028A8 STACK EQU f
7580 ENO

ff*H* TOT At. ERRORS 0-- 0

SYMBOL TABLE - APPROXIMATELY 4'15 SYMBOL ENTRIES LEFT

ABORTIT 00007C ADOERROR OOOOOC AO[lRACIA 01F9E9 AODRBEGI oo23D4

AOORENO 00244F AOORF 0020E2 ADDRTEST 0022F8 ASCIICH oo22EO
BEGIN 002000 BEL 000007 BINARYAO 002268 8S 000008
BUSERROR 000008 CHECK 002238 CR OooOOD DELAY 002'l[lA
EN03 002148 EN031 002'15C END32 002'158 ENDS 002'198
ENDA[J 002208 ENOME X 002236 ENOP[; 0022AO ENOll 002'108
ENOTEST 00209C ENDW 002'104 EOT 000004 ERROR1 00246F
ERROR2 0024A[) ERROR30 oo24EC ERROR31 002S2A ERROR4 00254C
ERRORS 002580 ERRORBUS 002370 EVEN 0023'16 EXITAOR 002328
EXITBA 002394 FAILURE 002246 lNA[l[l 0021F2 INITACIA 0020A2
INITIRQ 0020BA INMEX 00220£ INPUT-l 002284 I NPUTHEX 0020CO
IRQb8S0 00234A IRQACIA 0000b4 LEVEL71 R 002366 LF OOOODA
lOOP 0020'12 LOOP1 002080 LOOPAO 002'lFA LOOPOUT 0022CC
LOOPT-l 0020f=2 LOOPT3 002'12A LOOPTS 002'17C LPT'l 002'1E4
LPT2 002'1EO LWALK OOl-tA2 LWALK'l 002°1 AA MODULE'1 002398
176 The 68000 Hardware and Software

MOOULE2 0023A2 MODULE3 0023AC MOOULE4 0023B6 MODULES 0023CO

000 00232E OKT3 002'154 OKT5 002'194 OKTST1 002'104
OKTW 002-1 CA OTHERWIS 0023CA OUTCH'1 0022A8 OUTHEX 0022C4
POATA 002290 POATA-1 002294 RBIN'1 00226E RBIN2 002274
RBIN3 002280 SPACE 00233E SPC 000020 SPUR I OUS 000060
SPURIOUS 00235C STACK 0028A8 START 000004 STOPPED'! 0022F2
STOPPING 0022EC STRING1 0026[11 STRING2 002738 STRIN63 002772
STRING4 0027A9 STRINGS 0025F b SUI TEMEX 002222 TEST 1 0020EC
TEST2 00210E TEST3 002-124 TEST31 002250 TEST4 002'162
TESTS 002'176 TEXTBUS 002626 TEXT I RQ 002653 TEXTLEVE 0026AC
TEXTRST 0025CE TEXTSPUR 00267E TRAPCHEK 000018 WALK 002'19E

t1EMOR'( TEST S : (C) '1 9B/1 nY Mr CROPROCE: SS , I Ne

Press any key to stop program

BEG1NNJ:NG (-lD[)I~E:SS "~_'"MM" > 7ElOO
ENDING ADDRESB ..-. -"~. > 7 ElO4
.~

E N D 0 F r E s T "1

DO YOU WANT CONTINUE THE TEST ",' (YIN) y

I r'~; IMPOSBIBLE TO CAJ~I?Y ""1" IN D 7 IN :::::::::::: > oooo lBO'"
JT'S IMPOSSIBLE TO CARRY "'1 " IN D (,) IN ::::-.:::~::: > ()()()0 7 B()'1
IT l'~) IMPOSS.[l3l..E TO CAI~I~Y '····1" IN D ~) IN :::::::::::: > O()()()7BO"1
IT' s IMPOSSIBL.E TO CARr't~ y "'1" IN D It IN :::-':::::::-M': > 0000/ so-
IT'S IMPOSSIBLE TO CAt~I~Y n'I" IN D ;.~ 3? IN ::::::::::::: > D() () () 700 "1
IT' f; IMPOS~)IBL..E TO C(,,'~I;:Y "1 " IN [) '1 IN
,~ =::::::::::: > oo()o7 B o'1
.r r' ~J '[~1PO~)GIt3LE TO Cf'l~ J~ Y IN D o IN
' ..•. , u ::::::::::::: ) () () 0 () 7BO '-1
o
JT' ~3 I MP O~)S I BL.E TO CARI~Y "'1" IN D 7 odd IN
I r : ~3 I"1POS~3 I BI...E TO CAJ~t~ y " .. ,.' IN D (, addressesI N , :::::::::::: >
::::::::::::: >
()()()() 7 B ~~
()()()()7BO~3

IT'B IMPOSSIBLE TO Cf"-\~~R''r' "-1 " IN [) ~'; IN :::::::::::::: ) 0OOO7B()~}

IT'B IMPOGBIBl...E TO C('~I~ I~ y IN D it IN
u .., , ,
:::::::::::: ) O()()07B()::3
IT' f:~ IMPO~)B IBI...E TO C~~RI~ y " '1 .'~ IN n ;.~ 3? IN :::::::::::: > ()O(l()7B():~
.f T T~, IMPOB~3 I13LE TO C(~I~I?Y '····1'·· IN D '-1 IN :::::-.:::::::: ) O(){)07BO:]
I "r '~; I MPO~>S IBI...E TO C{-\Rr~Y ""1 IN D () IN N :::::::::::::: > ()()()()7BO~;

E N D 0 F T r G T ,')
,,0:..

1::: N D o F

··'0···· ... ,
IT '!~) I ~1P O~)~·;:I. BI'OF TO Ci~RRY IN [) .•j 1N OCtOO?~~()'1
1 r'~; r r1 P 0 ~:3 ~3 I E: l. F TO Ct~r~ I~ y "'0" IN D ...•.•j
line IN ::::::::::::: > f)UDO/UO:]
fault
F N D 0 F T E ~) T ';

END MEMOI~~ y TF~:3T~;

PI?Ef.)S ON RE'SET TO QUIT

Crash occurs because a data bus line is down (odd address LDS = 0; UDS = 1).
 Programming Exercises 177

MEMORY TE~~TS: (C) '19El'; BY MICROPROCESB ,INC

Press any key to stop program

BEGINNING (-l[)[)I~ESS -....-_.-.) ?B()()
ENDING ADDI?EBS .-.------ > 7~}()~.~

END o F T EST ..,

DO YOU ~J(.lNT CONTINUE: THE TEST . ? ('(/N) Y

IT'S IMPOBSTI3I...E TO CI~~I~'~Y ,.. ..l " IN D"'I IN ::::::::::::) OO()(J7BO()
rr 1 SIMP OS~) I Eo} 1... [ TO C(.lR I~ y ""1'" IN 1)'1'1 IN ::::::-.:::::: > ()()()()7B()~~

line fault
END o F

IT'S 1 MP 0 S S I Eo} I... E T o ~JI~ 1 TE""1 ." IN :::::~:::::::: > O()()07BOO

PI~E~3S ON ABOI~ T TO CONTINlJE program stopped via keyboard

oOf FST~) Pf<OGR(.-IM RUNNl NG level 7 interrupt

END o F E B r :]

IT'S IMPOSSIBL..E TO NO'" IN [)'1 ~i

C(-lr.~.r~ y IN :::::::::::::::: ) OOOO?BOO
r T' ~3 IMPOBBIBLE TO CAI?I?Y "'0" IN D·ll.t IN :::::::::::::: > OOOOlBOO
IT'S IMPO~)SlBI...E TO Cf~ll~ I~ '( · .. 0.., IN [)'1 :~ IN :::::::::::::: > 0OOO7BO()
IT'S It-1POS~3 IBLE TO C(~,~,~y ,.' ()" IN D'I;~! IN ::::::::::::: > 0OOO7BOO
IT'S 1 MP 0 f; SIB LE TO CAr~RY
..,() ....
IN [)'1 () 11? IN ::::::::::::::: > O()()()/BO()
IT' ~3 IMPOSGIBLE TO C(.~I~I~ Y . . 0" IN D a:;~ IN :::::::::::::: > iJOI.J()/BOO
IT'S IMPOSSIBLE TO Cf.ll~~ RY ..,() ....
IN D B even IN ::::::::::::::: > O()()()7HOO
.f T 1 ~3 I 1'11' OB~3 I t3 LE TO CAI~I~Y IN
,.' ()'" 1)"1 ~:; addresses IN ::::::::::::::: > ()()OO7nO::.~
IT' ~) IMP O~) BIB L.. E TO cr,p F·~ Y 0"
IN
()'"
D'1I, TN :::::::::::::: > o()() 0 7 B ()~?
IT'B I l'iP O~)~3 I BLETO C(~I~I~Y "0" IN
.... () ..,
1)"1::3 IN :::::::::::::::: > oo()() 7 no~:.~
JT' s I ~iPO~)S I BL..E TO C~~lRRY IN [')'1 ~! IN ::::::::::::::: > ()0007 B()~!
Ir"s IMPOBBIBLE TO CAI~J~Y "() '.' IN I)'" () 11? IN :::::::::::::: > (){){)()7BI.J:':~
IT'S IMPOS~; IBLF.: TO C~~\R I~ \{
.... ()'"
IN o 9 IN :::::::::::::: > 00007 B()~!
IT'S It'1POBGI13l..E TO f:A'~I~Y uO" IN D B IN :::::::::::::: ) o()oo7 an ;:.~
E: N [) 0 F T E c.
,,) T 'i
TIMING PI~~OBLEMS IN :::::::::::::: > 0OOO7BO()
TIl-1ING PI~OI3LEMB IN ::::::::::::::: > o o o o 7BO ;;~

END MEMor~ Y TESTS

P I~ ES~3 oN I~ EBE r r o QUI T

Same program crash as in previous simulation, but this time at even

addresses (LDS = 1; UDS = 0).
 178 The 68000 Hardware and Software

ME MOR Y TESr S : (C) '1 9B It BY M J: CR OP R OCE: S S ., INC

Press any key to stop program

BEG INN J NG ~~ [) DR E: SS MM 'M' M_} 7 ElOO
ENDING ADDt~EBS M
.....M> 7FFF

END <) F rEG T "

DO YOU '-'JANT CONT 1NUE THE TEST ,~, (Y IN) Y

END <) F

~:~,[)D'~ E ~;f:::" s Er~RORS ::::::::::: > XXXX XXXX XXXX XXXX XXXX XXX X XXX'1 XXX>::
ADDI~E~3S" B E'~I~OI~S :::::::::::: ) XXXX
~(XXX X;'(XX XXXX XXXX XXXX XXX'" xrxx
f~,DDR E~)S' S [r~ r~ Ol~~ S :::::::::::: > XXXX XXXX XXXX XXXX XXX X XXXX XXX'1 XXXX
ADDI~ESB' S Et~I~OI~S ::::::::::::: > XXXX XXXX XXXX XXXX XXXX XXXX XXX"1 '1 xxx
ADDRE~)S'S ERRORS ::::::::::::: > XXXX XXXX XXXX XXXX XXXX XXXX XXX'1 '1'1 XX
ADDREBG'G ERJ~OI~B :-.:::::::::::: ) XXXX XXXX XXXX XXXX xxxx XXXX XXX'" XX;(X
(',D{)RE~)S" S ERRORS ::::::::::::: ) XXXX XXX
PRE~3G ON ABORT TO CONTINUE interrupt
-rEST~) PROGr~AM RUNNING
XXX)( XXXX XXXX XXXX XXX'1 '1'1 XX
ADDRE~3S' G EI~J~OI?S ::::::::::::: > XXXX XXXX XXXX XXX X XXXX XXXX XXX"1 "1 XXX
f~DDR E~~S'~) ERRORS :::::::::::: } XXXX XXXX )(XXX XXXX XXXX XXXX XXX'1 X'1XX
ADDJ~ES~J' B EI~I~Ot~S ::::::::::::: > XXXX XXX;( XXXX XXXX XXXX XXXX XXX'1 XXXX
{:,D[)I~ ESS ' S Er~RORS :::::::::::: > XXXX XXXX XXXX XXXX XXXX XXXX XXXX X"IXX
ADDI~ EB~; r ~3 EI~I~OI~S ::::-.:::::::::) XXXX XXXX XXXX XXXX XXXX XXXX XXXX -'I XXX
~~DOI~ E SS 7 ~) EI~RORS ::::::::::::: ) XXXX xxxx X:XXX xxxx xxxx X:x:XX >()t'~XX -1"1 XX
~'DDI~ESG'S E:1~t~OI?B :::::::::::: > XXXX XXXX XXXX XXXX XXXX XXXX XXXX ·1·'IXX
{,DDRESS'S ERI~OI~S ::::::::::::-.: > XXXX XXX X XXXX XXXX XXXx. XXXX XXXX '1XXX
ADD1~EBB' B Er~I?OI?B ::::::::::::;. XXXX XXX X XXXX XXXX XXXX XXX X XXXX X'IXX
~~,[)DR EBB'S EI~ROI~S :::::::::::::: > ),~XXX XXXX XXXX XXX X XXX X XXXX XXX'1 XXXX
ADDI~ ES~~ r s Et~I~OI~S ::::::::::::::: > XXXX XXXX XXXX XXXX XXXX XXXX XXX'1 X"IXX
f,DDRESS" S ERr~O'~S :::::::::::::: } XXXX XXXX XXXX XXXX XXXX XXX X XXX··, XXXX
f'D[)I~ E~3B ' S EI?I~ ()I~ ~3 :::::::::::: ) XXXX XXXX XXXX XXXX XXXX XXXX XXX"1 'IXXX
r.,DDRESS" s ERRORS :::::::::::::: > XXXX XXXX XXXX XXXX XXXX XXXX XXX-1 '1'1 XX

Crash occurs because an address line is down

 Programming Exercises 179

Press any key to stop program

BEGINNING (-l[)DRE~)S ) 7EJO()
END I NG (~DDJ~ ESG ~ _;. 7 FFF

END o F T EST

oo YOU lo..l~lNl CON'- I NtlE' THE TEST '",\ (YIN) ')'

END o F

f~,[)D~~ ESS 7 ~~ F~~R oas ::::::::::::::: > XXXX XXXX XXXX XXX X XXXX XXXX XXX1 XXXX
AJ)D'~ ESB T s EI~'?OI~ S ::::::::::::: > XXXX XXXX XXXX XXXX XXXX XXXX XXiX XXXX
~~i{)[)R E Ss r S ERRORS :::::::::::::;> XXXX XXXX XXXX XXXX XXXX XXXX XX11 XXXX
(.'DDJ~ESB' S EI~J~OR S :::::::::-.::::::) XXXX XXXX XXXX XXXX XXXX XXXX XiXX XXXX
(.iDDI~ESS' E I~ I~ or~~ S ::::::: :::::: >
S XXXX XXXX XXXX XXXX XXXX XXX X X1X1 XXXX
ADJ)I~EBS T S :::::::::::::::)
EI~f~OI?S XXXX XXXX XXXX XXXX XXXX XXXX X'I"I X XXXX
(.~'DDRESS' E; ERRORS :::::::::::::::) XXXX XXXX XXXX XXXX XXXX XXXX X111 XXXX
ADDf~ESB' S E I~ I~ () I~ S :::: ::::::: :::: ) XXX X XXXX XXXX XXXX XXX X XXXX iXXX XXXX
~~,[)[)R E~;S' S ERRORS :::::::::::::::~) XXX)( XXXX XX
SPUJ~ IOU!, INTEI~f?UP T !!!

SPUf.~ IOUS INTEI~RlJPT!!!

So long~the ~line connected to the
SP U l~ r 0 US I N TE I~ I~ IJP T !!! inputs IPLO to IPL2 via a 74LS148 circuit
is low, the 68000 loops in the spurious
~)PUI~ lOUS INTEr·~RUPT!!! interrupt procedure.

SPUJ~ IOUS INTEI?J':UPT!!!

SPUR JOUS l:NlE:r~RUP T !!!

npl..H~ 10U~3 INTERI?UP T !!!

Several address lines are down
The VPA input of the 68000 is disconnected from the decoding logic of the
ACIA 6850 circuit.
Two consequences are: address errors
pressing a key causes an interrupt (IRQ ACTA 6850)
leading to a spurious interrupt. In fact, recognition of the absence of the
VPA signal on (autovectored) interrupt causes the 68000 to branch to the
exception table at address $60 (24 x 4 = 9610 = $60).
180 The 68000 Hardware and Software

Press any key to stop program

BEGINNING f.\DDRESS .......... > 7BOO
ENDING t~DDf~ ES~, ............ > 7::::0Ll

F N D <) F T F S T '1

[:11:) YOU ~'Jf.\NT CONTINUE THE TEST ..., (YIN) Y

IT'S Il-iPO~:>BIBLE TO Ct~t~f~Y ' ....,,,. IN D 7 IN :::::::::::: > 0OOO7BO"1
IT'S IMPOSSIBLE TO Cfo\RRY 1"1 u IN D 6 IN :::::::::::: > OO()07 BO'1
IT'S IMPOSSIBI.E TO Ct~I?I~Y ""'1 IN D r.·.s IN :::::::::::::: > n 0OOO7BO"1
IT'S Ii"'POSSIBl..E TO Cf~ll~ IX~ Y ." '1 ." IN D It IN ::::::::::::: > ()0 ()0 7 B() '1
IT'S '(MPOB~3IBLE TO Ct~I~I~,( "'1 ". IN D ~3 IN :-.:::::::::: > I] D oo7BO"1
IT' ~~ IMPOSSIBLE TO CAR~?Y ""1'" IN [) ~! IN ::::::::::::: > oo()()7 ~~ () '1
.c r ~3 IMPOS~;IBLE TO CAI?I?Y
T IN D "1 IN ::..-:::::::::::;.
1.' •• , '..
OOOO?BO'I
IT'S IMPOSSIBLE TO C~~RI~ y "'1'" IN D 0 IN ::::::::::::: > ()0 ()0 7 H() '1
IT'S Il'1POSBIBLE TO Y ""'1'" IN D 7
Ct~l~ I,~ IN ::::::::::::: > O()()O?BO:3
IT 7 S IMPO~)f:)IBI...E TO ""1'" IN [) c>
cro\r~I~Y IN ::::::'.':::: ) o() 0 ()7 EJ 0 ~~
IT' ~3 Il'iPOBS IBI...E TO CI~t~I~Y ""'1" IN D ~) IN ::::::::::: ) DO()() 7BO::3
IT:' ~; Tr'1PO~)~:;1 BLE TO Cfo\f.~RY ""1 " IN D It IN ::::::::::::::: > ()o0 ()7 B o:~
IT'S t MP0~'~3.r BLE TO Ct~l~l~Y '····1'"' IN D :3 .eN :::::::::::: ) DO()()7BO::3
Ill'S IMPOSSIBl.E TO CARRY "'1" IN [) ~? IN ::::::::::::: ) O()OO7B03
r T'~;:) Il-iPOGB II3LE TO CAI~t~Y ""1" IN D "1 IN ::::::::::: ) O()()07BO::3
IT'S It--'POSSIBI...E TO c~~r~ f~ ''1' ""1 IN D 0 u IN ::::::::::::: > OOO()7B03

E N D o F T E B T ;;!

IT'S J~iP ossn BI...E TO ~JR I TE '1'1 'I

IN =::::::::::::: } O()()07BOO
i=\DDI~ E~:)::3 EI~I?OI?S ::::::::::::::: ) XXXX xxxx XXXX XXXX XXXX XXXX XXX>:: X'IX)(
IT'S IMF'OSSIBL.E TO ~'JH IrE u "1'" IN ::::::::::::: > O()()()7BO/'l
F N D 0 F T E ("'
,:> T ;'3

Il'S IMPOSSIBLE TO CARRY ." () .., IN o 7 IN ::::::::::::: > o()()o7 B()'1

Il'iP OS~3 II3LE TO CAI~I~ '(
IT)' :3 "1]'" IN D I'~ IN :::::::-.:::: > o()()() 7BO "1
IT"S IMPO~)SlBLE TO Y " 0'"
Cf.il;~I'~ IN n ~:; IN ::::::::::::: > ()()()() 7 B()'1
IT' ~3 IMPOSSIBLE TO C(."~'~Y "0'" IN D it IN :::::::::::::: ) ()()()()7BO"1
IT"S I t1P O~:: SIB l..E TO C('\I~~ RY "'0" IN [) :~}
.....
IN ::::::::::::: > oono 7 BO'1
IT" ~, IMPOSBIBl.E TO CA'~I?,( "'0'" TN D e; IN ::::::::::::: > O()()07BO'1
IT" ~) I MF'0 s B 1 BLE TO C('\I~F~Y
..•• () u
IN [) '1 IN ::::::::::::: > ()o Cl () 7 B0 '1
IT" s I MP O~3~3:C 13 LE TO Ct~t~l~ y "'0" IN D I] IN ::::::::::::::: > DO()O/80'"
IT"S IMPOSSIBLE TO C(il~~ F~ Y "'0" IN [) -rl IN ::::::::::::: > O()(J07BO:·}
IT'S r MPoss I 131...E TO CI~t~l~Y "() '." IN D 6 IN :::::::::::::: ) O()()07BO:]
IT' s IMPOSSIBLE TO CARRY "'OU IN D s IN ::::::::::::: > 0OOO7BC):·}
IT'S I~1POBSIBI...E TO Ct"?I~ y "I]N IN D I.t IN ::::::::::::: > OO()07BO::3
I'r' ~) IMPOSSIBLE TO CAI~~R y "() " IN [) :-} IN ::::::::::::::: ) O()OO7H()~j
I T r ~3 IMPOS~3 JBLE ro C(.~l~RY
". () ,.'
IN D :':~ IN ::::::::::::: > DO()() 7BD:3
. , 0 .., :::::::::::::: >
IT' ~~ I MI-" O~)~~ 3. BI..E TO Cf.\I~ry~Y IN D '1 IN ()O(}()7BO:~
IT 7G Il-1POSSIBI...E TO 1.~i~l~ I~ Y "() " IN D I.) IN :::::::::::::: ) ()n 0 ()7 BO::3
E N D 0 F T E S T 'i
 Programming Exercises 181

MEMOf~ Y T EST S : (C) '1 9 B 't UY MI Cf~ 0 P F<~ OCE: SS '1 INC

Press any key to stop program

BEGINNING AD[)I~ESS ........... ) 7 BO't
ENDING ADDR[·:SB ......... _. ) 7 a(}E~

F N D 0 F T E B r .',
DO YOU ~IANT CONTINUE THE TEST ...,\ (YIN) y
IT'S IMPOSSIBL.E TO CA'~'~Y ""1" IN D·'I ~) IN ::::::::::::: > O()O()7BO it
IT'S Ifv1POSSIBl..E TO CAr~RY u'1 N
IN [)·1't IN ::::::::::::: > O()()07BO't
IT'S IMPOBSII3LE ro CAR'~Y "'1'" IN D·'I ~3 IN ::.:::::::::::: > ()()()0 7BO it
IT'S . , ..! u
IMPOSSIOl..E TO CARRY IN [)'1 ;.~ IN :::::::::::::: > OO()()7HO.lt
IT'S IMPOSBIBLE TO CAJ~J~ '( "·'1" IN 1)'-1'1 IN :::::::::::: > ()()()() 7BO/.t
IT'S IMPOS~)IBl..E TO CARRY ""1" IN [) 9 IN :::::::::::-.:: > O()()07BO't
IT' s IMP OBS I B1... (-: TO CAI~'~Y "'1" IN D B IN ::::::::::::: > OO()()/BOlt
IT'S J MP 0 S E> I BLE TO Cf~r~RY U·1 ~,
IN [)'1 ~:; IN :::::::::::::: > 00007 EJOtJ
IT' s IMPOB~3.r131._E TO CAR'~,( ""1" IN 1)·'1 it IN ::::::::::::: > ()OO()7BO(~
IT'S IMPOSSIBLE TO C(.,RRY . , ..!." IN [)'13 IN ::::::::::::: > ()o ()() 7 H()tJ
:r T '~) Il~POBB'[BLE ro C(~I~I~ y ""1'" IN D·I:..~ IN ::::::::::::: > O()()()700,,S
IT' ~; IMPOSSIBLE TO C(~I~ R'( ""'!" IN n·1··! IN :::::::::::::: > O()()()7B()t~
IT' ~, IMPOSSIBLE TO C(.\I~I~ y ".1 n IN D 9 IN :::::::::::::: ) ()OOO7BO"S
IT' s IMP O~)SIBl..E TO CAI\:RY ""1" IN D El IN :~ :::: :::: ::: > O()()()7B06
IT'B IMPOSSIBLE TO Ct~I~I~Y "'1" IN 1)"1 ~) IN ::::::::::::: > DOD()7~30B
IT'S IMPOSSIBLE TO C~~RRY' ""'!" IN D"!', IN ::::::::-.:::-.:: ) 0000/" BOB
:er's I t'1P OSB I Bl_E TO CAI?I~Y 1."'11.' IN 1)'13 IN :.:::::::::::: ) OOD07BOB
ITI'S I~1POSSIBI...E TO C{il~ I~ Y "'1'" IN D"! ~! IN :::::::::::::: ) ()OOO?BOa
IT' ~3 Il--1POSSIBI...E TO CA1~I?Y n "1 " IN D"" IN :::::::::::::: ) ()()()()7BOB
IT' s IMf'OSS lFJl.,E TO CAI~~RY " ..! ,~
IN o 9 IN ::::::::::::::: > OOOOi'~JOB
t T l' ~3 IMP O~; SIB I... E TO Ct~I~I~ y ""1" IN D B IN ::::::::::::: > {)()()()7nOB

F.:: N D 0 F T E ~) T ~~

IT'S IMPOSSIBLE TO l·JI~ ITE "'1 u IN :;::::: :::: :.~ > onOO7BOLt
('~DDI~E~3G'~, EI~I?OI~B :::::::::::: ) XXXX xxxx xxxx xxxx xxxx XXXX )(XXX '1"IX)(
IT' s IMPO~)~)18LE TO ~JR 1 TE . , ..! . , IN :;::::::::::: > OO(J07BOB

E N I) o F T E ("'
,) T ::3

IT I'~) IMPO~)SIBI...E TO C~~R I~ 'y' "'0'" IN [)'1 ~:; IN :::::::::::::: ) DO()O7 E~O,(1
IT'S IMPO~3SlI3I...E TO CAI~I?Y NO"" IN D'" it IN :.:::::::::::: > ()()I]07BO,(t
ITI' s IMPOSSlI3LF.:" TO C(;lr·~ R'y
.., () ..,
IN [)"13 IN ::::::::::::::: > 0OOO7EJ04
IT' ~3 IMPOB~3 IBLE TO CAI~'~Y "0" IN D"I ~~ IN ::::::::::::::: > ()()00 7BO /of
IT'S IMPOSSII3I...E TO CAI~~ R\( "I]" IN ()'10 IN :::::::::::::: > O()()()7BO't
IT' ~3 IMPOBSIBLE TO CAI~I~ Y ",0···· IN D ,,'j IN :::::::::::::: > ()()OO7BOlt
JT '1~) IMPO~)SIBLE TO CARRY "'0" IN [) B IN ::::::::::::: ) OOCl();' BO',
.r T'~, IMPOS~3 II3LE TO CAI~I~ Y UO" IN D·1!.:i IN ::::::::::::: > ODOO7BO(S
IT'S IMPO~;SlBL.,E TO CAr~RY "0" IN [v! '; IN :::::::::::::: > O()()()7B06
IT' ~, IMPOS~3 IBLE TO CAJ~I~ y "'010" IN D"I ::3 IN ::::.:::::::: > OO()()7B06
IT'S IMPOSSIBL.E TO CARF~Y ." ()" IN D'1 ;~ IN ::::::::::::::: > ()()()O i' EJCU)
IT' s IMP 0 S ~5 I: Bl. E TO C(~I~I~Y "() " IN D"I () IN :::::::::::::: > O()()()7B06
IT'S IMPOSSIBLE TO c~~r~R '( " 0" IN D ~) IN :::::::::::::: > O()()07B06
IT' s (t"1POBBIBLE TO C(."~ t~ Y IN D B
" ( ) I.'
IN ::::::::::::::: ) 00 D() 7BO{j
IT' ~~ IMPOSSIBLE TO CAr~RY .'10" IN L)'1 ~:; IN ::::::::::::::: > oooo 7 EJOB
IT'S I t"1P OS~3 I BI... E TO CAJ~I~Y '.'() N IN 1)'1 it IN ::::::::::::;:: ) ()()()07BOB
J'f' s IMPO~;S IBLE TO C('\RI~Y
.... () ..••
IN ()'1 ~~ IN :::::::::::::: ) ()()OO7HOEJ
() ,..
IT'S IMPOS~3 IBLE TO CAI?I?Y
".
IN D'L~~ IN :::::::::::::: > OO()07BOB
IT'S IMPO~)S IBl E TO CAF~I~Y "O·'~ IN [)'1 () IN :::::::::::::: > ()(JOO/BOB
182 The 68000 Hardware and Software

MEMOF~Y TESTS: (C) '19~l'i BY ~ilCr~OPROCESS '1 INC

Press any key to stop program

UEGINNIN(~ (-\[)[)RES~) •. _.....•• > 7FF(-\
ENDING ADD1~ES~3 _- > ~~()OO

BU~) Et~l~ Ol~ Ot~ ADDt~ESf, EI~ I~OI~ OO()O(3DOO

IT 7~) IMP 0 SS I BLET 0 C ~~R RY ," '1 ." IN [)'1'1 IN :::::::::::: > O()(107FFE
BUS ERROR OR ADDRESS ERROR 000080()()
BUS E]~I~OR OR A[)[)f~ESS ERROR OO()OBO()()
BUS EI~t~ Ol~ Ol~ f~DDt?EBS EI~I~OI~ OODOBOOO
BUS ERROR 01:< A[)Df~E~)S EI~'I<OR O()()OB()()()
PI~ESS ON I~E!.JEr ro (~UIT

A data line is down

There is no more RAM available from address 'SOOO (no DTACK, therefore
bus error)
 Appendix I Memory Reference Instructions

Mnemonic Function OPeration Size Assembler notation Details

MOVE Transfer source Src,dst B/W/LW MOVE.Size Src,dst Insufficient memory to
to destination memory instructions, but
the memory to register,
register to memory and
operand to memory modes
are sufficient for most
applications.

ADD Add destination operand Src,dst B/W/Uv ADD. Size Src,dst Impossible to ADD memory
to source operand. to memory.
Result in destination

SUB Subtract destination Src,dst B/W/LW SUB.Size Src,dst Impossible to SUB memory
operand to memory.
from source operand.
Result in destination

eMP Compare destination with Src,dst B/W/LW CMP.Size Src,dst Impossible to CaMP memory
source to memory; dst is a Dn
register.
AND AND destination operand Src,dst B/W/LW AND.Size Src,dst Impossible to AND memory
(X) to source operand. to memory. Src and dst
w Result in destination cannot be an An register.
Src can be immediate.

OR Inclusive OR destination Src,dst B/\v/LW OR. Size Src,dst Impossible to OR memory

operand to source to memory. Src and dst
operand. Result in cannot be an An register.
destination Src can be i~nediate.

EaR Exclusive OR destination Src,dst B/W/LW EOR.Size Src,dst Impossible to EaR memory
operand to source to memory. Src and dst
operand. Result in cannot be an An register.
destination Src can be immediat2.

CLR Clear destination dst B/W/LW CLR.Size dst Destin~tion cannot be an

operand An register.

NEG Two's complement of dst B/W/LW NEG.Size dst Destination cannot be an

destination operand An register.

NEGX ~~o's complement with dst B/\'l/LW NEGX.Size dst Destination cannot be an
extend bit of the An register.
destination operand
NOT One's complement of dst B/W/LW NOT. Size dst Destination cannot be an
destination operand An register.

TST Compare operand with dst B/W/LW TS'LSize dst Dtstination cannot be an
zero. CCR is set An register.
 Appendix Special Memory Reference Instructions

Mnemonic Function Operation Size Assembler notation Details

LEA Load effective Src,An UoJ LEA Src,An Whole register is affected
address by the instruction. CCR
is not modified

PEA Save effective Src LW PEA Src Src-) (SP)

address to stack

MOVEP Transfer from Dn,dst W/LW MOVEP.L Dn,d (dst) After transfer the data
register On alternate or MOVEP occupies alternate bytes
even or odd addresses in memory. Special 8-bit
to memory block peripherals

MOVEP Load On with data Src,Dn W/LW MOVEP.L d(Src),On Load data from alternate
from memory block or MOVEP memory byte. Special 8-
of even or odd bit peripherals
addresses

MOVEM Transfer multiple regs,dst W/LW MOVEM.L regs,dst List of registers can be
registers or MOVEM written: 00-D5 means that
registers DO to D5 are
transferred; DO/D5 that
registers DO and D5 are
.... transferred
(X)
~ MOVEM Load multiple Src,regs W/LW MOVEM.L src,regs If effective address (Src)
registers or MOVEM is postincrement, only
memory to register
transfer is allowed

AODX Add destination operand Src,dst B/h'/LW ADDX.Size Dn,Onl Src and dst use data
with extend bit X to or ADDX.Size -(An), register or predecrement
source operand. Result -(AnI) address modes
in destination

SUBX Subtract destination Src,dst B/W/LW SUBX.Size Dn,Onl Src and dst use data
operand with extend bit or SUBX.Size -(An), register or predecrement
X from source operand. -(AnI) address modes
Result in destination

ABCD Decimal addition Src,dst B ABCD Dn,Dnl Src and dst use data
with carry (bit X) or ABCD -(An) - (AnI) register or predccrement
address modes

SBCD Decimal subtraction Src,dst B SBCD Dn,Dnl Src and dst use data
with carry (bit X) or SBCD -(An) - (AnI) register or predecrement
address modes
 Appendix 2 Special Memory Reference Instructions (continued)

Mnemonic Function Operation Size Assembler notation Details

NBCD Destination operand dst B NBCD dst This i~struction carries

and extension bit out the 10's complement
subtracted from zero if X = 0 or 9 's if X = 1

MULS Multiply two signed Src,Dn W MULS Src,Dn Destination is always

16-bit operands to a Dn register. Src
give 32-bit result cannot be an address
register

MULU Multiply two unsigned Src,Dn W MULU Src,Dn Destination is always

16-bit operands to a Dn register. Src
give 32-bit result cannot be an address
register
DrvS* Divide signed 32-bit Src,Dn W Drvs Src,Dn Destination is always
by l6-bit operand to a Dn register. Src
give 32-bit result. cannot be an address
Quotient is LSB word; register
remainder is MSB of
........ result
Q)
0'1 DIVU* Divide unsigned 32-bit Src,Dn W Drvu Src,Dn Destination is always
by l6-bit operand to a Dn register. Src
give 32-bit result. cannot be an address
Quotient is LSB word; register
remainder is MSB of
result

BSET* Test bit specified by numb,dst B/LW BSET.Size # numb,dst numb can be contents
destination operand. or of a Dn register or
After test, bit is set BSET.Size Dn,dst an operand (# numb)
to 1

BCLR* Test bit specified by numb,dst B/LW BCLR.Size # numb,dst numb can be contents
destination operand. or of a Dn register or
After test, bit is BCLR.Size Dn,dst an operand (# numb)
set to 0

BCIIG* Test bit specified by numb,dst B/U-J BCHG.Size # numb,dst numb can be contents
operand, change its or of a Dn register or
value and write BCHG.Size Dn,dst an operand (# numb)
comolemented value in
bit"Z of CCR

BTST* Test bit specified by numb,dst B/U'J BTST.Size # numb,dst numb can be contents
destination operand. or of a Dn register or
After test, bit is BTST.Size Dn,dst an operand (# numb)
unmodified
 Appendix 2 Special Memory Reference Instructions (continued)

Mnemonic Function Operation Size Assembler notation Details

CMPM Memory comparison by Src,dst B/W/LW CMPM.Size (An)+,(An)+ Src and dst use
virtual subtraction exclusively post-
of source from increment address
destination mode

CHK* Test contents of Src,Dn hi CHK Src,Dn If content of register

a register <0 or greater than upper
bound, processor executes
trap CHK

TAS* Test and set an dst B TAS.B dst Tests byte operand
operand designated by dst.
If dst = 0, MSB bit
of dst is set to 1
(indivisible instruction)

SWAP Exchanges the high On L SWAP Dn

order bits (16-31 )
with the low order bits
(0-15) of a Dn register
Q)
"
0)
EXT Extends sign bit Dn W/LW EXT Dn If size is word,bit
7 is copied to bits
8 to 15. If size is
long word, bit 15 is
copied to bits 16
to 31

EXG Exchanges contents Xn,Xm LW EXG Xn, Xm Exchange between:

of two registers (for On or An data registers
register) address registers
data register/address
register

*See detailed study

 Appendix 3 Shift and Rotate Instructions *See detailed study

Mnemonic Function Operation Size Assembler notation Details

ASL* Arithmetic Om,Dn B/W/LW ASL.Size Dm,Dn Shift count contained

shift left # cnt,Dn ASL.Size # cnt,Dn in Dm (1 to 6 3 ) . # cnt
dst ASL. \\1 dst indicates total of
shifts (1 to 8). Only
1 bit shift in dst

ASH* Arithmetic Om,Dn B/W/LW ASR.Size Dm,Dn Shift count contained

shift right # cnt,Dn ASR.Size # cnt,Dn in Dm (1 to 63). # cnt
ASR.W dst indicates total of
dst shifts (1 to 8). Only
1 bit shift in dst

[{OL* Hotation Dm,Dn B/\v/LvJ ROL.Size Dm,Dn Rotation number is

to left # cnt,Dn ROL.Size # cnt,Dn contained in Dm (1 to
dst ROL. \\1 dst 63) • # cnt indicates
total of rotations
(1 to 8). Only 1 bit
rotation in dst

ROR* Rotation Om,Dn B/W/LW ROR.Size Dm,Dn Rotation number is

00 to right # cnt,Dn ROR.Size # cnt,Dn contained in Om (1 to
~ dst ROR.W dst 63) . # cnt indicates
total of rotations
(1 to 8). Only 1 bit
rotation in dst

HOXL* Hotate left Dm,Dn B/W/Uv ROXL.Size Dm,Dn Same as HOL with
with extend # cnt,Dn ROXL.Size # cnt,Dn extend bit included
dst ROXL.W dst in rotation

HOXH* Rotate right Om,Dn B/v.)jL\\1 ROXR.Size Dm,Dn Same as ROH with
with extend # cnt,Dn ROXR.Size # cnt,Dn extend bit X included
dst ROXR. \\1 dst in rotation

LSL* Logical shift Om,Dn B/\v/LW lSL.Size Dm,Dn Shift count contained
to left # cnt,Dn LSL.Size # cnt,On in Dm (1 to 63). # cnt
dst LSL. \\1 dst indicates total of
shifts. Only 1 bit
shift in c1st

LS/{* Logical shift Om,Dn B/W/LW LSR.Size Om,Dn Shift count contained in
to right # cnt,Dn LSR.Size # cnt,On OM (1 to 63). # cnt indi-
dst LSR.W dst cates total of shifts.
On 1y 1 bi t 5 h if t 5 in d s t
 Appendix 4 Program Control Instructions

Mnemonic Function Operation Size Assembler notation Details

,JMP Unconditional jUl.1p addr JMP addr

JSf< Jump to subroutine addr JSR addr

HTS Return from subroutine R'fS

RTH Return and restore CCR RTR CCR ::::-egister and

program counter
are .:-ecovered
from stack

LINK* Link to stack An, Link An,# displacement -32768 < displacement
# dis~lacement < 32767 +32767

UNLK* llnlink from stack An UNLK An

BRA Unconditionul branch addr 16 B/vv BRA displacement If size is byte

-128 < displacement < +127
ex> If size is word
ex> -32768 < displacement < +32767

BSH Branch to subroutine addr 16 B/W BSR displacement If size is byte

-128 < displacern0:1t < +127
If size is word
-32768 < displucement < +32767

:3cc Branch if cc condition addr 16 B/W Bcc displacement If cc condition is true

is true PC + displacement -) PC

[mcc* Loop(s) primitive On,addr 16 W OBcc On,displacement If cc is false

On = 1 -) On.

If On<)l, then
PC + displacement -) PC
Else NOP

Scc* Sot byte ~ccording dst B Scc,B dst If cc condition is true

to conch tion 1 "s -) destination
Else 0 's -) destinution

*See detailed study

 Appendix 4 Program Control Instructions (continued)

Mnemonic Function Operation Size Assembler notation Details

MOVE Transfers source Src,CCR \v !'10VE Src, CCR Src uses all address
to CCR register modes except address
register direct

MOVE Transfers SR SR,dst W r·10VE SR,dst dst uses all address

register to modes eA~ept: address
destination register d~~ect, ifi@ediate,
relative, relative to PC

OIL B Inclusive OR between # data,CCR B OR.B # data,CCR

CCR and data specified
by instruction

EOR.B Exclusive OR between It data,CCR B EOR.B # data,CCR

CCR and data specified
by instruction

AND.B Logical AND between # data,CCR B AND.B # data,CCR

..... CCR and data specified
Q)
co by instruction
Src uses all address
MOVE Transfers source to Src,SR W MOVE Src,SR
iI10des except address
SR register
register direct.
Privileged instructiOi.

OR Inclusive OR between # data,SR W OR # data,SR Privileged instruction

SR and data specified
by instruction

I\ND Logical AND between # data,SR \v AND # data,SR Privileged instruction

Sr and data specified
by instruction

EOH Exclusive OR between # data,SR W EOR # data,SR Privileged instruction

SR and data specified
by instruction

r-iOVE Transfers user stack USP,An LW MOVE.L USP,An Privileged instructio~

pointer to An register

~10VE Transfers An register l\n,USP Lv~ r·\OVE. L An, USP Privileqed ~nstr~ction
to user stack pointer
 Appendix 4 Program Control Instructions (continued)

Mnemonic Function Operation Size Assembler notation Details

RTE Return from exception RTE (SP) + -) SR
(SP) + -) PC
Privileged instruction

STOP* Load SR register # data STOP # data # data -) SR, then

with data specified STOP
by instruction. Then Privileged instruction
stop processor

RESET Output RESET line is RESET Privileged instruction

set low for 124 clock
cycles

NOP No operation occurs NOP

..... PC -) -(SSP)
TRAP Sequence branches to TRAP # number
~ vector number shown SR -) -(SSP)
by the instruction (Vector) -) PC

THAPV Sequence branches if TRAPV If V = 1, then

overflow indicator = 1 PC -) -(SSP)
SH - (SSP) ,
(vector TRAPV) -) PC
Else NOP
Appendix 5 PAL Devices

Advantages of Using PALs

Programmable array logic (or logic array) devices have
a unique place in the world of logic design. Not only
do they offer many advantages over conventional logic,
such as TTL, they also provide many features not found
anywhere else.
Special features of the PAL family include

Programmable replacement for conventional TTL

logic.

Help to reduce Ie inventories substantially and

simplify their control.

Reduce chip count by at least 4 to 1.

Simplify and speed up prototyping and board

layout.

Save space with 20-pin and 24-pin DIP packages.

High speed, i5 ns being a typical propagation

delay.

Programmed on standard PROM programmers.

Programmable tristate outputs.

Special feature eliminates the possibility of

copying by competitors.

PA£R.)is a registered trademark of Monolithic Memories Inc.

191
192 The 68000 Hardware and Software

16R4

QUA D " INPUT REGiSTERE D

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(Courtesy of Monol ith ic Memories)

 Appendix 5 PAL Devices 193

18L4

aUAD l' INPUT

AN D-OR · IHVEAT GATE ARRAY

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194 The 68000 Hardware and Software

10L8

OCTAL 10 INPUT
AHO-QR·IHVERT QATE ARRAY

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 Appendix 5 PAL Devices 195

Appllcetlon

Z1log 8500 Interface with the 88000Mlcropl'OCHlOr

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(Courte sy of Monolithic Memor ies)

196 The 68000 Hardware and Software

Interface Controller for 68000 I'P Logic Diagram PAL20X10

to Zilog 8500 Peripherals
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