La K454P
La K454P
La K454P
BOM P/N : PCB 3JJ LA-K454P REV1 MB PCB 3JJ LA-K454P REV1 MB GOLD A31 ! PCB 3JJ LA-K454P REV1 MB TRIPOD A31 ! PCB 3JJ LA-K454P REV1 MB HANNSTARB A31 !
1
PCB 1
ZZZ
DAA000OJ000
PCB@
Rev: 1.0 2
@ : Un-pop Component
EMI@/ESD@/RF@ : EMI, ESD and RF Component 2021.04.21
@EMI@/@ESD@/@EMC@ : EMI, ESD and RF Un-POP Component
PCB@/PCBR1@/PCBR3@ : MB PCB Partnumber
ARK@/SIF@ : ARK or SIF sku
3 3
TYPEC@ : Type-C
GN20P0@/GN20P1@/GN20P0D@ : GPU
Security Classification Compal Secret Data Compal Electronics, Inc.
GC6@ : GC6 function for GPU Issued Date 2020/03/05 Deciphered Date 2021/12/31 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
X76S@/X76M@/X76H@ : VRAM option MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-K454P
Wednesday, April 21, 2021 Sheet 1 of 121
A B C D E
A B C D E
Block Diagram
.P
~6
31
1 1
ap
en
De
eDPx4 1.4b
2~
.P
.P
83
32
4
DP0 0~3 DDR4 Channel A 3200 MT/S_1.2V DDR4-SODIMM x2
DDR4 Channel B 3200 MT/S_1.2V Max Capacity 64GB
IM
DHo
PA C 4
nn
ce
HDMI2.1
o
c
t
r.P
U
04
2N/ W1
PG0 b
Vn
-0P 82
G 08
D
A
I
I
PF
1P 82
RD
DG
MA s .
RV
rP
xa
nn
B
-e
a
m
6
/
GFX x8
1P
/04
H
P
/b
1
PCIE 0~7
cp
OR
rPr
xat
m
5C
19
61
LT
i
RGB
hg
no
i
MB.
F
M2
L
t
3~
3~
W
.P
53
62
P
(
5
)
03
P
LE
.P
3M
26
TB
F2
70
C0
T6
TS
DP2 0~3 USB2.0 Port 6
R
SBU
.P
54
SUo
epo
yT
Cr
nn
ce
I2C
c
VBUS/CC I2C
.P
44
/D
2 2
E
PD Cypress CCG4
oZ
en
L
B1
DEF
B
aM
L61
UC
oT
4
/
M
r
S
x
f
5C
19
LT
J
t
i
(
i
)
I2C
To EC Port 0
USB2 USB2.0
.P
54
.P
37
iw
re
ma
DMIC
M
h
R
C
I
a
t
I
.P
83
iw
DH
re
ma
USB2.0 Port 3 DMIC
M
h
C
a
t
I
1De
82 .P
SS
23
2
.
0 86
CP
ne
I
SU
epG
ro
yT1
USB3.1 Port 1
.P
17
P1
1
B
t
ew
SU
3B
oP
)
hS
ne
)e
ra
USB2.0 Port 1
(
2De
.
(
r
82 .P
SS
JUSB1
M+
2A
2
.A
0 86
Port 2~3
.P
37
SU
eR
e
D
B
i
O
B
-
r
v
r
I
/
USB3.1 Port 4 From LED driver
SU
SP
78
91
epG
oP
yT1
t
B
r
3
SU
3B
)1
ne
.
(
CLK Port3 Port 5 PCI-E USB2.0 Port 4
LW
B+o
NAE
/R
WP
Tt
eK
B
S
SU
eR
y
l
A
e
3 3
D
i
B
-
r
v
r
Port 2 USB2.0 USB3.1 Port 5
.P
25
SU
SP
78
91
epG
oP
yT1
t
B
r
4
SU
3B
)1
ne
.
(
USB2.0 Port 5
CM
/U
B
C M
eK
oZ
en
eP
Port 7 USB2.0
.P
46
K
U
r
y
4
P.73
/O
ID
UA
JR
eR
B
la8
e
no
ro
en
54
t
k
t
PCI-E Port 4
c
SG
TR
21
B5
c
L
CLK Port2
CD
.2
G5
ir
hC
eg
V3
ne
ra
5
aB
/
V
tt
y
DMIC
PC
CV
CV
U
CX
iM
eHo
UA
UA
lG
cV RD
_X
ro MA
CP
hpo
sd
noa
bo
/ek
ae
te
da
la
h
uA
oCk4
id
ed
e
c
bm
oe
c
eR
J
c
la
HDA
t
LA
3C
52
Gd
Gd
UPe
UP
oC
.1
V2
.1
53
OR
r
PS
I
M
BM
23
ap
cu
oT
P.77
PWM I2C
F sn
x x
4 4
2 2
d
CE
PS2
BK
59
24
am
ro
Q
eS
hT
re
.P
46
/D
BK
iS K
l
ta
E
(
I2C KSI/KSO
i
M
)
CN7
17
W8M
7T
r
x
f1B
B
.P
85
35
99
Backlight
F
P.77
LED
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2020/03/05 Deciphered Date 2018/02/05 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K453P
Date: Wednesday, April 21, 2021 Sheet 2 of 121
A B C D E
A B C D E
BAT TBD
PBAT_CHG_SMBCLK
Board ID Table for AD channel PBAT_CHG_SMBDAT +3VALW_EC
CHGR TBD
Vcc 3.3V +/- 1%
Ra 100K +/- 1% BOARD ID Table GPU ID Table
Board ID +TP_VDD Touch Pad TBD
Rb V AD_BID min V AD_BID typ V AD_BID max EC AD3 Board ID GPU ID DAT_TP_SIO_I2C_CLK
0 0 0.000V 0.000V 0.300V 0x00 - 0x13 0 EVT@ 0 GN20E3@ CLK_TP_SIO_I2C_DAT
1 12K +/- 1% 0.347V 0.354V 0.360V 0x14 - 0x1E 1 DVT1@ 1 GN20E4@
2 15K +/- 1% 0.423V 0.430V 0.438V 0x1F - 0x25 2 DVT2@ 2 GN20E5@
UPD1_SMBCLK
3 20K +/- 1% 0.541V 0.550V 0.559V 0x26 - 0x30 3 PVT@ 3 GN20E7@ UPD1_SMBDAT +3V_VSYS CCG5C 0x08
2 4 27K +/- 1% 0.691V 0.702V 0.713V 0x31 - 0x3A 4 4 GN20P0@ 2
Voltage Rails
Power Plane Description S0 S0ix S3 S4/S5 DS3
+19V_VIN
3
+12.6V_BATT+ 3
+19VB
+VCC_CORE
www.teknisi-indonesia.com +VCCGT
+VCCSA
+VCCIO
+3.3V_BAT_LDO
+RTC_CELL
+5VALW
+3VALW
+3VALW_PCH
+3VALW_DSW
+1.8V_PRIM
+1VALW
+1.2V_DDR
+0.6V_DDR_VTT
+2.5V_MEM
+VCCST
+VCCSTG
+5VS
+3VS
4 4
+1.8VS
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K453P
Date: Wednesday, April 21, 2021 Sheet 3 of 121
A B C D E
A B C D E
1V8_AON_EN
EM5209VF GPU
(UG3) P.37 +1V8_AON
(UG1) P.35
EN_1.8V
BLM15PX600SN1D
+1.8V_RUN_AUDIO_IO
5A_Z80_0805 +19VB_1.8V SY8388RHC +1.8VALWP JUMP_43X79 +1.8VALW_GPU (LA2) P.56
ALC3254-VA3-CG
(PL1811)P.90 (PU1801) P.90 (PJ1802)P.90
0_0603_5% (UA2)
P.56
(RA43) P.56
+1.8V_RUN_AUDIO
SUSP#
1 1
FP241AH
(JHDT1) P.8
(PUB1)
2 NCP303150DMNTWG MHDZIR22MEM3-RT APU_AUD_PWR_EN 2
ACES_50521-01041
WLAN_EN (JCCG1) P.44
SY6288C20AAC APCI0147-P007A
+3.3V_WLAN (JWLAN1)
(UW1) P.52 P.52
BLM15PX600SN1D ALC3254-VA3-CG
(LA16) P.56
+3.3V_RUN_AUDIO_DVDD (UA2) P.56
BLM15BD121SN1D
EN_3V (LE1) P.89 +EC_VCCA
0_0603_5% KB9542Q-E
+3VALW (RE6) P.58
+3VALW_EC
(UE1) 0_0402_5% CPU
JUMP_43X118 0_0603_5% P.58 (RC144) P.11 +3VS_APU (UC1F)P.11
+3VALWP (RE526)P.89
+VCC_IO2
ELC_BL_EN
(PJP301/PJP302)
PL311 TPS51225CRUKR P.87
+19VB_3/5V SY6288C20AAC
PL312 +3.3V_ELC STM32F070CBT6TR 0_0603_5%
(PU301) (UEL3)P.62 BLM15AG121SN1D (RV50) +3V_EDP_SW1
PL313 +VDDA (UEL1) P.39 BLM15BD121SN1D
3
+5VALWP JUMP_43X118 (LEL1) P.62 P.62 (LV6) P.39 VDD33_A 3
PS8461EQFN66GTR
P.87 (PJP501/PJP502) TR PJ2301 SDAN_606043-008001 (UV1)
P.87 +3VS_TOUCH BLM18KG331SN1D
(Q27) P.63 (JTP2) P.63 G9661MRE1U
(UV35) P.39 +1.2VS (LV7) (LV8)
EN_5V
PCH_PWR_EN +3VS (LV9) (LV10)P.39 P.39
SY6288C20AAC CPU
+3VALW_APU (UC1F)P.11 PI3DPX1205A1ZLBEX
(UC20)P.62 0_0402_5%
(RT303) P.45 +3VS_MUX (UT9) P.45
3V3_SYS_EN
LOTES_AHDM0008-P002A SDAN_606044-040041
AOZ1334DI-01
+3V3_SYS (JHDMI1) (JIO1) P.73
(UG4) P.37 P.40
SDAN_606044-040041 LOTES_APCI0103
(JIO2) P.73
(JIO1) P.73
LOTES_APCI0103
(JIO2) P.73
SUSP#
SUSP#
EM5209VF
+5VS_OUT JUMP_43X118
(UZ2) P.78 (JP4) P.78
AP2330W-7 CYPD4126-40LQXIT
(UT3) P.44
+5V_CONN_P1
(UT1) P.44
VBUS_P_CTRL_P1
SY6861A1AAC CYPD4126-40LQXIT
+CCG_VBUS P.45 EN_+12V
(UT8) P.45 (JUSBC1) TWVM_WTB1220
(JFAN1)
BLM15PX600SN1D_2P ALC3254-VA3-CG
JUMP_43X39 VIN_+12V RT9297GQW +12VP JUMP_43X39 P.77
+VDDA_AVDD1 (PJ1201) P.111 (PU1201) P.111 (PJ1202) P.111 +12V_FAN
(LA15) P.56 (UA2) P.56 TWVM_WTB1220
4 4
DDTA144VCA-7-F
+WHITE_LED_BAT (JIO1)
(Q23) P.65
P.73
USB_EN
Security Classification Compal Secret Data Compal Electronics, Inc.
SY6288C20AAC Issued Date 2020/08/25 2021/12/31 Title
+5V_USB LOTES_AUSB0182 Deciphered Date
(UU1) P.71
(JUSB1) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Map
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K453P
Date: Wednesday, April 21, 2021 Sheet 4 of 121
A B C D E
5 4 3 2 1
ACIN ACIN
EC_ON 2.182ms EC_ON
+5VALW 2.192ms +5VALW
200ms
ON/OFFBTN# ON/OFFBTN#
88.4ms
3V_EN 8.356s 3V_EN
+3VALW 739.0us 1.825ms +3VALW
88.44ms
0.75_1.8VALW_PWREN 0.75_1.8VALW_PWREN
1.123ms
+1.8VALW 7.066ms +1.8VALW
634.7us
+0.75VALW 900.2us +0.75VALW
101ms
PBTN_OUT# 2.496ms PBTN_OUT#
116.8ms
EC_RSMRST# 8.356s EC_RSMRST#
SLP_S5# 160.0us 1.300ms SLP_S5#
SLP_S3# 159.5us 1.32ms SLP_S3#
SYSON 120.6ms
59.48ms SYSON
+1.2V_VDDQ 530.2us 1.130ms +1.2V_VDDQ
C C
+0.6VS_VTT 585.2us 330.0us +0.6VS_VTT
+2.5V 1.35ms 2.07ms +2.5V
20.57ms
SUSP# 56.76ms 22.4ms 63.78ms SUSP#
356.5us
+5VS 3.199ms 362.4us 2.94ms +5VS
349.2us
+3VS 1.504ms 358.9us 1.485ms +3VS
1.016ms
+1.8VS 5.234ms 1.017ms 5.38ms +1.8VS
KBRST# 24.65ms 56.7ms 26.52ms 63.72ms KBRST#
0.75VS_PWR_EN# 24.28ms 56.76ms 74.2ms 63.8ms 0.75VS_PWR_EN#
218.7us
+0.75VS 741.5us 248.6us 830.2us +0.75VS
21.8ms
VR_ON 83.2ms 21.8ms 91.88ms VR_ON
2.45ms
+APU_CORE 86.18us 2.22ms 70.0us +APU_CORE
2.2ms
+APU_CORE_SOC 182.8us 2.175ms 200.us +APU_CORE_NB
27.45ms
VGATE 2.507ms 2.521ms 33.55ms VGATE
SYS_PWRGD_EC 39.98ms 30.49ms 41.46ms 24.59ms SYS_PWRGD_EC
APU_PWROK 17.87ms 3.64ms 17.96ms 3.64ms APU_PWROK
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
POWER SEQUENCE
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K453P
Date: Wednesday, April 21, 2021 Sheet 5 of 121
5 4 3 2 1
5 4 3 2 1
UC1B @
PCIE
H6 P_GPP_RXP7 P_GPP_TXP7 N2
H7 P_GPP_RXN7 P_GPP_TXN7 N4
teknisi-indonesia.com
APU PN Table
UC1 UC1
S IC RYZEN5 100-000000296 3.3G APU A31 ! S IC RYZEN7 100-000000295 3.2G APU A31!
R5@ R7@
SA0000E3X3L SA0000E1P3L
A A
UC1
S IC RYZEN9 100-000000300 3.3G APU A31! Security Classification Compal Secret Data Compal Electronics, Inc.
R9@ 2019/08/26 2020/08/26 Title
Issued Date Deciphered Date
SA0000E1N3L FP6_(1/7)_PEG/PCIE/SATA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K453P
Date: Wednesday, April 21, 2021 Sheet 6 of 121
5 4 3 2 1
5 4 3 2 1
UC1A @
MEMORY A UC1I @
<23> DDR_A_MA[13..0]
MEMORY B
DDR_A_DQ[63..0] <23> <24> DDR_B_MA[13..0]
DDR_A_MA0 AK26 MA_ADD0/RSVD
DDR_B_DQ[63..0] <24>
DDR_A_MA1 AG24 MA_ADD1/RSVD MA_DATA0/MAA_DATA8 K27 DDR_A_DQ0 DDR_B_MA0 AM29 MB_ADD0/RSVD
DDR_A_MA2 AG23 MA_ADD2/MAB_CA0 MA_DATA1/MAA_DATA9 L26 DDR_A_DQ1 DDR_B_MA1 AH31 MB_ADD1/RSVD MB_DATA0/MBA_DATA8 C27 DDR_B_DQ0
DDR_A_MA3 AG26 MA_ADD3/MAA_CA4 MA_DATA2/MAA_DATA13 N26 DDR_A_DQ2 DDR_B_MA2 AJ30 MB_ADD2/MBB_CA0 MB_DATA1/MBA_DATA9 A28 DDR_B_DQ1
DDR_A_MA4 AG27 MA_ADD4/MAA_CA5 MA_DATA3/MAA_DATA12 N27 DDR_A_DQ3 DDR_B_MA3 AH29 MB_ADD3/MBA_CA4 MB_DATA2/MBA_DATA13 F29 DDR_B_DQ2
DDR_A_MA5 AF21 MA_ADD5/MAA_CA3 MA_DATA4/MAA_DATA11 G27 DDR_A_DQ4 DDR_B_MA4 AG32 MB_ADD4/MBA_CA5 MB_DATA3/MBA_DATA12 F31 DDR_B_DQ3
D D
DDR_A_MA6 AF22 MA_ADD6/MAA_CA2 MA_DATA5/MAA_DATA10 H27 DDR_A_DQ5 DDR_B_MA5 AG30 MB_ADD5/MBA_CA3 MB_DATA4/MBA_DATA11 B27 DDR_B_DQ4
DDR_A_MA7 AF25 MA_ADD7/RSVD MA_DATA6/MAA_DATA15 M27 DDR_A_DQ6 DDR_B_MA6 AG31 MB_ADD6/MBA_CA2 MB_DATA5/MBA_DATA10 D27 DDR_B_DQ5
DDR_A_MA8 AF24 MA_ADD8/RSVD MA_DATA7/MAA_DATA14 N24 DDR_A_DQ7 DDR_B_MA7 AF30 MB_ADD7/RSVD MB_DATA6/MBA_DATA15 E32 DDR_B_DQ6
DDR_A_MA9 AE21 MA_ADD9/RSVD DDR_B_MA8 AG29 MB_ADD8/RSVD MB_DATA7/MBA_DATA14 F30 DDR_B_DQ7
DDR_A_MA10 AL21 MA_ADD10/MAB_CS_L1 MA_DATA8/MAA_DATA0 L23 DDR_A_DQ8 DDR_B_MA9 AF29 MB_ADD9/RSVD
DDR_A_MA11 AF27 MA_ADD11/MAA_CKE1 MA_DATA9/MAA_DATA1 N21 DDR_A_DQ9 DDR_B_MA10 AM30 MB_ADD10/MBB_CS_L1 MB_DATA8/MBA_DATA0 H31 DDR_B_DQ8
DDR_A_MA12 AE23 MA_ADD12/MAA_CKE0 MA_DATA10/MAA_DATA5 T21 DDR_A_DQ10 DDR_B_MA11 AF31 MB_ADD11/MBA_CKE1 MB_DATA9/MBA_DATA1 H30 DDR_B_DQ9
DDR_A_MA13 AM23 MA_ADD13_BANK2/RSVD MA_DATA11/MAA_DATA4 T22 DDR_A_DQ11 DDR_B_MA12 AE32 MB_ADD12/MBA_CKE0 MB_DATA10/MBA_DATA5 K31 DDR_B_DQ10
DDR_A_MA14_WE# AM21 MA_WE_L_ADD14/MAB_CKE1 MA_DATA12/MAA_DATA7 M22 DDR_A_DQ12 DDR_B_MA13 AP30 MB_ADD13_BANK2/RSVD MB_DATA11/MBA_DATA4 L30 DDR_B_DQ11
<23> DDR_A_MA14_WE#
DDR_A_MA15_CAS# AL27 MA_CAS_L_ADD15/RSVD MA_DATA13/MAA_DATA6 L24 DDR_A_DQ13 DDR_B_MA14_WE# AP31 MB_WE_L_ADD14/MBB_CKE1 MB_DATA12/MBA_DATA7 G30 DDR_B_DQ12
<23> DDR_A_MA15_CAS# <24> DDR_B_MA14_WE#
DDR_A_MA16_RAS# AL24 MA_RAS_L_ADD16/MAB_CKE0 MA_DATA14/MAA_DATA2 R21 DDR_A_DQ14 DDR_B_MA15_CAS# AP29 MB_CAS_L_ADD15/RSVD MB_DATA13/MBA_DATA6 H29 DDR_B_DQ13
<23> DDR_A_MA16_RAS# <24> DDR_B_MA15_CAS#
MA_DATA15/MAA_DATA3 R23 DDR_A_DQ15 DDR_B_MA16_RAS# AN29 MB_RAS_L_ADD16/MBB_CKE0 MB_DATA14/MBA_DATA2 K30 DDR_B_DQ14
<24> DDR_B_MA16_RAS#
MB_DATA15/MBA_DATA3 K29 DDR_B_DQ15
DDR_A_BA0 AL22 MA_BANK0/MAB_CS_L0 MA_DATA16/MAA_DATA17 P24 DDR_A_DQ16
<23> DDR_A_BA0
DDR_A_BA1 AK27 MA_BANK1/MAB_CA1 MA_DATA17/MAA_DATA16 R26 DDR_A_DQ17 DDR_B_BA0 AN31 MB_BANK0/MBB_CS_L0 MB_DATA16/MBA_DATA21 N32 DDR_B_DQ16
<23> DDR_A_BA1 <24> DDR_B_BA0
MA_DATA18/MAA_DATA21 T27 DDR_A_DQ18 DDR_B_BA1 AM32 MB_BANK1/MBB_CA1 MB_DATA17/MBA_DATA22 N29 DDR_B_DQ17
<24> DDR_B_BA1
DDR_A_BG0 AE27 MA_BG0/MAA_CS_L1 MA_DATA19/MAA_DATA20 V27 DDR_A_DQ19 MB_DATA18/MBA_DATA20 P30 DDR_B_DQ18
<23> DDR_A_BG0
DDR_A_BG1 AE26 MA_BG1/MAA_CS_L0 MA_DATA20/MAA_DATA19 P25 DDR_A_DQ20 DDR_B_BG0 AD29 MB_BG0/MBA_CS_L1 MB_DATA19/MBA_DATA19 L32 DDR_B_DQ19
<23> DDR_A_BG1 <24> DDR_B_BG0
MA_DATA21/MAA_DATA18 P27 DDR_A_DQ21 DDR_B_BG1 AD31 MB_BG1/MBA_CS_L0 MB_DATA20/MBA_DATA17 L31 DDR_B_DQ20
<24> DDR_B_BG1
DDR_A_ACT# AD22 MA_ACT_L/RSVD MA_DATA22/MAA_DATA23 V23 DDR_A_DQ22 MB_DATA21/MBA_DATA16 M30 DDR_B_DQ21
<23> DDR_A_ACT#
MA_DATA23/MAA_DATA22 T25 DDR_A_DQ23 DDR_B_ACT# AD30 MB_ACT_L/RSVD MB_DATA22/MBA_DATA18 L29 DDR_B_DQ22
<23> DDR_A_DM[7..0] <24> DDR_B_ACT#
DDR_A_DM0 L27 MA_DM0/MAA_DM1 MB_DATA23/MBA_DATA23 N31 DDR_B_DQ23
<24> DDR_B_DM[7..0]
DDR_A_DM1 N23 MA_DM1/MAA_DM0 MA_DATA24/MAA_DATA30 W22 DDR_A_DQ24 DDR_B_DM0 C30 MB_DM0/MBA_DM1
DDR_A_DM2 R27 MA_DM2/MAA_DM2 MA_DATA25/MAA_DATA31 Y23 DDR_A_DQ25 DDR_B_DM1 H32 MB_DM1/MBA_DM0 MB_DATA24/MBA_DATA30 R30 DDR_B_DQ24
DDR_A_DM3 Y24 MA_DM3/MAA_DM3 MA_DATA26/MAA_DATA26 AC24 DDR_A_DQ26 DDR_B_DM2 M29 MB_DM2/MBA_DM2 MB_DATA25/MBA_DATA31 R32 DDR_B_DQ25
DDR_A_DM4 AP27 MA_DM4/MAB_DM2 MA_DATA27/MAA_DATA27 AC23 DDR_A_DQ27 DDR_B_DM3 T29 MB_DM3/MBA_DM3 MB_DATA26/MBA_DATA26 V30 DDR_B_DQ26
DDR_A_DM5 AW23 MA_DM5/MAB_DM3 MA_DATA28/MAA_DATA28 V21 DDR_A_DQ28 DDR_B_DM4 AU30 MB_DM4/MBB_DM2 MB_DATA27/MBA_DATA27 V32 DDR_B_DQ27
DDR_A_DM6 AT21 MA_DM6/MAB_DM1 MA_DATA29/MAA_DATA29 W21 DDR_A_DQ29 DDR_B_DM5 BD28 MB_DM5/MBB_DM3 MB_DATA28/MBA_DATA28 P29 DDR_B_DQ28
DDR_A_DM7 AV18 MA_DM7/MAB_DM0 MA_DATA30/MAA_DATA24 AA24 DDR_A_DQ30 DDR_B_DM6 BB23 MB_DM6/MBB_DM1 MB_DATA29/MBA_DATA29 P31 DDR_B_DQ29
W24 RSVD_52 MA_DATA31/MAA_DATA25 AA22 DDR_A_DQ31 DDR_B_DM7 BD20 MB_DM7/MBB_DM0 MB_DATA30/MBA_DATA25 U31 DDR_B_DQ30
W31 RSVD_57 MB_DATA31/MBA_DATA24 U29 DDR_B_DQ31
C DDR_A_DQS0 M25 MA_DQS_H0/MAA_DQS_H1 MA_DATA32/MAB_DATA17 AP26 DDR_A_DQ32 C
<23> DDR_A_DQS0
DDR_A_DQS0# M24 MA_DQS_L0/MAA_DQS_L1 MA_DATA33/MAB_DATA16 AN24 DDR_A_DQ33 DDR_B_DQS0 E29 MB_DQS_H0/MBA_DQS_H1 MB_DATA32/MBB_DATA16 AT29 DDR_B_DQ32
<23> DDR_A_DQS0# <24> DDR_B_DQS0
DDR_A_DQS1 P22 MA_DQS_H1/MAA_DQS_H0 MA_DATA34/MAB_DATA21 AR25 DDR_A_DQ34 DDR_B_DQS0# D28 MB_DQS_L0/MBA_DQS_L1 MB_DATA33/MBB_DATA17 AU32 DDR_B_DQ33
<23> DDR_A_DQS1 <24> DDR_B_DQS0#
DDR_A_DQS1# P21 MA_DQS_L1/MAA_DQS_L0 MA_DATA35/MAB_DATA20 AU26 DDR_A_DQ35 DDR_B_DQS1 J31 MB_DQS_H1/MBA_DQS_H0 MB_DATA34/MBB_DATA21 AW31 DDR_B_DQ34
<23> DDR_A_DQS1# <24> DDR_B_DQS1
DDR_A_DQS2 T24 MA_DQS_H2/MAA_DQS_H2 MA_DATA36/MAB_DATA19 AN25 DDR_A_DQ36 DDR_B_DQS1# J29 MB_DQS_L1/MBA_DQS_L0 MB_DATA35/MBB_DATA20 AW30 DDR_B_DQ35
<23> DDR_A_DQS2 <24> DDR_B_DQS1#
DDR_A_DQS2# R24 MA_DQS_L2/MAA_DQS_L2 MA_DATA37/MAB_DATA18 AN27 DDR_A_DQ37 DDR_B_DQS2 N30 MB_DQS_H2/MBA_DQS_H2 MB_DATA36/MBB_DATA19 AR30 DDR_B_DQ36
<23> DDR_A_DQS2# <24> DDR_B_DQS2
DDR_A_DQS3 AA21 MA_DQS_H3/MAA_DQS_H3 MA_DATA38/MAB_DATA23 AR27 DDR_A_DQ38 DDR_B_DQS2# M31 MB_DQS_L2/MBA_DQS_L2 MB_DATA37/MBB_DATA18 AT31 DDR_B_DQ37
<23> DDR_A_DQS3 <24> DDR_B_DQS2#
DDR_A_DQS3# Y21 MA_DQS_L3/MAA_DQS_L3 MA_DATA39/MAB_DATA22 AU27 DDR_A_DQ39 DDR_B_DQS3 T30 MB_DQS_H3/MBA_DQS_H3 MB_DATA38/MBB_DATA23 AV30 DDR_B_DQ38
<23> DDR_A_DQS3# <24> DDR_B_DQS3
DDR_A_DQS4 AP23 MA_DQS_H4/MAB_DQS_H2 DDR_B_DQS3# T31 MB_DQS_L3/MBA_DQS_L3 MB_DATA39/MBB_DATA22 AW29 DDR_B_DQ39
<23> DDR_A_DQS4 <24> DDR_B_DQS3#
DDR_A_DQS4# AP24 MA_DQS_L4/MAB_DQS_L2 MA_DATA40/MAB_DATA30 AV25 DDR_A_DQ40 DDR_B_DQS4 AU29 MB_DQS_H4/MBB_DQS_H2
<23> DDR_A_DQS4# <24> DDR_B_DQS4
DDR_A_DQS5 AW22 MA_DQS_H5/MAB_DQS_H3 MA_DATA41/MAB_DATA31 AW25 DDR_A_DQ41 DDR_B_DQS4# AU31 MB_DQS_L4/MBB_DQS_L2 MB_DATA40/MBB_DATA29 AY29 DDR_B_DQ40
<23> DDR_A_DQS5 <24> DDR_B_DQS4#
DDR_A_DQS5# AV22 MA_DQS_L5/MAB_DQS_L3 MA_DATA42/MAB_DATA26 AV20 DDR_A_DQ42 DDR_B_DQS5 BA27 MB_DQS_H5/MBB_DQS_H3 MB_DATA41/MBB_DATA28 AY32 DDR_B_DQ41
<23> DDR_A_DQS5# <24> DDR_B_DQS5
DDR_A_DQS6 AT20 MA_DQS_H6/MAB_DQS_H1 MA_DATA43/MAB_DATA27 AW20 DDR_A_DQ43 DDR_B_DQS5# BB27 MB_DQS_L5/MBB_DQS_L3 MB_DATA42/MBB_DATA24 BC27 DDR_B_DQ42
<23> DDR_A_DQS6 <24> DDR_B_DQS5#
DDR_A_DQS6# AR20 MA_DQS_L6/MAB_DQS_L1 MA_DATA44/MAB_DATA28 AV27 DDR_A_DQ44 DDR_B_DQS6 BC23 MB_DQS_H6/MBB_DQS_H1 MB_DATA43/MBB_DATA25 BB26 DDR_B_DQ43
<23> DDR_A_DQS6# <24> DDR_B_DQS6
DDR_A_DQS7 AR18 MA_DQS_H7/MAB_DQS_H0 MA_DATA45/MAB_DATA29 AW26 DDR_A_DQ45 DDR_B_DQS6# BA23 MB_DQS_L6/MBB_DQS_L1 MB_DATA44/MBB_DATA27 BC25 DDR_B_DQ44
<23> DDR_A_DQS7 <24> DDR_B_DQS6#
DDR_A_DQS7# AT18 MA_DQS_L7/MAB_DQS_L0 MA_DATA46/MAB_DATA24 AU21 DDR_A_DQ46 DDR_B_DQS7 BC20 MB_DQS_H7/MBB_DQS_H0 MB_DATA45/MBB_DATA26 BA25 DDR_B_DQ45
<23> DDR_A_DQS7# <24> DDR_B_DQS7
Y26 RSVD_58 MA_DATA47/MAB_DATA25 AW21 DDR_A_DQ47 DDR_B_DQS7# BA20 MB_DQS_L7/MBB_DQS_L0 MB_DATA46/MBB_DATA30 BB30 DDR_B_DQ46
<24> DDR_B_DQS7#
Y27 RSVD_59 Y32 RSVD_61 MB_DATA47/MBB_DATA31 BA28 DDR_B_DQ47
MA_DATA48/MAB_DATA11 AT22 DDR_A_DQ48 Y30 RSVD_60
DDR_A_CLK0 AJ25 MA_CLK_H0/MAA_CKT MA_DATA49/MAB_DATA10 AP21 DDR_A_DQ49 MB_DATA48/MBB_DATA11 BA24 DDR_B_DQ48
<23> DDR_A_CLK0
DDR_A_CLK0# AJ24 MA_CLK_L0/MAA_CKC MA_DATA50/MAB_DATA14 AN19 DDR_A_DQ50 DDR_B_CLK0 AJ31 MB_CLK_H0/MBA_CKT MB_DATA49/MBB_DATA10 BC24 DDR_B_DQ49
<23> DDR_A_CLK0# <24> DDR_B_CLK0
DDR_A_CLK1 AJ22 MA_CLK_H1/MAB_CKT MA_DATA51/MAB_DATA15 AN18 DDR_A_DQ51 DDR_B_CLK0# AK30 MB_CLK_L0/MBA_CKC MB_DATA50/MBB_DATA14 BC22 DDR_B_DQ50
<23> DDR_A_CLK1 <24> DDR_B_CLK0#
DDR_A_CLK1# AJ21 MA_CLK_L1/MAB_CKC MA_DATA52/MAB_DATA12 AU23 DDR_A_DQ52 DDR_B_CLK1 AK32 MB_CLK_H1/MBB_CKT MB_DATA51/MBB_DATA15 BA22 DDR_B_DQ51
<23> DDR_A_CLK1# <24> DDR_B_CLK1
MA_DATA53/MAB_DATA13 AR22 DDR_A_DQ53 DDR_B_CLK1# AL31 MB_CLK_L1/MBB_CKC MB_DATA52/MBB_DATA12 BB25 DDR_B_DQ52
<24> DDR_B_CLK1#
MA_DATA54/MAB_DATA9 AN20 DDR_A_DQ54 MB_DATA53/MBB_DATA13 BD25 DDR_B_DQ53
MA_DATA55/MAB_DATA8 AP19 DDR_A_DQ55 MB_DATA54/MBB_DATA9 BB22 DDR_B_DQ54
MB_DATA55/MBB_DATA8 BD22 DDR_B_DQ55
MA_DATA56/MAB_DATA6 AT19 DDR_A_DQ56
DDR_A_CS0# AL25 MA_CS_L0/MAB_CA2 MA_DATA57/MAB_DATA7 AW18 DDR_A_DQ57 MB_DATA56/MBB_DATA4 BA21 DDR_B_DQ56
<23> DDR_A_CS0#
DDR_A_CS1# AM26 MA_CS_L1/MAB_CA5 MA_DATA58/MAB_DATA2 AU16 DDR_A_DQ58 DDR_B_CS0# AN30 MB_CS_L0/MBB_CA2 MB_DATA57/MBB_DATA5 BC21 DDR_B_DQ57
<23> DDR_A_CS1# <24> DDR_B_CS0#
MA_DATA59/MAB_DATA3 AW16 DDR_A_DQ59 DDR_B_CS1# AR31 MB_CS_L1/MBB_CA5 MB_DATA58/MBB_DATA2 BC18 DDR_B_DQ58
<24> DDR_B_CS1#
B MA_DATA60/MAB_DATA4 AW19 DDR_A_DQ60 MB_DATA59/MBB_DATA3 BB18 DDR_B_DQ59 B
MA_DATA61/MAB_DATA5 AU19 DDR_A_DQ61 MB_DATA60/MBB_DATA6 BB20 DDR_B_DQ60
MA_DATA62/MAB_DATA1 AP16 DDR_A_DQ62 MB_DATA61/MBB_DATA7 BB21 DDR_B_DQ61
MA_DATA63/MAB_DATA0 AT16 DDR_A_DQ63 MB_DATA62/MBB_DATA1 BB19 DDR_B_DQ62
DDR_A_CKE0 AD24 MA_CKE0/MAA_CA1 MB_DATA63/MBB_DATA0 BA18 DDR_B_DQ63
<23> DDR_A_CKE0
DDR_A_CKE1 AD25 MA_CKE1/MAA_CA0 RSVD_54 W27 DDR_B_CKE0 AC31 MB_CKE0/MBA_CA1
<23> DDR_A_CKE1 <24> DDR_B_CKE0
RSVD_53 W25 DDR_B_CKE1 AC29 MB_CKE1/MBA_CA0 RSVD_56 W30
<24> DDR_B_CKE1
RSVD_68 AC26 RSVD_55 W29
RSVD_69 AC27 RSVD_65 AA30
DDR_A_ODT0 AM24 MA_ODT0/MAB_CA3 RSVD_49 V26 RSVD_67 AB29
<23> DDR_A_ODT0
DDR_A_ODT1 AM27 MA_ODT1/MAB_CA4 RSVD_48 V24 DDR_B_ODT0 AP32 MB_ODT0/MBB_CA3 RSVD_50 V29
<23> DDR_A_ODT1 <24> DDR_B_ODT0
RSVD_63 AA27 DDR_B_ODT1 AR29 MB_ODT1/MBB_CA4 RSVD_51 V31
<24> DDR_B_ODT1
RSVD_62 AA25 RSVD_64 AA29
RSVD_66 AA31
DDR_A_ALERT# AE24 MA_ALERT_L/TEST31A
<23> DDR_A_ALERT#
MA_PAROUT/RSVD AK24 DDR_A_PAR DDR_B_ALERT# AE30 MB_ALERT_L/TEST31B
DDR_A_PAR <23> <24> DDR_B_ALERT#
DDR_A_EVENT# AK23 MA_EVENT_L MB_PAROUT/RSVD AM31 DDR_B_PAR
<23> DDR_A_EVENT# DDR_B_PAR <24>
DDR_A_RST# AD27 MA_RESET_L M_DDR4 AN21 M_DDR4 1 2 RC6 +1.2V_DDR DDR_B_EVENT# AL30 MB_EVENT_L
<23> DDR_A_RST# <24> DDR_B_EVENT#
FP6 REV 0.92 M_LPDDR4 AN22 M_LPDDR4 0_0402_5% DDR_B_RST# AC32 MB_RESET_L
PART 1 OF 13
<24> DDR_B_RST#
FP6 REV 0.92
1
FP6_BGA1140 PART 9 OF 13
RC7 FP6_BGA1140
0_0402_5%
EVENT# pull high
2
+1.2V_DDR
+1.2V_DDR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FP6_(2/7)_DDR4
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K453P
Date: Wednesday, April 21, 2021 Sheet 7 of 121
5 4 3 2 1
A B C D E
5
UC11
UC1C @ 1
P
NC 4 ENBKL_APU
DISPLAY/SVI2/JTAG/TEST
Y ENBKL_APU <9,58>
CPU_EDP_TX0P D11 DP0_TXP0 1V8_S0 DP_BLON A22 ENBKL_R ENBKL_R 2
<38> CPU_EDP_TX0P A
G
QC1A CPU_EDP_TX0N B11 DP0_TXN0 1V8_S0 DP_DIGON D23 ENVDD_R
G
<38> CPU_EDP_TX0N
2N7002KDW_SOT363-6 1V8_S0 DP_VARY_BL C23 INVTPWM NL17SZ07DFT2G_SC70-5
3
SB00000EO00 CPU_EDP_TX1P C11 DP0_TXP1 SA0000BIO00
<38> CPU_EDP_TX1P
CPU_EDP_TX1N A11 DP0_TXN1 DP0_AUXP D12 CPU_EDP_AUXP
1 <38> CPU_EDP_TX1N CPU_EDP_AUXP <38> 1
EC_SMB_CK2 6 1 APU_SIC EDP DP0_AUXN B12 CPU_EDP_AUXN
S
<29,58,64,68,77> EC_SMB_CK2 CPU_EDP_AUXN <38>
CPU_EDP_TX2P D10 C12 CPU_EDP_HPD
D
<38> CPU_EDP_TX2P DP0_TXP2 DP0_HPD
CPU_EDP_HPD <38> EDP
5
@ CPU_EDP_TX2N B10 DP0_TXN2
+1.8V_VDD
G
<38> CPU_EDP_TX2N
QC1B DP1_AUXP J20
2N7002KDW_SOT363-6 CPU_EDP_TX3P D9 DP0_TXP3 DP1_AUXN K20
<38> CPU_EDP_TX3P
5
EC_SMB_DA2 3 4
SB00000EO00
APU_SID
<38> CPU_EDP_TX3N
CPU_EDP_TX3N B9 DP0_TXN3
DP3: DP1_HPD L21 RC166 1 2 100K_0402_5%
1
UC9
P
DP2:
S
<29,58,64,68,77> EC_SMB_DA2 NC
G23 L19 APU_DP2_AUXP_C CC111 1 2 0.1U_0201_6.3V6K APU_DP2_AUXP 4 ENVDD_APU
D
DP1_TXP0 DP2_AUXP
Y ENVDD_APU <9,38>
@ H23 DP1_TXN0
DP1: HDMI DP2_AUXN M19 APU_DP2_AUXN_C CC112 1 2 0.1U_0201_6.3V6K APU_DP2_AUXN ENVDD_R 2
A
G
DP2_HPD M20 APU_DP2_HPD
Vgs=1.0-2.5V F22 DP1_TXP1 DP0: eDP APU_DP2_HPD <44>
NL17SZ07DFT2G_SC70-5
3
FH51S RC137 1 2 0_0402_5% G22 DP1_TXN1 DP3_AUXP M14 SA0000BIO00
add bypass Res. DP3_AUXN L14
RC138 1 2 0_0402_5% 0906 G21 DP1_TXP2 DP3_HPD L16 FH51S
H21 DP1_TXN2 ENVDD_R RC31 1 @ 2 0_0201_5% ENVDD_APU Downsize for eDP routing
DP_STEREOSYNC B23 DP_STEREOSYNC
F20 DP1_TXP3
G20 DP1_TXN3
+1.8V_VDD
5
UC10
1
P
NC 4 INVTPWM_R
Y INVTPWM_R <38>
INVTPWM INVTPWM 2
A
G
+3VS NL17SZ07DFT2G_SC70-5
3
SA0000BIO00
RC106 1 @ 2 1K_0201_1% APU_SID
RC105 1 2 1K_0402_5% APU_ALERT# TEST4 BB6 APU_TEST4 TP@ TC1
RC107 1 @ 2 1K_0201_1% APU_SIC TEST5 BD5 APU_TEST5 TP@ TC2
RC108 1 2 1K_0402_5% H_PROCHOT# SVC_PWR_APU +3VS
RC754 1 2 1K_0402_5% THERMTRIP# SVD_PWR_APU TEST6 AG12
ENBKL_APU RC3 1 2 4.7K_0402_5%
27P_0402_50V8J
27P_0402_50V8J
1 1 TEST14 G25 APU_TEST14
2 2
CC113
CC114
TEST15 K25 APU_TEST15 ENVDD_APU RC4 1 2 4.7K_0402_5%
TEST16 F25 APU_TEST16
TEST17 F26 APU_TEST17 INVTPWM_R RC7641 2 4.7K_0402_5%
2 2
TEST31 H26 APU_TEST31 TP@ TC3
@ESD@ 33P_0201_25V8F 33P_0201_25V8F +1.8V_VDD APU_DBREQ# AT2 DBREQ_L 1V8_S5 CPU_EDP_HPD RC755 1 2 100K_0402_5%
CC99 CC29 CC30 +0.75VS
.1U_0402_16V7K ESD@ ESD@
2
2 RC80 1 2 4.7K_0201_5% APU_RST# AW3 P3 SMU_ZVDDP RC145 1 2 196_0402_1% 7/21 add Follow AMD check list
RESET_L 1V8_S5 SMU_ZVDD
RC81 1 2 4.7K_0201_5% APU_PWROK AW4 PWROK 1V8_S5
APU_SIC B22 SIC TC11 TC12 TC13
Close to APU APU_SID D22 SID TP@ TP@ TP@
APU_ALERT# C22 ALERT_L 3V3_S0 VDDP_S5_SENSE AK7 APU_VDDP_SEN_H
APU_VDDP_SEN_H <99>
THERMTRIP# AN9 THERMTRIP_L 3V3_S0 VDDP_SENSE AK12 VDDP_SENSE
<58> THERMTRIP# VDDP_SENSE <99>
H_PROCHOT# B25 PROCHOT_L 3V3_S0 VDDCR_SOC_SENSE J23 VCC_SENSE_APU_CORE_SOC
<58,82,85> H_PROCHOT# VCC_SENSE_APU_CORE_SOC <97>
VDDCR_SENSE K22 VCC_SENSE_APU_CORE
VCC_SENSE_APU_CORE <97>
J21 VDDIO_MEM_S3_SENSE TC10
SVID <97> SVC_PWR_APU
RC22 1
RC23 1
2 0_0402_5% SVC_PWR_APU_R D25
2 0_0402_5% SVD_PWR_APU_R C25
SVC0
SVD0
1V8_S5
1V8_S5
VDDIO_MEM_S3_SENSE
TESTPOINT
AMD DEBUG +1.8VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FP6_(3/7)_DISP/MISC/HDT
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K453P
Date: Wednesday, April 21, 2021 Sheet 8 of 121
A B C D E
A B C D E
HDA_SDOUT AK6 AZ_SDOUT/TDM_FRM_PLAYBACK 3V3_S0 GENINT1_L/AGPIO89 AV15 AGPIO89 1 GC6@ 2 0_0201_5% RC139
GC6_FB_EN3V3 <29>
1
2 RC1611 2 0_0402_5% LAN_WAKE#_R AM2 AGPIO7/FCH_ACP_I2S_SDIN_BT 3V3_S5 3V3_S0 FANIN0/AGPIO84 AT10 1 2 RC62 0_0201_5% AMD Suggest pin 2
<73> LAN_WAKE# NVVDD_PGOOD <26,29,34,103,110>
2
RC1591 2 0_0402_5% KB_BL_DET_R AL4 AGPIO8/FCH_ACP_I2S_LRCLK_BT 3V3_S5 3V3_S0 FANOUT0/AGPIO85 AU10 AGPIO85 1 2 RC63 0_0201_5%
<64> KB_BL_DET KB_DET# <64>
2
2 1 FP6_BGA1140
CC102
0.22U_0201_6.3V6K @ CC32 FH51S DGPU_PWRGD change to NVVDD1_PG
1 2
1U_0201_6.3V6M ACPI Add GPU_EVENT# pin
2020/7/9 modify
+3VALW_APU
+3VALW
@
1 2
CC109
0.1U_0402_16V7K
5
B 4 APU_PCIE_RST#
APU_PCIE1_RST#_C RC39 1 @ 2 0_0402_5% 1 Y
A
G
1
2
UC4 RC152
3
RC151 @ @ 0_0402_5%
10K_0402_5% @
3 3
2
PLT_RST#
PLT_RST# <8,10,58>
1
MC74VHC1G08DFT2G SC70 5P
Strap Pin
+VDDIO_AUDIO
APU_SPI_CLK_R SYS_RST#
RC82 2 1 2.2K_0402_5% APU_WOV_CLK
USE 48MHZ CRYSTAL NORMAL RESET MODE RC83 2 1 2.2K_0402_5% APU_WOV_DAT
HDA H CLOCK (Default)
(Default)
1
RC1191 2 33_0201_5% HDA_SDOUT
<56> HDA_SDOUT_R
@
1
RC619
5
10K_0402_5%
10K_0402_5%
P
2
RC1221 @ 2 1K_0201_5% IN1 4
O SLP_S3#_R <58,62>
RC1231 @ 2 1K_0201_5% S0A3_GPIO 2
2
IN2
G
@
4 UC67 SA00000OH00 4
3
SYS_RST# 2 MC74VHC1G08DFT2G_SC70-5
<10> APU_SPI_CLK_R
@
1
2K_0201_1%
1U_0201_6.3V6M
2
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FP6_(4/7)_GPIO/HDA/STRAP
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K453P
Date: Wednesday, April 21, 2021 Sheet 9 of 121
A B C D E
A B C D E
RC9
UC1E @ 33_0402_5%
CLK/LPC/EMMC/SD/SPI/eSPI/UART PLT_RST_A# 1 2
PLT_RST# <8,9,58>
1
+3VS GPU CLKREQ_PCIE#0 AR13 CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92 dGPU
<26> CLKREQ_PCIE#0 x4 PCIE Express
JSSD1 SSD(PCIE) CLKREQ_PCIE#1 AP10 CLK_REQ1_L/AGPIO115 CC33
<68> CLKREQ_PCIE#1 GBE LAN
LAN CLKREQ_PCIE#2 AR15 CLK_REQ2_L/AGPIO116 150P_0402_50V8J
<73> CLKREQ_PCIE#2 WLAN 2
WLAN CLKREQ_PCIE#3 AT14 CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131
<52> CLKREQ_PCIE#3 SSD (PCIE/SATA) 2020/7/9 modify
RC65 1 2 10K_0402_5% CLKREQ_PCIE#0 JSSD2 SSD(PCIE/SATA) CLKREQ_PCIE#4 AN11 CLK_REQ4_L/OSCIN/EGPIO132
<68> CLKREQ_PCIE#4 RC8 close to UC1
RC66 1 2 10K_0402_5% CLKREQ_PCIE#1 AN13 CLK_REQ5_L/EGPIO120 SW PU/PD
RC67 1 2 10K_0402_5% CLKREQ_PCIE#2 AN15 CLK_REQ6_L/EGPIO121 VDD_33 2020/7/09 Modify +3VALW_APU
1 RC68 1 2 10K_0402_5% CLKREQ_PCIE#3 RC172 close to UC1 1
RC69 1 2 10K_0402_5% CLKREQ_PCIE#4 EGPIO70 AW14 MEM_ERROR_A HDMI_HPD_APU <40>
MEM_ERROR_A <58>
SW PU/PD LPC_PD_L/AGPIO21 BB13 1 @ 2 EC_SCI# RC71 2 @ 1 10K_0201_5%
LPCPD# <8>
CLK_PCIE_P0 AF11 GPP_CLK0P LAD0/ESPI1_DATA0/EGPIO104 BA16 LPC_AD0_R RC101 1 2 10_0402_5% RC760 0_0201_5%
<26> CLK_PCIE_P0 SSD (PCIE/SATA) LPC_AD0 <8,58>
GPU CLK_PCIE_N0 AF12 GPP_CLK0N LAD1/ESPI1_DATA1/EGPIO105 BA15 LPC_AD1_R RC102 1 2 10_0402_5%
<26> CLK_PCIE_N0 LPC_AD1 <8,58>
FH51S LAD2/ESPI1_DATA2/EGPIO106 BC13 LPC_AD2_R RC103 1 2 10_0402_5%
LPC_AD2 <8,58> +3VS
CLK_PCIE_P1 AG4 GPP_CLK1P LAD3/ESPI1_DATA3/EGPIO107 BB14 LPC_AD3_R RC104 1 2 10_0402_5%
<68> CLK_PCIE_P1 x4 PCIE Express LPC_AD3 <8,58>
JSSD1 SSD(PCIE) CLK_PCIE_N1 AG2 GPP_CLK1N SW PU/PD LPCCLK0/EGPIO74 BB15 LPC_CLK0 RC8 1 EMI@ 2 22_0402_5%
<68> CLK_PCIE_N1 LPC_CLK0_EC <8,58>
BD13 CLKRUN#
48MHz CRYSTAL LAN
<73> CLK_PCIE_P2
CLK_PCIE_P2
CLK_PCIE_N2
AG3
AG1
GPP_CLK2P
LPCCLK1/EGPIO75
SERIRQ/AGPIO87
BA12
BC15
LPC_CLK1_R RC172
SERIRQ_R RC86
1 EMI@
2
2 22_0402_5%
1 0_0402_5%
CLKRUN#
LPC_CLK1
<58>
<8>
MEM_ERROR_A RC769 1 @ 2 4.7K_0402_5%
<73> CLK_PCIE_N2 SERIRQ <58>
SW PU/PD LFRAME_L/EGPIO109 BA13 LPC_FRAME#_RRC87 2 1 0_0402_5%
LPC_FRAME# <8,58>
48M_X2 CLK_PCIE_P3 AF2 GPP_CLK3P MEM_ERROR_B RC770 1 @ 2 4.7K_0402_5%
<52> CLK_PCIE_P3 WLAN
WLAN CLK_PCIE_N3 AF4 GPP_CLK3N SW PU/PD LPC_RST_L/AGPIO32 BC12 PLT_RST_A#
<52> CLK_PCIE_N3
1 RC124 2 48M_X1 3V3_S0 AGPIO68 AU12 DGPU_PWROK <26,37,58,108> EGPIO108 RC72 2 1 10K_0402_5%
1M_0402_5% CLK_PCIE_P4 AH2 GPP_CLK4P SW PU/PD LPC_PME_L/AGPIO22 AP4 EC_SCI# EC_SCI# <58>
<68> CLK_PCIE_P4 dGPU Follow MDG.
JSSD2 SSD(PCIE/SATA) CLK_PCIE_N4 AH4 GPP_CLK4N
<68> CLK_PCIE_N4
2 1 AJ2 GPP_CLK5P LPC_CLK1 RC76 2 @ 1 10K_0402_5%
2 1 AJ4 GPP_CLK5N M.2 SSD SPI_ROM_REQ/EGPIO67 BA11
SPI_ROM_GNT/EGPIO76 BB11 LPCPD# RC77 2 @ 1 10K_0402_5%
AF8 GPP_CLK6P/WIFIBT_CLKP
AF9 GPP_CLK6N/WIFIBT_CLKN x4 PCIE TBT SLOT ESPI_RESET_L/KBRST_L/AGPIO129 AT15 KBRST# KBRST# <58>
YC2 ESPI_ALERT_L/LDRQ0_L/EGPIO108 BC11 EGPIO108
48MHZ_8PF_X3S048000D81H-W AK1 X48M_OSC RC74 10_0402_5%
SJ10000JP00 1V8_S5 SPI_CLK/ESPI_CLK BC10 APU_SPI_CLK 1 EMI@ 2
APU_SPI_CLK_R <9>
BA10 APU_SPI_MISO
3 4
PVT 48M_X1 BB3 X48M_X1
SPI_DI/ESPI_DATA
SPI_DO
SPI_WP_L/ESPI_DAT2
BB8
BA9
APU_SPI_MOSI
APU_SPI_WP#
16MB SPI ROM
3 4 SPI_HOLD_L/ESPI_DAT3 BC8 APU_SPI_HOLD#
PVT BD11 APU_SPI_CS#1 +SPI_VCC
1 1 SPI_CS1_L
48M_X2 BA5 BC9 PROJECT_ID1
teknisi-indonesia.com
X48M_X2 SPI_CS2_L/ESPI_CS_L/AGPIO30
CC40 CC41 SPI_CS3_L/AGPIO31 BB10 PROJECT_ID2
2.2P_0402_50V8C 2.2P_0402_50V8C 1V8_S0 SPI_TPM_CS_L/AGPIO29 BD8 APU_SPI_MISO RC14 1 2 10K_0402_5%
2 2
APU_SPI_WP# RC13 1 2 10K_0402_5%
AG10 RSVD_71
AG9 RSVD_70 APU_SPI_HOLD# RC12 1 2 10K_0402_5%
EGPIO143/UART0_TXD
BA17
BC16
UART_0_ARXD_DTXD
UART_0_ATXD_DRXD
UART_0_ARXD_DTXD <52>
UART_0_ATXD_DRXD <52>
EGPIO142/UART0_RTS_L/UART1_RXD BD15 UART_0_RTS#
UART_0_RTS# <52>
EGPIO140/UART0_CTS_L/UART1_TXD BC17 UART_0_CTS#
UART_0_CTS# <52>
32K_X2 AY4 X32K_X2 AGPIO144/SHUTDOWN_L/UART0_INTR BB16 MEM_ERROR_B
MEM_ERROR_B <58>
32K_X1 +1.8V_VDD +SPI_VCC
FP6 REV 0.92
1
PART 5 OF 13 RC149
SJ10000LT00 YC3 PVT FP6_BGA1140 +1.8VS 0_0603_5%
32.768KHZ_12.5PF_CM31532768DZFT 1 2
2
2 1 32K_X2 RC150
RC98 0_0603_5%
20M_0402_5% 1 @ 2
PVT
1
CC37
15P_0402_50V8J
CC36
15P_0402_50V8J §ó´«0.8 --°ª¥Ó½Ð®Æ ¸¹ ¤¤
2
UC7
APU_SPI_CS#1 1 8 +SPI_VCC
APU_SPI_MISO 2 CS# VCC 7 APU_SPI_HOLD#
APU_SPI_WP# 3 DO(IO1) HOLD#(IO3) 6 APU_SPI_CLK_R
4 WP#(IO2) CLK 5 APU_SPI_MOSI
GND DI(IO0)
2
W25Q64FWSSIQ_SOIC_8P @
SA0000CVG00 CC34
0.1U_0201_10V6K
USB Function UC1J @
USB
S IC FL 128M W74M12JWSSIQ SOIC8P SPI ROM 1
@EMI@
AC6 USBC0_DP/USB0_DP USBC0_TX1P/USB0_TXP/DP2_TXP2 AA1 USBC0_DP2_CTX_DRX_P1 APU_SPI_CLK_R 1 @EMI@ 2 1 2
<45> USB20_P0 USBC0_DP2_CTX_DRX_P1 <45>
MB TypeC AC7 USBC0_DN/USB0_DN USBC0_TX1N/USB0_TXN/DP2_TXN2 AA3 USBC0_DP2_CTX_DRX_N1
<45> USB20_N0 USBC0_DP2_CTX_DRX_N1 <45>
RC30 CC35
USB20_P1 AA8 USB1_DP USBC0_RX1P/USB0_RXP/DP2_TXP3 AA2 USBC0_DP3_CRX_DTX_P1 USBC0_DP3_CRX_DTX_P1 <45> 10_0402_5% 10P_0402_50V8J
+1.8V_VDD <71> USB20_P1
MB USB3 Rear USB20_N1 AA9 USB1_DN USBC0_RX1N/USB0_RXN/DP2_TXN3 AA4 USBC0_DP3_CRX_DTX_N1 USBC0_DP3_CRX_DTX_N1 <45>
<71> USB20_N1 Controller 0 MB TypeC
USB20_P2 Y10 USB2_DP USBC0_TX2P/DP2_TXP1 AC2 USBC0_DP1_CTX_DRX_P2 Co-lay SPI Socket with UC7
<52> USB20_P2
USB20_N2 Y9 AC4 USBC0_DP1_CTX_DRX_N2
USBC0_DP1_CTX_DRX_P2 <45> JUSBC1
WLAN/BT <52> USB20_N2
USB2_DN USBC0_TX2N/DP2_TXN1
USBC0_DP1_CTX_DRX_N2 <45>
RC94 1 2 4.7K_0402_5% APU_USBC_SCL JSKT1 CONN@
3 USB20_P3 Y7 USB3_DP USBC0_RX2P/DP2_TXP0 AC1 USBC0_DP0_CRX_DTX_P2 USBC0_DP0_CRX_DTX_P2 <45> APU_SPI_CS#1 1 8 +SPI_VCC 3
RC95 1 2 4.7K_0402_5% APU_USBC_SDA USB20_N3 Y6 AC3 USBC0_DP0_CRX_DTX_N2 APU_SPI_MISO 2 CS# VCC 7 APU_SPI_HOLD#
Camera USB3_DN USBC0_RX2N/DP2_TXN0
USBC0_DP0_CRX_DTX_N2 <45> SO/SIO1 HOLD#
APU_SPI_WP# 3 6 APU_SPI_CLK_R
USB1_TXP AE1 USB3_CTX_DRX_P1 4 WP# SCLK 5 APU_SPI_MOSI
USB3_CTX_DRX_P1 <71> GND SI/SIO0
USB1_TXN AE3 USB3_CTX_DRX_N1
USB3_CTX_DRX_N1 <71>
USB20_P4 AC9 USBC4_DP/USB4_DP Type-A MB USB3.2 SP07000H900
<73> USB20_P4
MB USB3 (IO/B) <73> USB20_N4 AC10 USBC4_DN/USB4_DN USB1_RXP AD8 USB3_CRX_DTX_P1 S SOCKET ACES 91960-0084N 8P FLASH ROM
USB20_N4
AD9 USB3_CRX_DTX_N1
USB3_CRX_DTX_P1 <71> JUSBC1 Rear Side
USB20_P5 AA11 USB5_DP
USB1_RXN
USB3_CRX_DTX_N1 <71> ACES_91960-0084N_MX25L3206EM2I
<73> USB20_P5
MB USB3 (IO/B) <73> USB20_N5 AA12 USB5_DN
USB20_N5
USB20_P6 W8 USB6_DP Controller 1
<62> USB20_P6
ELC USB20_N6 W9 USB6_DN USBC4_TX1P/USB4_TXP/DP3_TXP2 V3 USB3_CTX_DRX_P4
<62> USB20_N6 USB3_CTX_DRX_P4 <73>
USBC4_TX1N/USB4_TXN/DP3_TXN2 V1 USB3_CTX_DRX_N4
USB3_CTX_DRX_N4 <73>
USB20_P7 W11 USB7_DP Type-A IO/B USB3.0
<64> USB20_P7
MCU USB20_N7 W12 USB7_DN USBC4_RX1P/USB4_RXP/DP3_TXP3 U4 USB3_CRX_DTX_P4
<64> USB20_N7
USBC4_RX1N/USB4_RXN/DP3_TXN3 U2 USB3_CRX_DTX_N4
USB3_CRX_DTX_P4 <73> JIO2 Right side
+3VALW_APU USB3_CRX_DTX_N4 <73>
APU_USBC_SCL AL9 1V8_S5 W2
RC96 1
2020/7/14 modify
2 USB_OC0# APU_USBC_SDA AL8
USBC_I2C_SCL
USBC_I2C_SDA 1V8_S5
USBC4_TX2P/DP3_TXP1
USBC4_TX2N/DP3_TXN1 W4 Project ID
100K_0402_5% USBC4_RX2P/DP3_TXP0 W1
RC7561 2 USB_OC1# USBC4_RX2N/DP3_TXN0 W3
100K_0402_5% USB_OC0# AE9 USB_OC0_L/AGPIO16 +3VALW_APU
<44,45> USB_OC0#
RC7571 2 USB_OC2# USB_OC1# AE10 USB_OC1_L/AGPIO17 USB5_TXP AD2 USB3_CTX_DRX_P5
<71> USB_OC1# USB3_CTX_DRX_P5 <73>
100K_0402_5% USB_OC2# AE6 USB_OC2_L/AGPIO18 USB5_TXN AD4 USB3_CTX_DRX_N5
<73> USB_OC2# USB3_CTX_DRX_N5 <73>
RC7581 2 USB_OC3# USB_OC3# AE7 USB_OC3_L/AGPIO24 Type-A IO/B USB3.0
<73> USB_OC3#
100K_0402_5%
7/30 add USB5_RXP AD12 USB3_CRX_DTX_P5 USB3_CRX_DTX_P5 <73> JIO2 Right side
1
SW PU/PD USB5_RXN AD11 USB3_CRX_DTX_N5 USB3_CRX_DTX_N5 <73>
ARK@ @
RC715 RC707
eDP Camera 10K_0402_5% 10K_0402_5%
FP6 REV 0.92
2
RC1621 2 0_0201_1% USB20_P3 PART 10 OF 13
<38> USB20_P3_R RC1631 2 0_0201_1% USB20_N3 FP6_BGA1140 PROJECT_ID1
<38> USB20_N3_R PROJECT_ID2
RC2641 @ 2 0_0201_1%
<73> USB20_P3_IO RC2651 @ 2 0_0201_1%
<73> USB20_N3_IO
IO/B RU Camera
+1.8V_VDD
1
4 4
SIF@ @
RC716 RC708
10K_0402_5% 10K_0402_5%
2
QC3A
5
LBSS139DW1T1G_SOT363-6
TYPEC@
G
3 4 APU_USBC_SCL
<44> CCG4_APU_USBC_SCL
D
QC3B
Security Classification Compal Secret Data Compal Electronics, Inc.
2
LBSS139DW1T1G_SOT363-6
TYPEC@ 2019/08/26 2020/08/26
G
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K453P
Date: Wednesday, April 21, 2021 Sheet 10 of 121
A B C D E
A B C D E
VDDCR_SOC_7
VDDCR_6
VDDCR_7
H11
H15 1
2*180pF 3000ma 33ohm@100mhz DCR 0.04 +1.2V_DDR TDC: 6A AC20 VDDIO_MEM_S3_1 VDDCR_19 R8
AC28 VDDIO_MEM_S3_2 VDDCR_20 R14
AD23 VDDIO_MEM_S3_3 VDDCR_21 R16
VDDIO_MEM_S3_5
VDDCR_22
VDDCR_23
T7
T10 +APU_CORE Cap place at Power Side
TAI-TECH HCB1608KF-330T30 AD32 VDDIO_MEM_S3_6 VDDCR_24 T13
2 1 AE20 VDDIO_MEM_S3_7 VDDCR_25 T15
LC1 AE22 VDDIO_MEM_S3_8 VDDCR_26 T17
CC56
CC57
CC58
CC59
CC60
CC61
CC62
CC63
CC64
CC65
CC66
CC67
CC68
CC69
CC70
CC71
CC72
CC73
CC39
AE25 VDDIO_MEM_S3_9 VDDCR_27 U14
+1.8VS LC3 SM01000JX00 AE28 U16
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VDDIO_MEM_S3_10 VDDCR_28
TAI-TECH HCB1608KF-330T30 AF23 VDDIO_MEM_S3_11 VDDCR_29 V13
2 @ 1 AF26 VDDIO_MEM_S3_12 VDDCR_30 V15
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
180P_0402_50V8J
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
180P_0402_50V8J
180P_0402_50V8J
0.22U_0402_16V7K
AF28 VDDIO_MEM_S3_13 VDDCR_31 V17
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 AF32 VDDIO_MEM_S3_14 VDDCR_32 W7
AG20 VDDIO_MEM_S3_15 VDDCR_33 W10
AG22 VDDIO_MEM_S3_16 VDDCR_34 W14
AG25 VDDIO_MEM_S3_17 VDDCR_35 W16
AG28 VDDIO_MEM_S3_18 VDDCR_36 Y8
AJ20 VDDIO_MEM_S3_19 VDDCR_37 Y13
AJ23 VDDIO_MEM_S3_20 VDDCR_38 Y15
AJ26 VDDIO_MEM_S3_21 VDDCR_39 Y17
AJ28 VDDIO_MEM_S3_22 VDDCR_40 AA7
AJ32 VDDIO_MEM_S3_23 VDDCR_41 AA10
All BU(on bottom side under SOC)ACROSS VDDIO AND VSS SPLIT AK22
AK25
VDDIO_MEM_S3_24 VDDCR_42 AA14
AA16
AK28
VDDIO_MEM_S3_25
VDDIO_MEM_S3_26
VDDCR_43
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
1 @ 2 1 2 AM28 VDDIO_MEM_S3_33 VDDCR_51 AC18
AN28 VDDIO_MEM_S3_34 VDDCR_52 AD7 1 1 1
+1.8VS
CC54
CC55
CC51
CC52
CC53
CC104
CC105
CC106
0_0402_5% 1 1 1 1 1 AP28 VDDIO_MEM_S3_36 VDDCR_54 AD13
1 @ 2 AR32 VDDIO_MEM_S3_37 VDDCR_55 AD15
DA4 VDDCR_56 AD17 2 2 2
0910
22U_0603_6.3V6M
1U_0201_6.3V6M
22U_0603_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
VDD_18_2
VDDCR_65
VDDCR_66 AF17
1*1uF (BU) 2*1uF (BO+BU) VDDCR_67 AF19
+1.8VALW_APU TDC: 1A AL19 VDD_18_S5_1 VDDCR_68 AG14
AM18 VDD_18_S5_2 VDDCR_69 AG16
VDDCR_70 AG18
+3VALW_APU TDC: 0.25A AL17 VDD_33_S5_1 VDDCR_71 AH13
+1.8VS +1.8V_VDD RC89 +1.8VALW_APU +3VALW_APU AM16 VDD_33_S5_2 VDDCR_72 AH15
0_0603_5% VDDCR_73 AH17
1 2 TDC: 2A AL11 AH19
control by +0.75VALW
AL12
VDDP_S5_1
VDDP_S5_2
VDDCR_74
VDDCR_75 AJ7
P.66
CC74
CC75
CC76
CC77
CC78
CC79
CC80
CC81
CC82
1U_0201_6.3V6M
1U_0201_6.3V6M
22U_0603_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
22U_0603_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
+0.75VS
SCL/MBDG:
2*22uF (BO) +0.75VALW
SCL/MBDG:
1*22uF (BO)
RTC OF APU +RTC_APU +RTC_CELL
from BAT_LDO
8*1uF (BOx4+BUx4) 3*1uF (BOx1+BUx2)
1*180pF (BU)
RC79 1 2 0_0402_5%
SCL/MBDG: +RTC_APU_R
CC83
CC84
CC85
CC86
CC87
CC88
CC89
CC90
CC91
CC92
CC93
CC94
CC95
CC96
CC97
1*1uF
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1*0.22uF
close to UC1
22U_0603_6.3V6M
22U_0603_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
180P_0402_50V8J
22U_0603_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
RC73
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 W=20mils 1K_0402_5%
1 2
1 1 1
1
1
CC103 CC50 CLRP1 CC107 CC108
0.22U_0402_16V7K 1U_0201_6.3V6M SHORT PADS 0.1U_0201_10V6K 680P_0402_50V7K
BO BOx4 BUx4 BU BO BO BU
2
2 2 2
2
SCL/MBDG: SCL/MBDG:
+VDDCR_VDD 1*180pF +VDDCR_SOC 1*180pF for Clear CMOS
1*1uF
CC115 180P_0402_50V8J
CC116 180P_0402_50V8J
CC117 1U_0402_6.3V7K
1 1
2
4 4
1
2 2
D A19 VSS VSS L28 V22 VSS VSS AF14 AT23 VSS_252 D
A21 VSS VSS M1 V25 VSS VSS AF16 AU5 VSS_253
A23 VSS VSS M3 V28 VSS VSS AF18 AU8 VSS_254
A26 VSS VSS M5 W5 VSS VSS AF20 AU11 VSS_255
A30 VSS VSS M21 W13 VSS VSS AG5 AU13 VSS_256
C3 VSS VSS M23 W15 VSS VSS AG8 AU15 VSS_257
C10 VSS VSS M26 W17 VSS VSS AG11 AU18 VSS_258 RSVD_46 AV8
C32 VSS VSS M28 W19 VSS VSS AG13 AU20 VSS_259 RSVD_47 BD18
E7 VSS VSS M32 W23 VSS VSS AG15 AU22 VSS_260 RSVD_45 AV3
E8 VSS VSS N5 W26 VSS VSS AG17 AU25 VSS_261 RSVD_44 AU6
E10 VSS VSS N8 W28 VSS VSS AG19 AU28 VSS_262 RSVD_43 AR6
E11 VSS VSS N11 W32 VSS VSS AH14 AV1 VSS_263 RSVD_42 AR3
E12 VSS VSS N13 Y1 VSS VSS AH16 AV5 VSS_264 RSVD_41 AP1
E13 VSS VSS N15 Y3 VSS VSS AH18 AV7 VSS_265 RSVD_40 AN16
E14 VSS VSS N17 Y5 VSS VSS AH20 AV10 VSS_266 RSVD_39 AN4
E15 VSS VSS N22 Y11 VSS VSS AJ1 AV12 VSS_267 RSVD_38 AN2
E16 VSS VSS N25 Y14 VSS VSS AJ3 AV14 VSS_268 RSVD_37 AM14
E18 VSS VSS N28 Y16 VSS VSS AJ5 AV16 VSS_269 RSVD_36 AM13
E19 VSS VSS P1 Y18 VSS VSS AJ13 AV19 VSS_270 RSVD_35 AL29
E20 VSS VSS P5 Y20 VSS VSS AJ15 AV21 VSS_271 RSVD_34 AL15
E21 VSS VSS P14 Y22 VSS VSS AJ17 AV23 VSS_272 RSVD_33 AL14
E22 VSS VSS P16 Y25 VSS VSS AJ19 AV26 VSS_273 RSVD_32 AL13
E23 VSS VSS P18 Y28 VSS VSS AK5 AV28 VSS_274 RSVD_31 AK3
E25 VSS VSS P20 AA5 VSS VSS AK8 AV32 VSS_275 RSVD_30 AJ29
E26 VSS VSS P23 AA13 VSS VSS AK11 AW5 VSS_276 RSVD_29 AJ27
E27 VSS VSS P26 AA15 VSS VSS AK14 AW28 VSS_277 RSVD_28 AF6
F5 VSS VSS P28 AA17 VSS VSS AK16 AY6 VSS_278 RSVD_27 AE12
F19 VSS VSS P32 AA19 VSS VSS AK18 AY7 VSS_279 RSVD_26 AD6
F21 VSS VSS R5 AA23 VSS VSS AK20 AY8 VSS_280 RSVD_25 AD3
C F23 VSS VSS R11 AA26 VSS VSS AL1 AY10 VSS_281 RSVD_24 AC30 C
F28 VSS VSS R13 AA28 VSS VSS AL5 AY11 VSS_282 RSVD_23 AC12
G1 VSS VSS R15 AA32 VSS VSS AL7 AY12 VSS_283 RSVD_22 AB31
G3 VSS VSS R17 AB2 VSS VSS AL10 AY13 VSS_284 RSVD_21 AA20
G5 VSS VSS R19 AB4 VSS VSS AL16 AY14 VSS_285 RSVD_20 AA6
G16 VSS VSS R22 AB14 VSS VSS AM5 AY15 VSS_286 RSVD_19 Y12
G26 VSS VSS R25 AB16 VSS VSS AM8 AY16 VSS_287 RSVD_18 W6
G28 VSS VSS R28 AB18 VSS VSS AM11 AY18 VSS_288 RSVD_17 V12
G32 VSS VSS T1 AB20 VSS VSS AM15 AY19 VSS_289 RSVD_16 R12
H5 VSS VSS T3 AC5 VSS VSS AN1 AY20 VSS_290 RSVD_15 N19
H13 VSS VSS T5 AC8 VSS VSS AN5 AY21 VSS_291 RSVD_14 N12
H18 VSS VSS T14 AC11 VSS VSS AN7 AY22 VSS_292 RSVD_13 N10
H20 VSS VSS T16 AC13 VSS VSS AN10 AY23 VSS_293 RSVD_12 N9
H22 VSS VSS T18 AC15 VSS VSS AN23 AY25 VSS_294 RSVD_11 M13
H25 VSS VSS T20 AC17 VSS VSS AN26 AY26 VSS_295 RSVD_10 M12
H28 VSS VSS T23 AC19 VSS VSS AP5 AY27 VSS_296 RSVD_9 M11
J19 VSS VSS T26 AC22 VSS VSS AP8 BB1 VSS_297 RSVD_8 M6
K1 VSS VSS T28 AC25 VSS VSS AP13 BB32 VSS_298 RSVD_7 L12
K3 VSS VSS T32 AD1 VSS VSS AP15 BD3 VSS_299 RSVD_6 K19
K5 VSS VSS U13 AD5 VSS VSS AP18 BD7 VSS_300 RSVD_5 F16
K16 VSS VSS U15 AD14 VSS VSS AP20 BD10 VSS_301 RSVD_4 F14
K21 VSS VSS U17 AD16 VSS VSS AP25 BD12 VSS_302 RSVD_3 F12
K26 VSS VSS U19 AD18 VSS VSS AR1 BD14 VSS_303 RSVD_2 F10
VSS V2 AD20 VSS VSS AR5 BD16 VSS_304 RSVD_1 C26
VSS V4 AE5 VSS VSS AR7
FP6 REV 0.92 AE11 VSS VSS AR12
PART 7 OF 13 FP6 REV 0.92
FP6_BGA1140 PART 8 OF 13 FP6 REV 0.92
FP6_BGA1140 PART 11 OF 13
B FP6_BGA1140 Project ID +3VALW_APU
B
UC1L @
WiFi
UC1M @ GPUID 100K_0201_5% 2 N20E@ 1 RC169
CAMERAS <73> PX_INT# N7 AGPIO256/WIFIBT_BT_DATA EGPIO267/RFIC_SPI_CLK P8 OD_EN_R OD_EN_R <38>
<73> ALC_INT# R7 AGPIO257/WIFIBT_BT_VALID EGPIO268/RFIC_SPI_SS R9 GPUID 100K_0201_5% 1 N20P@ 2 RC171
D21 CAM0_CSI2_CLOCKP CAM0_CLK A18 <73> PX_DIS# N6 AGPIO258/WIFIBT_BT_SYNC AGPIO269/RFIC_SPI_DATA R6
A20 CAM0_CSI2_CLOCKN
<73> IRCAM_DET# T6 AGPIO259/WIFIBT_BT_CLK
CAM0_I2C_SCL C18
D18 CAM0_CSI2_DATAP0 CAM0_I2C_SDA B17
B18 CAM0_CSI2_DATAN0
AGPIO264/WIFIBT_QSPI_CLK
SIF LOW SIF@
B21 CAM0_CSI2_DATAN2 P6 AGPIO265/WIFIBT_QSPI_SS
ARK HIGH ARK@
WIFIBT_DATA_RXP V7
C20 CAM0_CSI2_DATAP3 WIFIBT_DATA_RXN V6
B20 CAM0_CSI2_DATAN3
WIFIBT_DATA_TXP V9
N20E / N20P
C15 CAM1_CSI2_CLOCKP CAM1_CLK A13 WIFIBT_DATA_TXN V10
A15 CAM1_CSI2_CLOCKN
LOW N20P@
B13 +1.8V_VDD
D16
CAM1_I2C_SCL
D13
NV - GN20P
B16
CAM1_CSI2_DATAP0
CAM1_CSI2_DATAN0
CAM1_I2C_SDA FP6 REV 0.92
PART 12 OF 13
GPUID
A A
2
FP6_BGA1140
PART 13 OF 13
SPK_ID2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2019/08/26 Deciphered Date 2020/08/26 Title
FP6_(7/7)_GND/RSVD/CSI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K453P
Date: Wednesday, April 21, 2021 Sheet 12 of 121
5 4 3 2 1
5 4 3 2 1
D D
C
www.teknisi-indonesia.com C
Reserve
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K453P
Date: Wednesday, April 21, 2021 Sheet 13 of 121
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K453P
Date: Wednesday, April 21, 2021 Sheet 14 of 121
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K453P
Date: Wednesday, April 21, 2021 Sheet 15 of 121
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K453P
Date: Wednesday, April 21, 2021 Sheet 16 of 121
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K453P
Date: Wednesday, April 21, 2021 Sheet 17 of 121
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K453P
Date: Wednesday, April 21, 2021 Sheet 18 of 121
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K453P
Date: Wednesday, April 21, 2021 Sheet 19 of 121
5 4 3 2 1
5 4 3 2 1
D D
C C
Reserve
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K453P
Date: Wednesday, April 21, 2021 Sheet 20 of 121
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RSV
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K453P
Date: Wednesday, April 21, 2021 Sheet 21 of 121
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RSV
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K453P
Date: Wednesday, April 21, 2021 Sheet 22 of 121
5 4 3 2 1
5 4 3 2 1
Interleaved Memory
Note:
Layout Note: Check voltage tolerance of
Place near JDIMM1 VREF_DQ at the DIMM socket
DDR4 support Even Parity check in DRAMs.
+1.2V_DDR
CRB use 0.1uF x12 (6 pop,6 unpop),180pF x1,100uF x2
REVERSE TYPE (4 mm)
D D
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 1
CD2
CD3
CD4
CD5
CD6
CD7
2 2 2 2 2 2 JDIMM1A CONN@
DDR_A_DQ[7..0] <7>
DDR_A_CLK0 137 RVS 8 DDR_A_DQ0
<7> DDR_A_CLK0 CK0(T) DQ0
DDR_A_CLK0# 139 7 DDR_A_DQ1
<7> DDR_A_CLK0# CK0#(C) DQ1
DDR_A_CLK1 138 20 DDR_A_DQ2
<7> DDR_A_CLK1 CK1(T) DQ2
DDR_A_CLK1# 140 21 DDR_A_DQ3
<7> DDR_A_CLK1# CK1#(C) DQ3 4 DDR_A_DQ4
DDR_A_CKE0 109 DQ4 3 DDR_A_DQ5
<7> DDR_A_CKE0 CKE0 DQ5
DDR_A_CKE1 110 16 DDR_A_DQ6
+1.2V_DDR <7> DDR_A_CKE1 CKE1 DQ6
JDIMM1B CONN@ 17 DDR_A_DQ7
RVS DDR_A_CS0# 149 DQ7 13 DDR_A_DQS0
FH51S downsize by sourcer demand <7> DDR_A_CS0# S0# DQS0(T) DDR_A_DQS0 <7>
111 141 DDR_A_CS1# 157 11 DDR_A_DQS0#
Follow MA51 Follow CRB design
+1.2V_DDR 112 VDD1 VDD11 142
+1.2V_DDR <7> DDR_A_CS1#
162 S1# DQS0#(C) DDR_A_DQS0#
DDR_A_DQ[15..8]
<7>
<7>
117 VDD2 VDD12 147 165 S2#/C0 28 DDR_A_DQ8
1 VDD3 VDD13 S3#/C1 DQ8
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
@ +1.2V_DDR 118 148 29 DDR_A_DQ9
+ CD18 123 VDD4 VDD14 153 DDR_A_ODT0 155 DQ9 41 DDR_A_DQ10
1 1 1 1 1 1 1 1 VDD5 VDD15 <7> DDR_A_ODT0 ODT0 DQ10
CD10
CD11
CD12
CD13
CD14
CD15
CD16
2
SGA20331E10 129 159 24 DDR_A_DQ12
2 RD3 130 VDD7 VDD17 160 DDR_A_BG0 115 DQ12 25 DDR_A_DQ13
2 2 2 2 2 2 2 2 1K_0402_1% 135 VDD8 VDD18 163
+0.6V_DDR_VTT <7> DDR_A_BG0
DDR_A_BG1 113 BG0 DQ13 38 DDR_A_DQ14
SGA00009S00 +VREFA_CA 136 VDD9 VDD19 <7> DDR_A_BG1
DDR_A_BA0 150 BG1 DQ14 37 DDR_A_DQ15
330U 2V H1.9 +3VS VDD10 +2.5V_MEM <7> DDR_A_BA0
DDR_A_BA1 145 BA0 DQ15 34 DDR_A_DQS1
<7> DDR_A_BA1 DDR_A_DQS1 <7>
1
BA1 DQS1(T)
9mohm POLY 255
VDDSPD VTT
258
<7> DDR_A_MA[13..0] DQS1#(C)
32 DDR_A_DQS1#
DDR_A_DQS1# <7>
FH51S 15mil DDR_A_MA0 144
PC sample = 1.5K A0 DDR_A_DQ[23..16] <7>
164 257 DDR_A_MA1 133 50 DDR_A_DQ16
others = 1k ohm VREFCA VPP1 259 DDR_A_MA2 132 A1 DQ16 49 DDR_A_DQ17
VPP2 A2 DQ17
CD20 4.7U_0402_6.3V6M
CD22 0.1U_0201_10V6K
CD21 0.1U_0201_10V6K
CD19 1000P_0402_50V7K
DDR_A_MA3 131 62 DDR_A_DQ18
+1.2V_DDR A3 DQ18
CD31 1U_0201_6.3V6M
1 99 DDR_A_MA4 128 63 DDR_A_DQ19
VSS VSS A4 DQ19
2
1 2 2 1 2 102 DDR_A_MA5 126 46 DDR_A_DQ20
RD4 5 VSS VSS 103 DDR_A_MA6 127 A5 DQ20 45 DDR_A_DQ21
VSS VSS 1 A6 DQ21
1K_0402_1% 6 106 DDR_A_MA7 122 58 DDR_A_DQ22
9 VSS VSS 107 DDR_A_MA8 125 A7 DQ22 59 DDR_A_DQ23
2 1 1 2 VSS VSS A8 DQ23
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
180P_0402_50V8J
1
VSS VSS 2 A9 DQS2(T)
CD61
CD62
CD63
CD64
CD65
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
CD24
CD25
CD98
CD26
0.1U_0201_6.3V6K
CT412
0.1U_0201_6.3V6K
CT413
0.1U_0201_6.3V6K
CT414
0.1U_0201_6.3V6K
CT417
0.1U_0201_6.3V6K
CT415
236 DDR_A_DQ57
DQ57 249 DDR_A_DQ58
DQ58 250 DDR_A_DQ59
Address : A0 2 2 2
Part Number: SP07001CW0L
Part Value: S SOCKET DEREN 40-42271-26001RHF DDR A31
DQ59
DQ60
DQ61
232
233
245
DDR_A_DQ60
DDR_A_DQ61
DDR_A_DQ62
DQ62 246 DDR_A_DQ63
+3VS DQ63 242 DDR_A_DQS7
DQS7(T) DDR_A_DQS7 <7>
240 DDR_A_DQS7#
DQS7#(C) DDR_A_DQS7# <7>
1
1
0_0402_5%
RD5
0_0402_5%
RD6
0_0402_5%
RD27
DEREN 40-42271-26001RHF
SP07001CW0L
@ @ @
2
DDR_A_SA2
DDR_A_SA1
DDR_A_SA0
Layout Note:
1
1
0_0402_5%
0_0402_5%
0_0402_5%
RD25
RD9
2
+0.6V_DDR_VTT
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1
CD108
CD27
CD28
CD29
CD30
DVT 2 2 2 2 2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR4 DIMMA_RVS
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K453P
Date: Wednesday, April 21, 2021 Sheet 23 of 121
5 4 3 2 1
5 4 3 2 1
Note:
Layout Note: Check voltage tolerance of
Place near JDIMM2 VREF_DQ at the DIMM socket
+1.2V_DDR
Interleaved Memory
(4 mm)
D D
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 1
STD
CD86
CD67
CD78
CD93
CD71
CD81
2 2 2 2 2 2
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
DDR_B_CKE0 109 3 DDR_B_DQ5
<7> DDR_B_CKE0 CKE0 DQ5
1 1 1 1 1 1 1 1 DDR_B_CKE1 110 16 DDR_B_DQ6
<7> DDR_B_CKE1 CKE1 DQ6
CD82
CD90
CD96
CD77
CD68
CD88
CD103
CD104
17 DDR_B_DQ7
JDIMM2B CONN@ DDR_B_CS0# 149 DQ7 13 DDR_B_DQS0
<7> DDR_B_CS0# S0# DQS0(T) DDR_B_DQS0 <7>
STD DDR_B_CS1# 157 11 DDR_B_DQS0#
2 2 2 2 2 2 2 2 <7> DDR_B_CS1# S1# DQS0#(C) DDR_B_DQS0# <7>
@ 111 141 162
+1.2V_DDR 112 VDD1 VDD11 142
+1.2V_DDR 165 S2#/C0 28 DDR_B_DQ8
DDR_B_DQ[15..8] <7>
Follow CRB design 117 VDD2 VDD12 147 S3#/C1 DQ8 29 DDR_B_DQ9
+1.2V_DDR 118 VDD3 VDD13 148 DDR_B_ODT0 155 DQ9 41 DDR_B_DQ10
VDD4 VDD14 <7> DDR_B_ODT0 ODT0 DQ10
123 153 DDR_B_ODT1 161 42 DDR_B_DQ11
VDD5 VDD15 <7> DDR_B_ODT1 ODT1 DQ11
124 154 24 DDR_B_DQ12
VDD6 VDD16 DQ12
2
129 159 DDR_B_BG0 115 25 DDR_B_DQ13
VDD7 VDD17 <7> DDR_B_BG0 BG0 DQ13
RD243 130 160 DDR_B_BG1 113 38 DDR_B_DQ14
+1.2V_DDR 1K_0402_1% 135 VDD8 VDD18 163
+0.6V_DDR_VTT <7> DDR_B_BG1
DDR_B_BA0 150 BG1 DQ14 37 DDR_B_DQ15
VDD9 VDD19 <7> DDR_B_BA0 BA0 DQ15
+VREFB_CA 136
<7> DDR_B_BA1
DDR_B_BA1 145 34 DDR_B_DQS1
DDR_B_DQS1 <7>
+3VS VDD10 +2.5V_MEM BA1 DQS1(T) 32 DDR_B_DQS1#
<7> DDR_B_MA[13..0] DDR_B_DQS1# <7>
1
255 258 DDR_B_MA0 144 DQS1#(C)
VDDSPD VTT A0 DDR_B_DQ[23..16] <7>
15mil DDR_B_MA1 133 50 DDR_B_DQ16
PC sample = 1.5K A1 DQ16
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
180P_0402_50V8J
CD94
CD97
CD66
CD85
CD84 4.7U_0402_6.3V6M
CD76 0.1U_0201_10V6K
CD80 0.1U_0201_10V6K
CD87 1000P_0402_50V7K
DDR_B_MA4 128 63 DDR_B_DQ19
A4 DQ19
CD89 1U_0201_6.3V6M
1 99 DDR_B_MA5 126 46 DDR_B_DQ20
VSS VSS A5 DQ20
2
1 1 1 1 1 2 102 DDR_B_MA6 127 45 DDR_B_DQ21
1 2 2 1 VSS VSS A6 DQ21
RD253 5 103 1 DDR_B_MA7 122 58 DDR_B_DQ22
C VSS VSS A7 DQ22 C
1K_0402_1% 6 106 DDR_B_MA8 125 59 DDR_B_DQ23
9 VSS VSS 107 DDR_B_MA9 121 A8 DQ23 55 DDR_B_DQS2
2 1 1 2 VSS VSS A9 DQS2(T) DDR_B_DQS2 <7>
10 167 DDR_B_MA10 146 53 DDR_B_DQS2#
DDR_B_DQS2# <7>
1
14 VSS VSS 168 2 DDR_B_MA11 120 A10_AP DQS2#(C)
VSS VSS A11 DDR_B_DQ[31..24] <7>
15 171 DDR_B_MA12 119 70 DDR_B_DQ24
18 VSS VSS 172 DDR_B_MA13 158 A12 DQ24 71 DDR_B_DQ25
19 VSS VSS 175 DDR_B_MA14_WE# 151 A13 DQ25 83 DDR_B_DQ26
VSS VSS <7> DDR_B_MA14_WE# A14_WE# DQ26
22 176 DDR_B_MA15_CAS# 156 84 DDR_B_DQ27
VSS VSS <7> DDR_B_MA15_CAS# A15_CAS# DQ27
23 180 DDR_B_MA16_RAS# 152 66 DDR_B_DQ28
VSS VSS CRB use 1uF x1 <7> DDR_B_MA16_RAS# A16_RAS# DQ28
26 181 67 DDR_B_DQ29
27 VSS VSS 184 DDR_B_ACT# 114 DQ29 79 DDR_B_DQ30
VSS VSS <7> DDR_B_ACT# ACT# DQ30
30 185 80 DDR_B_DQ31
Place near to SO-DIMM connector. 31 VSS
VSS
VSS
VSS
188
<7> DDR_B_PAR
DDR_B_PAR 143
PARITY
DQ31
DQS3(T)
76 DDR_B_DQS3
DDR_B_DQS3 <7>
Layout Note: Layout Note: 35 189 DDR_B_ALERT# 116 74 DDR_B_DQS3#
VSS VSS <7> DDR_B_ALERT# ALERT# DQS3#(C) DDR_B_DQS3# <7>
36 192 CD73 @EMI@ DDR_B_EVENT# 134
Place near JDIMM2.257,259 Place near JDIMM2.255 39 VSS VSS 193 .1U_0402_16V7K
<7> DDR_B_EVENT#
DDR_B_RST# 108 EVENT# 174 DDR_B_DQ32
DDR_B_DQ[39..32] <7>
VSS VSS <7> DDR_B_RST# RESET# DQ32
40 196 2 1 DDR_B_RST# 173 DDR_B_DQ33
43 VSS VSS 197 DQ33 187 DDR_B_DQ34
44 VSS VSS 201 SMB_0_SDA 254 DQ34 186 DDR_B_DQ35
CRB use 0.1uF x2,180pF x1 CRB use 1uF x1 VSS VSS <9,23> SMB_0_SDA SDA DQ35
47 202 SMB_0_SCL 253 170 DDR_B_DQ36
VSS VSS <9,23> SMB_0_SCL SCL DQ36
48 205 169 DDR_B_DQ37
+2.5V_MEM +3VS 51 VSS VSS 206 DDR_B_SA2 166 DQ37 183 DDR_B_DQ38
VSS VSS DT23 SA2 DQ38
52 209 DDR_B_SA1 260 182 DDR_B_DQ39
56 VSS VSS 210 3 DDR_B_SA0 256 SA1 DQ39 179 DDR_B_DQS4
VSS VSS SA0 DQS4(T) DDR_B_DQS4 <7>
57 213 1 177 DDR_B_DQS4#
VSS VSS DQS4#(C) DDR_B_DQS4# <7>
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
60 214 2 DDR_B_RST#
VSS VSS DDR_B_DQ[47..40] <7>
1 1 1 1 1 61 217 92 195 DDR_B_DQ40
VSS VSS CB0_NC DQ40
CD79
CD83
CD75
CD105
CD95
1
10K_0402_5%
RD244
245 DDR_B_DQ62
DQ62
0_0402_5%
RD247
0_0402_5%
RD248
246 DDR_B_DQ63
DQ63 242 DDR_B_DQS7
DQS7(T) DDR_B_DQS7 <7>
240 DDR_B_DQS7#
DQS7#(C) DDR_B_DQS7# <7>
@ @
2
1
0_0402_5%
0_0402_5%
0_0402_5%
RD249
RD252
RD246
+0.6V_DDR_VTT
12/14 DVT2 modify 12/14 DVT2 modify 12/14 DVT2 modify
ESD request ESD request ESD request
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1
CD109
CD70
CD74
CD92
CD72
@
DT21 DT20 DT19
DVT 2 2 2 2 2 3 +2.5V_MEM 3 +0.6V_DDR_VTT 3 +1.2V_DDR
1 1 1
A 2 2 2 A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR4 DIMMB_STD
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K453P
Date: Wednesday, April 21, 2021 Sheet 24 of 121
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
VRAM Configuration
Samsung Hynix Micron X76
UM9 SAM@ UM9 HYNIX@ UM9 MIC@ ZZZ3 X76S@
C C
K4Z80325BC-HC14 1.2V H56C8H24AIR-S2C FBGA 180P MT61K256M32JE-14:A1.2V ALT. GROUP PARTS VRAM 4G SAM
SA0000C626L SA0000DUW1L SA0000BND7L X7691031L61
K4Z80325BC-HC14 1.2V H56C8H24AIR-S2C FBGA 180P MT61K256M32JE-14:A1.2V ALT. GROUP PARTS VRAM 4G HYN
SA0000C626L SA0000DUW1L SA0000BND7L X7691031L63
K4Z80325BC-HC14 1.2V H56C8H24AIR-S2C FBGA 180P MT61K256M32JE-14:A1.2V ALT. GROUP PARTS VRAM 4G MIC
B SA0000C626L SA0000DUW1L SA0000BND7L X7691031L62 B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RSV
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K453P
Date: Wednesday, April 21, 2021 Sheet 25 of 121
5 4 3 2 1
A B C D E
+1V8_AON
1
GC OFF 1.0 GPU Power ON/OFF S IC N20Z-QS1-A1 BGA 1358 S
GPU@QS1@
SA0000E1W1L
S IC GN20-P0-A1 BGA 1358 GPU S
GPU@P0@
SA0000DXP0L
S IC GN20-P0-A1 BGA 1358 GPU A31 !
GPU@R3@P0@
SA0000DXP2L
1 2 CG330
RG99 100K_0201_5% 0.1U_0201_10V6K UG1 UG1
5
2
VCC
PEX_RST# 1
<12> PEX_RST# IN B 4
OUT Y DGPU_PEX_RST# <29,40>
2
GND
<9,52,68,73> APU_PCIE_RST# IN A
1
1 S IC GN20-P1-A1 BGA 1358 GPU S S IC GN20-P1-A1 BGA 1358 GPU A31 ! 1
RG100 @ GPU@P1@ GPU@R3@P1@
UG6 100K_0201_5% SA0000DXQ0L SA0000DXQ2L
3
NL17SZ08EDFT2G_SOT353-5
UG1 UG1
2
+1V8_AON
S IC GN20-P0-D-A1 BGA 1358 GPU S S IC GN20-P0-D-A1 BGA 1358 GPU A31 !
1 GPU@P0D@ GPU@R3@P0D@
SA0000EEC0L SA0000EEC2L
CG331
0.1U_0201_10V6K
2
5
+1V8_AON UG1A
VCC
1 1/17 PCI_EXPRESS
<10,37,58,108> DGPU_PWROK IN B +PEX_VDD +PEX_VDD
4 ALL_GPWRGD
OUT Y
Under GPU
1
2 PEX_WAKE# doesn¡¦t apply in notebook
GND
<9,29,34,103,110> NVVDD_PGOOD IN A RG101
10K_0201_5%
MBD.
@ T74 PAD~D PEX_WAKE# AP11 AL27
UG7 PEX_WAKE_N PEX_DVDD_1 AL28
3
PEX_DVDD_2
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
10U_0603_6.3VAM
10U_0603_6.3VAM
22U_0603_6.3VAM
NL17SZ08EDFT2G_SOT353-5 DGPU_PEX_RST# 1 2 DGPU_PEX_RST#_R AN11 AL29
2
RG102 0_0201_1% PEX_RST_N PEX_DVDD_3 AM26
PEX_DVDD_4 1 1 1 1 1 1 1
CG348
CG349
CG350
CG351
CG357
CG358
CG360
1 3 QG8 CLKREQ_PEG#7_R AU11 AM28
<10> CLKREQ_PCIE#0 PEX_CLKREQ_N PEX_DVDD_5
BSS138W_SOT-323-3-X AM29
S
AR12 PEX_DVDD_6 AM30
<10> CLK_PCIE_P0 AT12 PEX_REFCLK PEX_DVDD_7 AN29 2 2 2 2 2 2 2
<10> CLK_PCIE_N0 PEX_REFCLK_N PEX_DVDD_8 AN30
CG332 1 2 0.22U_0201_6.3VAM PEG_CRX_C_GTX_P0 AN13 PEX_DVDD_9 AP30
<6> PEG_CRX_GTX_P0 PEX_TX0 PEX_DVDD_10
CG333 1 2 0.22U_0201_6.3VAM PEG_CRX_C_GTX_N0 AP13 AR30
<6> PEG_CRX_GTX_N0 PEX_TX0_N PEX_DVDD_11 AT30
AV13 PEX_DVDD_12 AU30
<6> PEG_CTX_C_GRX_P0 PEX_RX0 PEX_DVDD_13
4.7U_0402_6.3VAM
4.7U_0402_6.3VAM
AW13 AV30
<6> PEG_CTX_C_GRX_N0 PEX_RX0_N PEX_DVDD_14 AW30 1 1
PEX_DVDD_15
Near GPU
CG354
CG355
CG334 1 2 0.22U_0201_6.3VAM PEG_CRX_C_GTX_P1 AR14 AY30
<6> PEG_CRX_GTX_P1 PEX_TX1 PEX_DVDD_16
CG335 1 2 0.22U_0201_6.3VAM PEG_CRX_C_GTX_N1 AT14
<6> PEG_CRX_GTX_N1 PEX_TX1_N
AW14 2 2
<6> PEG_CTX_C_GRX_P1 PEX_RX1
AY14
<6> PEG_CTX_C_GRX_N1 PEX_RX1_N
CG336 1 2 0.22U_0201_6.3VAM PEG_CRX_C_GTX_P2 AN15
<6> PEG_CRX_GTX_P2 PEX_TX2
CG337 1 2 0.22U_0201_6.3VAM PEG_CRX_C_GTX_N2 AP15
<6> PEG_CRX_GTX_N2 PEX_TX2_N
AV15
<6> PEG_CTX_C_GRX_P2 PEX_RX2
AW15
<6> PEG_CTX_C_GRX_N2 PEX_RX2_N AL24
CG338 1 2 0.22U_0201_6.3VAM PEG_CRX_C_GTX_P3 AR16 PEX_CVDD_1 AL25
<6> PEG_CRX_GTX_P3 PEX_TX3 PEX_CVDD_2
2 CG339 1 2 0.22U_0201_6.3VAM PEG_CRX_C_GTX_N3 AT16 AL26 2
<6> PEG_CRX_GTX_N3 PEX_TX3_N PEX_CVDD_3 AM24
<6>
<6>
PEG_CTX_C_GRX_P3
PEG_CTX_C_GRX_N3
AW16
AY16 PEX_RX3
PEX_RX3_N
PEX_CVDD_4
Under GPU +1V8_MAIN +1V8_MAIN
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
10U_0603_6.3VAM
10U_0603_6.3VAM
22U_0603_6.3VAM
AL19
AV17 PEX_HVDD_3 AL20
<6> PEG_CTX_C_GRX_P4 PEX_RX4 PEX_HVDD_4 1 1 1 1 1 1
CG361
CG362
CG363
CG373
CG374
CG376
AW17 AL21
<6> PEG_CTX_C_GRX_N4 PEX_RX4_N PEX_HVDD_5 AL22
CG342 1 2 0.22U_0201_6.3VAM PEG_CRX_C_GTX_P5 AR18 PEX_HVDD_6 AL23
<6> PEG_CRX_GTX_P5 PEX_TX5 PEX_HVDD_7 2 2 2 2 2 2
CG343 1 2 0.22U_0201_6.3VAM PEG_CRX_C_GTX_N5 AT18 AM16
<6> PEG_CRX_GTX_N5 PEX_TX5_N PEX_HVDD_8 AM18
AW18 PEX_HVDD_9 AM20
<6> PEG_CTX_C_GRX_P5 PEX_RX5 PEX_HVDD_10
AY18
<6> PEG_CTX_C_GRX_N5 PEX_RX5_N +1V8_MAIN
CG344 1 2 0.22U_0201_6.3VAM PEG_CRX_C_GTX_P6 AN19
<6> PEG_CRX_GTX_P6 PEX_TX6
CG345 1 2 0.22U_0201_6.3VAM PEG_CRX_C_GTX_N6 AP19 AM22
<6> PEG_CRX_GTX_N6 PEX_TX6_N PEX_PLL_HVDD
Near GPU
4.7U_0402_6.3VAM
4.7U_0402_6.3VAM
1U_0201_6.3VAM
AV19
<6> PEG_CTX_C_GRX_P6 PEX_RX6 16 mils 1 1
CG367
CG368
AW19 1
<6> PEG_CTX_C_GRX_N6 PEX_RX6_N
CG377
CG346 1 2 0.22U_0201_6.3VAM PEG_CRX_C_GTX_P7 AR20
<6> PEG_CRX_GTX_P7 PEX_TX7 2 2
CG347 1 2 0.22U_0201_6.3VAM PEG_CRX_C_GTX_N7 AT20
<6> PEG_CRX_GTX_N7 PEX_TX7_N 2
AW20
<6> PEG_CTX_C_GRX_P7 PEX_RX7
AY20
<6> PEG_CTX_C_GRX_N7 PEX_RX7_N
AN21
AP21 PEX_TX8
PEX_TX8_N
AV21
AW21 PEX_RX8
PEX_RX8_N
AR22
AT22 PEX_TX9
PEX_TX9_N
AW22
AY22 PEX_RX9
PEX_RX9_N
AN23
AP23 PEX_TX10
PEX_TX10_N
AV23
AW23 PEX_RX10
PEX_RX10_N
AR24
AT24 PEX_TX11
PEX_TX11_N
3 AW24 3
AY24 PEX_RX11
PEX_RX11_N
AN25
AP25 PEX_TX12
PEX_TX12_N
AV25
AW25 PEX_RX12
PEX_RX12_N
AR26
AT26 PEX_TX13
PEX_TX13_N
AW26
AY26 PEX_RX13
PEX_RX13_N
AN27
AP27 PEX_TX14
PEX_TX14_N
AV27
AW27 PEX_RX14
PEX_RX14_N AU29
AR28 PEX_CVDD_SENSE
AT28 PEX_TX15
PEX_TX15_N
AW28 AW29 PEX_TERMP 1 2
AY28 PEX_RX15 PEX_TERMP RG103 2.49K_0201_1%
PEX_RX15_N
@ QN20-P1_FCBGA1358~D
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NV(1/8) PCI EXPRESS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K662P
Date: Wednesday, April 21, 2021 Sheet 26 of 121
A B C D E
A B C D E
UG1K
5/17 IFPAB
DVI DP
SL/DL
1 AV1 1
TXC/TXC IFPA_L3_N
TXC/TXC
AV2
2 1 IFPAB_RSET AP9 IFPA_L3
RG64 1K_0201_1% IFPAB_RSET
TXD0/0
AW3
IFPA_L2_N AY3
TXD0/0 IFPA_L2
+IFP_PLLVDD
16 mils AN9
IFPAB_PLLVDD AV5
TXD1/1 IFPA_L1_N
TXD1/1 AW5
IFPA_L1
1U_0201_6.3VAM
1
CG307
TXD2/2
AY5
IFPA_L0_N AY6
TXD2/2 IFPA_L0
2
AJ6
IFPA_AUX_SDA_N AK6
IFPA_AUX_SCL
IFPAB
TXC
AW9
Under GPU TXC
IFPB_L3_N
IFPB_L3
AV9
TXD0/3
AV8
IFPB_L2_N AW8
TXD0/3 IFPB_L2
TXD1/4 AW6
IFPB_L1_N AV6
TXD1/4 IFPB_L1
TXD2/5
AY8
IFPB_L0_N AY9
TXD2/5 IFPB_L0
AK7
AL15 IFPB_AUX_SDA_N AJ7
+PEX_VDD IFP_IOVDD_5 IFPB_AUX_SCL
AL16
IFP_IOVDD_6
4.7U_0402_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
AM11
AM12 IFP_IOVDD_7
1 1 1 1 IFP_IOVDD_8
CG308
CG309
CG310
CG311
@ QN20-P1_FCBGA1358~D
2 2 2 2
2
Near GPU 2
1U_0201_6.3VAM
+IFP_PLLVDD AN8 TXC
AM5 CG8635 AJ1
IFPCD_PLLVDD IFPC_L3 GPU_HDMI_CLKP <40> TXC IFPE_L3_N
RF@ 1 TXC
AJ2
IFPE_L3
CG319
TXD0 AN5 10P_0402_50V8J
GPU_HDMI_TX_N0 <40>
2
IFPC_L2_N
1U_0201_6.3VAM
AR6
TXD1 IFPC_L1_N GPU_HDMI_TX_N1 <40>
TXD1
AR5 AM3
2
TXD2
IFPC_L1
IFPC_L0_N
AT5
AT6
GPU_HDMI_TX_P1
GPU_HDMI_TX_N2
<40>
<40>
Under GPU TXD1
TXD1
IFPE_L1_N
IFPE_L1
AM2
AM1
TXD2 IFPC_L0 GPU_HDMI_TX_P2 <40> TXD2 IFPE_L0_N
TXD2 AN1
IFPE_L0
+PEX_VDD AL11
AL13 AL12 IFP_IOVDD_1
+PEX_VDD IFP_IOVDD_3 IFP_IOVDD_2
1U_0201_6.3VAM
1U_0201_6.3VAM
AL14
IFP_IOVDD_4
4.7U_0402_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1 1
CG8432
CG320
1 1 1 1 @ QN20-P1_FCBGA1358~D
CG313
CG314
CG8433
CG316
@ QN20-P1_FCBGA1358~D
2 2
2 2 2 2
UG1M
Near GPU 7/17 IFPD
Under GPU
3
C, D share the filter Under GPU 3
HDMI DP
AJ5
IFPD_AUX_SDA_N AK5
IFPD_AUX_SCL
TXC
AN2
IFPD TXC
IFPD_L3_N
IFPD_L3
AN3
AR3
TXD0 IFPD_L2_N AR2
TXD0 IFPD_L2
TXD1
AR1
IFPD_L1_N AT1
TXD1 IFPD_L1
AT2
TXD2 IFPD_L0_N AT3
TXD2 IFPD_L0
+PEX_VDD AM14
AN12 IFP_IOVDD_9
IFP_IOVDD_10
4.7U_0402_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1 1 1 1
CG8435
CG317
CG8434
CG318
@ QN20-P1_FCBGA1358~D
2 2 2 2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NV(2/8) IFP_ABCDEF
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K662P
Date: Wednesday, April 21, 2021 Sheet 27 of 121
A B C D E
A B C D E
UG1B UG1C
2/17 FBA 3/17 FBB
1 1
1U_0201_6.3VAM
FBA_D2 P34 FBB_D2 J8
FBA_D3 N37 FBA_D2 16 mils 1 FBB_D3 E11 FBB_D2
FBA_D3 FBB_D3
CG8431
FBA_D4 R32 FBB_D4 G11
FBA_D5 U33 FBA_D4 FBB_D5 F7 FBB_D4
FBA_D6 U35 FBA_D5 FBB_D6 H10 FBB_D5
FBA_D7 U37 FBA_D6 2 FBB_D7 E6 FBB_D6
FBA_D8 E38 FBA_D7 FBB_D8 J4 FBB_D7
FBA_D9 J36 FBA_D8 FBB_D9 D4 FBB_D8
FBA_D10 L35 FBA_D9 FBB_D10 F5 FBB_D9
FBA_D11 J34 FBA_D10 FBB_D11 G2 FBB_D10
FBA_D12
FBA_D13
FBA_D14
F37
N33
K37
FBA_D11
FBA_D12
FBA_D13
Under GPU FBB_D12
FBB_D13
FBB_D14
H7
J2
J6
FBB_D11
FBB_D12
FBB_D13
FBA_D15 FBA_D14 FBA_CMD0 FBA_CMD[0..24] <35> FBB_D15 FBB_D14 FBB_CMD0 FBB_CMD[0..24] <35>
E36 Y36 H1 D14
FBA_D16 J40 FBA_D15 FBA_CMD0 AA39 FBA_CMD1 FBB_D16 A5 FBB_D15 FBB_CMD0 A17 FBB_CMD1
FBA_D17 D40 FBA_D16 FBA_CMD1 AA32 FBA_CMD2 FBB_D17 E1 FBB_D16 FBB_CMD1 J15 FBB_CMD2
FBA_D18 E37 FBA_D17 FBA_CMD2 AC34 FBA_CMD3 FBB_D18 D2 FBB_D17 FBB_CMD2 E17 FBB_CMD3
FBA_D19 J38 FBA_D18 FBA_CMD3 AA33 FBA_CMD4 FBB_D19 F2 FBB_D18 FBB_CMD3 H15 FBB_CMD4
FBA_D20 C39 FBA_D19 FBA_CMD4 Y37 FBA_CMD5 FBB_D20 C5 FBB_D19 FBB_CMD4 D17 FBB_CMD5
FBA_D21 C40 FBA_D20 FBA_CMD5 Y35 FBA_CMD6 FBB_D21 F1 FBB_D20 FBB_CMD5 E14 FBB_CMD6
FBA_D22 H40 FBA_D21 FBA_CMD6 AA35 FBA_CMD7 FBB_D22 B4 FBB_D21 FBB_CMD6 G15 FBB_CMD7
FBA_D23 G39 FBA_D22 FBA_CMD7 Y39 FBA_CMD8 FBB_D23 A3 FBB_D22 FBB_CMD7 A15 FBB_CMD8
FBA_D24 U38 FBA_D23 FBA_CMD8 V40 FBA_CMD9 FBB_D24 A6 FBB_D23 FBB_CMD8 B14 FBB_CMD9
FBA_D25 K39 FBA_D24 FBA_CMD9 Y40 FBA_CMD10 FBB_D25 A12 FBB_D24 FBB_CMD9 B15 FBB_CMD10
FBA_D26 R38 FBA_D25 FBA_CMD10 Y38 FBA_CMD11 FBB_D26 C8 FBB_D25 FBB_CMD10 A14 FBB_CMD11
FBA_D27 T39 FBA_D26 FBA_CMD11 W37 FBA_CMD12 FBB_D27 A11 FBB_D26 FBB_CMD11 F17 FBB_CMD12
FBA_D28 L38 FBA_D27 FBA_CMD12 AA40 FBA_CMD13 FBB_D28 B7 FBB_D27 FBB_CMD12 B17 FBB_CMD13
FBA_D29 L40 FBA_D28 FBA_CMD13 AA38 FBA_CMD14 FBB_D29 B12 FBB_D28 FBB_CMD13 D15 FBB_CMD14
FBA_D30 M40 FBA_D29 FBA_CMD14 V38 FBA_CMD15 FBB_D30 D12 FBB_D29 FBB_CMD14 C15 FBB_CMD15
FBA_D31 U40 FBA_D30 FBA_CMD15 V39 FBA_CMD16 FBB_D31 A8 FBB_D30 FBB_CMD15 C14 FBB_CMD16
FBA_D32 AN32 FBA_D31 FBA_CMD16 AA37 FBA_CMD17 FBB_D32 D28 FBB_D31 FBB_CMD16 E15 FBB_CMD17
FBA_D33 AP35 FBA_D32 FBA_CMD17 AC38 FBA_CMD18 FBB_D33 F28 FBB_D32 FBB_CMD17 C17 FBB_CMD18
FBA_D34 AR36 FBA_D33 FBA_CMD18 AC33 FBA_CMD19 FBB_D34 D24 FBB_D33 FBB_CMD18 J17 FBB_CMD19
FBA_D35 AM34 FBA_D34 FBA_CMD19 AC36 FBA_CMD20 FBB_D35 J26 FBB_D34 FBB_CMD19 D18 FBB_CMD20
FBA_D36 AJ33 FBA_D35 FBA_CMD20 Y33 FBA_CMD21 FBB_D36 G27 FBB_D35 FBB_CMD20 J14 FBB_CMD21
FBA_D37 AL33 FBA_D36 FBA_CMD21 Y32 FBA_CMD22 FBB_D37 H24 FBB_D36 FBB_CMD21 H14 FBB_CMD22
FBA_D38 AK34 FBA_D37 FBA_CMD22 AC32 FBA_CMD23 FBB_D38 F24 FBB_D37 FBB_CMD22 H17 FBB_CMD23
FBA_D39 AK36 FBA_D38 FBA_CMD23 AC39 FBA_CMD24 FBB_D39 C29 FBB_D38 FBB_CMD23 A18 FBB_CMD24
FBA_D40 AW34 FBA_D39 FBA_CMD24 V34 FBB_D40 D35 FBB_D39 FBB_CMD24 F13
FBA_D41 AP33 FBA_D40 FBA_CMD25_NC V36 FBB_D41 E32 FBB_D40 FBB_CMD25_NC G14
FBA_D42 AT35 FBA_D41 FBA_CMD26_NC V32 FBA_CMD27 FBB_D42 F30 FBB_D41 FBB_CMD26_NC H13 FBB_CMD27
FBA_D43 FBA_D42 FBA_CMD27 FBA_CMD28 FBA_CMD[28..52] <35> FBB_D43 FBB_D42 FBB_CMD27 FBB_CMD28 FBB_CMD[28..52] <35>
AU37 AD35 G32 E18
FBA_D44 AY33 FBA_D43 FBA_CMD28 AG38 FBA_CMD29 FBB_D44 H28 FBB_D43 FBB_CMD28 A23 FBB_CMD29
FBA_D45 AR32 FBA_D44 FBA_CMD29 AD32 FBA_CMD30 FBB_D45 C36 FBB_D44 FBB_CMD29 J18 FBB_CMD30
FBA_D46 AU32 FBA_D45 FBA_CMD30 AG37 FBA_CMD31 FBB_D46 D37 FBB_D45 FBB_CMD30 F20 FBB_CMD31
FBA_D47 AW32 FBA_D46 FBA_CMD31 AD33 FBA_CMD32 FBB_D47 D31 FBB_D46 FBB_CMD31 H18 FBB_CMD32
FBA_D48 AY36 FBA_D47 FBA_CMD32 AD37 FBA_CMD33 FBB_D48 A33 FBB_D47 FBB_CMD32 B20 FBB_CMD33
FBA_D49 AW35 FBA_D48 FBA_CMD33 AD36 FBA_CMD34 FBB_D49 B39 FBB_D48 FBB_CMD33 G18 FBB_CMD34
FBA_D50 AW37 FBA_D49 FBA_CMD34 AC37 FBA_CMD35 FBB_D50 B37 FBB_D49 FBB_CMD34 D22 FBB_CMD35
FBA_D51 AU39 FBA_D50 FBA_CMD35 AD40 FBA_CMD36 FBB_D51 B34 FBB_D50 FBB_CMD35 A20 FBB_CMD36
FBA_D52 AY35 FBA_D51 FBA_CMD36 AG33 FBA_CMD37 FBB_D52 A38 FBB_D51 FBB_CMD36 E21 FBB_CMD37
FBA_D53 AT38 FBA_D52 FBA_CMD37 AF33 FBA_CMD38 FBB_D53 A32 FBB_D52 FBB_CMD37 F21 FBB_CMD38
FBA_D54 AT40 FBA_D53 FBA_CMD38 AC40 FBA_CMD39 FBB_D54 B38 FBB_D53 FBB_CMD38 A21 FBB_CMD39
FBA_D55 AV40 FBA_D54 FBA_CMD39 AF34 FBA_CMD40 FBB_D55 C32 FBB_D54 FBB_CMD39 D21 FBB_CMD40
FBA_D56 AR40 FBA_D55 FBA_CMD40 AG39 FBA_CMD41 FBB_D56 B25 FBB_D55 FBB_CMD40 B23 FBB_CMD41
FBA_D57 AJ39 FBA_D56 FBA_CMD41 AF38 FBA_CMD42 FBB_D57 C26 FBB_D56 FBB_CMD41 C21 FBB_CMD42
FBA_D58 AP39 FBA_D57 FBA_CMD42 AF37 FBA_CMD43 FBB_D58 A30 FBB_D57 FBB_CMD42 C20 FBB_CMD43
FBA_D59 AK40 FBA_D58 FBA_CMD43 AG40 FBA_CMD44 FBB_D59 C24 FBB_D58 FBB_CMD43 C23 FBB_CMD44
FBA_D60 AJ37 FBA_D59 FBA_CMD44 AD38 FBA_CMD45 FBB_D60 A24 FBB_D59 FBB_CMD44 C18 FBB_CMD45
FBA_D61 AJ40 FBA_D60 FBA_CMD45 AF39 FBA_CMD46 FBB_D61 C30 FBB_D60 FBB_CMD45 B18 FBB_CMD46
FBA_D62 AN38 FBA_D61 FBA_CMD46 AF36 FBA_CMD47 FBB_D62 A29 FBB_D61 FBB_CMD46 H20 FBB_CMD47
FBA_D63 AN40 FBA_D62 FBA_CMD47 AF32 FBA_CMD48 FBB_D63 B31 FBB_D62 FBB_CMD47 J20 FBB_CMD48
FBA_D63 FBA_CMD48 AG32 FBA_CMD49 FBB_D63 FBB_CMD48 J21 FBB_CMD49
FBA_CMD49 AF40 FBA_CMD50 FBB_CMD49 B21 FBB_CMD50
<35> FBA_DBI[0..7] FBA_DBI0 FBA_CMD50 FBA_CMD51 <35> FBB_DBI[0..7] FBB_DBI0 FBB_CMD50 FBB_CMD51
R35 AG36 F10 H21
FBA_DBI1 L33 FBA_DQM0 FBA_CMD51 AD39 FBA_CMD52 FBB_DBI1 G4 FBB_DQM0 FBB_CMD51 D20 FBB_CMD52
FBA_DBI2 F38 FBA_DQM1 FBA_CMD52 AH35 FBB_DBI2 C3 FBB_DQM1 FBB_CMD52 G23
FBA_DBI3 P40 FBA_DQM2 FBA_CMD53_NC AG34 FBB_DBI3 B10 FBB_DQM2 FBB_CMD53_NC E23
FBA_DBI4 AL35 FBA_DQM3 FBA_CMD54_NC AH33 FBA_CMD55 FBB_DBI4 F26 FBB_DQM3 FBB_CMD54_NC J23 FBB_CMD55
FBA_DBI5 AU34 FBA_DQM4 FBA_CMD55 FBB_DBI5 H30 FBB_DQM4 FBB_CMD55
FBA_DBI6 AV38 FBA_DQM5 FBB_DBI6 C35 FBB_DQM5
FBA_DBI7 AL39 FBA_DQM6 FBB_DBI7 A27 FBB_DQM6
FBA_DQM7 FBB_DQM7
P38 E8
FBA_WCK01 FBA_WCK01 <35> FBB_WCK01 FBB_WCK01 <35>
P39 D8
FBA_WCK01_N FBA_WCK01# <35> FBB_WCK01_N FBB_WCK01# <35>
E39 B2
FBA_WCK23 FBA_WCK23 <35> FBB_WCK23 FBB_WCK23 <35>
E40 B3
FBA_WCK23_N FBA_WCK23# <35> FBB_WCK23_N FBB_WCK23# <35>
AN36 C27
FBA_WCK45 FBA_WCK45 <35> FBB_WCK45 FBB_WCK45 <35>
AN37 B27
FBA_WCK45_N FBA_WCK45# <35> FBB_WCK45_N FBB_WCK45# <35>
AW39 B36
FBA_WCK67 FBA_WCK67 <35> FBB_WCK67 FBB_WCK67 <35>
AV39 A36
FBA_WCK67_N FBA_WCK67# <35> FBB_WCK67_N FBB_WCK67# <35>
H37 F3
FBA_WCKB01 FBA_WCKB01 <35> FBB_WCKB01 FBB_WCKB01 <35>
H38 E3
FBA_WCKB01_N FBA_WCKB01# <35> FBB_WCKB01_N FBB_WCKB01# <35>
N40 A9
FBA_WCKB23 FBA_WCKB23 <35> FBB_WCKB23 FBB_WCKB23 <35>
N39 B9
FBA_WCKB23_N FBA_WCKB23# <35> FBB_WCKB23_N FBB_WCKB23# <35>
AV35 D33
FBA_WCKB45 FBA_WCKB45 <35> FBB_WCKB45 FBB_WCKB45 <35>
AV36 C33
FBA_WCKB45_N FBA_WCKB45# <35> FBB_WCKB45_N FBB_WCKB45# <35>
AM40 A28
FBA_WCKB67 FBA_WCKB67 <35> FBB_WCKB67 FBB_WCKB67 <35>
AM39 B28
FBA_WCKB67_N FBA_WCKB67# <35> FBB_WCKB67_N FBB_WCKB67# <35>
FB_VREF F35 R31 K13
FB_VREF FB_PLLVDD_3 +FB_PLLVDD FB_PLLVDD_1 +FB_PLLVDD
RG59
1U_0201_6.3VAM
1U_0201_6.3VAM
16 mils 16 mils
2.49K_0402_1%
RG59
3.9P_0402_50V8C
@ QN20-P1_FCBGA1358~D 1 @ QN20-P1_FCBGA1358~D 1
1
CG287
CG290
1
CG293
2 2
GN20P@
49.9_0402_1% 2
N18P@
2
SD034499A80
+1V8_MAIN
Near GPU +FB_PLLVDD
LG2
1 2
22U_0603_6.3VAM
4.7U_0402_6.3VAM
4.7U_0402_6.3VAM
50 mils PBY160808T-300Y-N_2P
1 1 1
CG285
CG286
CG8430
2 2 2
+FBVDDQ +FBVDDQ
+FBVDDQ +FBVDDQ
1
1
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
1
1
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
RG38
RG39
RG40
RG41
RG32
RG33
RG34
RG35
3 FBB_CMD14 FBB_CMD17 3
CKE_A CKE_B
2
FBA_CMD14 FBA_CMD17
+FBVDDQ
+FBVDDQ
FBB_CMD3
FBA_CMD3
Reset Debug
10K_0402_1%
10K_0402_1%
FBB_CMD31
Debug
1
1
10K_0402_1%
10K_0402_1%
RG1527 @
RG1528 @
FBA_CMD31
Reset
1
1
RG1525 @
RG1526 @
10K_0201_5%
10K_0201_5%
1
1
10K_0201_5%
10K_0201_5%
RG42
RG43
RG36
RG37
FBB_CMD27
2
FBA_CMD27
2
FBB_CMD55
FBA_CMD55
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NV(3/8) MEMORY_FB_ABCD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K662P
Date: Wednesday, April 21, 2021 Sheet 28 of 121
A B C D E
A B C D E
DGPU_PEX_RST#
DGPU_PEX_RST# <26,40> +1V8_AON
UG1O +1V8_AON
10/17 MISC1 QG6A
5
LBSS139DW1T1G_SOT363-6
N18_N20_NVVDD_EN RG115 1 2 10K_0201_5%
G
U1 VGA_SMB_CK2 RG106 1 2 2.2K_0201_5% VGA_SMB_CK2 4 3
I2CS_SCL VGA_SMB_DA2 EC_SMB_CK2 <8,58,64,68,77>
D
V1 RG107 1 2 2.2K_0201_5% FRAME_LOCK# RG116 1 2 10K_0201_5%
I2CS_SDA
2
THERM_OVERT# P1
OVERT U2 I2CC_SCL RG108 1 2 2.2K_0201_5% THERM_ALERT# RG117 1 2 10K_0201_5%
G
AP8 I2CC_SCL V2 I2CC_SDA RG109 1 2 2.2K_0201_5% VGA_SMB_DA2 1 6
TS_VREF I2CC_SDA I2CC for OVRM EC_SMB_DA2 <8,58,64,68,77>
D
GPU_PWR_LEVEL_R RG119 1 2 10K_0201_5%
M2 U3 I2CB_SCL RG110 1 2 2.2K_0201_5% QG6B LBSS139DW1T1G_SOT363-6
1 THERMDN I2CB_SCL V3 I2CB_SDA RG111 1 2 2.2K_0201_5% ADC_MUX_SEL RG120 1 2 2.2K_0201_5% 1
M1 I2CB_SDA I2CB for DDS
THERMDP
P3 DGPU_PEX_RST#
GPIO0 NVVDD_PWM_VID <103>
P7 GC6_FB_EN
GPIO1 GC6_FB_EN <34>
R4
@ T76 PAD~D GPU_JTAG_TCK AY11 GPIO2 U6 QG7A
JTAG_TCK GPIO3
5
@ T77 PAD~D GPU_JTAG_TMS AV11 U7 N18_N20_NVVDD_EN RG1530 1 N18P@ 2 0_0402_1% LBSS139DW1T1G_SOT363-6
JTAG_TMS GPIO4 1V8_MAIN_EN <34,37>
@ T78 PAD~D GPU_JTAG_TDI AW11 V4 FRAME_LOCK# GC6_FB_EN RG113 1 2 10K_0201_5%
G
@ T79 PAD~D GPU_JTAG_TDO AW12 JTAG_TDI GPIO5 R7 GPU_NVVDD_PSI# I2CC_SCL 4 3
GPU_JTAG_TRST# JTAG_TDO GPIO6 SCL_GPU <34,103>
D
@ T80 AV12 M6 MEM_VREF_CTL RG118 1 2 100K_0201_5%
JTAG_TRST_N GPIO7
2
PAD~D @ T81 AY12 L8
NVJTAG_SEL GPIO8 MEM_VDD_CTL <108>
PAD~D M7 THERM_ALERT# Level FBVDD
G
Y3 GPIO9 L5 MEM_VREF_CTL I2CC_SDA 1 6
<34> ADC_IN_P ADC_IN GPIO10 MEM_VREF_CTL <35> SDA_GPU <34,103>
1
D
Y4 R8 MEM_VDD_CTL H 1.35V/1.25V
<34> ADC_IN_N ADC_IN_N GPIO11
RG105 M3 GPU_PWR_LEVEL_R 2 1 DG5 QG7B LBSS139DW1T1G_SOT363-6
10K_0201_5% External current sense for power monitoring
GPIO12
GPIO13
P6
GPU_PWR_LEVEL <58> L 1.25V/1.2V GPU To PWR PSI
1
P5 RB751S-40_SOD523-2-X
RG104 GPIO14 P2
2
GPIO18
1
R3
GPIO19 R5 RG139
GPIO20
1
R2 100K_0201_5%
GPIO21 M5 ADC_MUX_SEL RG140
GPIO22 ADC_MUX_SEL <34>
U5 10K_0201_5%
2
GPIO23 L7
GPIO24 R6 GPU_FBVDD_PSI#
GC6_FB_EN3V3 <9>
2
GPIO25 M4
GPIO26 GPU_ROM_WP# <30,32>
R1 GPU_NVVDD_PSI# 1 2
GPIO27 GPU_IFPC_HPD# <40> NVVDD_PSI# <103>
M8 RG143 0_0201_1%
RFU_GPIO28
3
Pin Name Default Function P8
RFU_GPIO29 P9 GC6_FB_EN 5 G
D
QG9A
JTAG_TRST L JTAG module will drive signal. RFU_GPIO30 R9
RFU_GPIO31
S
LBSS139DW1T1G_SOT363-6
1
GPU side need to pull low as default
U9
4
RFU_GPIO32 V9 RG141
NVJTAG_SEL L Test Mode --> Disable RFU_GPIO33 U10
RFU_GPIO34 10K_0201_5%
V10
RFU_GPIO35
2
H Test Mode --> Enable @ QN20-P1_FCBGA1358~D
BSS138W_SOT-323-3-X
D
3 1 QG21
NVVDD_PGOOD <9,26,29,34,103,110>
G
2
+1V8_AON
6
D
2 2 G QG9B 2
S
LBSS139DW1T1G_SOT363-6
DVT1 modify GC6 seq follow E board
1
RG145
20K_0201_5%
2
GPU_FBVDD_PSI# 1 2
+1V8_AON PSI_FBVDDQ <108>
RG148 0_0201_1%
1
RG204 RG146
VCC
PG_0.95VS_VGAP 1 100K_0201_1% 10K_0201_5%
IN B 4 1 2
2 OUT Y
GND
2
IN A
1
CD60
UG12 0.1U_0402_10V7K
3
NL17SZ08EDFT2G_SOT353-5
2
+1V8_AON
7/29 EVT modify
DG4 GN20P@
1
RB751S-40_SOD523-2-X
RG1708
RG153
10K_0201_5% 2 1 1 GN20P@2 3V3_SYS_EN
3V3_SYS_EN <34,37>
DG3 N18P@
RB751S-40_SOD523-2-X
2
4.99K_0201_1%
THERM_OVERT# 1 2 N18_N20_NVVDD_EN 2 1 NVVDD_EN
NVVDD_EN <34,103,110>
DG2
+1V8_AON +1V8_AON RB751S-40_SOD523-2-X
1 GN20P@2
CG429
RG150 10K_0201_5% CG428
1 2 1
1
CG428
RG154 GN20P@
3 0.1U_0201_10V6K +3VS 0.1U_0201_10V6K 3
10K_0201_5%
5
2
2200P_0201_25V7K
VCC
2
3
S
DGPU_PEX_RST# 1 N18P@
IN B
1
G
4 2 QG13 SE00000WL00
2 OUT Y RG155
BSS138W_SOT-323-3-X
GND
IN A D RG150
10K_0201_5%
1
UG8
D
2
1
NL17SZ08EDFT2G_SOT353-5
GC6_FB_EN 2 QG12
G BSS138W_SOT-323-3-X THERM_OVERT#_R <87>
S 100K_0201_5%
3
N18P@
SD043100380
+1V8_AON
For N18P 1V8_MAIN EN to NVVDD_EN RC delay
1
CG430
0.1U_0201_10V6K
2
5
1 VCC Jason0720 Note-Viper-MLK +1V8_AON
B 4 Reserve for PEXVDD quick power down CG460
Y FBVDD/Q_EN <34,108>
PG_0.95VS_VGAP 2 A 0.1U_0201_10V6K
<110> PG_0.95VS_VGAP G UG9 1 2
1
74LVC1G32GW_TSSOP5
5
RG156
10K_0201_5% RG258
VCC
NVVDD_PGOOD 1 0_0201_1%
<9,26,29,34,103,110> NVVDD_PGOOD IN B 4 PEX_VDD_ENP_R 1 2
PEX_VDD_ENP <34,110>
2
1 2 2 OUT Y
GND
<9,37> DGPU_PWR_EN IN A
RG257 1
0_0201_1% 1 CG461
UG101 0.22U_0201_6.3VAM
3
CG459 NL17SZ08EDFT2G_SOT353-5 @
2200P_0201_25V7K 2
@ 2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NV(4/8) GPIO
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K662P
Date: Wednesday, April 21, 2021 Sheet 29 of 121
A B C D E
5 4 3 2 1
+1V8_AON
+1V8_AON
RG92 1 2 10K_0201_5% GPU_ROM_WP#_R VBIOS ROM
RAMCFG UG1P
+1V8_AON
RG250 1
N18P@
GN20P@
2 10K_0201_5%
RG81 HYNIX@
12/17 MISC2
ref. P.164 DG-09845-001_v02 +1V8_AON +1V8_AON
(reserved 10K pull down)
1
100K_0201_5%
RG80
100K_0201_5%
RG82
100K_0201_5%
RG84
100K_0201_5%
RG86
100K_0201_5%
RG88
100K_0201_5%
RG90
100K_0201_5%
RG74
10K_0201_5%
RG76
100K_0201_5%
RG78 GN20P@
@
1
MIC@ HYNIX@ @ Y8 GPU_ROM_CS# @ @
@ ROM_CS_N RG94 1
2
D 100K_0201_5% Y7 GPU_ROM_SI 10K_0201_5% D
ROM_SI Y9 GPU_ROM_SO CG328
SD043100380 STRAP0 V5 ROM_SO Y10 GPU_ROM_SCLK 0.1U_0201_10V6K
2
STRAP1 V8 STRAP0 ROM_SCLK 2
STRAP2 Y5 STRAP1 UG10
STRAP3 V7 STRAP2 GPU_ROM_CS#RG95 1 2 33_0201_5% GPU_ROM_CS#_R 1 8
STRAP3 CS# VCC
1
100K_0201_5%
RG75
10K_0201_5%
RG77
100K_0201_5%
RG79 N18P@
STRAP4 U8 GPU_ROM_SO RG96 1 2 0_0201_1% GPU_ROM_SO_R 2 7
STRAP5 V6 STRAP4 RG1518 1 2 0_0201_1% GPU_ROM_WP#_R 3 DO(IO1) HOLD#(IO3) 6 GPU_ROM_SCLK_R RG97 1 EMI@ 2 33_0201_5% GPU_ROM_SCLK
STRAP5 <29,32> GPU_ROM_WP# WP#(IO2) CLK
RG83 MIC@ GN20P@ 4 5 GPU_ROM_SI_R RG98 1 2 33_0201_5% GPU_ROM_SI
GND DI(IO0)
1
1
100K_0201_5%
RG81
100K_0201_5%
RG83
100K_0201_5%
RG85
100K_0201_5%
RG87
100K_0201_5%
RG89
100K_0201_5%
RG91
W25Q16JWSSIQ_SO8
2
SA0000DHJ00 GN20P@
2
SAM@ SAM@ @ UG10 RG1711
100K_0201_5% 33_0201_5%
2
2
@EMI@
SD043100380
1
1
@ QN20-P1_FCBGA1358~D
teknisi-indonesia.com
C C
B B
4.7U_0402_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
CG303
CG304
CG8436
1U_0201_6.3VAM
CG306
XTALIN_R L2 L1 XTALOUT_R
XTAL_IN XTAL_OUT RG70 L M L 1 0 0 1
1
@ QN20-P1_FCBGA1358~D 100K_0201_5%
RG71 RG72 N18P@
EMI@ EMI@ L L M 1 0 0 0
2
10K_0201_5%
10K_0201_5%
0_0201_1% 0_0201_1%
1
H H H 0 1 1 1
2
2
RG67
RG68
RG73 @
10M_0201_5%
1 2
H H L 0 1 1 0
2
YG1
18P_0201_50V8J
1
27MHZ_10PF_XRCGB27M000F2P18R0 H L H 0 1 0 1
CG325
XTALIN 1 3 XTALOUT
1
1 3
1
H L L 0 1 0 0
2 NC1 NC2
CG326 CG327
10P_0201_25V8
2 4
10P_0201_25V8 L H H 0 0 1 1
2 2
A L H L 0 0 1 0 A
L L H 0 0 0 1 Default
L L L 0 0 0 0
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NV(4/8) STRAP, ROM, XTAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K662P
Date: Wednesday, April 21, 2021 Sheet 30 of 121
5 4 3 2 1
5 4 3 2 1
UG1D UG1E
15/17 GND_1/2 16/17 GND_2/2
@ QN20-P1_FCBGA1358~D
@ QN20-P1_FCBGA1358~D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NV(6/8) GND, RFUs
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K662P
Date: Wednesday, April 21, 2021 Sheet 31 of 121
5 4 3 2 1
5 4 3 2 1
L9
VDD_SENSE NVVDD_VCC_SENSE <103>
L10
GND_SENSE NVVDD_VSS_SENSE <103>
@ QN20-P1_FCBGA1358~D
B B
FUSE_SRC
RG1529 1 GN20P@2 0_0402_1%
UG1I +1V8_AON
+1V8_AON
6
UG5
1
Close Y2 AR8
17/17 1V8 / NC
P10
Under GPU Near GPU
VIN1 VOUT1 +FUSE_SRC NC_1 1V8_1
5 2 AR9 R10
VIN2 VOUT2 NC_2 1V8_2
2.2U_0201_6.3V6M
CG294 N18P@
2.21K_0402_1%
RG63
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
4.7U_0402_6.3VAM
4.7U_0402_6.3VAM
4.7U_0402_6.3VAM
1 AT8
NC_3
1
CG296
CG297
CG298
CG299
CG300
CG301
CG8437
N18P@ AV3
GS7616SC-R_SOT363-6 AW2 NC_5
2.2U_0201_6.3V6M NC_6
2
N18P@
N18P@ Y6
2 NC_7 2 2 2 2 2 2 2 2
2
1 2
<29,30> GPU_ROM_WP#
RG157 N18P@ 0_0201_1%
1
Y2 +FUSE_SRC
RG62 FUSE_SRC
N18P@
10K_0201_5%
2
@ QN20-P1_FCBGA1358~D
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NV(7/8) POWERS
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K662P
Date: Wednesday, April 21, 2021 Sheet 32 of 121
5 4 3 2 1
5 4 3 2 1
FBVDDQ_GPU
Under GPU Near GPU
+FBVDDQ +FBVDDQ
D D
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
10U_0603_6.3VAM
10U_0603_6.3VAM
1 1 1 1 1 1 1 1
CG379
CG380
CG381
CG382
CG383
CG384
CG411
CG412
2 2 2 2 2 2 2 2
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
22U_0603_6.3VAM
22U_0603_6.3VAM
22U_0603_6.3VAM
22U_0603_6.3VAM
22U_0603_6.3VAM
1 1 1 1 1 1 1 1 1 1 1
CG387
CG388
CG389
CG390
CG391
CG392
CG421
CG422
CG423
CG424
CG425
2 2 2 2 2 2 2 2 2 2 2
10U_0603_6.3VAM
10U_0603_6.3VAM
10U_0603_6.3VAM
10U_0603_6.3VAM
1 1 1 1
CG403
CG404
CG405
CG406
2 2 2 2
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NV(8/8) GPU DECOUPLING
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K662P
Date: Wednesday, April 21, 2021 Sheet 33 of 121
5 4 3 2 1
A B C D E
2
RG171 RG170 45492@
NCP45492XMNTWG_QFN32_4X4 0_0402_5% 0_0402_5% RG187 45492@ CG436 475_0402_1%
SA0000CQX00 @ 649_0402_1% 1000P_0402_50V SD034475080
45492@ 2 1 1 2
1
8 mils +3V_OC_PWR 45492@
20mil
1U_0402_25V6K
RG188 45492@ CG437
1
649_0402_1%
CG6802
CSSP_B+ RG172 2 @ 1 100_0402_1% 1000P_0402_50V
<104> CSSP_B+
OVRM Gen2 with GN20P0/P1 GND_FET 2 1 1 2
1 1
CG443 1
2
680P_0402_50V7K UG11 RG189 45492@ CG438
UG11 45495@ 68.1K_0402_1% 0.015U_0402_25V7K
27 3 BS_IN1 2 @ 1 CSSP_B+ 1 2 SH_IN BOM option
RG173 2 VCC BS_IN1 6 BS_IN2 2 @ 1 CSSP_FBVDD
0_0402_5% VIN1P 2 BS_IN2 11 BS_IN3 RG1704 2 1 0_0402_5% 68.1K_0402_1% SH_O1 RG200 1 45492@ 2 475_0402_1% RG172 45495@ RG205 RG174 45495@ RG175 45495@
CSSN_B+ 1 2 VIN1N 1 SH_IN_P1 BS_IN3 14 BS_IN4 RG1705 2 1 0_0402_5% BS_IN1 RG190
<104> CSSN_B+ SH_IN_N1 BS_IN4
CSSP_FBVDD 1 @ 2 1 45492@ 2 VIN2P 5 SH_O2 RG201 1 45495@ 2 0_0402_5%
<104> CSSP_FBVDD SH_IN_P2
NCP45495XMNTWG_QFN32_4X4 RG174 RG205 VIN2N 4
SA0000DUX00 49.9_0402_1% 49.9_0402_1% 1 @ 2 R37 SH_IN 12 SH_IN_N2 9 GND_FET RG191 1 45495@ 2 0_0402_5% 1 2
2 +3V_OC_PWR SH_IN_P3 GND_FET
45495@ CG444 RG1702 0_0402_5% 13
0.47U_0402_50V7K 15 SH_IN_N3 0.015U_0402_25V7K
SH_IN_P4 0_0402_5% 0_0402_5% 49.9_0402_1% 49.9_0402_1%
45495@ CSSP_FBVDD 1 2 R36 16 32 SH_O1 45492@ CG439 SD028000080 SD028000080 SD034499A80 SD034499A80
@ RG175 1 RG1703 0_0402_5% SH_IN_N4 SH_O1 7 SH_O2 45495@
0_0402_5% ADC_IN_P 20 SH_O2 10 SH_O3 @ CG445
CSSN_FBVDD 1 2 ADC_IN_N 19 DIFF_OUT_P SH_O3 17 SH_O4 0.015U_0402_25V7K RG172 45492@ RG174 45492@
<104> CSSN_FBVDD DIFF_OUT_N SH_O4
RG183 1 2
CG434 0_0402_5% BS_OK 30 RG192
+3V_OC_PWR 1 2 ADC_IN_P_RC 1 2 BS_OK 0_0402_5% SH_O3 RG207 1 @ 2 0_0402_5%
RG176 IMON 8 29 ADC_MUX_SEL_R 1 2
10K_0402_5% NC MUX_SEL ADC_MUX_SEL <29>
47P_0402_50V8J BV_REF 18 SH_O4 RG208 1 @ 2 0_0402_5%
<29> ADC_IN_P NC
2 1 BS_OK ADRS0 21 100_0402_1% 49.9_0402_1%
<29> ADC_IN_N NC
CG435 @ PAD~D T318 31 28 1 2 SD034100080 SD034499A80
RG135 1 2 ADC_IN_N_RC 1 2 NC ENABLE RG1693
10K_0402_5% BG_REF_OUT 23 30.1K_0402_1% 0.015U_0402_25V7K
2 1 SKIP 47P_0402_50V8J 0_0402_5% BS_REF 24 BG_REF_OUT 25 SKIP 1 @ 2 @ CG446
RG184 ADRS1 22 BS_REF SKIP BS_REF BOM option BS_IN BOM option
RG206 CM_REF_IN RG196 45495@ RG193 45495@ RG189 45495@ RG190 45495@
10K_0402_5% 33 26 MODE_SEL
GND MODE_SEL
2
2 @ 1 MODE_SEL SH_O2 RG215 1 @ 2 0_0402_5%
IOUT_NVVDD <103>
10K_0402_5% 2
RG212 NCP45492XMNTWG_QFN32_4X4 RG197 CG455
10K_0201_5% 100P_0201_50V8J
1 45495@ 2 ADRS0 SA0000CQX00 @ 10K_0402_5% 31.6K_0402_1% 0_0402_5% 0_0402_5%
7/24 Reserve
1
@ 1 SD028100280 SD034316280 SD028000080 SD028000080
RG209
10K_0402_5%
2 2 @ 1 ADRS1 IMON RG196 45492@ RG193 45492@ RG189 45492@ RG190 45492@ 2
2
RG1706 0_0402_5% 0_0402_5% RG193 RG194 681K_0402_1% 243K_0402_1% 75K_0402_1% 75K_0402_1%
0_0402_5% 45495@ BS_REF 1 45492@ 2 110K_0402_1% 10K_0402_5% SD034681380 SD000004200 SD034750280 SD034750280
1 @ 2 R39 BS_IN4 BG_REF_OUT RG216 1 45495@ 2 0_0402_5% RG177 1 @ 2 2 1
2
1
RG213 SKIP 0_0402_5% 1000P_0402_50V
10K_0201_5% SH_O4 1 45495@ 2 1 2
1 @ 2 ADRS0
RG195 RG196
D
1
RG182 365K_0402_1% 681K_0402_1%
10K_0402_5% 2 QG20 RG1683 2 45492@ 1 2 @ 1
<29> GC6_FB_EN
2 @ 1 MODE_SEL G BSS138W_SOT-323-3-X 0_0402_5%
S @ BG_REF_OUT 1 45492@ 2 CG442
3
1000P_0402_50V
ADRS1 1 2
45492@
+NVVDD +1V8_AON
10mil
10mil
1
1
RG163
+5VALW RG159 +5VALW 10_0402_1%
10K_0201_5%
2
2
1
RG158 RG162
DMN53D0LDW-7 2N SOT363-6
DMN53D0LDW-7 2N SOT363-6
10K_0201_5% 10K_0402_5%
3
3 3
2
2
QG14B
QG16B
5 5
DMN53D0LDW-7 2N SOT363-6
DMN53D0LDW-7 2N SOT363-6
4
4
6
6
QG14A
QG16A
2 1V8_AON_EN 2
<29,103,110> NVVDD_EN <37> 1V8_AON_EN
1
+3V3_SYS
10mil
1
+PEX_VDD +5VALW RG169
+FBVDDQ 10_0402_1%
10mil 10mil +1V8_MAIN
2
1
10 mils
1
DMN53D0LDW-7 2N SOT363-6
1
+5VALW RG161 +5VALW RG165 10K_0402_5%
10_0201_1% 3_0402_5% +5VALW RG167
3
51_0402_5%
QG19B
N18P@
2
2
1
2
1
RG160 RG164 10_0402_1% 5
DMN53D0LDW-7 2N SOT363-6
DMN53D0LDW-7 2N SOT363-6
DMN53D0LDW-7 2N SOT363-6
DMN53D0LDW-7 2N SOT363-6
10K_0201_5%
10K_0201_5%
4
3
3
2
6
QG15B
QG17B
QG18B
QG19A
4 5 5 4
5 3V3_SYS_EN 2
DMN53D0LDW-7 2N SOT363-6
DMN53D0LDW-7 2N SOT363-6
<29,37> 3V3_SYS_EN
DMN53D0LDW-7 2N SOT363-6
4
1
6
6
QG15A
QG17A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
OC, Discharging
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K662P
Date: Wednesday, April 21, 2021 Sheet 34 of 121
A B C D E
A B C D E
@
UM11
@
UM12
C2 B4 @ @
<28> FBA_EDC1 EDC0_A DQ0_A FBA_D9 <28>
C13 A3 UM9 UM10
<28> FBA_EDC0 EDC1_A DQ1_A FBA_D13 <28>
T2 B3 C2 B4
<28> FBA_EDC2 EDC0_B DQ2_A FBA_D10 <28> <28> FBA_EDC4 EDC0_A DQ0_A FBA_D35 <28>
T13 B2 C13 A3
<28> FBA_EDC3 EDC1_B DQ3_A FBA_D14 <28> <28> FBA_EDC5 EDC1_A DQ1_A FBA_D34 <28>
E3 T2 B3 C2 B4 C2 B4
DQ4_A FBA_D12 <28> <28> FBA_EDC7 EDC0_B DQ2_A FBA_D33 <28> <28> FBB_EDC1 EDC0_A DQ0_A FBB_D11 <28> <28> FBB_EDC4 EDC0_A DQ0_A FBB_D38 <28>
E2 T13 B2 C13 A3 C13 A3
DQ5_A FBA_D15 <28> <28> FBA_EDC6 EDC1_B DQ3_A FBA_D32 <28> <28> FBB_EDC0 EDC1_A DQ1_A FBB_D13 <28> <28> FBB_EDC5 EDC1_A DQ1_A FBB_D35 <28>
D2 F2 E3 T2 B3 T2 B3
1 <28> FBA_DBI1 DBI0#_A DQ6_A FBA_D8 <28> DQ4_A FBA_D39 <28> <28> FBB_EDC2 EDC0_B DQ2_A FBB_D15 <28> <28> FBB_EDC7 EDC0_B DQ2_A FBB_D37 <28>
D13 G2 E2 T13 B2 T13 B2 1
<28> FBA_DBI0 DBI1#_A DQ7_A FBA_D11 <28> DQ5_A FBA_D37 <28> <28> FBB_EDC3 EDC1_B DQ3_A FBB_D8 <28> <28> FBB_EDC6 EDC1_B DQ3_A FBB_D34 <28>
R2 B11 D2 F2 E3 E3
<28> FBA_DBI2 DBI0#_B DQ8_A FBA_D6 <28> <28> FBA_DBI4 DBI0#_A DQ6_A FBA_D38 <28> DQ4_A FBB_D12 <28> DQ4_A FBB_D39 <28>
R13 A12 D13 G2 E2 E2
<28> FBA_DBI3 DBI1#_B DQ9_A FBA_D4 <28> <28> FBA_DBI5 DBI1#_A DQ7_A FBA_D36 <28> DQ5_A FBB_D14 <28> DQ5_A FBB_D36 <28>
B12 R2 B11 D2 F2 D2 F2
DQ10_A FBA_D5 <28> <28> FBA_DBI7 DBI0#_B DQ8_A FBA_D40 <28> <28> FBB_DBI1 DBI0#_A DQ6_A FBB_D9 <28> <28> FBB_DBI4 DBI0#_A DQ6_A FBB_D33 <28>
B13 R13 A12 D13 G2 D13 G2
DQ11_A FBA_D7 <28> <28> FBA_DBI6 DBI1#_B DQ9_A FBA_D47 <28> <28> FBB_DBI0 DBI1#_A DQ7_A FBB_D10 <28> <28> FBB_DBI5 DBI1#_A DQ7_A FBB_D32 <28>
J10 E12 B12 R2 B11 R2 B11
<28> FBA_CLK0 CK_T DQ12_A FBA_D1 <28> DQ10_A FBA_D44 <28> <28> FBB_DBI2 DBI0#_B DQ8_A FBB_D0 <28> <28> FBB_DBI7 DBI0#_B DQ8_A FBB_D41 <28>
K10 E13 B13 R13 A12 R13 A12
<28> FBA_CLK0# CK_C DQ13_A FBA_D2 <28> DQ11_A FBA_D46 <28> <28> FBB_DBI3 DBI1#_B DQ9_A FBB_D7 <28> <28> FBB_DBI6 DBI1#_B DQ9_A FBB_D44 <28>
G10 F13 J10 E12 B12 B12
<28> FBA_CMD14 CKE#_A DQ14_A FBA_D0 <28> <28> FBA_CLK1 CK_T DQ12_A FBA_D41 <28> DQ10_A FBB_D5 <28> DQ10_A FBB_D42 <28>
M10 G13 K10 E13 B13 B13
<28> FBA_CMD17 CKE#_B DQ15_A FBA_D3 <28> <28> FBA_CLK1# CK_C DQ13_A FBA_D45 <28> DQ11_A FBB_D2 <28> DQ11_A FBB_D47 <28>
G10 F13 J10 E12 J10 E12
<28> FBA_CMD44 CKE#_A DQ14_A FBA_D43 <28> <28> FBB_CLK0 CK_T DQ12_A FBB_D3 <28> <28> FBB_CLK1 CK_T DQ12_A FBB_D40 <28>
U4 M10 G13 K10 E13 K10 E13
DQ0_B FBA_D16 <28> <28> FBA_CMD41 CKE#_B DQ15_A FBA_D42 <28> <28> FBB_CLK0# CK_C DQ13_A FBB_D6 <28> <28> FBB_CLK1# CK_C DQ13_A FBB_D46 <28>
V3 G10 F13 G10 F13
DQ1_B FBA_D22 <28> <28> FBB_CMD14 CKE#_A DQ14_A FBB_D4 <28> <28> FBB_CMD44 CKE#_A DQ14_A FBB_D45 <28>
U3 U4 M10 G13 M10 G13
DQ2_B FBA_D23 <28> DQ0_B FBA_D63 <28> <28> FBB_CMD17 CKE#_B DQ15_A FBB_D1 <28> <28> FBB_CMD41 CKE#_B DQ15_A FBB_D43 <28>
J5 U2 V3
<28> FBA_CMD10 CABI#_A DQ3_B FBA_D17 <28> DQ1_B FBA_D61 <28>
K5 P3 U3 U4 U4
<28> FBA_CMD9 CABI#_B DQ4_B FBA_D19 <28> DQ2_B FBA_D60 <28> DQ0_B FBB_D16 <28> DQ0_B FBB_D63 <28>
P2 J5 U2 V3 V3
DQ5_B FBA_D21 <28> <28> FBA_CMD37 CABI#_A DQ3_B FBA_D57 <28> DQ1_B FBB_D22 <28> DQ1_B FBB_D58 <28>
N2 K5 P3 U3 U3
DQ6_B FBA_D20 <28> <28> FBA_CMD38 CABI#_B DQ4_B FBA_D59 <28> DQ2_B FBB_D20 <28> DQ2_B FBB_D61 <28>
M2 P2 J5 U2 J5 U2
DQ7_B FBA_D18 <28> DQ5_B FBA_D62 <28> <28> FBB_CMD10 CABI#_A DQ3_B FBB_D23 <28> <28> FBB_CMD37 CABI#_A DQ3_B FBB_D62 <28>
U11 N2 K5 P3 K5 P3
DQ8_B FBA_D25 <28> DQ6_B FBA_D58 <28> <28> FBB_CMD9 CABI#_B DQ4_B FBB_D17 <28> <28> FBB_CMD38 CABI#_B DQ4_B FBB_D56 <28>
V12 M2 P2 P2
DQ9_B FBA_D29 <28> DQ7_B FBA_D56 <28> DQ5_B FBB_D18 <28> DQ5_B FBB_D57 <28>
RG4 2 1 121_0402_1% J14 U12 U11 N2 N2
ZQ_A DQ10_B FBA_D28 <28> DQ8_B FBA_D54 <28> DQ6_B FBB_D19 <28> DQ6_B FBB_D60 <28>
RG5 2 1 121_0402_1% K14 U13 V12 M2 M2
ZQ_B DQ11_B FBA_D30 <28> DQ9_B FBA_D51 <28> DQ7_B FBB_D21 <28> DQ7_B FBB_D59 <28>
P12 RG6 2 1 121_0402_1% J14 U12 U11 U11
DQ12_B FBA_D27 <28> ZQ_A DQ10_B FBA_D53 <28> DQ8_B FBB_D31 <28> DQ8_B FBB_D53 <28>
P13 RG7 2 1 121_0402_1% K14 U13 V12 V12
DQ13_B FBA_D26 <28> ZQ_B DQ11_B FBA_D55 <28> DQ9_B FBB_D25 <28> DQ9_B FBB_D48 <28>
N13 P12 RG11 2 1 121_0402_1% J14 U12 RG13 2 1 121_0402_1% J14 U12
DQ14_B FBA_D31 <28> DQ12_B FBA_D48 <28> ZQ_A DQ10_B FBB_D30 <28> ZQ_A DQ10_B FBB_D51 <28>
M13 P13 RG12 2 1 121_0402_1% K14 U13 RG14 2 1 121_0402_1% K14 U13
DQ15_B FBA_D24 <28> DQ13_B FBA_D50 <28> ZQ_B DQ11_B FBB_D29 <28> ZQ_B DQ11_B FBB_D50 <28>
N13 P12 P12
DQ14_B FBA_D49 <28> DQ12_B FBB_D27 <28> DQ12_B FBB_D55 <28>
M13 P13 P13
DQ15_B FBA_D52 <28> DQ13_B FBB_D26 <28> DQ13_B FBB_D52 <28>
N5 H3 N13 N13
TCK CA0_A FBA_CMD1 <28> DQ14_B FBB_D28 <28> DQ14_B FBB_D54 <28>
F10 G11 M13 M13
TDI CA1_A FBA_CMD13 <28> DQ15_B FBB_D24 <28> DQ15_B FBB_D49 <28>
N10 G4 N5 H3
TDO CA2_A FBA_CMD12 <28> TCK CA0_A FBA_CMD33 <28>
F5 H12 F10 G11
TMS CA3_A FBA_CMD24 <28> TDI CA1_A FBA_CMD45 <28>
H5 N10 G4 N5 H3 N5 H3
CA4_A FBA_CMD11 <28> TDO CA2_A FBA_CMD35 <28> TCK CA0_A FBB_CMD1 <28> TCK CA0_A FBB_CMD33 <28>
H10 F5 H12 F10 G11 F10 G11
CA5_A FBA_CMD15 <28> TMS CA3_A FBA_CMD46 <28> TDI CA1_A FBB_CMD13 <28> TDI CA1_A FBB_CMD45 <28>
J12 H5 N10 G4 N10 G4
CA6_A FBA_CMD22 <28> CA4_A FBA_CMD36 <28> TDO CA2_A FBB_CMD12 <28> TDO CA2_A FBB_CMD35 <28>
D4 J11 H10 F5 H12 F5 H12
<28> FBA_WCKB01 WCK0_T_A CA7_A FBA_CMD23 <28> CA5_A FBA_CMD43 <28> TMS CA3_A FBB_CMD24 <28> TMS CA3_A FBB_CMD46 <28>
D5 J4 J12 H5 H5
<28> FBA_WCKB01# WCK0_C_A CA8_A FBA_CMD0 <28> CA6_A FBA_CMD48 <28> CA4_A FBB_CMD11 <28> CA4_A FBB_CMD36 <28>
D11 J3 D4 J11 H10 H10
<28> FBA_WCK01 WCK1_T_A CA9_A FBA_CMD2 <28> <28> FBA_WCK45 WCK0_T_A CA7_A FBA_CMD47 <28> CA5_A FBB_CMD15 <28> CA5_A FBB_CMD43 <28>
D10 D5 J4 J12 J12
<28> FBA_WCK01# WCK1_C_A <28> FBA_WCK45# WCK0_C_A CA8_A FBA_CMD34 <28> CA6_A FBB_CMD22 <28> CA6_A FBB_CMD48 <28>
L3 D11 J3 D4 J11 D4 J11
CA0_B FBA_CMD5 <28> <28> FBA_WCKB45 WCK1_T_A CA9_A FBA_CMD32 <28> <28> FBB_WCKB01 WCK0_T_A CA7_A FBB_CMD23 <28> <28> FBB_WCK45 WCK0_T_A CA7_A FBB_CMD47 <28>
M11 D10 D5 J4 D5 J4
CA1_B FBA_CMD18 <28> <28> FBA_WCKB45# WCK1_C_A <28> FBB_WCKB01# WCK0_C_A CA8_A FBB_CMD0 <28> <28> FBB_WCK45# WCK0_C_A CA8_A FBB_CMD34 <28>
R4 M4 L3 D11 J3 D11 J3
<28> FBA_WCK23 WCK0_T_B CA2_B FBA_CMD7 <28> CA0_B FBA_CMD29 <28> <28> FBB_WCK01 WCK1_T_A CA9_A FBB_CMD2 <28> <28> FBB_WCKB45 WCK1_T_A CA9_A FBB_CMD32 <28>
R5 L12 M11 D10 D10
<28> FBA_WCK23# WCK0_C_B CA3_B FBA_CMD20 <28> CA1_B FBA_CMD52 <28> <28> FBB_WCK01# WCK1_C_A <28> FBB_WCKB45# WCK1_C_A
R11 L5 R4 M4 L3 L3
<28> FBA_WCKB23 WCK1_T_B CA4_B FBA_CMD8 <28> <28> FBA_WCKB67 WCK0_T_B CA2_B FBA_CMD40 <28> CA0_B FBB_CMD5 <28> CA0_B FBB_CMD29 <28>
R10 L10 R5 L12 M11 M11
<28> FBA_WCKB23# WCK1_C_B CA5_B FBA_CMD16 <28> <28> FBA_WCKB67# WCK0_C_B CA3_B FBA_CMD50 <28> CA1_B FBB_CMD18 <28> CA1_B FBB_CMD52 <28>
K12 R11 L5 R4 M4 R4 M4
CA6_B FBA_CMD21 <28> <28> FBA_WCK67 WCK1_T_B CA4_B FBA_CMD39 <28> <28> FBB_WCK23 WCK0_T_B CA2_B FBB_CMD7 <28> <28> FBB_WCKB67 WCK0_T_B CA2_B FBB_CMD40 <28>
K11 R10 L10 R5 L12 R5 L12
CA7_B FBA_CMD19 <28> <28> FBA_WCK67# WCK1_C_B CA5_B FBA_CMD42 <28> <28> FBB_WCK23# WCK0_C_B CA3_B FBB_CMD20 <28> <28> FBB_WCKB67# WCK0_C_B CA3_B FBB_CMD50 <28>
K4 K12 R11 L5 R11 L5
CA8_B FBA_CMD6 <28> CA6_B FBA_CMD49 <28> <28> FBB_WCKB23 WCK1_T_B CA4_B FBB_CMD8 <28> <28> FBB_WCK67 WCK1_T_B CA4_B FBB_CMD39 <28>
@ K3 K11 R10 L10 R10 L10
+FBA_VREFC CA9_B FBA_CMD4 <28> CA7_B FBA_CMD51 <28> <28> FBB_WCKB23# WCK1_C_B CA5_B FBB_CMD16 <28> <28> FBB_WCK67# WCK1_C_B CA5_B FBB_CMD42 <28>
2 1 K1 K4 K12 K12
VREFC CA8_B FBA_CMD28 <28> CA6_B FBB_CMD21 <28> CA6_B FBB_CMD49 <28>
CG13 820P_0402_25V7 @ K3 K11 K11
+FBA_VREFC CA9_B FBA_CMD30 <28> CA7_B FBB_CMD19 <28> CA7_B FBB_CMD51 <28>
C1 +FBVDDQ 2 1 K1 K4 K4
VDDQ1 VREFC CA8_B FBB_CMD6 <28> CA8_B FBB_CMD28 <28>
J1 E1 CG14 820P_0402_25V7 @ K3 @ K3
<28> FBA_CMD3 RESET# VDDQ2 +FBB_VREFC CA9_B FBB_CMD4 <28> +FBB_VREFC CA9_B FBB_CMD30 <28>
H1 C1 +FBVDDQ 2 1 K1 2 1 K1
VDDQ3 L1 J1 VDDQ1 E1 CG15 820P_0402_25V7 VREFC CG16 820P_0402_25V7 VREFC
VDDQ4 <28> FBA_CMD31 RESET# VDDQ2
B1 P1 H1 C1 +FBVDDQ C1 +FBVDDQ
D1 VSS1 VDDQ5 T1 VDDQ3 L1 J1 VDDQ1 E1 J1 VDDQ1 E1
VSS2 VDDQ6 VDDQ4 <28> FBB_CMD3 RESET# VDDQ2 <28> FBB_CMD31 RESET# VDDQ2
F1 J2 B1 P1 H1 H1
G1 VSS3 VDDQ7 K2 D1 VSS1 VDDQ5 T1 VDDQ3 L1 VDDQ3 L1
M1 VSS4 VDDQ8 C4 F1 VSS2 VDDQ6 J2 B1 VDDQ4 P1 B1 VDDQ4 P1
N1 VSS5 VDDQ9 F4 G1 VSS3 VDDQ7 K2 D1 VSS1 VDDQ5 T1 D1 VSS1 VDDQ5 T1
R1 VSS6 VDDQ10 N4 M1 VSS4 VDDQ8 C4 F1 VSS2 VDDQ6 J2 F1 VSS2 VDDQ6 J2
U1 VSS7 VDDQ11 T4 N1 VSS5 VDDQ9 F4 G1 VSS3 VDDQ7 K2 G1 VSS3 VDDQ7 K2
A2 VSS8 VDDQ12 B5 R1 VSS6 VDDQ10 N4 M1 VSS4 VDDQ8 C4 M1 VSS4 VDDQ8 C4
V2 VSS9 VDDQ13 U5 U1 VSS7 VDDQ11 T4 N1 VSS5 VDDQ9 F4 N1 VSS5 VDDQ9 F4
C3 VSS10 VDDQ14 B10 A2 VSS8 VDDQ12 B5 R1 VSS6 VDDQ10 N4 R1 VSS6 VDDQ10 N4
D3 VSS11 VDDQ15 U10 V2 VSS9 VDDQ13 U5 U1 VSS7 VDDQ11 T4 U1 VSS7 VDDQ11 T4
F3 VSS12 VDDQ16 C11 C3 VSS10 VDDQ14 B10 A2 VSS8 VDDQ12 B5 A2 VSS8 VDDQ12 B5
G3 VSS13 VDDQ17 F11 D3 VSS11 VDDQ15 U10 V2 VSS9 VDDQ13 U5 V2 VSS9 VDDQ13 U5
M3 VSS14 VDDQ18 N11 F3 VSS12 VDDQ16 C11 C3 VSS10 VDDQ14 B10 C3 VSS10 VDDQ14 B10
N3 VSS15 VDDQ19 T11 G3 VSS13 VDDQ17 F11 D3 VSS11 VDDQ15 U10 D3 VSS11 VDDQ15 U10
R3 VSS16 VDDQ20 J13 M3 VSS14 VDDQ18 N11 F3 VSS12 VDDQ16 C11 F3 VSS12 VDDQ16 C11
T3 VSS17 VDDQ21 K13 N3 VSS15 VDDQ19 T11 G3 VSS13 VDDQ17 F11 G3 VSS13 VDDQ17 F11
A4 VSS18 VDDQ22 C14 R3 VSS16 VDDQ20 J13 M3 VSS14 VDDQ18 N11 M3 VSS14 VDDQ18 N11
E4 VSS19 VDDQ23 E14 T3 VSS17 VDDQ21 K13 N3 VSS15 VDDQ19 T11 N3 VSS15 VDDQ19 T11
H4 VSS20 VDDQ24 H14 A4 VSS18 VDDQ22 C14 R3 VSS16 VDDQ20 J13 R3 VSS16 VDDQ20 J13
L4 VSS21 VDDQ25 L14 E4 VSS19 VDDQ23 E14 T3 VSS17 VDDQ21 K13 T3 VSS17 VDDQ21 K13
P4 VSS22 VDDQ26 P14 H4 VSS20 VDDQ24 H14 A4 VSS18 VDDQ22 C14 A4 VSS18 VDDQ22 C14
V4 VSS23 VDDQ27 T14 L4 VSS21 VDDQ25 L14 E4 VSS19 VDDQ23 E14 E4 VSS19 VDDQ23 E14
C5 VSS24 VDDQ28 P4 VSS22 VDDQ26 P14 H4 VSS20 VDDQ24 H14 H4 VSS20 VDDQ24 H14
2 T5 VSS25 V4 VSS23 VDDQ27 T14 L4 VSS21 VDDQ25 L14 L4 VSS21 VDDQ25 L14 2
C10 VSS26 A1 C5 VSS24 VDDQ28 P4 VSS22 VDDQ26 P14 P4 VSS22 VDDQ26 P14
VSS27 VDD1 +FBVDDQ VSS25 VSS23 VDDQ27 VSS23 VDDQ27
T10 V1 T5 V4 T14 V4 T14
A11 VSS28 VDD2 H2 C10 VSS26 A1 C5 VSS24 VDDQ28 C5 VSS24 VDDQ28
VSS29 VDD3 VSS27 VDD1 +FBVDDQ VSS25 VSS25
E11 L2 T10 V1 T5 T5
H11 VSS30 VDD4 E5 A11 VSS28 VDD2 H2 C10 VSS26 A1 C10 VSS26 A1
VSS31 VDD5 VSS29 VDD3 VSS27 VDD1 +FBVDDQ VSS27 VDD1 +FBVDDQ
L11 P5 E11 L2 T10 V1 T10 V1
P11 VSS32 VDD6 E10 H11 VSS30 VDD4 E5 A11 VSS28 VDD2 H2 A11 VSS28 VDD2 H2
V11 VSS33 VDD7 P10 L11 VSS31 VDD5 P5 E11 VSS29 VDD3 L2 E11 VSS29 VDD3 L2
C12 VSS34 VDD8 H13 P11 VSS32 VDD6 E10 H11 VSS30 VDD4 E5 H11 VSS30 VDD4 E5
D12 VSS35 VDD9 L13 V11 VSS33 VDD7 P10 L11 VSS31 VDD5 P5 L11 VSS31 VDD5 P5
F12 VSS36 VDD10 A14 C12 VSS34 VDD8 H13 P11 VSS32 VDD6 E10 P11 VSS32 VDD6 E10
G12 VSS37 VDD11 V14 D12 VSS35 VDD9 L13 V11 VSS33 VDD7 P10 V11 VSS33 VDD7 P10
M12 VSS38 VDD12 F12 VSS36 VDD10 A14 C12 VSS34 VDD8 H13 C12 VSS34 VDD8 H13
N12 VSS39 G12 VSS37 VDD11 V14 D12 VSS35 VDD9 L13 D12 VSS35 VDD9 L13
R12 VSS40 A5 M12 VSS38 VDD12 F12 VSS36 VDD10 A14 F12 VSS36 VDD10 A14
VSS41 VPP1 +1V8_AON VSS39 VSS37 VDD11 VSS37 VDD11
T12 V5 N12 G12 V14 G12 V14
A13 VSS42 VPP2 A10 R12 VSS40 A5 M12 VSS38 VDD12 M12 VSS38 VDD12
VSS43 VPP3 VSS41 VPP1 +1V8_AON VSS39 VSS39
V13 V10 T12 V5 N12 N12
B14 VSS44 VPP4 A13 VSS42 VPP2 A10 R12 VSS40 A5 R12 VSS40 A5
VSS45 VSS43 VPP3 VSS41 VPP1 +1V8_AON VSS41 VPP1 +1V8_AON
D14 V13 V10 T12 V5 T12 V5
F14 VSS46 G5 B14 VSS44 VPP4 A13 VSS42 VPP2 A10 A13 VSS42 VPP2 A10
G14 VSS47 NC1 M5 D14 VSS45 V13 VSS43 VPP3 V10 V13 VSS43 VPP3 V10
M14 VSS48 NC2 F14 VSS46 G5 B14 VSS44 VPP4 B14 VSS44 VPP4
N14 VSS49 G14 VSS47 NC1 M5 D14 VSS45 D14 VSS45
R14 VSS50 M14 VSS48 NC2 F14 VSS46 G5 F14 VSS46 G5
U14 VSS51 N14 VSS49 G14 VSS47 NC1 M5 G14 VSS47 NC1 M5
180-BALL
VSS52 SGRAM GDDR6 R14 VSS50 M14 VSS48 NC2 M14 VSS48 NC2
U14 VSS51 N14 VSS49 N14 VSS49
180-BALL
VSS52 SGRAM GDDR6 R14 VSS50 R14 VSS50
MT61K256M32JE-13-A_FBGA180~D U14 VSS51 U14 VSS51
180-BALL 180-BALL
VSS52 SGRAM GDDR6 VSS52 SGRAM GDDR6
MT61K256M32JE-13-A_FBGA180~D
MT61K256M32JE-13-A_FBGA180~D MT61K256M32JE-13-A_FBGA180~D
+FBVDDQ
1
RG9 @ +FBVDDQ
549_0402_1%
1
2
RG16 @
1 @ 2 +FBA_VREFC W=16mils 549_0402_1%
1
RG8
2
931_0402_1% RG10
D 1K_0402_1% 1 @ 2 +FBB_VREFC W=16mils
1
1
2 QG2 @ RG15
<29> MEM_VREF_CTL
2
1
Use Integrated VREFC MEM_VREF_CTL 2 QG3 @
2
G BSS138W_SOT-323-3-X
S
3
Use Integrated VREFC
UM10
3 3
10U_0603_6.3VAM
22U_0603_6.3VAM
22U_0603_6.3VAM
22U_0603_6.3VAM
22U_0603_6.3VAM
22U_0603_6.3VAM
22U_0603_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
10U_0603_6.3VAM
10U_0603_6.3VAM
22U_0603_6.3VAM
22U_0603_6.3VAM
22U_0603_6.3VAM
22U_0603_6.3VAM
22U_0603_6.3VAM
22U_0603_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
10U_0603_6.3VAM
10U_0603_6.3VAM
22U_0603_6.3VAM
22U_0603_6.3VAM
22U_0603_6.3VAM
22U_0603_6.3VAM
22U_0603_6.3VAM
22U_0603_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
10U_0603_6.3VAM
10U_0603_6.3VAM
22U_0603_6.3VAM
22U_0603_6.3VAM
22U_0603_6.3VAM
22U_0603_6.3VAM
22U_0603_6.3VAM
22U_0603_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CG17
CG18
CG19
CG20
CG21
CG22
CG23
CG447
CG24
CG25
CG26
CG27
CG50
CG51
CG52
CG53
CG54
CG55
CG56
CG448
CG57
CG58
CG59
CG60
CG83
CG84
CG85
CG86
CG87
CG88
CG89
CG449
CG90
CG91
CG92
CG93
CG116
CG117
CG118
CG119
CG120
CG121
CG122
CG450
CG123
CG124
CG125
CG126
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
+FBVDDQ CLOSE OR UNDER DRAM +FBVDDQ CLOSE OR UNDER DRAM +FBVDDQ CLOSE OR UNDER DRAM +FBVDDQ CLOSE OR UNDER DRAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1U_0201_6.3VAM
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CG28
CG29
CG30
CG31
CG32
CG33
CG34
CG35
CG36
CG37
CG38
CG39
CG40
CG41
CG42
CG43
CG44
CG45
CG61
CG62
CG63
CG64
CG65
CG66
CG67
CG68
CG69
CG70
CG71
CG72
CG73
CG74
CG75
CG76
CG77
CG78
CG94
CG95
CG96
CG97
CG98
CG99
CG100
CG101
CG102
CG103
CG104
CG105
CG106
CG107
CG108
CG109
CG110
CG111
CG127
CG128
CG129
CG130
CG131
CG132
CG133
CG134
CG135
CG136
CG137
CG138
CG139
CG140
CG141
CG142
CG143
CG144
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
10U_0603_6.3VAM
10U_0603_6.3VAM
10U_0603_6.3VAM
10U_0603_6.3VAM
10U_0603_6.3VAM
10U_0603_6.3VAM
10U_0603_6.3VAM
10U_0603_6.3VAM
10U_0603_6.3VAM
10U_0603_6.3VAM
10U_0603_6.3VAM
10U_0603_6.3VAM
10U_0603_6.3VAM
10U_0603_6.3VAM
10U_0603_6.3VAM
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CG46
CG47
CG48
CG49
CG79
CG80
CG81
CG82
CG112
CG113
CG114
CG115
CG145
CG146
CG147
CG148
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM_GDDR6_AB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K662P
Date: Wednesday, April 21, 2021 Sheet 35 of 121
A B C D E
A B C D E
1 1
2 2
3 3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K662P
Date: Wednesday, April 21, 2021 Sheet 36 of 121
A B C D E
5 4 3 2 1
5
4 11 10U_0603_6.3V6M
1 VCC VBIAS GND 2
B 4 1V8_AON_EN 1V8_MAIN_EN_R 5 10 1 2
Y 1V8_AON_EN <34> ON2 CT2
DGPU_PWR_EN 2 A CG8 220P_0402_50V8J
<9,29> DGPU_PWR_EN G UG2 1 +1.8VALW_GPU 6 9 +1V8_MAIN
VIN2_1 VOUT2_1
1
74LVC1G32GW_TSSOP5 7 8
3
RG1 CG3 VIN2_2 VOUT2_2
1
100K_0201_5% 1U_0201_6.3V6M 15
2 GPAD CG6
1
EM5209VF_DFN14_3X2-X 10U_0603_6.3V6M
2
CG4 2
10U_0603_6.3V6M
2
+1V8_AON
1
RG2
10K_0201_5%
+3VALW GN20P@
2
NV_3V3(For Sequence)
1
3V3_SYS_EN
3V3_SYS_EN <29,34>
RG3
100K_0201_5% 1
GN20P@ +3VALW
6
D CG9 UG4
2
C D C
DGPU_PWR_EN 5 2N7002KDW_SOT-363-6-X +5VALW 3 1
G QG1B VBIAS
GN20P@ 3V3_SYS_EN 4 5 CG11
S ON GND
1 0.1U_0201_10V6K
4
2
1
C57 +1V8_MAIN +1V8_AON EM5201V_DFN3X3-8-X
1U_0402_6.3V6K CG12 SA00008A800
2 GN20P@
www.teknisi-indonesia.com
1U_0201_6.3V6M
2
1 Main SA00008A800
1
10K_0201_5% 2
RG545
VCC
2
DGPU_PWR_EN 1 2.2K_0201_1%
IN B 4 1 2 3V3_SYS_EN
1V8_MAIN_EN 2 OUT Y N18P@
GND
IN A
1 UG26
3
0.047U_0201_10V6K
CD402
N18P@
NL17SZ08EDFT2G_SOT353-5
2
N18P@
GPU Power Up Sequence GPU GC6 Entry Sequence GPU GC6 Exit Sequence GPU Power Down Sequence
B B
PXE_Link Active XXX XXX Detect Train All other power rails
+3V3_SYS
PEXVDD +1V8_AON
+NVVDD
GPU_GC6_FB_EN
GPU GC6 State
+PEX_VDD NVVDD_EN
+FBVDDQ
DGPU_PEX_RST#
T1 < 20ms
The ramp time for any rail must be more than 40us and less than 2ms. The entire entry/exit sequence must complete within 200 ms.
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DGPU_DC/DC Interface
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K662P
Date: Wednesday, April 21, 2021 Sheet 37 of 121
5 4 3 2 1
A B C D E
2
19
2
DE5
1
<8> CPU_EDP_HPD
ENBKL
20
21
19
20
From SIF module (eDP) DV1 ESD@
+3VS_CAM +MIC_VCC
<58> BKOFF# 21 AZ5125-02S.R7G_SOT23-3-X
+LCDVDD EDP_PWM 22
RB751S-40_SOD523-2-X LCD_TST_C 23 22 FV3 @
24 23 1 2
DMIC_DATA_EDP 25 24
C726 DMIC_CLK_EDP 26 25 0.5A_65V_T0603FF0500TM-X
RV41 1 @ 2 10K_0201_5% RF@ 1 2 27 26
1
R976 2 1 0_0402_5% 10P_0201_25V8 28 27
<9> LCD_CBL_DET# 28
OD_EN_D 29
30 29 +3VALW +3VS_CAM
30
DE3 DE6 +CAM_VCC 31
31 Pin 30
2 1 @ EDP_PWM OD_EN_R R144 2 1 0_0402_5% OD_EN 1 2 OD_EN_D 32 R979 1 @ 2 0_0402_5%
<8> INVTPWM_R <12> OD_EN_R +MIC_VCC
33 32 RSV for NV/non-NV
RB751S-40_SOD523-2-X RB751S-40_SOD523-2-X 34 33 Q2
+LCDVDD
W=60 mils 35 34 AO3419L_SOT23-3 +CAM_VCC
DE4 RF@C727 10P_0201_25V8 36 35 FV2
EC (BIST MODE) LCD_TST EDP_PWM 36
D
2 1 @ 1 2 1 2 37 3 1 1 2
<58> LCD_TST 37
0.22U_0201_6.3V6K
R6 1 2 100K_0201_5% ENBKL 38
RB751S-40_SOD523-2-X R7 100K_0201_5% +DCBAT_LCD
W=60 mils 39 38 1
1 0.5A_65V_T0603FF0500TM-X
1
C3
40 39 C1 10U_0402_6.3V6M
1 @ 2 OD_EN_D 40 4.7U_0402_6.3V6M C2 @
1.5A 1 2 2
RV42 100K_0201_5% RF@ 41
GND 2
G
CV17 42
10P_0201_25V8 43 GND
2
LCD_TST R962 1 2 100_0402_1% LCD_TST_C 2 44 GND 1 R8 2
GND +3VALW
100K_0201_5%
1
STARC_300E40-1010RA-G3 7/30 modify
SP010022J00 R9
10K_0201_5%
200 ohm change to
10K
2
+5VS +5VS_ALIEN_LED
FV4 ARK@
1
1 2
D Q1
0.5A_65V_T0603FF0500TM-X JAW1 R10 1 2 0_0201_1% 2 AO3416L_SOT-23-3-X
<58,66> PCH_PWR_EN
+5VS_ALIEN_LED 1
1
G 7/30 modify
1
2 S
<63> ALIEN_LED_R_DRV#
3 2 R132
Update
<63> ALIEN_LED_G_DRV# footprint
3
4 3 100K_0201_5%
2 <63> ALIEN_LED_B_DRV# 4 2
5 @
6 5
High Active
2
+LCDVDD 7 6
8 7
9 8 11
9 GND
2
10 12
RV730 10 GND
27_0402_1% SDAN_615005-010041
+5VALW SP01002S500
CONN@
1
2
LV1 EMI@
RV731 1 2 USB20_P3_EDP
<10> USB20_P3_R 1 2
6
10K_0402_5%
QV10A
DMN66D0LDW-7_SOT363-6 4 3 USB20_N3_EDP +VDDIO_AUDIO +3VS_CAM
1
2 <10> USB20_N3_R 4 3
DLM0NSN900HY2D_4P-X
DMIC 1.8V POWER 1 1 DMIC 3.3V POWER
1
1
3
2
QV10B AZC199-02S.R7G_SOT23-3-X 0.1U_0201_10V6K 2.2K_0201_1% 0.1U_0201_10V6K
ESD@ 2 UA1 SA0000ANI00 2
DMN66D0LDW-7_SOT363-6
+VDDIO_AUDIO
1
ENVDD 5 1 6
2
VCCA VCCB
1
2 5 UFC_OE RA1 1 2 0_0201_1%
4
GND DIR
APU_WOV_CLK 3 4 WOV_CLK_L RE548 2 EMI@ 1 0_0402_5% APU_WOV_CLK_L
<9> APU_WOV_CLK A B
RA124 1 @ 2 2.2K_0201_1% +3VS_CAM
2021/03/08 modify, 74LVC1T45GW_SC-88
To PCH +3VS_CAM
From Module
DMIC 1.8V POWER
1
DMIC 3.3V POWER
1
@ RA122
2.2K_0201_1% RA123 @
UA3 SA00001NQ00 2.2K_0201_1%
Main Func = LCDVDD monitor 5 1
2
VCC NC
2
2 APU_WOV_DAT_L
A
3 APU_WOV_DAT 4 3 DATA INPUT 3
<9> APU_WOV_DAT Y GND
DATA OUTPUT 74LVC1G17GW_TSSOP_5P
DV15
2
<8,9> ENVDD_APU
10U_0402_6.3V6M
1
1
C5
+3VALW +LCDVDD_R +LCDVDD C728
2
2 47U_0603_6.3V6M
U7
C4 2 1 5 1 1 2
IN OUT R13 0_0603_5%
10U_0402_6.3V6M 2
GND
ENVDD 4
EN OC
3 7/30 Del
Unuse OC
1
SY6288C20AAC_SOT23-5-X
R12
4
100K_0201_5% 4
2
High Active
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eDP/Camera
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K661P
Date: Wednesday, April 21, 2021 Sheet 38 of 121
A B C D E
5 4 3 2 1
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eDP MUX/DDS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K454P
Date: Wednesday, April 21, 2021 Sheet 39 of 121
5 4 3 2 1
5 4 3 2 1
2
CV32 2 1 0.1U_0201_6.3V6K HDMI_C_CLKN 4 3
<27> GPU_HDMI_CLKN 4 3 RX25
150_0201_1%
CV33 2 1 0.1U_0201_6.3V6K HDMI_C_CLKP 1 2 @EMI@ +5VS +HDMI_5V_OUT
<27> GPU_HDMI_CLKP 1 2
1
D EXC24CG900U_4P FV5 D
1 EMI@ 2 HDMI_L_CLKP 1 2 HDMI_CLKP 1 2 +3V3_SYS
RV15 5.6_0402_1% RV16 0_0201_5%
1200P_0402_50V7K
10U_0603_6.3V6M~D
0.1U_0201_6.3V6K
1.1A_6V_SPR-P110
1 1 1
1
CV34 @EMI@
CV35
CV36
1 EMI@ 2 HDMI_L_TX_N0 1 2 HDMI_TX_N0
RV17 5.6_0402_1% RV18 0_0201_5% RV19
LV3 @EMI@ 10K_0402_5%
2
CV37 2 1 0.1U_0201_6.3V6K HDMI_C_TX_N0 1 2 2 2 2 @
<27> GPU_HDMI_TX_N0 1 2 RX26
2
150_0201_1%
CV38 2 1 0.1U_0201_6.3V6K HDMI_C_TX_P0 4 3 @EMI@
<27> GPU_HDMI_TX_P0 4 3
1
EXC24CG900U_4P
1 EMI@ 2 HDMI_L_TX_P0 1 2 HDMI_TX_P0
RV21 5.6_0402_1% RV22 0_0201_5%
2
CV39 2 1 0.1U_0201_6.3V6K HDMI_C_TX_N1 4 3 HDMI_TX_N2 3
<27> GPU_HDMI_TX_N1 4 3 D2-
RX27 HDMI_TX_P1 4
150_0201_1% 5 D1+
CV40 2 1 0.1U_0201_6.3V6K HDMI_C_TX_P1 1 2 @EMI@ HDMI_TX_N1 6 D1_shield
<27> GPU_HDMI_TX_P1 1 2 D1-
HDMI_TX_P0 7
1
EXC24CG900U_4P 8 D0+
1 EMI@ 2 HDMI_L_TX_P1 1 2 HDMI_TX_P1 HDMI_TX_N0 9 D0_shield
RV26 5.6_0402_1% RV27 0_0201_5% HDMI_CLKP 10 D0-
11 CK+ 20
HDMI_CLKN 12 CK_shield GND1 21
13 CK- GND2 22
1 EMI@ 2 HDMI_L_TX_N2 1 2 HDMI_TX_N2 14 CEC GND3 23
RV28 5.6_0402_1% RV29 0_0201_5% HDMI_CTRL_CLK 15 Reserved GND4
LV5 @EMI@ HDMI_CTRL_DAT 16 SCL
SDA
2
CV41 2 1 0.1U_0201_6.3V6K HDMI_C_TX_N2 1 2 17
<27> GPU_HDMI_TX_N2 1 2 DDC/CEC_GND
RX28 18
150_0201_1% HDMI_HPD 19 +5V
C HP_DET C
CV42 2 1 0.1U_0201_6.3V6K HDMI_C_TX_P2 4 3 @EMI@
<27> GPU_HDMI_TX_P2 4 3 LOTES_AHDM0008-P002A
1
EXC24CG900U_4P DC232002B00
1 EMI@ 2 HDMI_L_TX_P2 1 2 HDMI_TX_P2
RV31 5.6_0402_1% RV32 0_0201_5%
Update HDMI2.0 Connecter
+3V3_SYS HDMI_Down
D
1
2 QX5
G BSS138 1N SOT23-3
1
S
3
RX18
100K_0402_5%
2
B B
+HDMI_5V_OUT
DGPU_PEX_RST#
SDM10U45-7_SOD523-2
SDM10U45-7_SOD523-2
2
+3VALW
+1V8_AON
DV10
DV9
QX6
1
LMBT3904WT1G_SC70-3-X
10K_0201_5%
10K_0201_5%
C
1
1
RV33
2 1 2 HDMI_HPD
2
2
2K_0201_1%
2K_0201_1%
B
RV34
RX19 150K_0201_5%
E
RV35
RV36
3
+1V8_AON
1
2
CX6
1
1
2
RX20
1
4 3 HDMI_CTRL_CLK_R 2 1 HDMI_CTRL_CLK 10K_0201_5% +1.8V_VDD
<27> GPU_HDMI_CTRL_CLK CX5
QV8B RV37 1 2 RX21
2
2
2
0.1U_0201_10V6K
5
1 6 HDMI_CTRL_DAT_R 2 1 HDMI_CTRL_DAT UX3
<27> GPU_HDMI_CTRL_DAT
QX4A
VCC
QV8A RV38 DMN53D0LDW-7 2N SOT363-6 1
DMN53D0LDW-7 2N SOT363-6 33_0201_1% 2 4 IN B
OUT Y 2 DGPU_PEX_RST#
GND
IN A DGPU_PEX_RST# <26,29>
1
A A
NL17SZ08EDFT2G_SOT353-5
3
3
QX4B
DMN53D0LDW-7 2N SOT363-6
5
4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K661P
Date: Wednesday, April 21, 2021 Sheet 40 of 121
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RSV
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K661P
Date: Wednesday, April 21, 2021 Sheet 41 of 121
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Thunderbolt (1/2)
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K661P
Date: Wednesday, April 21, 2021 Sheet 42 of 121
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Thunderbolt (2/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K661P
Date: Wednesday, April 21, 2021 Sheet 43 of 121
5 4 3 2 1
5 4 3 2 1
+3VALW +3.3V_VDD_PIC
+CCG_VBUS
RT614 1 2 0_0603_5%
1
RT1
TYPEC@ 100K_0402_1%
+5V_CONN_P1 +3.3V_VDD_PIC
2
VBUS_MON_P1
1U_0603_16V7
1
1U_0603_16V7
1U_0603_16V7
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
2 1 1 1 1 1 1 1
CT3
CT4
CT5
CT6
CT7
CT52
CT57
RT3 CT9
10K_0402_1% 0.1U_0402_10V7K
1 2 2 2 2 2 2 2
2
TYPEC@
TYPEC@
+5V_CONN_P1 +3.3V_VDD_PIC
TYPEC@ TYPEC@ TYPEC@ CT8 TYPEC@
D D
TYPEC@ TYPEC@ 1 2
1U_0603_16V7
place near UT1.8 place near UT1.31/32
20 mils
TYPEC@
CT11 1 2 390P_0402_50V7K
31
32
33
8
UT1 TYPEC@
13 VBUS_MON_P1 CT10 1 2 390P_0402_50V7K
V5V_P1
VDDD
VDDIO
VCCD
VBUS_MON_P1/GPIO
TP1 CCG4_SWD_IO 1 7
SWD_IO/AR_RST# CC2_P1 CCG4_CC2_P1 <45>
TP2 CCG4_SWD_CLK 2 9
SWD_CLK/I2C_CFG_EC CC1_P1 CCG4_CC1_P1 <45>
HPD_P1 18 11
HPD_P1/GPIO VBUS_P_CTRL_P1 VBUS_P_CTRL_P1 <45>
12 VBUS_C_CTRL_P1
VBUS_C_CTRL_P1
RT117
19 20 100K_0402_1%
+3.3V_VDD_PIC VCONN_MON__P1/GPIO VBUS_DISCHARGE_P1 VBUS_DISCHARGE <45>
TYPEC@ VBUS_P_CTRL_P1 1 TYPEC@2
14
RT6 1 2 4.7K_0402_5% CCG4_XRES CCG4_XRES 10 OVP_TRIP_P1 27 CCG4_ID2
XRES GPIO3 RT118
21 100K_0402_1%
GPIO2
0.1U_0402_10V7K
TP3 1 30 VBUS_C_CTRL_P1 1 TYPEC@2
GPIO4 34 APU_RST#_R
OCP_DET_P2/GPIO
CT13
TYPEC@ 15 35
<58> INT#_TYPEC I2C_INT_EC GPIO5 +3.3V_VDD_PIC
17 36
2 <58,77> EC_SMB_CK3 I2C_SCL_SCB1_EC GPIO6
16 37
<58,77> EC_SMB_DA3 I2C_SDA_SCB1_EC GPIO7
1 2 4 38
<45> MUX_AUX_FLIP I2C_SCL_SCB2_AR GPIO8
UT3 RT1664 0_0201_1% 3
+5VALW 1 2 5 I2C_SDA_SCB2_AR/VSEL_1_P1 39
<45> MUX_AUX_EN# I2C_INT_AR_P1/OCP_DET_P1 GPIO9
2 RT1660 0_0402_5%
GND
2
40
1 1 @ 2 6 GPIO10 RT1661
IN <10,45> USB_OC0# GPIO1
1 RT1657 0_0201_1% 10K_0402_5%
3 +5V_CONN_P1 CCG4_ID1 25 22
OUT SCL_3 NC1
2
CT12 26 QC4
G
1
0.1U_0402_10V7K CCG4_APU_USBC_SCL 29 SDA_3/MUX_CTRL_3_P1/VSEL_2_P1 23
2
TYPEC@
AP2330W-7_SC59-3 20 mils <10>
<10>
CCG4_APU_USBC_SCL
CCG4_APU_USBC_SDA
CCG4_APU_USBC_SDA 28 SCL_4/MUX_CTRL_1_P1 NC2 APU_RST#_R 1 3
APU_RST# <8>
SDA_4/MUX_CTRL_2_P1 24
S
TYPEC@ NC3
41
0.2A OCP for VCONN! VSS BSS138W_SOT-323-3-X
CYPD4126-40LQXIT_QFN40_6X6
SA0000AXC30
C C
Type-C DP HPD
+3.3V_VDD_PIC
+3VS_APU
1
1
RT71
RT70 2.2K_0402_5%
2
2.2K_0402_5% TYPEC@
TYPEC@ RT2 +3VALW
2
1M_0402_5%
2
2
CCG4_APU_USBC_SDA +3.3V_VDD_PIC
G
1
QC5 1 3 HPD_P1
<8> APU_DP2_HPD
1
CCG4_APU_USBC_SCL JCCG1
D
1
RT1659 1
1
2
BSS138W_SOT-323-3-X RT1658 2.2K_0402_5% 2 CCG4_XRES
RX24 2.2K_0402_5% TYPEC@ 2 3 CCG4_SWD_CLK
100K_0201_5% TYPEC@ 3 4 CCG4_SWD_IO
2
4 5 EC_SMB_DA3
2
EC_SMB_DA3 5 6 EC_SMB_CK3
1
6 7
7 +5VALW
8
EC_SMB_CK3 8 9
9 10
10
11
GND1 12
GND2
ACES_50521-01041-P01
CONN@
B B
MODID
CCG4 ID1: L7
CCG4 ID2: L0
+3.3V_VDD_PIC +3.3V_VDD_PIC
1
RT4 RT64
4.7K_0402_5% 20K_0402_5%
TYPEC@ @
2
CCG4_ID1 CCG4_ID2
1
RT115 RT65
33K_0402_5% 10K_0402_5%
TYPEC@ TYPEC@
2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cypress PD Control
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.3(X02)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F121P
Date: Wednesday, April 21, 2021 Sheet 44 of 121
5 4 3 2 1
5 4 3 2 1
Main Function:
+3.3V_VDD_PIC
2
+CCG_VBUS
RT130
0_0402_5%
TYPEC@ +CCG_VBUS
2
Near Pin A4,A9,B4,B9
1
UT10 TYPEC@ DT9
10 1 APU_DP2_AUXP CEST23NC24VU_SOT23-3
VCC 1D+ 2 APU_DP2_AUXP <8>
0.1U_0201_25V6K
0.1U_0201_25V6K
0.1U_0201_25V6K
0.1U_0201_25V6K
9 APU_DP2_AUXN ESD@
D <44> MUX_AUX_FLIP S 1D- 3 APU_DP2_AUXN <8> D
MUX_SBU1 8 RT1662 1 TYPEC@2 0_0201_5% 1 1 1 1
D+ 2D+ 4
CT48
CT49
CT50
CT51
MUX_SBU2 7 RT1663 1 TYPEC@2 0_0201_5%
1
6 D- 2D- 5
<44> MUX_AUX_EN# OE# GND RV722 1 @EMI@ 2 5.6_0201_5%
NX3DV221GM_XQFN10U10_2X1P55 2 2 2 2
1
LV11 EMI@
RT119 USBC0_DP2_C_CTX_DRX_P1 4 3 USBC0_DP2_C_CTX_DRX_P1_L
TYPEC@ 4 3
10K_0402_5%
USBC0_DP2_C_CTX_DRX_N1 1 2 USBC0_DP2_C_CTX_DRX_N1_L JUSBC1 CONN@
2
1 2 A1 B12
DLM0NSN500HY2D_4P GND_A1 GND_B12
RV721 1 @EMI@ 2 5.6_0201_5% USBC0_DP2_C_CTX_DRX_P1_L A2 B11 USBC0_DP3_C_CRX_DTX_P1_L
USBC0_DP2_C_CTX_DRX_N1_L A3 SSTXP1 SSRXP1 B10 USBC0_DP3_C_CRX_DTX_N1_L
RV724 1 @EMI@ 2 5.6_0201_5% SSTXN1 SSRXN1
A4 B9
LV12 EMI@ VBUS_A4 VBUS_B9
USBC0_DP3_C_CRX_DTX_P1 1 2 USBC0_DP3_C_CRX_DTX_P1_L CCG4_CC1_P1 A5 B8 MUX_SBU2
S OE# OUT PUT 1 2 <44> CCG4_CC1_P1 CC1 SBU2
USB20_P0_L A6 B7 USB20_N0_L
USBC0_DP3_C_CRX_DTX_N1 4 3 USBC0_DP3_C_CRX_DTX_N1_L USB20_N0_L A7 DP1 DN2 B6 USB20_P0_L
Low Low 1D+/1D- 4 3 DN1 DP2
Bottom
DLM0NSN500HY2D_4P MUX_SBU1 A8 B5 CCG4_CC2_P1
High Low 2D+/2D- RV723 1 @EMI@ 2 5.6_0201_5% SBU1 CC2 CCG4_CC2_P1 <44>
TOP
A9 B4
VBUS_A9 VBUS_B4
RV726 1 @EMI@ 2 5.6_0201_5% USBC0_DP0_C_CRX_DTX_N2_L A10 B3 USBC0_DP1_C_CTX_DRX_N2_L
USBC0_DP0_C_CRX_DTX_P2_L A11 SSRXN2 SSTXN2 B2 USBC0_DP1_C_CTX_DRX_P2_L
LV13 EMI@ SSRXP2 SSTXP2
USBC0_DP1_C_CTX_DRX_P2 4 3 USBC0_DP1_C_CTX_DRX_P2_L A12 B1
4 3 GND_A12 GND_B1
USBC0_DP1_C_CTX_DRX_N2 1 2 USBC0_DP1_C_CTX_DRX_N2_L 1 4
1 2 GND1 GND4
RT612 1 @EMI@ 2 0_0201_5% DLM0NSN500HY2D_4P 2 3
RV725 1 @EMI@ 2 5.6_0201_5% GND2 GND3
LT4 EMI@
C <10> USB20_P0 4 3 USB20_P0_L LOTES_AUSB0528-P303A C
4 3 RV728 1 @EMI@ 2 5.6_0201_5% DC233200429
DT10 DLM0NSN500HY2D_4P
3
3 3
0.22U_0201_6.3V6K 2 1 CT107 USBC0_DP1_C_CTX_DRX_P2
8 <10> USBC0_DP1_CTX_DRX_P2
0.22U_0201_6.3V6K 2 1 CT108 USBC0_DP1_C_CTX_DRX_N2
<10> USBC0_DP1_CTX_DRX_N2
5V@3A AZ1045-04FR7_DFN2510P10E10-9-X
<10> USBC0_DP0_CRX_DTX_P2
0.33U_0201_6.3V6M
0.33U_0201_6.3V6M
2
2
1 CT109
1 CT110
USBC0_DP0_C_CRX_DTX_P2
USBC0_DP0_C_CRX_DTX_N2
<10> USBC0_DP0_CRX_DTX_N2
CT62 TYPEC@ 10U 6.3V 0402
1 2
+CCG_VBUS
UT8 TYPEC@
+CCG_VBUS
+5VALW 5 1
IN OUT
1
B B
RT33
3 100_1206_5%
<10,44> USB_OC0# FLAG
TYPEC@
2
4 2 USBC0_DP2_C_CTX_DRX_P1_L 1 2 USBC0_DP1_C_CTX_DRX_P2_L 1 2
<44> VBUS_P_CTRL_P1 EN GND DT1 ESD@ DT2 ESD@
1
SY6861A1AAC SOT23
RT62 D QT3
10K_0402_5% 2 2N7002K_SOT23-3 PESD5V0H1BSF_SOD962-2-2 PESD5V0H1BSF_SOD962-2-2
<44> VBUS_DISCHARGE
@ G
S USBC0_DP2_C_CTX_DRX_N1_L 1 2 USBC0_DP1_C_CTX_DRX_N2_L 1 2
2
RT32
TYPEC@
100K_0402_5%
TYPEC@ PESD5V0H1BSF_SOD962-2-2 PESD5V0H1BSF_SOD962-2-2
2
USBC0_DP3_C_CRX_DTX_P1_L 1 2 USBC0_DP0_C_CRX_DTX_P2_L 1 2
DT5 ESD@ DT6 ESD@
PESD5V0H1BSF_SOD962-2-2 PESD5V0H1BSF_SOD962-2-2
PESD5V0H1BSF_SOD962-2-2 PESD5V0H1BSF_SOD962-2-2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TypeC CONN
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K661P
Date: Wednesday, April 21, 2021 Sheet 45 of 121
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
www.teknisi-indonesia.com
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RSV
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K661P
Date: Wednesday, April 21, 2021 Sheet 46 of 121
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RSV
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K661P
Date: Wednesday, April 21, 2021 Sheet 47 of 121
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RSV
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K661P
Date: Wednesday, April 21, 2021 Sheet 48 of 121
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RSV
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K661P
Date: Wednesday, April 21, 2021 Sheet 49 of 121
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RSV
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K661P
Date: Wednesday, April 21, 2021 Sheet 50 of 121
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RSV
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K661P
Date: Wednesday, April 21, 2021 Sheet 51 of 121
5 4 3 2 1
5 4 3 2 1
RW8 1 @ 2 0_0603_5%
+3.3V_WLAN +3.3V_WLAN
80 mils
APU_BT_ON_R RW2 1 2 10K_0201_5%
WL_OFF#_R RW3 1 2 10K_0201_5%
+3VALW
0.01U_0201_10V6K
10U_0402_6.3V6M
10U_0402_6.3V6M
0.01U_0201_10V6K
+3.3V_WLAN
CW1
0.1U_0201_10V6K
CW2
CW3
0.1U_0201_10V6K
CW4
CW5
10P_0201_25V8
CW6 RF@
CW7
1 1 1 1 1 1 1
UW1
D +3VALW D
5 1
IN OUT 2 2 2 2 2 2 2
2
GND
<58> WLAN_EN 4 3 2 1
EN OC RW34 10K_0402_5%
SY6288C20AAC_SOT23-5
Place near Pin 2,4 Place near Pin 72,74
2
+3.3V_WLAN
for G3 BT issue
1
JWLAN1 CONN@
1 2 RW1
3 GND_1 3.3VAUX_2 4 10K_0402_5% @
<10> USB20_P2 USB_D+ 3.3VAUX_4
2
G
5 6 TC9
<10> USB20_N2 USB_D- LED1#
7 8 @
2
9 GND_7 PCM_CLK 10 APU_BT_WAKE#_L 3 1
SDIO_CLK PCM_SYNC 7/17 Del cnvi function APU_BT_WAKE# <9>
11 12
D
13 SDIO_CMD PCM_OUT 14
15 SDIO_DAT0 PCM_IN 16 QW1
17 SDIO_DAT1 LED2# 18 L2N7002WT1G_SC-70-3
19 SDIO_DAT2 GND_18 20 APU_BT_WAKE#_L SB00001GE00
21 SDIO_DAT3 UART_WAKE 22 UART_0_ARXD_R_DTXD
23 SDIO_WAKE UART_TX
SDIO_RST
32 UART_0_ATXD_R_DRXD 2 1
33 UART_RX 34 UART_0_CTS#_R RW7 100K_0402_5%
PCIE_CTX_C_DRX_P5 35 GND_33 UART_RTS 36 UART_0_RTS#_R
<6> PCIE_CTX_C_DRX_P5 PET_RX_P0 UART_CTS
PCIE_CTX_C_DRX_N5 37 38 E51TXD_P80DATA_R RW6 1 2 0_0402_5%
<6> PCIE_CTX_C_DRX_N5 PET_RX_N0 CLink_RST EC_TX <58>
39 40 E51RXD_P80CLK_R RW5 1 2 0_0402_5%
GND_39 CLink_DATA EC_RX <58>
PCIE_CRX_DTX_P5 41 42
<6> PCIE_CRX_DTX_P5 PER_TX_P0 CLink_CLK
PCIE_CRX_DTX_N5 43 44
<6> PCIE_CRX_DTX_N5 PER_TX_N0 COEX3
45 46
47 GND_45 COEX2 48
<10> CLK_PCIE_P3 REFCLK_P0 COEX1
C 49 50 SUSCLK_WLAN C
<10> CLK_PCIE_N3 REFCLK_N0 SUSCLK(32KHz) SUSCLK_WLAN <10,58>
51 52 WL_RST#_R
53 GND_51 PERST0# 54 APU_BT_ON_R
<10> CLKREQ_PCIE#3 CLKREQ0# W_DISABLE2#
RW4 1 2 0_0201_1% WLAN_WAKE#_R 55 56 WL_OFF#_R
<9> WLAN_WAKE# PEWAKE0# W_DISABLE1#
57 58
59 GND_57 I2C_DAT 60
61 RSVD/PCIE_RX_P1 I2C_CLK 62
63 RSVD/PCIE_RX_N1 I2C_IRQ 64
65 GND_63 RSVD_64 66
67 RSVD/PCIE_TX_P1 RSVD_66 68 +3.3V_WLAN
69 RSVD/PCIE_TX_N1 RSVD_68 70 @
71 GND_69 RSVD_70 72 SUSCLK_WLAN CW14 1 2 22P_0402_50V8J
73 RSVD_71 3.3VAUX_72 74
75 RSVD_73 3.3VAUX_74
GND_75 76
77 GND1
GND2
LOTES_APCI0147-P007A
SP07001GF00
E Key CONN
RW12 1 @ 2 0_0402_5%
+3VALW
+3VALW
5
5
UW3
1 +1.8VS 1
P
P
NC <9,26,68,73> APU_PCIE_RST# IN1
4 UART_0_ATXD_R_DRXD 4 WL_RST#_R
2 Y UART_0_ATXD_R_DRXD RW10 1 @ 2 1K_0402_5% 2 O
<10> UART_0_ATXD_DRXD A <59> WL_RST# IN2
G
G
B B
@ UART_0_RTS#_R RW19 1 @ 2 1K_0402_5%
1
NL17SZ07DFT2G_SC70-5 UW2 SA0000BIP00
3
3
1
SA0000BIO00 UART_0_ARXD_R_DTXD RW23 1 @ 2 1K_0402_5% MC74VHC1G08DFT2G_SC70-5 RW13
UART_0_CTS#_R RW22 1 @ 2 1K_0402_5% RW14 100K_0402_5%
10K_0402_5%
+3VALW
2
+3VS
2
5
NC 4 UART_0_RTS#_R
2 Y
<10> UART_0_RTS# A
G
@
NL17SZ07DFT2G_SC70-5
3
SA0000BIO00
+1.8V_VDD
5
UW5
1
P
4 NC
<10> UART_0_ARXD_DTXD Y 2 UART_0_ARXD_R_DTXD
A
G
@ NL17SZ07DFT2G_SC70-5
3
SA0000BIO00
+1.8V_VDD
5
UW6
1
P
4 NC
<10> UART_0_CTS# Y 2 UART_0_CTS#_R
A
G
A @ NL17SZ07DFT2G_SC70-5 A
3
SA0000BIO00
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WLAN/BT (w/ CNVi) M.2
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K661P
Date: Wednesday, April 21, 2021 Sheet 52 of 121
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RSV
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K661P
Date: Wednesday, April 21, 2021 Sheet 53 of 121
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RSV
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K661P
Date: Wednesday, April 21, 2021 Sheet 54 of 121
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RSV
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K661P
Date: Wednesday, April 21, 2021 Sheet 55 of 121
5 4 3 2 1
2 1
+3VS +5VS
+1.8VS 10mA place close to pin41 place close to pin46
@ +5V_RUN_PVDD_L 1 @ 2
RA2 1 @ 2 0_0603_5% place close to pin20 +1.8V_RUN_AUDIO +3.3V_RUN_AUDIO_DVDD 2 1 RA4 0_0805_5%
0.1U_0201_10V6K
10U_0603_10V6M
0.1U_0201_10V6K
10U_0603_10V6M
LA1 BLM15PX600SN1D_2P
10U_0603_10V6M
0.1U_0201_10V6K
1 1 1 1
+1.8VALW_GPU +3VALW +5VALW
0.1U_0201_10V6K
10U_0603_10V6M
10P_0201_25V8
CA3
CA4
CA5
CA6
1 1
CA7
CA8
CA35 RF@
1 1 1
+1.8VALW_GPU
CA9
CA10
RA43 1 2 0_0603_5% 2 1 1 2
LA16 BLM15PX600SN1D_2P 2 2 2 2 RA44 0_0805_5%
8/5 Co-lay +1.8V_VDD for MS 2 2
2 2 2 8/5 Co-lay +5VALW for MS
8/5 Co-lay +3VALW for MS +1.8VS
Close to UA1 pin14 +5VS RA37 1 2 0_0402_5%
HDA_BIT_CLK_R 500mA LA3 RF Request
2 @ 1 place close to pin40 +VDDA_AVDD1 LA2
BLM15PX600SN1D_2P +1.8V_RUN_AUDIO_IO 2 1 RA38 1 @ 2 0_0402_5%
1
33_0201_5% 33P_0402_50V8J
RA5 @EMI@
10U_0603_10V6M
0.1U_0201_10V6K
10P_0201_25V8
DMIC_CLK_CODEC 2019-02-14 BLM15PX600SN1D_2P
8/5 RA37 POP,RA38@
CA30 RF@
10P_0201_25V8
0.1U_0201_10V6K
10U_0603_10V6M
1 1 1
CA13
CA14
CA33 RF@
1 1 1 1
+5VALW
CA11
CA12
CA17 RF@ LA15
2
2 1 2 2 2
10P_0201_25V8
2 2 2 2
1 BLM15PX600SN1D_2P DA1
8/5 Co-lay +5VALW for MS
CA18 @EMI@
2
<58> BEEP#
2
RF Request RF Request 1 PC_BEEP
3
<9> APU_SPKR
BAT54C_SOT23-3~D
UA2
B B
34 AUD_PC_BEEP 1 2 BEEP_R 1 2 PC_BEEP
6 PCBEEP CA16 0.1U_0402_10V7K RA8 1K_0201_5%
I2C-DATA 30 RING2
7 MIC2-L/RING2 1 2
SLEEVE/RING2 please keep 40 mils trace width
I2C-CLK 31 SLEEVE RA6 10K_0201_5%
15 MIC2-R/SLEEVE
<9> HDA_SYNC_R AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 mils trace width
SYNC 36 LINE1-L 1 2 HP_OUT_L
14 LINE2-L CA19 10U_0603_10V6M
<9> HDA_BIT_CLK_R BCLK 35 LINE1-R 1 2 HP_OUT_R
HDA_SDOUT_R 17 LINE2-R CA20 10U_0603_10V6M
<9> HDA_SDOUT_R SDATA-OUT 42 INT_SPK_L+
13 SPK-OUT-L+
DC-DET/EPAD 43 INT_SPK_L-
1 2 HDA_SDIN_R 16 SPK-OUT-L-
<9> HDA_SDIN0 SDATA-IN
RA7 33_0201_5% 44 INT_SPK_R-
11 SPK-OUT-R-
I2S-MCLK 45 INT_SPK_R+
10 SPK-OUT-R+
I2S-BCLK 27 HP_OUT_L 1 2 AUD_HP_OUT_L
HPOUT-L RA11 10_0402_5%
9 26 HP_OUT_R 1 2 AUD_HP_OUT_R
I2S-OUT HPOUT-R RA12 10_0402_5%
12
+3.3V_RUN_AUDIO_DVDD I2S-LRCK
330P_0402_50V8J
330P_0402_50V8J
8 1 1 +3.3V_RUN_AUDIO_DVDD BEEP_R
I2S-IN
CA21 @EMI@
CA22 @EMI@
0.1U_0402_10V7K
100P_0201_50V8J
1 GPIO2 1 2 Place close to codec
I2S-EN/SPDIF-OUT/GPIO2/DMIC-DATA34/DMIC-CLK-IN
CA24 @
RA15 10K_0201_5% 1 1
2 2
CA23
DMIC_DATA_CODEC_R
1 @ 4 2
<38> DMIC_DATA_CODEC RA9 0_0201_1% GPIO0/DMIC-DATA12
1 2 DMIC_CLK_CODEC_R 5
<38> DMIC_CLK_CODEC LA4 EMI@ BLM15PX331SN1D GPIO1/DMIC-CLK 2 2
+3.3V_RUN_AUDIO_DVDD 1 @ 2 1 2 PD# 2
RA33 10K_0201_5% CA26 1U_0402_10V6K PDB
48
1 2 PD# AUD_SENSE_A JD1
<58> EC_MUTE# RA18 0_0201_1% 47
JD2
<9> HDA_RST#_R
1 @ 2 1 2 RF Request
RA34 0_0201_1% CA27 2.2U_0402_6.3V6M
1 2 38 +1.8V_RUN_AUDIO
RA16 100K_0402_5% VREF
1 2 39 +3VLP
CA28 4.7U_0402_6.3V6M LDO1-CAP
1 2 32 33 1 2
CA29 10U_0603_10V6M MIC2-CAP 5VSTB/AUX_MODE RA17 0_0402_1%
40 +VDDA_AVDD1
AVDD1
10P_0201_25V8
SLEEVE 2 1 +MIC2-VREFO-R 29
2.2K_0402_5%12 mil MIC2-VREFO-R
CA32 RF@
RA19 20 +1.8V_RUN_AUDIO 1
RING2 2 1 +MIC2-VREFO-L 28 CPVDD/AVDD2
RA20 2.2K_0402_5%12 mil MIC2-VREFO-L 3 +3.3V_RUN_AUDIO_DVDD
DVDD
18 +1.8V_RUN_AUDIO_IO 2
DVDD-IO
1 2 CPVEE 25 41 +5V_RUN_PVDD_L
CA39 2.2U_0603_6.3V6K CPVEE PVDD1
CBN 24 46
CBN PVDD2
1 2 CBP 23 49
CA40 2.2U_0603_6.3V6K CBP G
1 2 21 37
CA44 10U_0603_10V6M LDO2-CAP AVSS1
1 2 19 22
CA48 10U_0603_10V6M LDO3-CAP AVSS2
ALC3254-VA3-CG_MQFN48_6X6
680P_0402_50V7K
680P_0402_50V7K
INT_SPK_L+ EMI@ LA11 1 2 BLM15PX121SN1D_2P-X INT_SPKR_L+ 5 7 1 1
5 GND
220P_0402_50V8J
CA50 ESD@
220P_0402_50V8J
CA51 ESD@
A 1 EMI@ 2 INT_SPK_L- EMI@ LA12 1 2 BLM15PX121SN1D_2P-X INT_SPKR_L- 4 1 1 A
4
EMI@
CC118
CC119
EMI@
RA23 0_0402_1% INT_SPK_R+ EMI@ LA13 1 2 BLM15PX121SN1D_2P-X INT_SPKR_R+ 3
INT_SPK_R- EMI@ LA14 1 2 BLM15PX121SN1D_2P-X INT_SPKR_R- 2 3
1 2 2 2
1 2 1 2 2
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
CA53 EMI@
CA54 EMI@
CA55 EMI@
1
ESD@ ESD@ QA1
EMI@ 2
G AUD_HP_NB_SENSE <73>
1 2 2N7002KW_SOT323-3 1
CA61 0.1U_0402_10V7K S CA25 @
3
EMI@
2
0.1U_0201_10V6K Add for solve
1 2 pop noise and
CA62 0.1U_0402_10V7K detect issue
EMI@
1 2
CA63 0.1U_0402_10V7K
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2020/03/05 Deciphered Date 2018/10/01 Title
GNDA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Audio Codec ALC3254
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K453P
Date: Wednesday, April 21, 2021 Sheet 56 of 121
2 1
5 4 3 2 1
Main Function:
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RSV
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K661P
Date: Wednesday, April 21, 2021 Sheet 57 of 121
5 4 3 2 1
5 4 3 2 1
Main Func = EC
+EC_VCCA
0.1U_0402_16V7K
CE4
0.1U_0402_16V7K
CE5
0.1U_0402_16V7K
CE6
0.1U_0402_16V7K
CE2
1000P_0402_50V7K
CE7
1000P_0402_50V7K
CE3
@ @ @ @ 0.1U_0402_16V7K
1
2 2 2 2 1 1
RE12
0_0402_5% +1.8V_VDD +3VALW_EC
+VCC0 2
+VCC_IO2 RE511 2 @ 1 0_0603_5%
RE526 2 1 0_0603_5%
111
117
124
D D
22
33
96
67
9
UE1
2
VCC_LPC
VCC
VCC
VCC
VCC0
PECI_VTT
AVCC
VCC_IO2
+3VALW_EC RE517
10/17 TYPEC@ @ 10K_0402_5%
INT#_TYPEC RE506 1 2 2.2K_0402_5% LPC/eSPI & MISC
MEM_ERROR_A 1 21 AC_DIS
<10> MEM_ERROR_A AC_DIS <85>
1
KBRST# 2 GA20/GPIO00 PWM0/GPIO0F 23 BEEP#
<10> KBRST# KBRST#/GPIO01 PWM1/GPIO10 BEEP# <56> PH: ESPI Type (Intel eSPI Master Attached Flash Sharing Topology)
SERIRQ 3 PWM Output 26 PWM_FAN1 SWTRAP
<10> SERIRQ SERIRQ FANPWM0/GPIO12 PWM_FAN1 <77> PL: LPC Type (The Legacy Share-SPI ROM Topology (SPI-Wire-OR mode))
LPC_FRAME# 4 27 PWM_FAN2
<8,10> LPC_FRAME# LFRAME#/ESPI_CS# FANPWM1/GPIO13 7/17 modify EC Comment wait Power modify Name PWM_FAN2 <77>
CE12 @EMI@ RE14 @EMI@ LPC_AD3 5
<8,10> LPC_AD3 LAD3/ESPI_IO3
22P_0402_50V8J 33_0402_5% LPC_AD2 7 CE11 2 1 100P_0402_50V8J ECAGND
<8,10> LPC_AD2 LAD2/ESPI_IO2
2 1 2 1 LPC_AD1 8 63 VCIN1_BATT_TEMP
<8,10> LPC_AD1 LAD1/ESPI_IO1 AD0/GPIO38 VCIN1_BATT_TEMP <82,85>
2
LPC_AD0 10 64 EC_PME# 0_0402_5% 2 @ 1 RE37
+3VALW_EC Know issue from CG13 <8,10> LPC_AD0 LAD0/ESPI_IO0 AD1/GPIO39 PCIE_WAKE# <9>
65 I_ADP_R RE516
(Need to reserve) AD2/GPIO3A I_ADP_R <85>
LPC_CLK0_EC 12 AD Input 66 AD_BID0 6.8K_0402_5%
<8,10> LPC_CLK0_EC PCICLK/ESPICLK AD3/GPIO3B
RE514 1 2 47K_0402_5% EC_RST# PLT_RST# 13 75 I_BATT_R
<8,9,10> PLT_RST# PCIRST#/GPIO05 AD4/GPIO42 I_BATT_R <85>
EC_RST# 37 76 ENBKL_APU
ENBKL_APU <8,9>
1
ECRST# AD5/GPIO43 2019/02/11: (ENE SPEC) Pull down need <8K
0.1U_0402_16V7K
CE20
1 EC_SCI# 20
<10> EC_SCI# SCI#/GPIO0E
CLKRUN# RE52 1 @ 2 CLKRUN#_R 38
<10> CLKRUN# CLKRUN#/GPIO1D
0_0402_5% RTC_DIS 14
<66> RTC_DIS GPIO07/ESPI_RST# 68 MEM_ERROR_B
2 DA0/GPIO3C MEM_ERROR_B <10>
SWTRAP Follow N3V3 MLK STR
ESD@
DA Output 70
Follow N3V3 MLK STR KSI0 55 DA1/GPIO3D 71 RGB_PER_KEY_INT#
KSI0/GPIO30 DA2/GPIO3E RGB_PER_KEY_INT# <64>
KSI1 56 72 LCD_TST
KSI1/GPIO31 DA3/GPIO3F LCD_TST <38>
KSI2 57 +5VALW
KSI[0..7] KSI3 58 KSI2/GPIO32 83 EC_MUTE#
<64> KSI[0..7] KSI3/GPIO33 SCL2/GPIO4A EC_MUTE# <56>
KSI4 59 84 USB_EN# USB_EN# 10K_0402_5% 2 @ 1 RE18
KSI4/GPIO34 SDA2/GPIO4B USB_EN# <71,73>
KSI5 60 85 EC_SMB_CK3
KSI5/GPIO35 SCL3/GPIO4C EC_SMB_CK3 <44,77>
KSI6 61 86 EC_SMB_DA3
KSO0[0..9] KSI6/GPIO36 SDA3/GPIO4D EC_SMB_DA3 <44,77>
KSI7 62 87 TP_CLK
<64> KSO0[0..9] KSI7/GPIO37 PSCLK3/GPIO4E TP_CLK <63> 10/18
KSO00 39 PS2 Interface 88 TP_DATA
KSO0/GPIO20 PSDAT3/GPIO4F TP_DATA <63>
KSO01 40
KSO[10..16] KSO02 41 KSO1/GPIO21
<64> KSO[10..16] KSO2/GPIO22
KSO03 42 97
KSO04 43 KSO3/GPIO23 SHICS#/GPIO60 98 AUX_ON
KSO05 44 KSO4/GPIO24 SHICLK/GPIO61 99
AUX_ON <73> WOL_EN(High Active)
KSO5/GPIO25 Int. K/B GPIO SHIDO/GPIO62 0.75VS_PWR_EN <78,99>
KSO06 45 109
KSO07 46 KSO6/GPIO26 Matrix VCIN0/GPIO78 VCIN0_PH <82>
KSO08 47 KSO7/GPIO27
KSO09 48 KSO8/GPIO28 119 GPU_PWR_LEVEL +3VALW_EC
KSO9/GPIO29 MISO_SHR_ROM/GPIO5B GPU_PWR_LEVEL <29>
KSO10 49 120 DGPU_PWROK
KSO10/GPIO2A MOSI_SHR_ROM/GPIO5C DGPU_PWROK <10,26,37,108>
KSO11 50 SPI ROM 126 USB_POWERSHARE_VBUS_EN 0.75VS_PWR_EN RE31 1 2 10K_0402_5%
KSO11/GPIO2B SPICLK_SHR_ROM/GPIO58 USB_POWERSHARE_VBUS_EN <73>
KSO12 51 128 USB_PWR_SHR_EN_L# 4ZONE_KB_DET# RE549 1 2 10K_0402_5%
KSO12/GPIO2C SPICS#_SHR_ROM/GPIO5A USB_PWR_SHR_EN_L# <73>
KSO13 52
KSO14 53 KSO13/GPIO2D
KSO14/GPIO2E
PU at EC side KSO15
KSO16
54
81 KSO15/GPIO2F AD6/GPIO40
73
74
GPU_ID
VGATE +3VALW_EC
KSO16/GPIO48 AD7/GPIO41 VGATE <97>
82 89 4ZONE_KB_DET# 4ZONE_KB_DET# <64>
+3VALW <112> OVUV_EC KSO17/GPIO49 LOCK#/GPIO50 90 LIGHT_BAR_DET# LIGHT_BAR_DET# <63> LIGHT_BAR_DET#10K_0402_5% 2 1 RE19
C 7/17 modify EC Comment wait Power modify Name GPIO52 91 CAP_LED# C
CAPSLED#/GPIO53 CAP_LED# <64>
RE510 1 2 2.2K_0402_5% EC_SMB_CLK1 EC_SMB_CLK1 77 GPIO 92 BAT1_LED#
<82,85> EC_SMB_CLK1 SCL0/GPIO44 WDT_LED/GPIO54 BAT1_LED# <65>
RE509 1 2 2.2K_0402_5% EC_SMB_DAT1 BATT/CHARGER EC_SMB_DAT1 78 93 BAT2_LED#
<82,85> EC_SMB_DAT1 SDA0/GPIO45 SCROLED#/GPIO55 11/19 change to 0 ohm @ BAT2_LED# <65>
RE532 1 2 2.2K_0402_5% EC_ESB_CLK EC_SMB_CK2 79 95 SYSON +3VLP
<8,29,64,68,77> EC_SMB_CK2 SCL1_BT/GPIO46 GPIO56 SYSON <89>
RE533 1 2 2.2K_0402_5% EC_ESB_DAT APU, GPU, SSD EC_SMB_DA2 80 121 VR_ON
<8,29,64,68,77> EC_SMB_DA2 Follow N3V3 MLK STR SDA1_BT/GPIO47 GPIO57/XCLK32K VR_ON <97,99>
PBTN_OUT# 15 SMBUS 127 0.75_1.8VALW_PWREN
<9> PBTN_OUT# Follow N3V3 MLK STR SCL4/GPIO08 GPIO59/DPWROK 0.75_1.8VALW_PWREN <90,99,100>
PTP_DIS# 19 ON/OFF# 100K_0402_5% 2 1 RE534
<63> PTP_DIS# SDA4/GPIO0D
EC_ESB_CLK 17
<59> EC_ESB_CLK SCL5/GPIO0B
Thermal EC_ESB_DAT 18 100 EC_RSMRST#
+3VS <59> EC_ESB_DAT SDA5/GPIO0C FANFB2/RSMRST# EC_RSMRST# <9>set OD APU power rail 1.8V
7/23 modify FANFB3/GPIO64
VCIN1/GPIO65
101
102 INT#_TYPEC
0_0402_5% 2 RE537 1
WLAN_EN
INT#_TYPEC
<52>
<44>
RE536 1 2 2.2K_0402_5% EC_SMB_CK2 GPIO 103 VCOUT1_PH RE43 1 2 0_0402_5%
VCOUT1/GPIO66 H_PROCHOT# <8,82,85>
RE535 1 2 2.2K_0402_5% EC_SMB_DA2 104 VCOUT0 RE35 1 2 0_0402_5%
teknisi-indonesia.com
VCOUT0/GPIO67 VCOUT0_PH# <87>
RE30 1 2 0_0402_5% SLP_S3#_EC 6 105 BKOFF# +3VS_SSD
<9,62> SLP_S3#_R GPIO04 GPIO68 BKOFF# <38>
PS_ID 16 106 EC_TP_INT#
<82> PS_ID OWM/GPIO0A GPIO69 EC_TP_INT# <63>
KB_LED_PWM 25 107 PCH_PWR_EN SSD_SCP# 100K_0402_5% 2 1 RE524
<64> KB_LED_PWM PWM2/GPIO11 GPIO6A PCH_PWR_EN <38,66>
TACH_FAN1 28 108 SSD_SCP#
<77> TACH_FAN1 FANFB0/GPIO14 GWG/GPIO6B SSD_SCP# <68>
TACH_FAN2 29
<77> TACH_FAN2 EC_TX 30 FANFB1/GPIO15
<52> EC_TX TXD/GPIO16 GPIO
EC_RX 31 110 HW_ACAV_IN
<52> EC_RX RXD/GPIO17 AC_IN/GPIO79 HW_ACAV_IN <9,62,85,112>
SYS_PWRGD_EC 32 112 EC_ON
<9> SYS_PWRGD_EC POWER_FAIL1/GPIO18 GPIO7A/ALW_PWR_EN EC_ON <87>
POK 34 114 ON/OFF#
<87> POK PWM3/GPIO19 GPIO7B/ON/OFFBTN# ON/OFF# <73>
NUM_LED# 36 GPIO 115 LID_CL_SIO#
+3VALW <64> NUM_LED# NUMLED#/GPIO1A GPIO7C/LID_IN LID_CL_SIO# <59>
116 SUSP#
GPIO7D SUSP# <62,78,89>
118
RE23 1 2 10K_0402_5% EC_PME# RE515 1 @ 2 0_0402_5% XCLKI 122 PECI
<10,52> SUSCLK_WLAN XCLKI/GPIO5D
RE50 1 2 0_0402_5% SLP_S5#_R 123
<9,62,85> SLP_S5# GPIO5E
125 THERMTRIP#
GPIO7E THERMTRIP# <8>
AGND
ESD@
GND
GND
GND
GND
GND
HW_ACAV_IN CE14 1 2 100P_0402_50V8J
11
24
35
94
113
69
10/18 Del R-short
ECAGND 1 2 follow Loki AMD
LE2
BLM15BD121SN1D_2P
@EMI@
SLP_S3#_R CE18 1 2 0.1U_0402_16V7K Follow N3V3 MLK STR
ESD@ @ESD@
VCOUT1_PH CE24 1 2 100P_0402_50V8J VCOUT0_PH# CE22 1 2 0.1U_0201_10V6K
@ESD@
PBTN_OUT# CE15 1 2 0.1U_0201_10V6K
ESD@
POK CE21 1 2 0.1U_0201_10V6K
@ESD@
SUSP# DE1 2 1 CK0402101V05_0402-2
AD_BID0
2
0_0402_1%
RE9
0.1U_0402_16V7K
CE9
Rb @
0_0402_1% 12K_0402 +-1% 15K_0402_1% 20K_0402_1% 2
1
GN20E GN20P
2
RE542 GN20E3@ RE542 GN20E4@ RE542 GN20E5@ RE542 GN20E7@ RE542 GN20P0@ RE542 GN20P1@ RE542 GN20P0D@
1
A GPU_ID A
2
0_0402_1%
RE542
0.1U_0402_16V7K
CE66
Rb @
0_0402_1% 12K_0402 +-1% 15K_0402_1% 20K_0402_1% 27K +-1% 0402 1/16W 33K +-1% 0402 1/16W 43K +-1% 0402 2
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P058-EC ENE-KB9022QD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
0.1(X00)
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K001P
Date: Wednesday, April 21, 2021 Sheet 58 of 121
5 4 3 2 1
5 4 3 2 1
D D
+3VALW
1
47K_0402_5%
RE530
UE10
EC_ESB_CLK 1 13
<58> EC_ESB_CLK ESB_CLK TEST_EN#
2 14
WL_RST# <52>
2
GPIO00 GPIO08/CAS_DAT
3 15
RST# GPIO09
EC_ESB_DAT 4 16
<58> EC_ESB_DAT ESB_DAT GPIO0A Lan_RST# <73>
0.1U_0402_16V7K~D
2
5 17
GPIO01 GPIO0B MASK_SATA_LED# <65>
CE63
6 18
1 GPIO02 GPIO0C/PWM0
7 19
GPIO03 GPIO0D/PWM1 ELC_BL_EN <62>
8 20 APU_AUD_PWR_EN
GPIO04 GPIO0E/PWM2 APU_AUD_PWR_EN <78>
9 21 ELC_BATT_CHG_LED#
<62> ELC_KBBL_EN GPIO05 GPIO0F/PWM3 ELC_BATT_CHG_LED# <62>
TP_EN# 10 22 ELC_BATT_LOW_LED#
<63> TP_EN# GPIO06 GPIO10/ESB_RUN# ELC_BATT_LOW_LED# <62>
MCU_PWR_EN 11 23 BaseAddOpt1 +3VALW
<64> MCU_PWR_EN GPIO07/CAS_CLK GPIO11/BaseAddOpt
12 24
GND
GND VCC +3VALW
1
.1U_0402_16V7K
1 R972
CE62
KC3810_QFN24_4X4 @ 0_0402_5%
W=60 mils
25
2
2 BaseAddOpt1
1
C R973 C
@ 0_0402_5%
+3VALW
2
1
47K_0402_5%
RE531
UE11 ARK@
EC_ESB_CLK 1 13 DVT1 9/10 add address option resistance
ESB_CLK TEST_EN#
2 14
2
GPIO00 GPIO08/CAS_DAT
3 15
RST# GPIO09
EC_ESB_DAT 4 16
ESB_DAT GPIO0A
0.1U_0402_16V7K~D
2
IR_CAM_EN 5 17
<73> IR_CAM_EN GPIO01 GPIO0B
CE64
PWR_R_EC 6 18
1 <63> PWR_R_EC GPIO02 GPIO0C/PWM0
PWR_B_EC 7 19 +3VALW
<63> PWR_B_EC GPIO03 GPIO0D/PWM1
POWER_ON_LED# 8 20
<63> POWER_ON_LED# GPIO04 GPIO0E/PWM2
1
ELC_EC# 9 21 R974
<63> ELC_EC# GPIO05 GPIO0F/PWM3 @ 0_0402_5%
LCD_VCC_TEST_EN 10 22
<38> LCD_VCC_TEST_EN GPIO06 GPIO10/ESB_RUN#
2
11 23 BaseAddOpt2
GPIO07/CAS_CLK GPIO11/BaseAddOpt
1
12 24
GND
2
2
B B
DVT1 9/10 add address option resistance
+3VLP
S5 LID CLOSE
1
RE135 RE136
100K_0201_5% @ UE6 @ 332K_0402_1%
1 8
A# VCC
LID_POWER_ON# <58>
2
2 7 CEXT_UE6
<62,73> LID_SW# B R/CEXT
2
RC759 CLR#_UE6 3 6
CLR# CEXT D
1
0_0201_5% @
DE2 4 5 LID_POWER_ON#_G 2 QE3
2 1 GND Q G
<58> LID_CL_SIO# 2N7002KW_SOT323-3
1
1
10U_0402_6.3V6M
SN74LVC1G123DCUR_VSSOP8-X 1
CE39
RB751S-40_SOD523-2-X @ RE137 S @
3
@ 1M_0201_5% @
2
2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GPIO Expander/WDT/S5 LID
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K661P
Date: Wednesday, April 21, 2021 Sheet 59 of 121
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RSV
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K661P
Date: Wednesday, April 21, 2021 Sheet 60 of 121
5 4 3 2 1
5 4 3 2 1
1K
1K
+3VALW_PCH
MOS JDIMM1
BE26 PCH_SMBCLK MEM_SMBCLK 253 JDIMM2
MOS
BF26 PCH_SMBDATA MEM_SMBDATA 254
D D
1K
53 XDP
1K
+3VALW_PCH
51
em
oC
ek
a
tH
L
BF25 SML0CLK
-H
CP
BE24 SML0DATA
1K
1K
+3VALW_PCH
MOS
BF27 SML1CLK
MOS
BE27 SML1DATA
1.8K
4.7K
1.8K
+1V8_AON
4.7K
+3VS
N-MOS UG8
B62 GPU_THM_SMBCLK VGA_SMB_CK2 BJ8 GPU 0x9E
N-MOS
A59 GPU_THM_SMBDAT VGA_SMB_DA2 BH8
4.7K 2.2K
4.7K
+3VALW_EC 2.2K
+TP_VDD
UT1
MOS Titan Ridge
B B51 DAT_TP_SIO_I2C_CLK I2C_1_SCL_R 6 JTP1 TBD B
MOS
A48 CLK_TP_SIO_I2C_DAT I2C_1_SDA_R 7 V1 V2
EM
1C
15
5
2.2K 2.2K
2.2K
+3V_VSYS 0x08 2.2K
+3V_VSYS
UT34
A58 UPD1_SMBCLK UPD1_SMBCLK 17 CCG5 4 TBT_I2C_SCL
B61 UPD1_SMBDAT UPD1_SMBDAT 16 3 TBT_I2C_SDA
4.7K
4.7K +3VALW_EC
0 ohm PUB1
B27 PBAT_CHG_SMBCLK SCL_CHG 22 PWR
0 ohm TBD
A25 PBAT_CHG_SMBDAT SDA_CHG 21 Charger
100 ohm
A
CLK_SMB 7 PBATT1 TBD A
100 ohm
DAT_SMB 6
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SMBus Block Diagram
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K661P
Date: Wednesday, April 21, 2021 Sheet 61 of 121
5 4 3 2 1
5 4 3 2 1
1
0.1U_0201_10V6K
0.1U_0201_10V6K
1U_0201_6.3V6M
1U_0201_6.3V6M
0.1U_0201_10V6K
1 1 1 1 1
CEL1
CEL2
CEL5
CEL6
CEL7
REL1 @
HC
mo
r
10K_0201_5%
P
F
2 2 2 2 2 1 @ 2 SIO_SLP_S0#_ELC
<58,78,89> SUSP#
2
REL43 0_0201_1%
<9> ELC_BOOT_MODE
D D
1
1 2
<59> ELC_KBBL_EN
REL56 0_0201_1% REL2
TO
WH
ed
oo
ao
OB
2.2K_0201_5%
bb
l
00
==
10
rr
TO
ed
oo
ao
OB
WS
l
2
t
+3VS +3VS +3.3V_ELC
+3.3V_ELC
1
JELC1 CONN@
OSC24M_IN_R REL3 1 EMI@ 2 0_0201_1% OSC24M_IN REL4 REL6 1 2 SYS_SWDIO
3 1 2 4 SYS_SWCLK
10K_0201_5% 10K_0201_5% 3 4 6
HC
mo
5
r
UEL1 @
P
5 6 8
2
G
7
2
1 2 OSC24M_OUT_R REL8 1 EMI@ 2 0_0201_1% OSC24M_OUT 44 9 7 8 10 ELC_RESET
REL7 10M_0201_5% 3 1 NRST 7 BOOT0 9 10
<9> ELC_RESET NRST
D
1
SJ100010200 DVT SJ100004X00 Change to SJ100010200 OSC24M_OUT 6
YEL1 CEL8 OSC24M_IN 5 PF1-OSC_OUT CVILU_CH51102M100-0P
12MHZ_12PF_X3S012000DC1H-X QEL1 4 PF0-OSC_IN
0.1U_0201_10V6K PC15-OSC32_OUT
1 3 AO3416L_SOT-23-3-X 2 +VDDA 3
2 4 PC14-OSC32_IN
1 1 9
+3.3V_ELC 8 VDDA
CEL9 CEL10 VSSA
15P_0201_50V8J 15P_0201_50V8J 48
2 2 36 VDD4 +3.3V_ELC
VDD3
01
24
VD
VDD2
do
1T
1
f
1
VDD1
/
9
i
y
for I2C Rising/Falling tuning 47
VSS3
+3.3V_ELC 35
23 VSS2 7/13 Modify
+3.3V_ELC VSS1 Close UEL1
1
C REL9 2 REL10 REL11 C
SM
PC13 100K_0201_5% UEL1
10K_0201_5% 100K_0201_5%
o
+3VLP SIO_SLP_S0#_ELC 28 38
f
r
33_0201_5%
27 PB15 PA15 37 SYS_SWCLK_R RA39 1 2 SYS_SWCLK
DEL1
2
PB14 PA14
1
LID_SW# 10K_0402_5% 2 1 RE17 26 34 SYS_SWDIO
REL12 REL13 1 2 25 PB13 PA13 33
<59,73> LID_SW# PB12 PA12 USB20_P6 <10>
1K_0402_5% 1K_0402_5% 22 32
PB11 PA11 USB20_N6 <10>
21 31 S IC STM32F070CBT6 LQFP 48P MCU GDL53
RB751S-40_SOD523-2-X 46 PB10 PA10 30 SA0000AWJB0
2
45 PB9 PA9 29 ARK@
43 PB8 PA8 17 ELC_SPI_MOSI
<63,64> I2C_DAT 42 PB7 PA7 16 ELC_SPI_MISO
<63,64> I2C_CLK PB6 PA6
41 15 ELC_SPI_CLK UEL1
40 PB5 PA5 14 ELC_SPI_CS#
39 PB4 PA4 13 BATT_LOW_LED
20 PB3 PA3 12 SLP_S3
BATT_CHG_LED 19 PB2 PA2 11 SLP_S5
ACIN# 18 PB1 PA1 10
PB0 PA0
S IC STM32F070CBT6TR LQFP 48P MCU GDL56
STM32F070CBT6TR_LQFP48_7X7 SA0000AWJC0
SIF@
SA0000AWJ70
+3.3V_ELC +3.3V_ELC
1
REL15 REL16
100K_0201_5% 100K_0201_5%
2
SLP_S3 SLP_S5
+3VALW +3.3V_ELC
3
D D
5 QEL2B 5 QEL4B
<9,58> SLP_S3#_R G <9,58,85> SLP_S5# G
B 2N7002KDW_SOT-363-6-X 2N7002KDW_SOT-363-6-X UEL3 B
5 1
S S IN OUT
4
1 2 1 1
GND
CEL11 4 3 2 @ 1 +3VALW CEL12 CEL14 +3.3V_ELC
4.7U_0402_6.3V6M EN OC REL24 0.1U_0201_10V6K 10U_0402_6.3V6M
2 SY6288C20AAC_SOT23-5-X 10K_0201_5% 2 2
+3.3V_ELC +3.3V_ELC
0.1U_0201_10V6K
1
CEL13
<59> ELC_BL_EN
1
1
100K_0201_5% 100K_0201_5% +3.3V_ELC
ARK@ REL45 UEL2
100K_0201_5% 8 1 ELC_SPI_CS# 1 REL20 2
2
3+
_V
eb
ro
ah
LE
i
DI(IO0) GND
3
.
v
33_0201_5% EMI@ REL19
6
0N
3SNONONO
4SNOFOFO
5SNOFOFO
S ONONO
2 QEL4A 5 QEL3B RC767 15_0201_1% REL17
<9,58,85,112> HW_ACAV_IN <59> ELC_BATT_LOW_LED#
2
G 2N7002KDW_SOT-363-6-X G 2N7002KDW_SOT-363-6-X 0_0402_5% @EMI@
CACAAB
wolu
tata y
I I TT
y
l f
e
b
N No
(b
te
ry
))
ARK@ SIF@ REL46
S S 33_0201_5% 7/13 Modify
1
(ln
t
r
F F
F F
1
1
@EMI@
CEL15
22P_0201_50V8J
2
+3.3V_ELC
1
REL26
A 100K_0201_5% A
ARK@
2
BATT_CHG_LED
6
D
2 QEL3A RC768
<59> ELC_BATT_CHG_LED# G 2N7002KDW_SOT-363-6-X 0_0402_5%
ARK@ SIF@
S Security Classification Compal Secret Data Compal Electronics, Inc.
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ELC (1) STM32F070CB
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K661P
Date: Wednesday, April 21, 2021 Sheet 62 of 121
5 4 3 2 1
5 4 3 2 1
DA
Main Func = ELC Main Func = Power LED Main Func = ON/OFF TRON
00 1 0
0123
DADA
DA
+5VALW
+5VALW
+3.3V_ELC +3.3V_ELC ELC_EC#
<59> ELC_EC#
1
+5VALW
5
REL27
G
1
1
10K_0201_5%
3
REL30 1 REL28
4.7K_0201_5% CEL16 100K_0201_5% S QEL8
2
ARK@ UEL4 ARK@ 0.1U_0201_10V6K PWR_R_7313# 4 3 AO3419L_SOT23-3
S
PWR_R# <73>
D
ARK@
2
24 27 2 Power_LED 2
RESET Vcc QEL5B
1
G
3 TRON_TOP_R_DRV# 2N7002KDW_SOT-363-6-X REL29
D
25 OUT0 4 TRON_TOP_G_DRV#
D
+5VS D
<62,64> I2C_CLK SCL OUT1 1K_0201_5%
6
26 5 TRON_TOP_B_DRV# D
1
<62,64> I2C_DAT SDA OUT2 6 TRON_BOT_R_DRV# 2 QEL2A
<59> POWER_ON_LED#
2
AD0_2 31 OUT3 8 TRON_BOT_G_DRV# G
A0 OUT4 2N7002KDW_SOT-363-6-X
AD1_2 32 9 TRON_BOT_B_DRV# +PWR_LED
AD2_2 1 A1 OUT5 10 PWR_R_7313# S JTRON1 CONN@
1
BAT1_LED#
1
A2 OUT6
6
AD3_2 2 11 PWR_G_7313# D 1
A3 OUT7 14 PWR_B_7313# 2 QEL5A CEL17 2 1
OUT8 <59> PWR_R_EC G 2
12 15 ALIEN_LED_R_DRV# 2N7002KDW_SOT-363-6-X 0.1U_0201_10V6K 3
N.C. OUT9 ALIEN_LED_R_DRV# <38> 3
1
13 16 ALIEN_LED_G_DRV# 2 TRON_TOP_R_DRV# 4
N.C. OUT10 ALIEN_LED_G_DRV# <38> S 4
28 17 ALIEN_LED_B_DRV# REL32 TRON_TOP_G_DRV# 5
ALIEN_LED_B_DRV# <38>
1
29 N.C. OUT11 19 10K_0201_5% TRON_TOP_B_DRV# 6 5
30 N.C. OUT12 20 TRON_BOT_R_DRV# 7 6
N.C. OUT13 21 TRON_BOT_G_DRV# 8 7
2
OUT14 8
1
22 TRON_BOT_B_DRV# 9
REL37 OUT15 10 9
10K_0201_5% 7 23 11 10
ARK@ 18 GND GND 33 12 11
GND GND +5VALW +5VALW 13 12
2
14 GND1
TLC59116FIRHBR_VQFN32_5X5 ELC_EC# ELC_EC# GND2
1
ACES_50208-01201-P01
5
REL36 REL38
G
SP01001UP00
10K_0201_5% 10K_0201_5%
2
PWR_G_7313# 4 3 PWR_B_7313# 4 3
S
PWR_G# <73> PWR_B# <73>
D
+3.3V_ELC
QEL6B QEL7B
1
2N7002KDW_SOT-363-6-X REL39 2N7002KDW_SOT-363-6-X REL40
1K_0201_5% 1K_0201_5%
1
1
REL48 REL49 REL50 REL51
2
Reference LS-H665P 4.7K_0201_5% 4.7K_0201_5% 4.7K_0201_5% 4.7K_0201_5%
@ @ ARK@ @
BAT2_LED#
2
6
C D D C
AD0_2 2 QEL6A 2 QEL7A
G <59> PWR_B_EC G
2N7002KDW_SOT-363-6-X 2N7002KDW_SOT-363-6-X
AD1_2
1
S S
1
AD2_2 REL41
10K_0201_5%
AD3_2
2
1
1
1 R970 2 7/29 add
TP_WAKE@ 0_0201_1%
1
R136 @
R15 R16 0_0402_5%
2.2K_0201_5% 2.2K_0201_5%
2
B B
+5VS
CEL18
2
S
3 1 1 2 8
D
<62,63,64> I2C_DAT 8
1 7
<62,63,64> I2C_CLK 7
TP_WAKE@ R137 +3VS 6
C22 Q27 TP_WAKE@ 100_0603_1% 5 6
G
2
5
1
.1U_0402_16V7K TR PJ2301 1P SOT23-3 REL44 1 2 0_0201_1% 4
2 D <58> LIGHT_BAR_DET# 4
SB000006R10 Q4 3
Close to UE1 +3VS_TOUCH
<59> TP_EN#
1 2 TP_ON#_GATE 2 2N7002K_SOT23-3 2 3
2
G 1
TP_CLK 4.7K_0402_5% 1 2 R134 R135 1
S
EC/PS2 TP_DATA 4.7K_0402_5% 1 2 R133 20K_0402_1% TWVM_FPC0511-12RC-TAGHT
3
SP01002U100
C21
100P_0402_50V8J
1 1
+3VS_TOUCH
ESD@
ESD@
2 2
1
R141
2.2K_0201_5%
2
Q28 TP_CLK 1
G
<58> TP_CLK 1
<9> TP_I2C_INT#_APU
1 3 TP_I2C_INT# SDAN_606043-008001 Security Classification Compal Secret Data Compal Electronics, Inc.
2020/03/05 2018/02/05 Title
D
<58> KSI[0..7]
1
R28
3
100K_0201_5% JKB1 CONN@
2
G
Q7 1
R2 <9> KB_DET# 1
DDTA144VCA-7-F_SOT23-3 KSI7 2
2
CAP_LED# 3 1 CAP_LED_R# 2 KSI6 3 2
<58> CAP_LED# 1 3
10P_0201_25V8
KSI4 4
D
4
C14
R1
KSI2 5
KSI5 6 5
Q6 2 KSI1 7 6
AO3416L_SOT-23-3-X 7
RF@
KSI3 8
1
KSI0 9 8
CAP LED Control KSO05 10 9
10
CAP_LED_Q 1 2 CAP_LED KSO04 11
LOW actived from KBC GPIO R29 1K_0402_5% KSO07 12 11
KSO06 13 12
+3VS KSO08 14 13
+5VS KSO03 15 14
KSO01 16 15
KSO02 17 16
17
1
KSO00 18
R942 KSO12 19 18
19
3
100K_0201_5% KSO16 20
20
2
G
Q85 KSO15 21
R2
KSO13 22 21
DDTA144VCA-7-F_SOT23-3
2
NUM_LED# 3 1 NUM_LED_R# 2 KSO14 23 22
<58> NUM_LED# 23
KSO09 24
D
R1
KSO11 25 24
KSO10 26 25
Q8 CAP_LED 27 26
AO3416L_SOT-23-3-X NUM_LED 28 27
1
C 29 28 31 C
NUM LED Control 30 29 GND1
30 GND2
32
NUM_LED_Q 1 2 NUM_LED
LOW actived from KBC GPIO R31 1K_0402_5%
ACES_51631-03001-W01
DC022004240
+5VS +5VALW
R980 1 2 0_0603_5%
LE3 EMI@
1 2 USB20_N7_R R981 1 @ 2 0_0603_5% JMCU1 CONN@
<10> USB20_N7 1 2 1
2 1
4 3 USB20_P7_R +3.3V_ELC 3 2
<10> USB20_P7 4 3 +3VALW 3
4
DLM0NSN900HY2D_4P-X 5 4
PD on MCU/B side 6 5
6
7
<58> 4ZONE_KB_DET# 7
1
8
RE129 9 8
USB20_N7_R 10 9
10K_0201_5% 10
USB20_P7_R 11
12 11
2
13 12
13
SIF only <58> RGB_PER_KEY_INT#
14
15 14
15
16
<8,29,58,68,77> EC_SMB_CK2 16
17
<8,29,58,68,77> EC_SMB_DA2 18 17
B Keyboard Backlight <59> MCU_PWR_EN
<62,63> I2C_CLK
19 18
19
B
20
<62,63> I2C_DAT 20
KB Backlight Power Consumption: 400mA max.
21
+5VS +5V_KB_BL GND
TVNST52302AB0_SOT523-3-X
TVNST52302AB0_SOT523-3-X
TVNST52302AB0_SOT523-3-X
AZC199-02S.R7G_SOT23-3-X
22
F2 GND
2
1 2
DK1 @ESD@
DK2 ESD@
DK3 ESD@
DK4 ESD@
3
2
0.5A_6V_0402L050SLKR SDAN_606044-020041-X
1 1 SP01002UU00
1
C11 C12 RF@
1
0.1U_0201_10V6K 10P_0201_25V8
2 2
JKBBL1 CONN@
1
1 2 KB_LED_DET 2 1
<9> KB_BL_DET
R26 17.4K_0201_1% 3 2 8/3 SP01002BY00
4 3
1
KB_BL_CTRL#
R27 4 Change to SP01002HP00
1
10K_0201_5%
C56 RF@ 5
GND 6
10P_0201_25V8
2
2 GND
1
CVILU_CF61042D0R0-10-NH
D Q5 SP01002HP00
2 AO3416L_SOT-23-3-X
<58> KB_LED_PWM
G
S
3
7/30 modify
A Update footprint A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MCU Per Key/4 Zone KB
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K661P
Date: Wednesday, April 21, 2021 Sheet 64 of 121
5 4 3 2 1
5 4 3 2 1
BJT
+3VALW
R1: 47 K +5VALW
D
Low actived from KBC GPIO R2: 10 K D
2
G
3
R2 Q19
DDTA144VCA-7-F_SOT23-3
1 6 CHG_AMBER_LED_R# 2
S
<58> BAT1_LED#
D
<59> MASK_SATA_LED# 1 @ 2
R1
R121 10K_0201_5%
Q20A
2N7002KDW_SOT-363-6-X
1
2
5
G
3
SATA_LED#_R 3 1 BATT_WHITE_LED_R# +AMBER_LED_BAT
S R2
D
4 3 BATT_WHITE_LED_R# 2 Q23
S
<58> BAT2_LED#
D
Q22 R1 DDTA144VCA-7-F_SOT23-3
AO3416L_SOT-23-3-X Q20B
2N7002KDW_SOT-363-6-X
C C
1
+WHITE_LED_BAT
R123
100K_0201_5%
+3VS
2
1
SATA_LED#_R
B R124 B
100K_0201_5%
2
D
5 Q25B
G 2N7002KDW_SOT-363-6-X
S
4
6
D
<9> SATA_LED# R122 1 2 0_0201_1% 2 Q25A
G 2N7002KDW_SOT-363-6-X
<68> SSD_DAS#
S
1
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LED (SIF)
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K661P
Date: Wednesday, April 21, 2021 Sheet 65 of 121
5 4 3 2 1
5 4 3 2 1
D D
1 +3VALW
UC20
D 5 1
C +3VALW IN OUT +3VALW_APU C
2 RTC_DIS
RTC_DIS <58>
G 2
GND
1
S
Q9 R30 4 3 RC156 1 2 10K_0402_5%
<38,58> PCH_PWR_EN
3
2N7002K_SOT23-3 100K_0402_5% EN OC
SY6288C20AAC_SOT23-5
2
1
0.1U_0603_25V7K
CC110
2
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RTC Gen9
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K661P
Date: Wednesday, April 21, 2021 Sheet 66 of 121
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
C C
B B
www.teknisi-indonesia.com
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RSV
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K661P
Date: Wednesday, April 21, 2021 Sheet 67 of 121
5 4 3 2 1
5 4 3 2 1
PCIe
JSSD1 , 2280 +3VS_SSD1
JSSD1 CONN@
+3VS_SSD +3VS_SSD1 1 2
3 GND3 3P3VAUX_1 4
JP2 PJP@ 5 GND4 3P3VAUX_2 6
1 2 200 mils <6> PCIE_CRX_DTX_N3 7 PERn3 NC1 8 RS1 1 2 0_0201_1%
SSD_SCP# <58>
1 2 <6> PCIE_CRX_DTX_P3 9 PERp3 NC2 10 RS2 1 2 0_0201_1%
GND5 DAS/DSS# SSD_DAS# <65>
10P_0201_25V8
0.1U_0402_10V7K
1000P_0402_50V7K
22U_0603_6.3V6M
JUMP_43X118 11 12
<6> PCIE_CTX_C_DRX_N3 PETn3 3P3VAUX_3
If UZ3 pop-up , JP2 no need to short 1 1 1 1 13 14
D <6> PCIE_CTX_C_DRX_P3 PETp3 3P3VAUX_4 D
CS4 RF@
CS1
CS2
CS3
15 16
17 GND6 3P3VAUX_5 18
<6> PCIE_CRX_DTX_N2 19 PERn2 3P3VAUX_6 20
2 2 2 2 <6> PCIE_CRX_DTX_P2 21 PERp2 NC3 22
23 GND7 NC4 24
<6> PCIE_CTX_C_DRX_N2 PETn2 NC5
25 26
<6> PCIE_CTX_C_DRX_P2 PETp2 NC6
27 28
29 GND8 NC7 30
PCIE SSD <6> PCIE_CRX_DTX_N1 31 PERn1 NC8 32
<6> PCIE_CRX_DTX_P1 33 PERp1 NC9 34
35 GND9 NC10 36
<6> PCIE_CTX_C_DRX_N1 PETn1 NC11
37 38
<6> PCIE_CTX_C_DRX_P1 PETp1 DEVSLP
39 40 RS8 1 2 0_0201_1% SSD_I2C_CLK
41 GND10 NC12 42 RS9 1 2 0_0201_1% SSD_I2C_DAT
<6> PCIE_CRX_DTX_N0 43 PERn0/SATA-B+ NC13 44 RS10 1 2 0_0201_1% SSD_ALERT#
<6> PCIE_CRX_DTX_P0 PERp0/SATA-B- NC14
DS
45 46
S
47 GND11 NC15 48
J
33P_0402_50V8J
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
150U_B2_6.3VM_R35M
1
1 1 1 1 1
+
CS21
CS22
CS23
CS24
CS25
CS26 67 68 SUSCLK_SSD1
2 2 2 2 2 2 NC SUSCLK(32kHz) TC7
@ @ +3VS_SSD1 RS17 1 2 10K_0201_5% 69 70
71 PEDET(NC-PCIE/GND-SATA) 3P3VAUX_7 72
73 GND14 3P3VAUX_8 74
75 GND15 3P3VAUX_9
GND16
76 78
77 GND1 NPTH1 79
GND2 NPTH2
+1.8V_VDD
C LOTES_YPCI0020-P001A +3VS C
DC04000OM00 SSD_I2C_CLK 1 @ 2
SSD_I2C_DAT RS14 1 @ 2 4.7K_0201_5%
SSD_ALERT# RS15 1 @ 2 4.7K_0201_5%
RS16 10K_0201_5%
2
G
6 1 SSD_I2C_CLK
S
<8,29,58,64,77> EC_SMB_CK2
D
QS1A
2N7002KDW_SOT-363-6-X
5
@
G
+3VS_SSD +3VS_SSD2
JP3 PJP@
1 2 3 4 SSD_I2C_DAT
S
1 2 <8,29,58,64,77> EC_SMB_DA2
D
JUMP_43X118 QS1B
If UZ3 pop-up , JP2 no need to short 2N7002KDW_SOT-363-6-X
@
DS
SJ
33P_0402_50V8J
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
150U_B2_6.3VM_R35M
1 JSSD2 CONN@
1 1 1 1 1 1 2
+ GND3 3P3VAUX_1
CS27
CS28
CS29
CS30
CS31
CS32
3 4
5 GND4 3P3VAUX_2 6
<6> PCIE_CRX_DTX_N11 7 PERn3 NC1 8 RS5 1 2 0_0201_1% SSD_SCP#
2 2 2 2 2 @ 2 @ <6> PCIE_CRX_DTX_P11 9 PERp3 NC2 10 RS6 1 2 0_0201_1% SSD_DAS#
11 GND5 DAS/DSS# 12
<6> PCIE_CTX_C_DRX_N11 PETn3 3P3VAUX_3
13 14
B <6> PCIE_CTX_C_DRX_P11 PETp3 3P3VAUX_4 B
15 16
17 GND6 3P3VAUX_5 18
<6> PCIE_CRX_DTX_N10 19 PERn2 3P3VAUX_6 20
<6> PCIE_CRX_DTX_P10 21 PERp2 NC3 22
23 GND7 NC4 24
<6> PCIE_CTX_C_DRX_N10 PETn2 NC5
25 26
PCIE/SATA SSD <6> PCIE_CTX_C_DRX_P10
27 PETp2 NC6 28
29 GND8 NC7 30
<6> PCIE_CRX_DTX_N9 31 PERn1 NC8 32
<6> PCIE_CRX_DTX_P9 33 PERp1 NC9 34
35 GND9 NC10 36
<6> PCIE_CTX_C_DRX_N9 PETn1 NC11 DEVSLP0 <9>
37 38
<6> PCIE_CTX_C_DRX_P9 PETp1 DEVSLP
39 40 RS11 1 2 0_0201_1% SSD_I2C_CLK
41 GND10 NC12 42 RS12 1 2 0_0201_1% SSD_I2C_DAT
<6> PCIE_CRX_DTX_P8 43 PERn0/SATA-B+ NC13 44 RS13 1 2 0_0201_1% SSD_ALERT#
<6> PCIE_CRX_DTX_N8 45 PERp0/SATA-B- NC14 46
RS155 1 @ 2 0_0402_5% 47 GND11 NC15 48
SATA SSD SATA_2 <6> PCIE_CTX_C_DRX_N8
49 PETn0/SATA-A- NC16 50 SSD_PCIE_RST#
<6> PCIE_CTX_C_DRX_P8 PETp0/SATA-A+ PERST#
51 52
+3VALW 53 GND12 CLKREQ# 54 CLKREQ_PCIE#4 <10>
<10> CLK_PCIE_N4 REFCLKN PEWake#
55 56
<10> CLK_PCIE_P4 REFCLKP NC17
57 58
GND13 NC18
FH51S
5
APU_PCIE_RST# 1
P
GND14 3P3VAUX_8
1
76 78
2
77 GND1 NPTH1 79
GND2 NPTH2
0 SATA
1 PCIe
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2020/03/05 Deciphered Date 2018/02/05 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NGFF SSD x2
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K453P
Date: Wednesday, April 21, 2021 Sheet 68 of 121
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RSV
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K661P
Date: Wednesday, April 21, 2021 Sheet 69 of 121
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RSV
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K661P
Date: Wednesday, April 21, 2021 Sheet 70 of 121
5 4 3 2 1
5 4 3 2 1
+5V_USB
+5VALW
1 1
CU3 UU1 SA000079400 Change to SA00007AO00 +5V_USB
10U_0402_6.3V6M CU4
1U_0402_10V6K
2 2
D D
100U_1206_6.3V6M
100U_1206_6.3V6M
10U_0402_6.3V6M
UU1
W=80 mils
CU8
1 1 1 1
OUT
CU6
CU7
5
IN 2
4 GND @
<58,73> USB_EN# ENB 2 2 2
3
OCB USB_OC1# <10>
1
SY6288D20AAC_SOT23-5 1
CU13
0.1U_0201_10V6K @ CU14
2
0.1U_0201_10V6K
2
LU1 EMI@
4 3 USB20_P1_R
<10> USB20_P1 4 3
1 2 USB20_N1_R +5V_USB
<10> USB20_N1 1 2
C C
DLM0NSN900HY2D_4P-X JUSB1 CONN@
USB3_CTX_C_DRX_P1_L 9
RU2 1 @EMI@ 2 0_0201_1% 1 SSTX+
USB3_CTX_C_DRX_N1_L 8 VBUS
USB20_P1_R 3 SSTX-
7 D+
RU3 1 @EMI@ 2 0_0201_1% USB20_N1_R 2 GND 10
USB3_CRX_C_DTX_P1_L 6 D- GND 11
4 SSRX+ GND 12
DLM0NSN500HY2D_4P USB3_CRX_C_DTX_N1_L 5 GND GND 13
1 2 USB3_CTX_C_DRX_P1 4 3 USB3_CTX_C_DRX_P1_L SSRX- GND
<10> USB3_CTX_DRX_P1 4 3
C724 0.22U_0201_6.3V6K LOTES_AUSB0182-P001A
DC23300K7B0
<10> USB3_CTX_DRX_N1 1 2 USB3_CTX_C_DRX_N1 1 2 USB3_CTX_C_DRX_N1_L
C725 0.22U_0201_6.3V6K 1 2
LU2 EMI@
USB20_N1_R
RU4 1 @EMI@ 2 0_0201_1% USB20_P1_R
7/13 Modify
2
RU5 1 @EMI@ 2 0_0201_1%
ESD@ DU2
B PESD5V0U2BT_SOT23-3-X B
DLM0NSN500HY2D_4P
<10> USB3_CRX_DTX_P1 1 2 USB3_CRX_C_DTX_P1 4 3 USB3_CRX_C_DTX_P1_L
CT130 0.33U_0201_6.3V6M 4 3
1
<10> USB3_CRX_DTX_N1 1 2 USB3_CRX_C_DTX_N1 1 2 USB3_CRX_C_DTX_N1_L
CT129 0.33U_0201_6.3V6M 1 2
LU3 EMI@
DU1 ESD@
USB3_CRX_C_DTX_N1_L 1 1 10 9 USB3_CRX_C_DTX_N1_L
USB3_CRX_C_DTX_P1_L 2 2 9 8 USB3_CRX_C_DTX_P1_L
USB3_CTX_C_DRX_N1_L 4 4 7 7 USB3_CTX_C_DRX_N1_L
USB3_CTX_C_DRX_P1_L 5 5 6 6 USB3_CTX_C_DRX_P1_L
3 3
A AZ1045-04FR7_DFN2510P10E10-9-X A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB3.1 TypeA Gen1
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K661P
Date: Wednesday, April 21, 2021 Sheet 71 of 121
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RSV
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K661P
Date: Wednesday, April 21, 2021 Sheet 72 of 121
5 4 3 2 1
5 4 3 2 1
RW36 1 @ 2 0_0402_5%
D D
+3VALW
5
1
P
teknisi-indonesia.com
<9,26,52,68> APU_PCIE_RST# IN1 4 Lan_RST_R#
2 O
<59> Lan_RST# IN2
1
UW7 SA0000BIP00
3
1
MC74VHC1G08DFT2G_SC70-5 RW37
RW38 100K_0402_5% +1.8V_VDD
10K_0402_5%
2
2
ALC_INT# 10K_0201_5% 2 1 RV45
PX_INT# 10K_0201_5% 2 1 RV46
PX_DIS# 10K_0201_5% 2 1 RV47
B Key CONN
JIO2
SP01002TO00
SDAN_606044-040041
1
3 GND 3P3VAUX
2
4
+19VB 0630 update
<59> IR_CAM_EN GND 3P3VAUX
42 5 6
<12> IRCAM_DET#
41 GND2 GND FULL_CARD_PWR_OFF#
40 GND1 0630 update <12> PX_INT#
7
9 USB_D+ W_DISABLE1#
8
10
+PWR_LED
<12> ALC_INT#
<6> PCIE_CRX_DTX_N4 39 40 11 USB_D- LED1#
<12> PX_DIS#
C <6> PCIE_CRX_DTX_P4 38 39 GND
C
37 38
to LAN <6>
<6>
PCIE_CTX_C_DRX_N4
PCIE_CTX_C_DRX_P4
36 37
35 36 20 +3VALW
34 35 21 AUDIO0 22
<10> CLK_PCIE_N2 33 34 23 GND_WWAN AUDIO1 24
<10> CLK_PCIE_P2 32 33 <10> USB20_N4 25 RESERVED AUDIO2 26 +5VALW
31 32 <10> USB20_P4 27 RESERVED AUDIO3 28
30 31 29 GND IUM_RFU 30
<10> USB3_CRX_DTX_N4
<9> LAN_WAKE# 29 30 31 USB3_TX- UIM_RESET 32
<10> USB3_CRX_DTX_P4
28 29 33 USB3_TX+ UIM_CLK 34
<10> CLKREQ_PCIE#2
Lan_RST_R# 27 28 35 GND UIM_DATA 36
<10> USB3_CTX_DRX_N4
<58> AUX_ON 26 27 37 USB3RX- UIM_PWR 38
<10> USB3_CTX_DRX_P4
25 26 39 USB3RX+ NC 40
+3VS 24 25 41 GND GNSS0 42
<10> USB3_CRX_DTX_N5 LID_SW# <59,62>
23 24 43 NC GNSS1 44
<10> USB3_CRX_DTX_P5 USB_OC3# <10>
+3VALW 22 23 45 NC GNSS2 46
USB_EN# <58,71>
21 22 47 GND GNSS3 48
<10> USB3_CTX_DRX_N5 USB_OC2# <10>
20 21 49 NC GNSS4 50
<10> USB3_CTX_DRX_P5 USB_POWERSHARE_VBUS_EN <58>
19 20 51 NC NC 52
USB_PWR_SHR_EN_L# <58>
+AMBER_LED_BAT 18 19 53 GND NC 54
ON/OFF# <58>
+WHITE_LED_BAT 17 18 <10> USB20_N5 55 NC NC 56 +3VLP
16 17 <10> USB20_P5 57 NC NC 58
15 16 59 GND NC 60 +3VS
14 15 <10> USB20_N3_IO 61 ANTCTL0 COEX3 62
13 14 <10> USB20_P3_IO 63 ANTCTL1 COEX2 64
12 13 <9> I2C_0_SDA 65 ANTCTL2 COEX1 66 +CAM_VCC
GNDA 11 12 67 ANTCTL3 SIM_DET 68
<9> I2C_0_SCL
10 11 RESET# SUSCLK
9 10 0630 update <38> DMIC_DATA_R
69
71 PEDET 3P3VAUX
70
72
PWR_R#
PWR_G#
<63>
<63>
<56> AUD_HP_NB_SENSE
8 9 73 GND 3P3VAUX 74 PWR_B# <63>
<56> AUD_HP_OUT_L1 <38> DMIC_CLK_R
7 8 75 GND 3P3VAUX
6 7 OC_USB3 76
<56> SLEEVE_R
5 6 GND1 77
4 5 GND2
<56> RING2_R
3 4 CONN@ LOTES_APCI0103-P001A
<56> AUD_HP_OUT_R1
2 3
GNDA 1 2
SP07001BL00
0630 update
B 1 B
JIO1 CONN@
SW1
ON/OFF# 1 2
TST71-N-220-T170-S017_2P
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IO Board CONN
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K661P
Date: Wednesday, April 21, 2021 Sheet 73 of 121
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DOCK(RSVD)
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K661P
Date: Wednesday, April 21, 2021 Sheet 74 of 121
5 4 3 2 1
5 4 3 2 1
(6) +3VALW
(3) +19VB
(3) +19VB
(2) +SDC_IN VOUT
VIN CHARGER 10k-ohm
(4) HW_ACAV_IN
ACOK (3) +3VLP (6) POK
D D
(5) EC_ON
(3) +19VB
+RTC_CELL
VIN
VOUT (8) +1.8VALW
(1) +3.3V_BAT_LDO
+1.8VALW
(3) +3VLP
(7) 0.75_1.8VALW_PWREN PG
EN
(5) EC_ON
VBAT GPIO79 GPIO7A (3) +19VB
AC_IN ALW_PWR_EN
VIN
VOUT (9) +0.75VALW
(6) +3VALW 0-ohm (6) +3VALW_APU
+0.75VALW
(6) +3VALW_APU VDD_33_S5 (6) POK GPIO19 GPIO59 (7) 0.75_1.8VALW_PWREN RC PG
PWM3 DPWROK
EN (3) +19VB
delay
(8) +1.8VALW 0-ohm (8) +1.8VALW_APU
VIN
VOUT (16) +2.5V_MEM
C
(8) +1.8VALW_APU VDD_18_S5 C
+2.5V_MEM
RSMRST_L (11) EC_RSMRST#
RSMRST#
PIN100
GPIO7B
ON/OFFBTN#
(10) PWRBTN# External PWRBTN (3) +19VB (15) SYSON
EN PG
SLP_S5#
(13) SLP_S5# GPIO5E GPIO56 (15) SYSON S5 VOUT (16) +1.2V_DDR
(8) +1.8VALW 0-ohm (8) +VDDIO_AUDIO
+1.2V_DDR
(8) +VDDIO_AUDIO VDDIO_AUDIO +0.6V_DDR
SLP_S3# (14) SLP_S3# GPIO04 GPIO7D (16) SUSP# S3 VOUT (17) +0.6V_DDR_VTT
(16) +1.2V_DDR
VDDIO_MEM_S3
+5VS
+3VS
VIN
VOUT (17) +3VS
(9) +0.75VALW
RESET_L (22) APU_RST#
VIN
(3) +19VB
+APU_SOC
GPIO41 (20) VGATE PGOOD
VOUT (20) +VDDCR_SOC
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Sequence Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K661P
Date: Wednesday, April 21, 2021 Sheet 75 of 121
5 4 3 2 1
5 4 3 2 1
Main Function:
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RSV
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K661P
Date: Wednesday, April 21, 2021 Sheet 76 of 121
5 4 3 2 1
5 4 3 2 1
+3VS
1
10K_0201_5%
10K_0201_5%
10K_0201_5%
10U_0603_25V6M
2
RF1
RF2
RF3
R977 1 2 4.7K_0201_5% EC_SMB_CK3_Q
PC
oC
tn
A
JFAN2
2
6
U
F
N
r
l
1 2 G2 5
+3VS G1
C32 0.1U_0201_10V6K 4
3 4
<58> PWM_FAN1 3
2 1 2
<58> TACH_FAN1 2
1
1
dA
rd
01
10
01
x0
h8
se
DF1
9
0
LRB751V-40T1G_SOD323-2-X TWVM_WTB1220-04RD-TAGHD
b
(
x
)
SP02001RJ00
CONN@
NCT7718_DXP_U4 +3VS
U4
1 1 1 8 EC_SMB_CK3_Q
VDD SCL
1
C
Q10 2 C33 @ C34 2 7 EC_SMB_DA3_Q
LMBT3904LT1G_SOT23-3 B 2200P_0201_25V7K D+ SDA
C 470P_0402_50V7K C
2
E 2 2 3 6 ALERT#_U4
G
3
NCT7718_DXN_U4 D- ALERT#
T_CRIT# 4 5
T_CRIT# GND
GPU VRAM CPU OTP
EC_SMB_CK3_Q 1 6
S
EC_SMB_CK3 <44,58>
D
NCT7718W_MSOP8
QS2A
Layout Note: 2N7002KDW_SOT-363-6-X
Layout Note:
5
C34 close U4 address same as APU
G
DXN and DXP routing width and spacing is 10 mil / 10
mil.
EC_SMB_DA3_Q 4 3
S
EC_SMB_DA3 <44,58>
D
QS2B
2N7002KDW_SOT-363-6-X
dA
hA
rd
01
10
01
x1
se
9
0
s +3VS +12V_FAN
b
(
x
)
+5VS
B NCT7718_DXP_U3 B
+3VS
1
1 1
1
C U3 CF2
1
10K_0201_5%
10K_0201_5%
10K_0201_5%
Q26 2 C53 @ C54 2 1 1 2 10U_0603_25V6M
D+ VCC 2
RF4
RF5
RF6
LMBT3904LT1G_SOT23-3 B 470P_0402_50V7K 2200P_0201_25V7K C55 0.1U_0201_10V6K
E 2 2 3 6 ALERT#_U3
3
PG
D- ALERT#
oC
tn
NCT7718_DXN_U3
o
EC_SMB_CK2 8 4 T_CRIT#_U3 JFAN1
U
F
N
r
l
<8,29,58,64,68> EC_SMB_CK2
2
SCL THERM# 6
GPU Core CPU Core G2
EC_SMB_DA2 7 5 5
<8,29,58,64,68> EC_SMB_DA2 SDA GND G1
4
3 4
Layout Note: F75399M_MSOP8
<58> PWM_FAN2
2 1 2 3
Layout Note: C54 close U3
<58> TACH_FAN2
1 2
DF2 1
DXN and DXP routing width and spacing is 10 mil / 10 LRB751V-40T1G_SOD323-2-X TWVM_WTB1220-04RD-TAGHD
mil. SP02001RJ00
CONN@
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FAN/Thermal
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K661P
Date: Wednesday, April 21, 2021 Sheet 77 of 121
5 4 3 2 1
5 4 3 2 1
+5VALW +5VS_OUT
1
JP4
1
PJP@
2
2
JUMP_43X118
+1.8VS/+3V_SSD for System
UZ2
CZ6 2 1 1 14 1 2 +1.8VALW_GPU +1.8VS
2 VIN1_1 VOUT1_1 13 CZ7 0.1U_0201_10V6K
1U_0201_6.3V6M VIN1_2 VOUT1_2
RZ1 1 2 0_0402_5% 5VS_ON 3 12 1 2 UZ3
ON1 CT1 CZ8 470P_0402_50V7K CZ13 2 1 1 14 1 2
4 11 2 VIN1_1 VOUT1_1 13 CZ17 0.1U_0201_10V6K
VBIAS GND 1U_0201_6.3V6M VIN1_2 VOUT1_2
RZ2 1 2 0_0402_5% 3VS_ON 5 10 1 2 RZ5 1 2 0_0402_5% 3 12 1 2
<58,62,78,89> SUSP# ON2 CT2 ON1 CT1
CZ9 2200P_0402_25V7K CZ16 470P_0402_50V7K
+3VALW 6 9 +3VS_OUT +5VALW 4 11
7 VIN2_1 VOUT2_1 8 VBIAS GND
VIN2_2 VOUT2_2 RZ4 1 2 0_0402_5% 5 10 1 2
<58,62,78,89> SUSP# ON2 CT2
1 15 1 CZ14 470P_0402_50V7K
GPAD 6 9
+3VALW VIN2_1 VOUT2_1 +3VS_SSD
CZ11 EM5209VF_DFN14_3X2-X CZ12 +3VS_OUT +3VS colay ?? 7 8
1U_0201_6.3V6M VIN2_2 VOUT2_2
0.1U_0201_10V6K
2 2 15
1 GPAD 1
JP5 PJP@
1 2 CZ18 EM5209VF_DFN14_3X2-X CZ15
1 2 1U_0201_6.3V6M 0.1U_0201_10V6K
JUMP_43X118 2 2
C
+0.75VS for System C
+3VALW +MIC_VCC
160mils(4.0A) UZ4
CZ19 2 1 1 14 1 2
+0.75VALW U22 +0.75VS 2 VIN1_1 VOUT1_1 13 CZ24 0.1U_0201_10V6K
SB00001EO00
DMN3009LFV-13_POWERDI3333-8-5 1U_0201_6.3V6M VIN1_2 VOUT1_2
3 RZ3 1 2 0_0402_5% 3 12 1 2
2 ON1 CT1 CZ22 470P_0402_50V7K
4.7U_0402_6.3V6M
C701
1U_0201_6.3V6M
C461
5 1 1 1 +5VALW 4 11
VBIAS GND
1
C702 RZ6 1 2 0_0402_5% 5 10 1 2
<59> APU_AUD_PWR_EN ON2 CT2
4.7U_0402_6.3V6M @ CZ20 470P_0402_50V7K
4
@ @2 @2 +1.8V_VDD 6 9 +VDDIO_AUDIO
2 7 VIN2_1 VOUT2_1 8
Vgs=1.0-3.0V VIN2_2 VOUT2_2
1 15 1
GPAD
+5VALW CZ23 EM5209VF_DFN14_3X2-X CZ21
1U_0201_6.3V6M 0.1U_0201_10V6K
1 @ 2 0.75VS_GATE 9/24 LOW active §ï¬°High active 2 2
R941 8/13 C Change to R
2
4.7K_0402_5%
+3VALW C16
0_0201_1%
@
2
G
@3 1
<58,99> 0.75VS_PWR_EN
S
Q84
L2N7002WT1G_SC-70-3
SB00001GE00
Vgs=1.0-2.0V
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC Interface
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K661P
Date: Wednesday, April 21, 2021 Sheet 78 of 121
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Debug APS,DEG
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K661P
Date: Wednesday, April 21, 2021 Sheet 79 of 121
5 4 3 2 1
5 4 3 2 1
PG
PC
U
&
U
D D
H1 H2 H3 H4
@ @ @ @
1
H_4P0-G-V H_4P0-G-V H_4P0-G-V H_4P0-G-V
H5 H6 H17
@ @ @
1
H_4P5X3P7-G-V H_3P7-G-V H_2P1-G-V
TP
H
H7 H8 H9 H10
@ @ @ @
1
H_2P1-G-V H_2P5-G-V H_2P4-G-V H_3P0-G-V
@ @ @ @
1
C C
H_2P6-G-V H_2P6-G-V H_2P6-G-V H_2P6-G-V
-d
fo
tS
na
f
H15 H16
@ @
1
H_3P3-G-V H_3P3-G-V
ud
la
ra
i
i
M
F
c
k
FD1 FD2 FD3 FD4 FD5 FD6
@ FIDUCIAL @ FIDUCIAL @ FIDUCIAL @ FIDUCIAL @ FIDUCIAL @ FIDUCIAL
1
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Screw Hole
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K661P
Date: Wednesday, April 21, 2021 Sheet 80 of 121
5 4 3 2 1
5 4 3 2 1
Power block
EN_5V
TPS51225CRUKR
Adapter +19VB
CHARGER
ISL95522A
+1.2VP/+0.6VSP 2.5VSP_PGOOD / 0.6V_DDR_VTT_ON
RT8207PGQW
SYSON
Battery +2.5V_MEMP
RT9059GQW
+3VALW
C C
+1.8VALWP 0.75_1.8VALW_PWREN
teknisi-indonesia.com SY8388RHC
EN_+12V
FBVDD/Q_EN +1.35VS_VGA +12VP_FAN
B
UP9529PQKF RT9297GQW B
AOZ5332QI*1 +5VS
+VDDCR_VDD/VDDCR_SOC SW
MP86901-CGLT-Z +0.75V_VDDP_S5 0.75VS_PWR_EN
SY8388RHC
+VDD_18 0.75_1.8VALW_PWREN
A
SY8386RHC A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_POWER BLOCK DIAGRAM
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K454P
Date: Wednesday, April 21, 2021 Sheet 81 of 121
5 4 3 2 1
A B C D
1
1000P_0402_50V7K
100P_0402_50V8J
100P_0402_50V8J
10P_0402_50V8J
+19V_ADPIN 1 2 FDV301N-G_SOT23-3
4 5 EMI@ PL3 SB503010020 PR5
PIN4 ADPIN 5 6 HBM 2 (2000~<4000)
1000P_0402_50V7K
EMI@ PC1
EMI@ PC2
EMI@ PC3
EMI@ PC4
RF@ PC5
1 5A_Z80_0805_2P 1 2.2K_0402_1%
6 7
1
PIN5 ADPIN 7 8
1
EMI@ PL4
2 PR3
33_0402_5%
PIN6 GND
2
8 9 5A_Z80_0805_2P PSID-4 1 3 PSID-3 1 2
S
D
2
2
9 10 2 2
1
PIN7 GND 10
1 2 PS_ID 1
PIN8 GND 11
G1 12 PSID
PIN9 GND
G
G2
2
PR4
PIN10 PSID TWVM_WTB2020-10RD-TAGHA
PR1
100K_0402_1% PSID-2
10K_0402_1%
1 2
ACES_50459-010H0M0-001 EMI@ PL5
+5VALW
BLM15AX601SN1D_2P
1
1 2 C
PSID-1 2 PQ2
B LMBT3904WT1G_SC70-3
1
E SB000013V00
3
PR2 HBM 3A (4000~<8000)
@ESD@ PD1 15K_0402_1%
CEST23NC24VU_SOT23-3
2
Adapter 180W / 240W
1
240W/19V=12.63A
EMI@ PL7
9A Z80 10M 1812_2P ESD@ PD2
1
1 2 TVNST52302AB0_SOT523-3
ESD@ PD3
1000P_0402_50V7K
1000P_0402_50V7K
100P_0402_50V8J
100P_0402_50V8J
TVNST52302AB0_SOT523-3
1
1
EMI@ PC8
EMI@ PC9
EMI@ PC10
EMI@ PC11
Battery Connector
3
2
2
PBATT1
Battery Bot Side CONN@
Before - ->Aftre 1
1
2
PIN1 GND- ->PIN 10 2
3
3 PR13 1 2 100_0402_1% 85 EC_SMB_CLK1
4 CLK_SMB
2
PIN2 GND- ->PIN0 9 4 5 DAT_SMB 2
5
PIN3 GND- ->PIN0 8 6
6 +3.3V_BAT_LDO_R PR14 1 2 100_0402_1% 85 EC_SMB_DAT1
7
PIN4 SYS_PRES#- ->PIN0 7 7 8
8
PIN5 BATT_PRS#- ->PIN0 6 9
9
10
PR17 1 2 0_0402_5%
+3.3V_BAT_LDO
PIN6 DAT_SMB#- ->PIN0 5 10
Battery 56W
56W/11.4V=4.91A
Battery 86W
86W/11.4V=7.54A
3 1U_0402_25V6K 3
1
PD612 smoke@ 9/29 PWR modify
2
2
2
+3VALW
1
20201202
2
+Z4012 2
2
10K_0402_1% @ PR18 D
1
PC6 0_0402_5% PR52
2
3
4 4
1 2 5 PQ3B PC7 2N7002KW_SOT323-3
1
1
S
1
3
D
1
S HBM 2 (2000~<4000) 1 2
PR6
VCIN1_BATT_TEMP 82,85 2 PQ4 BAS40CW_SOT323-3
4
6
1
1 2 2 PQ3A PR10 2N7002KW_SOT323-3 SB000009Q80 10M_0201_5%
+19V_VIN +RTC_CELL
2
2N7002KW_SOT323-3
G SB00000EO00 47K_0402_1% PR11 S HBM 2KV CPU thermal protection PH1
3
1
at 92 +/- 3 degree C
1
300K_0402_1% 1M_0402_1%
2
2
1
ECAGND
PC12
2
1U_0402_25VAK
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-DCIN / OTP / BATT CONN / RTC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K454P
Date: Wednesday, April 21, 2021 Sheet 82 of 121
A B C D
A B C D
1 1
2 2
3 3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- Reserve for PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K453P
Date: Wednesday, April 21, 2021 Sheet 83 of 121
A B C D
A B C D
1 1
2 2
3 3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- Reserve for PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K453P
Date: Wednesday, April 21, 2021 Sheet 84 of 121
A B C D
A B C D
CHG_N002
3 1UH_PCMB063T-1R0MS_12A_20%
1 5 CHG_N003 1 4 1 2
HBM 2 (2000~<4000)
SB000009Q80
2N7002KW_SOT323-3
PQB15 2 SH00000PJ00 NIKO@ PQB12 NIKO@ PQB14
D
1000P_0402_25V8J
1000P_0402_25V8J
0.1U_0402_25V7K
3 2 3 PK5N2EA_PDFN5X6P8-5 PK5N2EA_PDFN5X6P8-5
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10P_0402_50V8J
1 2 SB00001IC00 SB00001IC00 1
2200P_0402_50V7K
CHG_N001 G
RF@ PCB11
1
1
+19V_VIN
EMI@ PCB10
PCB3
PCB4
@ PCB5
@ PCB6
EMI@ PCB7
EMI@ PCB8
EMI@ PCB9
S
3
ASGATE_CHG_R PDB1
EMC@ PQB12 SMF4L22A_SOD123FL2
2
CSIN_CHG_R
EMP21N03HC_N_DFN56-8-5 CMSRC_CHG_R HBM 1C (1000~<2000)
CSIP_CHG_R
SB00001LC00 EMC@ PQB14 SB00001LC00
2
HBM 1C (1000~<2000) EMP21N03HC_N_DFN56-8-5
5 1 1 5
2 2
1
3 3 1/21 PVT PWR modify
PRB8
4
4.02K_0402_1%
CMSRC_CHG 2
CHG_N001
+19VB
teknisi-indonesia.com
1
+19VB
1
1
@ PCB1 PCB12 NEW ADD
1200P_0402_50V7K PRB1 0.022U_0402_25V7K
2
PRB5 PRB6
2.2_0603_5%
2
1
10/30 PWR modify 1_0402_1% 1_0402_1%
@ PDB5
2
2
ASGATE_CHG_R
CSIP_CHG
CSIN_CHG
SDMK0340L-7-F_SOD323-2~D
1000P_0402_50V7K
5
1U_0402_25V6K
2
NEW ADD PCB13
1
@ PQB17 SB000009Q80
2N7002KW_SOT323-3
0.1U_0402_25V6
HBM 2 (2000~<4000)
1 2
1
EMI@ PCB41
EMI@ PCB42
PRB7
D
1
1
4.02K_0402_1% PCB14 BGATE_CHG 4
PQB2_GATE 1 2 2
PQB2_GATE 112 +19V_VIN 0.033U_0402_25V7K @ PCB15 @ PDB6 PQB16
ASGATE_CHG 2
2
2200P_0402_50V7K
1
100K_0402_1%
100K_0402_1% S SB00001LC00
3
1
HBM 1C (1000~<2000)
@ PCB43
@ PCB16
AC_DIS
3
2
1
@ PRB45
0.1U_0402_25V7K
2
1
1
RB751V-40_SOD323-2
PCB17
2
2
2
374K_0402_1% PQB1
5
AON6354_N_DFN56-8-5
BST_CHG_R
2
PDB4
100K_0402_5%
BAS40CW_SOT323-3 HBM 1B (500~<1000)
1
2N7002KW_SOT323-3
1
HBM 2 (2000~<4000)
1
0.01UF_0402_25V7K
PRB11
BA_PWR 3
0_0603_5%
D
1
2
1 PDB3 UG1_CHG 4
1
SB000009Q80
+19V_VIN 2 PQB2_GATE 2
CHG_N004
PRB10
G PRB12
Package: 11.5 x 10.3 x 3
2
1
S 52.3K_0402_1%
3
2
1
PRB14
ACIN_CHG
LX1_CHG
1
3
2
1
100K_0402_1% PCB18 Rdc=8mohm
NTC_CHG
UG1_CHG
LG1_CHG
BST_CHG
PRB13
10_1206_5% SH00000XV00 +12.6V_BATT_R +12.6V_BATT
2
16
15
14
13
12
11
10
33
9
4.7U_0603_25V6K 4.7_0402_5% 2.2UH_MMD-10CZ-2R2M-X2L_13A_20% PRB18
1 2 DCIN_CHG 1 2 VDD_CHG SH00000XV00 0.005_1206_1%
CSIP
ACIN
CSIN
NTC
BOOT
UGATE
PHASE
LGATE
GND
10/28 PWR modify PRB16 200K_0402_1% LX1_CHG 1 2 1 4
1 2 17 8 VDDP_CHG 1 2
DCIN VDDP
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
0.1U_0402_25V7K
PCB22 2 3
1 2 VDD_CHG 18 7 ASGATE_CHG 2.2U_0402_16V6K
VDD ASGATE
75K_0402_1%
PRB17 182K_0402_1%
1
PCB24
PCB25
PCB26
PCB27
@ PCB28
PCB29
PCB21 1 2 PROG_CHG 19 6 QPCN_CHG
PROG QPCN
2
2
ACLIM CMSRC
5
0.22U_0402_25V6K SB00001IU00
1 PRB21 2 0_0402_5% SDA_CHG 21 SA0000DTQ0L 4 QPCP_CHG 1 2 HBM 1B (500~<1000)
2
SDA QPCP
82
1
1
768K_0402_1%
1 PRB26
82 2 0_0402_5% 22.6K_0402_1% EMI@ PCB30
H_PROCHOT# 680P_0402_50V7K
BATGONE
24 1 CSON_CHG
ACOK CSON
BGATE
CCLIM
2
COMP
BMON
AMON
PRB25
PSYS
PROH
VBAT
3
2
1
2
1 2 ACOK_CHG
25
26
27
28
29
30
31
32
PRB27 PRB28 @ PCB31
0_0402_5% 100K_0402_1% 10P_0402_50V8J 1/06 PVT PWR modify
1225 DVT2 PWR modify 1 2 1 2
CCLIM_CHG
BGATE_CHG
COMP_CHG
AMON_CHG
PSYS_CHG
VBAT_CHG
3
82 1 2 BATGONE_CHG 3
VCIN1_BATT_TEMP PQB4
@ PRB29 PRB30 200K_0402_1% LMUN5113T1G_SOT323-3
0_0603_5%
100K_0402_1% VDD_CHG 1 2 SB000013X00
1
HBM 1B (500~<1000)
@0@ PRB33
@ PRB32 374K_0402_1%
10/28 PWR modify
CHG_N005
1 2 2
@ PCB32
PRB34 0_0402_5% 1U_0402_25V6K
2
1 2 I_BATT_P 1 2
I_BATT_R
PQB5
LMUN5236T1G
1
1
1
2200P_0402_50V7K
0_0402_5%
SB000011K00
499_0402_1%
HBM 0B (125~<250)
PRB31
PRB37
10.5K_0402_1%
1
1
PCB33
560P_0402_50V7K
2_0402_5%
1
PRB35
1 2 CSOP_CHG_R
PRB38
SLP_S5# 2
2
2
1
BA_PWR
PCB34
1
I_ADP_R
PCB36 PRB40
2
0.1U_0402_25V6
0.1U_0402_25V6 0_0402_5%
CHG_N008
2
1 2 CSON_CHG_R
3
1
0.015U_0402_25V7K
PCB35
1
1 2
2
I_ADP_R 1 2 +12.6V_BATT
@ PCB38
Delay adaptor OC H_PROCHOT# PRB41 0.22U_0402_25V6K
2ms while hybrid power transition 100_0402_5% Effective Renesas
CPN Value capacitance recommend
+3VALW
VDD_CHG DCIN SE000013880 4.7uF_0603_25V 0.4uF 0.4uF
1
@ PCB40
H_PROCHOT# 0.1U_0402_25V6
1
PRB42
2
PRB43 D
2
1 2 CHG_N007 2
4
10K_0402_5%
CHG_N006 G VDDP SE000013780 2.2uF_0402_16V 0.55uF 0.4uF 4
0.047U_0402_25V7K
PRB44
2
160K_0402_1%
1
D S
PCB39
PQB6
3
PROH 2
G RUM002N02GT2L_VMT3 CBOOT SE00000WA00 0.47uF_0402_25V 0.22uF 0.2uF
2
SB000012P00
S HBM 2 (2000~<4000)
3
PQB7
RUM002N02GT2L_VMT3
SB000012P00
HBM 2 (2000~<4000)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_CHARGER
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K454P
Date: Wednesday, April 21, 2021 Sheet 85 of 121
A B C D
A B C D
1 1
2 2
3 3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- Reserve for PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K453P
Date: Wednesday, April 21, 2021 Sheet 86 of 121
A B C D
A B C D
3VALW
5VALW
Main Func = 3VALWP / 5VALWP Vout=3.4V
TDC 9.1A Vout= 5.16V
Peak Current 13A TDC 13.1A
OCP current 16.9A Peak Current 16.8A
OVP=3.824V~3.994V(112.5%~117.5%) OCP current 21.3A
UVP=1.869V~2.209V(55%~65%) OVP=5.805V~6.063V(112.5%~117.5%)
FSW=355kHz UVP=2.838V~3.354V(55%~65%)
FSW=300kHz
MOS (VGS = 4.5V )
1
TYP MAX MOS (VGS = 4.5V ) 1
JUMP@ PJP302
+3VALWP +5VALWP +3VALWP 1 2 +3VALW
PR301 PR504 1 2
10K_0402_1%
1 2
VFB=2V VFB=2V 15.8K_0402_1%
1 2
JUMP_43X118
1000P_0402_50V7K
22U_0805_25V6M
22U_0805_25V6M
0.1U_0402_25V6
EMI@ PC316
5A_Z80_0805_2P
high, it will
1
1
EMI@ PC304
EMI@ PC305
PC306
PC307
1 2 JUMP_43X118
1
1
pull high on VS
2200P_0402_50V7K
EMI@ PC302
EMI@ PC303
0.1U_0402_25V6
22U_0805_25V6M
22U_0805_25V6M
transfer circuit PR303 PR506
2
EMI@ PC308
EMI@ PC309
68K_0402_1% 93.1K_0402_1%
2
1
PC310
PC311
CS2 2
CS1 2
5
FB_3V
FB_5V
PQ301
2
2
SB000010H00 +3VALWP 2
5
HBM 600V
PQ501 Main: MAG. LAYERS
1
4 UG_3V SB000010H00
Package: 10 x 10 x 3
1
AON7534_DFN3X3-8-5
PR304 HBM 600V Idc=16A, Isat=20A
CS2
VFB2
VREG3
VFB1
CS1
10K_0402_1% 21 UG_5V 4 Rdc=6.5mohm
EN_3V 6 PAD
SH00001TW00
1
2
3
2
+3VALWP EN2 20 EN_5V
EN1 @ PR501
PL301 7 200_0402_1% PL501 +5VALWP
POK
3
2
1
2.2UH_MMD-06CZE2R2M-X6L_10A_20% PGOOD 19 VCLK_5V 1 2 1.5UH_TMPC1003H-1R5MG-D_16A_20%
SH00001KN00 PU301 VCLK SH00001TW00
1 2 LX_3V LX_3V 8 TPS51225CRUKR_QFN20_3X3
PC312 PR305 SW2 18 LX_5V LX_5V 1 2
SW1
330U_D2E_6.3VM_R25M
1 0.1U_0402_25V6 0_0603_5% SA00005LS00 PR502 PC502
Main: MAG. LAYERS 1 2 BST_3V_R 1 2 BST_3V 9
VBST2
0_0603_5% 0.1U_0402_25V6
+
ESR = 25mohm
PC313 Package: 6.95 x 6.6 x 3 17 BST_5V 1 2 BST_5V_R 1 2
VBST1
1
22U_0603_6.3V6M
22U_0603_6.3V6M
4.7_1206_5%
330U_D2E_6.3VM_R25M
Idc=10A, Isat=13A 1
5
EMI@ PR306
UG_3V 10
Rdc=12mohm DRVH2
1
2 +
ESR = 25mohm
PC505
PC506
PC504
PQ302 16 UG_5V
VREG5
DRVL2
DRVL1
SH00001KN00 SB00001OX00 DRVH1 PQ502
VO1
VIN
AONR36366 1N DFN 3X3 SB00001OX00 EMI@ PR503
2
2
HBM 1B (500~<1000) AONR36366 1N DFN 3X3 4.7_1206_5% 2
4 HBM 1B (500~<1000)
SN_3V
11
12
13
14
15
2
4
SN_5V
680P_0402_50V7K
LG_3V LG_5V
1
1
EMI@ PC314
EMI@ PC503
1
2
3
680P_0402_50V7K
3
2
1
footprint use AON7508_DFN8-5 +19VB_3/5V
+19VB_3/5V +5VALWP
2
2
footprint use AON7508_DFN8-5
+5VLP
3 3
2020/07/06 HW control
PC501
4.7U_0402_10V6M
2
EN
PR307
Rising=1.6~0.3V 0_0402_5%
EN_3V 1 2
PR308
0_0402_5%
EN_5V 1 2
PR309
EN_3V_5V
2.2K_0402_1%
1 2
EC_ON
PR507
PD501
0_0402_5%
1 2 1 2
VCOUT0_PH#
PR7536
0_0402_5% RB751V-40_SOD323-2
1 2
THERM_OVERT#_R
4.7U_0402_6.3V6M
1
1M_0402_5%
4 4
1
PR311
PC315
2
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_+3.3VALWP/+5VALWP
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K454P
Date: Wednesday, April 21, 2021 Sheet 87 of 121
A B C D
A B C D
1 1
2 2
3 3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- Reserve for PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K453P
Date: Wednesday, April 21, 2021 Sheet 88 of 121
A B C D
5 4 3 2 1
+1.2V_DDR
Main Func = 1.2VP / 0.6VSP / 2.5V_MEMP Vout= 1.203V
TDC 6.6A
Peak Current 9.4A
Input Current: 1.332A OCP current 12.22A
Pin19 need pull separate from +1.2VP. OVP=1.36V~1.44V(113%~120%)
1.203V*8A/0.85/9V=1.25A If you have +1.2V and +0.6V sequence question, UVP=0.72V~0.96V(60%~80%)
you can change from +1.2VP to +1.2VS.
FSW= ~538KHz
0.6V*1.05A/0.85/9V=0.082A
MOS (VGS = 4.5V )
D
PRM1 2.2_0603_5% +1.2VP TYP MAX
D
BST_DDR_R 1 2 BST_DDR
EMI@ PLM11 H/S Rds(on) : 11mohm 13mohm
5A_Z80_0805_2P
+19VB 1 2 +19VB_DDR L/S Rds(on) : 11mohm 13mohm
1
PCM34
0.1U_0402_25V6 UG_DDR
@JUMP@ PJPM1 +0.6VSP
2
1 2 +19VB_DDR UG_DDR
1 2
1000P_0402_50V7K
1000P_0402_50V7K
2200P_0402_50V7K
0.1U_0402_25V6
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
1U_0402_25V6K
10P_0402_50V8J
JUMP_43X39 LX_DDR
+0.6V_DDR_VTT
1
1
EMI@ PCM6
EMI@ PCM9
EMI@PCM38
EMI@PCM15
EMI@PCM10
PCM2
@ PCM3
@ PCM1
RF@ PCM30
PQM1
1
EMB09A03VP_EDFN3X3-8-10
HBM (500~<1000)
Vout= 1.203V
22U_0603_6.3V6M
22U_0603_6.3V6M
1 4
16
17
18
19
20
TDC 1.05A
D1
D1
D1
G1
2
1
PCM36
PCM37
2 3 Peak Current 1.5A
PHASE
UGATE
BOOT
VLDOIN
VTT
10 9 LX_DDR 21
@ PRM11 D1 D2/S1 PAD
2
0.01_1206_1% LG_DDR 15 1
LGATE VTTGND
G2
S2
S2
S2
14 2
8
PRM2 PGND VTTSNS
16.2K_0402_1%
LG_DDR 1 2 CS_DDR 13 PUM1 3
PCM31 CS RT8207PGQW_WQFN20_3X3 GND
2.2U_0402_6.3V6M
1 2 12 SA00007IH00 4 VTTREF_DDR
+5VALW PRM4 VDDP VTTREF JUMP@ PJPM2
5.1_0603_5% +1.2VP 1 2 +1.2V_DDR
1 2
1
1 2 VDD_DDR 11 5
VDD VDDQ
10/13 For PWR modify
PGOOD
PCM11 JUMP_43X118
PDM1 0.033U_0402_16V7K
+1.2VP
TON
2
PLM1 RB751V-40_SOD323-2 JUMP@ PJPM3
FB
S5
S3
1
1UH_PCMB063T-1R0MS_12A_20% PCM12 2 1 1 2
SH00000PJ00 2.2U_0402_6.3V6M 1 2
10
6
VDDP_DDR
1 2 LX_DDR JUMP_43X118
2
C C
1
PRM5
@EMI@ PRM3 2.2_0603_5% +1.2VP JUMP@ PJPM4
Main MAG. LAYERS 4.7_1206_5% 1 2 PRM6 1 2
S3_DDR
+0.6VSP 1 2 +0.6V_DDR_VTT
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
6.04K_0402_1%
Package: 6.95 x 6.6 x 2.8 +3VALW
1
1 2 JUMP_43X39
2
Idc=12A, Isat=15A
PCM4
PCM5
PCM32
PCM7
PCM8
PCM33
@ PRM8
Rdc=6.7mohm SN_DDR 100K_0402_5%
2
1 2
TON_DDR
S5_DDR
SH00000PJ00
1
@EMI@ PCM35
680P_0402_50V7K Pull high on EE side PRM7
Vout=0.75*(1+PRM6/PRM9)
2
510K_0402_1% PRM9
+19VB_DDR 1 2 10K_0402_1% =1.203V
@ PTPM1
2
10/13 For PWR modify
0.1U_0402_10V7K
PRM12
@ PCM13
0_0402_5%
1
1 89 2
SYSON
2
Mode Level +0.6VSP VTTREF_1.2V PRM10
0_0402_5%
S5 L off off 1 2
S3 L off on SUSP#
S0 H on on
1
Note: S3 - sleep ; S5 - power off @ PCM14
0.1U_0402_10V7K
www.teknisi-indonesia.com
2
B Input Current: 0.366A B
2.52V*0.37A/0.85/3V=0.366A
+3VALW
PR2501
1
0_0402_5%
SYSON 1 2 89
PR2509
0.1U_0402_16V7K
100K_0402_1% +2.5V_MEM
1
1M_0402_1%
PR2506
2
1
Vout= 2.52 V
@ PR2502
@ PC2502
0_0402_5%
2 1
TDC 0.203A
2
PU2501
RT9059GQW_WDFN10_3X3 Current limit 3.6A
+3VALW
VIN_2.5V 11
PAD +2.5V_MEMP
JUMP@ PJ2501 EN_2.5V 6 5 PGOOD_2.5V
1 2 VIN_2.5V 7 EN PGOOD 4 ADJ_2.5V
1 2 VIN ADJ/NC
2200P_0402_50V7K
22U_0603_6.3V6M
22U_0603_6.3V6M
0.1U_0402_25V6
8 3
VIN VOUT
EMI@ PC2513
JUMP_43X39 1 9 2
VIN VOUT
1
1
EMI@ PC2514
PC2501
PC2508
10 1
VDD VOUT
22P_0603_50V8
22U_0603_6.3V6M
22U_0603_6.3V6M
1
SA000071S00 PR2504
2
2
PC2506
PC2503
PC2504
21.5K_0402_1%
Rup
2
JUMP@ PJ2502
2
1 2
+2.5V_MEMP 1 2 +2.5V_MEM
ADJ_2.5V
FB=0.8V
PR2510 JUMP_43X79
A 1 2 VDD_2.5V A
+5VALW
1
PR2505
2.2_0402_1% 10K_0402_1%
1
PC2512
Rdown
Vout=0.8V*(1+Rup/Rdown)
2
2.2U_0402_10VAM
2
=2.52V
Note:
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2020/03/05 Deciphered Date 2018/12/31 Title
When design Vin=5V, please stuff snubber PWR_1.2VP/0.6VSP/+2.5V
to prevent Vin damage THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K454P
Date: Wednesday, April 21, 2021 Sheet 89 of 121
5 4 3 2 1
5 4 3 2 1
1.8V*6.2A/0.85/9V=1.46A PL1801
1UH_MMD-05AHN1R0M-X2L_8A_20%
330P_0402_50V7K
BST_+1.8V_R 1 2 LX_+1.8V 1 2
SH00001YU00
1
PC1808 PC1809
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
0.1U_0603_25V7K 4.7U_0402_10V6M @EMI@ PR1802
1
PC1813
PC1814
PC1815
PC1816
@ PC1819
4.7_1206_5%
1
VCC_+1.8V 1 2
2
2
PR1801 SN_1.8V
0_0603_5% PR1809
17
16
15
14
13
+3VALW
1K_0201_5%
1
Rup 200K_0402_1% JUMP@ PJ1802
1
EMI@ PL1811 @EMI@ PC1811 JUMP_43X79
EP
LX2
LX1
GND1
VCC
PR1807
5A_Z80_0805_2P PC1810 680P_0402_50V7K 1 2
+19VB +1.8VALWP +1.8VALW_GPU
1
1 2 2.2U_0402_6.3V6M 1 2
2
BST_+1.8V 1 12
+19VB_1.8V BS BYP
2
PJ1801
@JUMP@ JUMP_43X79
1 2 +19VB_1.8V 2 11 FB_1.8V
1 2 IN1 FB
2200P_0402_50V7K
0.1U_0402_25V6
PU1801
10U_0603_25V6M
1000P_0402_50V7K
1U_0402_25V6K
10P_0402_25V8J
10P_0402_25V8J
EMI@ PC1804
1
1
EMI@ PC1818
EMI@ PC1817
EMI@ PC1805
RF@ PC1806
PC1807
SY8388RHC_QFN16_2P5X2P5 @ PR1803 10K_0402_5%
Vout=0.6V* (1+Rup/Rdown)
RF@ PC1802
1
1
3 10 ILMT_+1.8V 1 2
IN2 ILMT +3VALW =1.8V
SA0000C7X00
Rdown
2
2 @ PR1804 10K_0402_5%
2
1 2 PR1808
4 9 EN_1.8V 100K_0402_1%
2
IN3 EN
TEST
GND
1 2
PG
LX
99,100 0.75_1.8VALW_PWREN
PR1805
8
0_0402_5%
VILMT
1
LX_+1.8V @ PC1812 PR1806 H : 12A
0.1U_0402_16V7K 1M_0402_1%
L : 8A
2
C Floating : 10A C
2
+3VALW
PR1810
10K_0402_5%
1 100 2 1.8V_PRIM_PG
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-+1.8V
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K454P
Date: Wednesday, April 21, 2021 Sheet 90 of 121
5 4 3 2 1
A B C D
1 1
2 2
3 3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-+1.05V
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K453P
Date: Wednesday, April 21, 2021 Sheet 91 of 121
A B C D
A B C D
1 1
2 2
3 3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-+VCCIOP
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K453P
Date: Wednesday, April 21, 2021 Sheet 92 of 121
A B C D
A B C D
1 1
2 2
3 3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- Reserve for PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K453P
Date: Wednesday, April 21, 2021 Sheet 93 of 121
A B C D
A B C D
1 1
2 2
3 3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- Reserve for PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K453P
Date: Wednesday, April 21, 2021 Sheet 94 of 121
A B C D
A B C D
1 1
2 2
3 3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- Reserve for PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K453P
Date: Wednesday, April 21, 2021 Sheet 95 of 121
A B C D
A B C D
1 1
2 2
3 3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- Reserve for PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K453P
Date: Wednesday, April 21, 2021 Sheet 96 of 121
A B C D
5 4 3 2 1
VDDCR_SOC:
Input Current:1.55*15/0.87/12=2.22A
CS5_SOC
CS5_SOC
1 2
CS_SUM2_2945 97
PRZ51
1.5K_0402_1%
CS4_VDD
CS4_VDD
1 2
CS_SUM1_2945 97
PRZ50
1.5K_0402_1%
CS3_VDD
CS3_VDD
1 2
CS_SUM1_2945 97
PRZ49
1.5K_0402_1%
CS2_VDD
CS2_VDD +3VALW
1 2
CS_SUM1_2945 97
4.7_0402_5%
PRZ48 98
1
1.5K_0402_1% PWM1_VDD
+3VALW
PRZ3
CS1_VDD 98
CS1_VDD PWM2_VDD
2
1 2 98
CS_SUM1_2945 97 PWM3_VDD
4.7U_0402_6.3V6M
PRZ45
4.99K_0402_1%
100_0402_5% PRZ47
C C
4.99K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
4.99K_0402_1%
+VDDCR_VDD 2 1 1.5K_0402_1% 98
1
PWM4_VDD
PRZ8
PRZ7
PRZ6
PRZ5
@ PRZ9
PRZ43
VCC_SENSE_APU_CORE
PCZ4
0_0402_5% 98
2 1 VOSEN1 PWM5_SOC
PWM5_SOC
PWM1_VDD
PWM2_VDD
PWM3_VDD
PWM4_VDD
2
2
1
2 1 VORTN1 2.2_0402_1%
97 2 1 +1.8VALW_GPU
differential net into CPU
1
2 1
VDD33
1
PRZ46 PCZ20
PRZ39 453_0402_1% @ PCZ14 1U_0201_6.3V6M
100_0402_5% 1 2
100P_0402_50V8J
2 1 2
2
41
40
39
38
37
36
35
34
33
32
31
PRZ34 FB1 PUZ1 1 2
VDIFF1
VSS_SEN_APU_CORE 100_0402_5% SVD
AGND
CS1
CS2
CS3
CS4
CS5
VDD33
PWM1
PWM2
PWM3
PWM4
2 1 VORTN2 SVD_PWR_APU PCZ7 @ PTPZ2
97 SVC 1U_0201_6.3V6M
2
0_0402_5% 1 30 SVC_PWR_APU
PRZ35 @ PCZ17 2 VDIFF1 PWM5 29
0.001U_0201_16V7K 3 FB1 SVD/PVID1 28 APU_PWROK 1 2
VCC_SENSE_APU_CORE_SOC
1
CS_SUM2
100_0402_5% 1.33K_0402_1%
VINSEN
100P_0402_50V8J
VDD18
IMON1
IMON2
2
ADDR
PG_B
PG_A
OCP_L_2945
IREF
2
PTPZ3 @
EN
CS_SUM1_2945
PRZ29 MP2945GU-0043-Z_QFN40_5X5
11
12
13
14
15
16
17
18
19
20
0_0402_5% 0310 PVT modify
1 2 98 PG_A_2945
VTEMP VGATE
97
IREF
B CS_SUM2_2945 B
1U_0201_6.3V6M
1U_0201_6.3V6M
49.9K_0402_1%
1
2 PG_B_2945 97
1
VGATE
PCZ18
PCZ10
97PRZ30
EN_2945 2 1 VR_ON
IMON1
IMON2
97
2
1
61.9K_0402_1%
PRZ10
2
VDD18_2945 0_0402_5%
0.1U_0402_25V6
PRZ31
VDD18_2945
CS_SUM1_2945
CS_SUM2_2945
PCZ5
1U_0201_6.3V6M
1U_0201_6.3V6M
1
VDD18_2945
ADDR 1
2
10K_0402_1%
PCZ19
PCZ3
2
VINSEN
@ PRZ33
1
680P_0402_50V7K
1
1
2200P_0402_50V7K
40.2K_0402_1%
1
9.76K_0402_1%
0.01U_0402_16V7K
PRZ28
1
4.99K_0402_1%
PCZ9
1
2
PRZ27
PCZ8
PCZ1
2
2
PRZ4
2
PRZ32
2
0_0402_5%
1
1/06 PVT PWR modify
1
2
75K_0402_5%
+19VB_CPU
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+VCORE_MP2945
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K454P
Date: Wednesday, April 21, 2021 Sheet 97 of 121
5 4 3 2 1
5 4 3 2 1
+19VB_CPU
Main Func = CPU_CORE_SW
+VDDCR_VDD
TDC= 58A
10U_0805_25VX7SK
10U_0805_25VX7SK
2200P_0402_50V7K
10P_0402_50V8J
4.7U_0603_25V6K
4.7U_0603_25V6K
4.7U_0603_25V6K
4.7U_0603_25V6K
0.1U_0402_25V6
EDP= Peak Current 110A 1 1
1
Loadline 1.1mV/A
1U_0402_25V6K
PCI43
PCI44
PCI45
PCI46
PCI150
PCI151
EMI@ PCI47
EMI@ PCI48
RF@PCI106
+3VALW
Layout closer pin1
2
2
2 2
PCI142
PUI04
1
EMI@ PLI11
9A Z80 10M 1812_2P 1 2 VCC_VDD4 14 1
VCC VIN
1 2 12/28 PWR DVT2 modify 8
+19VB_CPU 10/30 VIN1
1
for PPM Modify PRI49 PCI51
D
+19VB EMI@ PLI12 0_0402_5% 1U_0402_25V6K
D
9A Z80 10M 1812_2P
2
100U_D3L_25VM_R60M
100U_D3L_25VM_R60M
1 2 13 15 BST4_VDD
AGND BST
10U_0805_25VX7SK
10U_0805_25VX7SK
2200P_0402_50V7K
1000P_0402_50V7K
1
1000P_0402_50V7K
1U_0402_25V6K
10P_0402_50V8J
1U_0402_25V6K
4.7U_0603_25V6K
4.7U_0603_25V6K
4.7U_0603_25V6K
4.7U_0603_25V6K
0.1U_0402_25V6
1 1 PCI107
EMI@ PCI01
EMI@ PCI02
EMI@ PCI07
EMI@ PCI08
RF@PCI104
EMI@PCI109
1 4 1 1 PRI42 1U_0402_25V6K PLI04
1
1
+ +
PCI03
PCI04
PCI05
PCI06
PCI144
PCI145
EMI@PCI108
0_0402_5% 2 0.15UH_NA__36A_20%
2
SW
PCI09
PCI10
PWM_VDD4 LX_VDD4
2 3
PWM4_VDD
1 97 2 9
PWM SW1
3
4
4 1
+VDDCR_VDD
2
2
@ PRI44 2 2 2 2 1 2 VTEP_VDD4 11 SW2 3 2
VTEMP 97,98 VTEMP/FLT
0.01_1206_1%
1
PRI45 0_0402_5% 1 2 SYNC_VDD4 10 5 SH00001EE00
PRI41 2K_0402_1% SYNC PGND 6 EMI@ PRI43
1 2 CS_VDD4 12 PGND1 7
CS4_VDD CS PGND2 4.7_1206_5% M1 MAG LAYERS MMD-06DZER15MEM1L
M2 CHILISIN MHCB06040-R15M-C1R675
1U_0402_25V6K
PRI53
1SN_VDD4 2
Layout closer pin1 0_0402_5% MP86901-CGLT-Z_TQFN21_3X4-X M3 CYNTEC CMME064T-R15MS0R675
+3VALW Package: 7x 7 x 4
PCI139
Idc=36A, Isat=45A
PRI01 PUI01 Rdc=0.67mohm +/-5%
1
0_0402_5% SH00001EE00
1 2 VCC_VDD1 14 1 EMI@ PCI111
VCC VIN 8 680P_0402_50V7K
2
VIN1
1
PCI11
1U_0402_25V6K
2
13 15 BST1_VDD
AGND BST
1
PRI46 PCI13
PLI01
0_0402_5% 2 1U_0402_25V6K
2
PWM_VDD1 SW LX_VDD1
PWM1_VDD
1 97 2 9
PWM SW1
SW2
3
4
1 4
+VDDCR_VDD
1 97,98 2 VTEP_VDD1 11 2 3
VTEMP/FLT
1
VTEMP PRI04 0_0402_5%
1 2 SYNC_VDD1 10 5
SYNC PGND 6 PRI03 EMI@ 0.15UH_NA__36A_20%
PRI02 2K_0402_1% 12 PGND1 7 4.7_1206_5% SH00001EE00
CS PGND2
2
1 2 CS_VDD1
SN_VDD1
CS1_VDD
MP86901-CGLT-Z_TQFN21_3X4-X
M1 MAG LAYERS MMD-06DZER15MEM1L
PRI50 M2 CHILISIN MHCB06040-R15M-C1R675
0_0402_5% M3 CYNTEC CMME064T-R15MS0R675
1
PCI14 EMI@ Package: 7x 7 x 4
680P_0402_50V7K
Idc=36A, Isat=45A
2
Rdc=0.67mohm +/-5%
SH00001EE00
C C
+19VB_CPU
10U_0805_25VX7SK
10U_0805_25VX7SK
2200P_0402_50V7K
10P_0402_50V8J
4.7U_0603_25V6K
4.7U_0603_25V6K
4.7U_0603_25V6K
4.7U_0603_25V6K
0.1U_0402_25V6
1 1
1
1
PCI21
PCI27
PCI23
PCI24
PCI146
PCI147
EMI@ PCI25
EMI@ PCI26
RF@PCI110
1U_0402_25V6K
2
2 2
2
PCI140
PR21 PUI02
+VDDCR_SOC
1
0_0402_5%
1 2 VCC_VDD2 14
VCC VIN
1 TDC= 15 A
8
VIN1 EDP= Peak Current 20 A
2
PCI15
1U_0402_25V6K
Loadline 2.7mV/A
1
13 15 BST2_VDD
AGND BST
1
PCI17
PRI22 1U_0402_25V6K PLI02
0_0402_5% 2 0.15UH_NA__36A_20%
2
PWM_VDD2 SW LX_VDD2
PWM2_VDD
1 972 9
PWM SW1
SW2
3
4
1 4
+VDDCR_VDD
2 1
97,98 VTEP_VDD2 11 2 3
VTEMP/FLT
1
VTEMP
PRI47 1 2SYNC_VDD2 10 5 SH00001EE00
0_0402_5% SYNC PGND 6 PRI23 EMI@
PRI24 2K_0402_1% 12 PGND1 7 4.7_1206_5%
CS PGND2 M1 MAG LAYERS MMD-06DZER15MEM1L
M2 CHILISIN MHCB06040-R15M-C1R675
2
1 2 CS_VDD2
SN_VDD2
CS2_VDD
MP86901-CGLT-Z_TQFN21_3X4-X M3 CYNTEC CMME064T-R15MS0R675
PRI51
0_0402_5%
Package: 7x 7 x 4 +19VB_SOC
Idc=36A, Isat=45A
1
JUMP_43X79
1 2
1 2
10U_0805_25VX7SK
10U_0805_25VX7SK
2200P_0402_50V7K
0.1U_0402_25V6
4.7U_0603_25V6K
4.7U_0603_25V6K
4.7U_0603_25V6K
4.7U_0603_25V6K
1 1
1
EMI@PCG03
EMI@PCG04
PCG05
PCG06
PCG07
PCG08
PCG10
PCG11
B 1 4 B
2
2 3 2 2
+3VALW @ PRG43
+19VB_CPU 0.01_1206_1%
1U_0402_25V6K
10U_0805_25VX7SK
10U_0805_25VX7SK
2200P_0402_50V7K
10P_0402_50V8J
4.7U_0603_25V6K
4.7U_0603_25V6K
4.7U_0603_25V6K
4.7U_0603_25V6K
0.1U_0402_25V6
PCI143
1 1
1
1
PCI31
PCI32
PCI33
PCI34
PCI148
PCI149
EMI@ PCI35
EMI@ PCI36
RF@PCI105
PRG01 PUG1
+3VALW Layout closer pin1 0_0402_5%
1
1U_0402_25V6K
1 2 VCC_VDD5 14 1
2
2 2 VCC VIN 8
VIN1
1
2
PCI141
PCG09
PUI03 1U_0402_25V6K
2
13 15 BST_SOC
1
1
8
VIN1
1
2
1 PWM_VDD5 SW LX_VDD5
972 9 3 1 4
PWM5_SOC +VDDCR_SOC
2
1
PCI41
PRI32 1U_0402_25V6K PLI03 PRG42 1 2 SYNC_VDD5 10 5
0_0402_5% 2 0.15UH_NA__36A_20% 0_0402_5% SYNC PGND 6 EMI@ PRG03 0.15UH_NA__36A_20%
2
2
1 2 VTEP_VDD3 11 SW2 3 2 1 2 CS_VDD5
VTEMP 97,98 VTEMP/FLT CS5_SOC M1: MAG LAYERS MMD-06DZER15MEM1L
1SN_SOC
MP86901-CGLT-Z_TQFN21_3X4-X
M2: CHILISIN MHCB06040-R15M-C1R675
1
2
0_0402_5% Package: 7x 7 x 4 SH00001EE00
Idc=36A, Isat=45A
Rdc=0.67mohm +/-5%
SH00001EE00
1
EMI@ PCI42
680P_0402_50V7K
2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_+VCC_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K454P
Date: Wednesday, April 21, 2021 Sheet 98 of 121
5 4 3 2 1
A B C D
JUMP@ PJP752
1 2
+0.75V 1 2 +0.75VALW
JUMP_43X39
+0.75V
PL7502
PR7501 PC7507 0.68UH_CCCA-0518-R68-M_9A_+-20%
0_0603_5% 0.1U_0603_25V7K
1 2 BST_0.75V_R 1 2 LX_0.75V 1 2
470P_0402_50V7K
220U_D7_2VM_R4.5M
2
LX_0.75V
0.1U_0201_10V6K
1
1
VCC_0.75V
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
PR7514
1
+
PC7511
PC7512
PC7513
PC7514
PC7515
PC7516
PC7517
@ PC7518
PC7520
@EMI@ PR7502 10_0402_1%
PC7508 4.7_0603_5%
2
4.7U_0402_10V6M
+3VALW
2
2
2
SNB_0.75V
@ PJP751
17
16
15
14
13
1
1K_0201_1%
JUMP_43X79
@EMI@ PC7510
EP
LX2
LX1
GND1
VCC
Rup
PR7503
1 2 680P_0402_50V7K
2
1 2
1
PR7505
+19VB BST_0.75V 1 12 PC7509 100K_0201_1% PR7515
+19VB_0.75V
2
BS BYP 2.2U_0402_6.3V6M 0_0402_5%
2
EMI@ PL7501 1 2
5A_Z80_0805_2P
1 2 +19VB_0.75V 2 11 FB_0.75V
IN1 FB VFB=0.6V
2
1000P_0201_50V7K
1U_0402_25V6K
PUV702 @ PR7516
D
1
10U_0603_25V6M
10U_0603_25V6M
EMI@ PC7502
2200P_0402_50V7K
EMI@ PC7501
PC7503
EMI@ PC7504
ILIM_0.75V
0.1U_0402_25V6
1 3 10 1 2 2 0_0402_5%
IN2 ILMT +3VALW VR_ON 99
1
G
PC7505
PC7506
SA0000C7X00
Rdown
2
1
@ PQ8 S
2
3
1
2 4 9 2N7002KW_SOT323-3
IN3 EN
1
EMI@
PR7504
392K_0201_1%
TEST
GND
APU_VDDP_SEN_H
@ PR7506
PG
VILMT
LX
2
2 0_0402_5% 2
H : 12A
5
2
1 2
L : 8A 99 APU_VDDP_SEN_L
1
LX_0.75V 10/09 PWR modify 0_0402_5% Sensing nets uses differential mode to connect
+3VS PR7513
0_0402_5%
Vout=0.6V* (1+Rup/Rdown)
PR7510
2
=0.753V
1 2
10K_0402_5%
PR7511
0_0402_5%
1 2
90,100
0.75_1.8VALW_PWREN
0.022U_0402_25V7K
www.teknisi-indonesia.com
1
PC7519
PR7509
120K_0402_1%
2
+0.75VS
Vout = 0.753V
TDC = 2A
[AMD]: [SGY]
+VDDCR_VDD +VDDP OCP current = 8A
22uF_0603 X 2 470uF_ D2 x1 OVP = 0.904V (120% Type)
22uF_0603 X 6 UVP = 0.452V (60% Type)
Fsw = 500KHz
0.1uF_0201 x1 Delta IL = 1.44A
JUMP@ PJP753
1 2
3
+0.75V_S5 +0.75V_S5 1 2 +0.75VS 3
JUMP_43X39
PL7506
PR7532 PC7530 0.68UH_CCCA-0518-R68-M_9A_+-20%
0_0603_5% 0.1U_0603_25V7K
+0.75VALW _Input Current : 0.19A 1 2 BST_0.75V_S5_R
1 2 LX_0.75V_S5 1 2
Input Current = 0.753V*2A/0.85/9V=0.19A
470P_0402_50V7K
LX_0.75V_S5
VCC_0.75V_S5
0.1U_0201_10V6K
1
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
PR7519
1
1
PC7538
PC7526
PC7521
PC7524
PC7533
PC7537
PC7523
PC7540
@EMI@ PR7529 10_0402_1%
PC7532 4.7_0603_5%
2
4.7U_0402_10V6M
+3VALW
2
2
2
SNB_0.75V_S5
@ PJP754
17
16
15
14
13
1
1K_0201_1%
JUMP_43X79
@EMI@ PC7522
EP
LX2
LX1
GND1
VCC
Rup
PR7528
1 2 680P_0402_50V7K
2
1 2
1
PR7525
+19VB BST_0.75V_S5
1 12 PC7536 100K_0201_1% PR7520
+19VB_0.75V_S5
2
2
BS BYP 2.2U_0402_6.3V6M 0_0402_5%
2
EMI@ PL7505 1 2
5A_Z80_0805_2P
1 2 +19VB_0.75V_S5
2 11 FB_0.75V_S5
IN1 FB VFB=0.6V
1000P_0201_50V7K
1U_0402_25V6K
PUV03 @ PR7521
D
2
10U_0603_25V6M
10U_0603_25V6M
EMI@ PC7525
SY8388RHC_QFN16_2P5X2P5 0_0402_5%
1
2200P_0402_50V7K
EMI@ PC7535
PC7534
EMI@ PC7528
ILIM_0.75V_S5
0.1U_0402_25V6
1 3 10 1 2 2 PR7535
IN2 ILMT +3VALW VR_ON 99
1
G
PC7531
PC7527
SA0000C7X00 0_0402_5%
Rdown
2
@ PQ602 S
2
1
1
2 4 9 2N7002KW_SOT323-3
IN3 EN
1
EMI@
PR7524
392K_0201_1%
TEST
GND
VDDP_SENSE
@ PR7531
PG
VILMT
LX
0_0402_5%
H : 10A
5
1 2
L : 6A 99 APU_VDDP_SEN_L
Floating : 8A PR7523
1
LX_0.75V_S5 10/09 PWR modify 0_0402_5% Sensing nets uses differential mode to connect
+3VS
PR7533
0_0402_5%
PR7526 Vout=0.6V* (1+Rup/Rdown)
2
1 2 =0.753V
10K_0402_5%
4 4
1 2
0.75VS_PWR_EN
0.022U_0402_25V7K
PR7527
1
0_0402_5%
1
PC7529
PR7530
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_+0.75V_PRIM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K454P
Date: Wednesday, April 21, 2021 Sheet 99 of 121
A B C D
A B C D
330P_0402_50V7K
SH00001YU00
LX_+VDD_18
22U_0603_6.3V6M
22U_0603_6.3V6M
0.1U_0201_10V6K
PC1859
PC1863
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
4.7U_0402_10V6M @EMI@ PR1852
1
4.7_0603_5%
PC1864
PC1865
PC1866
PC1873
@ PC1868
@ PC1867
2
1
VCC_+VDD_18 1 2
2
2
2
PR1851 SN_+VDD_18 2
0_0603_5%
17
16
15
14
13
+3VALW
1
EMI@ PL7504
Rup PR1859
1K_0201_5%
2
1
5A_Z80_0805_2P @EMI@ PC1861 200K_0402_1%
LX2
LX1
GND1
VCC
EP
PR1857
PC1860 680P_0402_50V7K
+19VB
1
1 2 2.2U_0402_6.3V6M
2
BST_+VDD_18 1 12
+19VB_+VDD_18 BS BYP
2
@JUMP@ PJ1851
1 2 +19VB_+VDD_18 2 11 FB_+VDD_18
Vout=0.6V* (1+Rup/Rdown)
1 2 IN1 FB
=1.8V
2200P_0402_50V7K
10U_0603_25V6M
10P_0402_25V8J
0.1U_0402_25V6
PU2502
JUMP_43X79
1
1
1000P_0402_50V7K
1U_0402_25V6K
EMI@ PC1854
EMI@ PC1855
RF@ PC1856
PC1857
EMI@ PC1875
10P_0402_25V8J
3 10 ILMT_+VDD_18 1 2
RF@ PC1852
SA0000C7X00
Rdown PR1858
2
2
4 9 EN_+VDD_18
IN3 EN
TEST
GND
PG 1 2
LX
0.75_1.8VALW_PWREN 90,99
PR1855
5
1
120K_0402_1%
PC1862 PR1856
LX_+VDD_18 0.1U_0402_16V7K 1M_0402_1%
VILMT
2
H : 12A
2
3 +3VALW
L : 8A 3
Floating : 10A
PR1860
10K_0402_5% 9/21 EE modify
1 90 2 1.8V_PRIM_PG
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_+VPP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K454P
Date: Wednesday, April 21, 2021 Sheet 100 of 121
A B C D
4
3
2
1
2 1 2 1
2
1
+
PCI71 PCI58 PCI53
22U_0603_6.3V6M 22U_0603_6.3V6M 220U_D7_2VM_R4.5M
+VDDCR_VDD
2 1 2 1
2
1
+
PCI72 PCI59
22U_0603_6.3V6M 22U_0603_6.3V6M PCI54
2 1 2 1 220U_D7_2VM_R4.5M
2
1
+
A
A
2
1
+
@PCI122 PCI73 PCI60
+VDDCR_VDD
330U_D2_2V_Y 22U_0603_6.3V6M 22U_0603_6.3V6M PCI55
2 1 2 1 2 1 220U_D7_2VM_R4.5M
2 1 2 1 2 1 PCI56
470U_D2_2.5VM_R4.5M
@PCI124 PCI75 PCI62
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2
1
+
2 1 2 1 2 1
+VDDCR_VDD
PC57
@PCI125 PCI76 PCI63 470U_D2_2.5VM_R4.5M
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
22uF_0603 X 16
reserve:
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
220uF_D2 x3
2 1 2 1 2 1
+VDDCR_VDD
@PCI131 PCI82 PCI69
330uF_D2 x1
22uF_0603 X 28
22uF_0603 X 10
@PCI132 PCI83 PCI70
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1
PCI84
22U_0603_6.3V6M
2 1
PCI85
22U_0603_6.3V6M
B
B
Issued Date
Security Classification
C
C
2 1 2 1
[AMD]:
2
1
+
2020/03/05
PCI113 PCI96 PCI92
22U_0603_6.3V6M 22U_0603_6.3V6M 470U_D2_2.5VM_R4.5M
+VDDCR_SOC
2 1 2 1
2
1
+
+VDDCR_VDD
2 1 2 1 2 1
22uF_0603 X 7
@PCI133
+VDDCR_SOC
2 1 2 1 2 1
2018/12/31
PCI121 PCI112
resreve:
22U_0603_6.3V6M 22U_0603_6.3V6M
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+VDDCR_SOC
220uF_D7 x1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
22uF_0603 X 5
Size
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Title
Date:
D
D
Document Number
of
Compal Electronics, Inc.
121
Rev
0.1
4
3
2
1
A B C D
1 1
2 2
3 3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- Reserve for PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K453P
Date: Wednesday, April 21, 2021 Sheet 102 of 121
A B C D
5 4 3 2 1
NVVDD
Main Func = VGA CORE TGP 80W
EDPc 68A
Peak Current 225A
+3VALW +3VALW Fsw:450K
NVVDD 12/18 PWR DVT2 modify OCP=300A
12/28 PWR DVT2 modify
Input Current:1.2*68/0.87/12=7.8A +5VS +5VALW OLP=56A
2K_0402_5%
1
2K_0402_5%
PRV3
PRV2
1
D D
+1V8_AON
@
2_0402_5%
PRV5 PRV4
2
9/24 PWR modify
PRV176
0_0402_5% 2_0402_5% Place close to
1 2
SDA_GPU GPU pins
10K_0402_5%
PRV8 PRV9
2
1
1
Config GN20P +3V3_SYS +3VS 0_0402_5% 1K_0402_5% PRV12
@ PRV7
@0@ PRV6 1 2 1 2 100_0402_1%
SCL_GPU
0_0402_5% 1 2
10K_0402_5%
10K_0402_5%
PRV11 PCV2
Vmin 0.3
1
PRV175
0_0402_5% 1 2
2
10/13 PWR modify
@ PRV10
1 2110 PRV14
NVVDD_EN
2.2U_0402_16V6K 0_0402_5%
Vmax 1.3 NVVDD_PSI#
1 2 1 2
NVVDD_VSS_SENSE
2
PRV13 0_0402_5% PRV15
Vboot 0.75 110
1
@ PCV3 1 2
NVVDD_PGOOD +NVVDD
1000P_0402_50V7K
PRV16 0_0402_5% 100_0402_1%
R1 6.19K
2
1 2
NVVDD_PWM_VID
SDA_PWR_NVVDD
VID_BUFF_NVVDD
SCL_PWR_NVVDD
PWM_VID_NVVDD
1 2 VID_BUFF_NVVDD_R 1 2 1 2
R2 20.5K 10/16 PWR modify NVVDD_VCC_SENSE
VCC_NVVDD
VSN_NVVDD
VSP_NVVDD
PSI_NVVDD
2
EN_NVVDD
2.8K_0402_1%
@ PCV4 4700P_0402_50V7K PRV18 6.19K_0402_1% PRV17 0_0402_5%
R3 2.8K
PRV19
PRV20 20.5K_0402_1% PCV5 PCV6 PRV23
PRV21 PRV22 1 2VREF_NVVDD 47P_0402_50V8J 330P_0402_50V8J 49.9_0402_1%
274_0402_1% 13.7K_0402_1% 1 2 1 2DIFF_NVVDD_R 1 2
R4 13.7K
1
1 2 1 2
40
39
38
37
36
35
34
33
32
31
104 TMON_NVVDD
R5 0.274 11/12 PWR modify PCV8 PRV24 PRV25
2200P_0402_50V7K 3.3K_0402_1% 1K_0402_1%
PSI
VID_BUFF
PWM_VID
PGOOD
EN
SCL
SDA
VCC
VSN
VSP
1 2 1 2FB_NVVDD_R 1 2 1 2
PRV1
C 4.7n 1K_0402_1% PCV7 4700P_0402_50V7K
1 2 REFIN_NVVDD 1 30 COMP_NVVDD 1/21 PVT PWR modify
NVVDD_B+ PCV9 0.01U_0402_16V7K REFIN COMP
10/16 PWR modify PCV1 1 2 VREF_NVVDD 2
VREF FB
29 FB_NVVDD
C 0.01U_0402_50V7K C
1 2 VRMP_NVVDD 3 28 DIFF_NVVDD
VRMP DIFF
SS_NVVDD 4 27 FSW_NVVDD1 2 PCV10 1000P_0402_50V8J PRV27
SS FSW 1 2 0_0402_5%
I2C_NVVDD 5 26 TMON_NVVDD 80W@ PRV26 1 2
I2C PUV01 TMON 41.2K_0402_1% ON@ PRV28 24.9K_0402_1%
LPC1_NVVDD 6 NCP81611MNTXG_QFN40_5X5 25 IOUT_NVVDD 1 2
LPC1 IOUT
For VISHAY setting 11/12 PWR modify
PWM5_NVVDD 7 24 ILIM_NVVDD 1 2 IOUT_NVVDD
LPC2 SA0000CAE00 ILIM ON@ PRV29 84.5K_0402_1%
104 PWM4_NVVDD 8 23 CSCOMP_NVVDD
PWM4_NVVDD PWM4/PHTH1 CSCOMP
104 PWM3_NVVDD 9 22 CSSUM_NVVDD
PWM3_NVVDD PWM3/PHTH2 CSSUM
PWM1/PHTH4
104 10 21 80W@VIS@PRV29 80W@VIS@PRV28 80W@VIS@PRV37
PWM2_NVVDD PWM2/PHTH3 CSREF
100P_0402_50V8J
84.5K_0402_1% 24.9K_0402_1% 215K_0402_1%
SD034845280 SD034249280 SD034215380
DRON
0.01U_0402_16V7K
CSP4
CSP3
CSP2
CSP1
NC1
NC2
NC3
NC4
2
10K_0402_1%
10K_0402_1%
1K_0402_5%
1K_0402_5%
33K_0402_5%
26.1K_0402_1%
26.1K_0402_1%
PCV11
41
AGND
1
1
PRV30
PRV31
PRV32
PRV33
@ PRV34
@ PRV35
@ PRV36
ON@ PRV37
11
12
13
14
15
16
17
18
19
20
1
VREF_NVVDD 432K_0402_1%
2
PCV13
1 2
+5VALW
140_0402_1%
ON@ PRV38 499_0402_1%
PRV41
104 1 2
PWM1_NVVDD
10K_0402_5%
ON@ PCV14 100P_0402_50V8J
@ PRV45
104 1 2
DRON_NVVDD
PRV43 301K_0402_1%
2
1
CSP1_NVVDD
2200P_0402_50V7K
@ PRV42 ON@ PRV44 499_0402_1% 1 2 103,104
68K_0402_5% 1 2
PCV15
PRV46 301K_0402_1%
2
2
ON@ PCV18 100P_0402_50V8J 1 2 CSP2_NVVDD
103,104
1 2
B B
2K_0402_1%
@60W@ PRV142
PRV58 301K_0402_1%
ON@ PRV53 499_0402_1% 1 2 CSP3_NVVDD
103,104
261_0402_1%
1 2
PRV47
80W@ON@ 80W@ PRV59 301K_0402_1%
PCV17 100P_0402_50V8J 1 2 CSP4_NVVDD
104
103,104
+5VALW 1 2
@ PRV177
2
0_0402_5% 80W@ON@
CSREF_NVVDD
2
1 2 PRV56 499_0402_1%
1 2
+5VS
PRV178
0_0402_5%
1 2
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
ON@ for ON Semi only is 0 ohm ON@ for ON Semi only is 100p
2
Note: Resistor Control BOM Config VIS@ for VISHAY only is 3.32K ohm VIS@ for VISHAY only is 470p
PRV161
PRV162
PRV163
PRV164
1
1
ON@ for ON Semi only is 0 ohm VIS@ PRV38 VIS@ PRV44 VIS@ PRV53 80W@VIS@PRV56
10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1%
SD034100280 SD034100280 SD034100280 SD034100280
VIS@ for VISHAY only is 20K ohm
ON@
ON@
ON@
ON@
103,104
103,104
103,104
103,104
VIS@ PRV161 VIS@ PRV162 VIS@ PRV163 VIS@ PRV164
10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1% VIS@ PCV12 VIS@ PCV14 VIS@ PCV18 80W@VIS@PCV17
SD034100280 SD034100280 SD034100280 SD034100280 470P_0402_50V8J 470P_0402_50V8J 470P_0402_50V8J 470P_0402_50V8J
CSP4_NVVDD
CSP3_NVVDD
CSP2_NVVDD
CSP1_NVVDD
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_VGA_NCP81610MNTXG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K454P
Date: Wednesday, April 21, 2021 Sheet 103 of 121
5 4 3 2 1
1 2 3 4 5
EMI@ PCV99
0.1U_0402_25V6
EMI@ PLV13 2 3 2 3
5A_Z80_0805_2P Fsw:450K
1
10P_0402_50V8J
0.005_2512_1% 0.005_2512_1%
RF@ PCV32
2
1
A VISHAY@ for VISHAY MOS only A
CSSP_B+ CSSN_B+ CSSP_FBVDD CSSN_FBVDD
2
VIS@ PUV2 VIS@ PUV3 VIS@ PUV4 VIS@ PUV5
SIC830ED SCI830ED SCI830ED SCI830ED
SA0000E0Z00 SA0000E0Z00 SA0000E0Z00 SA0000E0Z00
Close to controller
(PUV1) pin3
NVVDD_B+
NVVDD_B+
PRV166
2 1 12/28 PWR DVT2 modify PRV170
10/30 for PPM Modify 2 1
0_0402_5%
10U_0805_25VX7SK
10U_0805_25VX7SK
10U_0805_25VX7SK
10U_0805_25VX7SK
2200P_0402_50V7K
1U_0402_25V6K
1000P_0402_25V8J
0.1U_0402_25V6
0_0402_5%
10U_0805_25VX7SK
10U_0805_25VX7SK
10U_0805_25VX7SK
10U_0805_25VX7SK
2200P_0402_50V7K
EMI@ PCV33
EMI@ PCV37
EMI@ PCV34
EMI@ PCV35
1000P_0402_25V8J
EMI@ PCV66
EMI@ PCV67
EMI@ PCV68
EMI@ PCV69
@ PCV72
0.1U_0402_25V6
1
1
PCV70
PCV71
@ PCV73
1U_0402_25V6K
1 PRV116
1
PCV38
PCV39
@ PCV36
@ PCV40
100U_D3L_25VM_R60M
100U_D3L_25VM_R60M
100U_D3L_25VM_R60M
PRV86 4.7_0603_5%
4.7_0603_5% @ PRV112
2
@ PRV87 0_0402_5% 1 2 2
1 1 1
2
0_0402_5% 1 2 2 1 2 TMON3_NVVDD BST3_NVVDD
+ + + 103,104 TMON_NVVDD
PCV42
PCV43
PCV55
103,104 TMON_NVVDD 1 2 TMON1_NVVDD
BST1_NVVDD
16
17
11
10
13
9
BST3_NVVDD_R
1
2 2 2
BST1_NVVDD_R +5VS
16
17
11
10
13
ZCD_EN
N/C
FAULT
VIN1
VIN
BOOT
9
1
+5VS 10/13 For PWR modify PCV80
PCV44 1/28 PWR PVT modify 0.22U_0603_25V7K
Use 0805 size
ZCD_EN Use 0805 size
N/C
FAULT
VIN1
VIN
BOOT
2
10/13 For PWR modify 0.22U_0603_25V7K 1
2
NC
2/9 PWR PVT modify
1 1 2 4 12 PHASE3_NVVDD
NC PVCC PHASE
1 2 4 12 PHASE1_NVVDD PCV77 1 2 VCC3_NVVDD 3
PVCC PHASE 2.2U_0402_6.3VAM VCC
PCV31 1 2 VCC1_NVVDD 3 2_0402_5% 2
Main: MAG LAYERS
VCC Main: MAG LAYERS AGND Package: 13.1 x 8.1 x 4
1
2.2U_0402_6.3VAM PRV107
Package: 13.1 x 8.1 x 4
1
2_0402_5% 2
AGND
PCV78 5
PGND
Idc=45A, Isat=77A
PRV88 PCV45 Idc=45A, Isat=77A 2.2U_0402_6.3VAM Rdc=0.48mohm +/-5%
2
2.2U_0402_6.3VAM 5 Rdc=0.48mohm +/-5% 20 ON@ PUV4
SH00001QL00 +NVVDD
2
PGND PGND2
SH00001QL00 +NVVDD 1/28 PWR PVT modify NCP303152MNTWG_PQFN41_5X6
1/28 PWR PVT modify 20
PGND2
ON@ PUV2 SA0000DIL00
B NCP303152MNTWG_PQFN41_5X6 HBM (2~<4KV) PLV3 B
SA0000DIL00 PLV1 103 PWM3_NVVDD 1 2 PWM3_NVVDD_R 14 8 LX3_NVVDD 1 2
HBM (2~<4KV) 1 2 PRV108 0_0402_5% PWM SW
1
103 PWM1_NVVDD 1 2 PWM1_NVVDD_R 14 8 LX1_NVVDD 103,104 1 2 DISB3_NVVDD 15 EMI@ 0.22UH_MHT-MHDZIR22MEM3-RT_45A_20%
PWM SW DRON_NVVDD DISB#
1
PRV90 0_0402_5% 0.22UH_MHT-MHDZIR22MEM3-RT_45A_20% PRV109 0_0402_5% PRV117 SH00001QL00
1 2 DISB1_NVVDD 15 EMI@ PRV92 SH00001QL00 18 4.7_1206_5%
103,104 DRON_NVVDD DISB# 103 CSP3_NVVDD IMON
PRV91 0_0402_5% 4.7_1206_5%
18 1 2 19
PGND1
103 CSP1_NVVDD 103,104
2
IMON CSREF_NVVDD PRV110 10_0402_1% REFIN
GL2
1 2 19 SN3_NVVDD
GL
PGND1
1
1 2 EMI@
GL
21
7
1 2 EMI@ PCV47 PCV81
680P_0402_50V7K 9/24 For PWR modify 680P_0402_50V7K
6
21
2
PCV79
PCV46 9/24 For PWR modify .1U_0402_16V7K
.1U_0402_16V7K
NVVDD_B+
C
NVVDD_B+ PRV171
C
2 1
10U_0805_25VX7SK
10U_0805_25VX7SK
10U_0805_25VX7SK
1000P_0402_25V8J
10U_0805_25VX7SK
2200P_0402_50V7K
1U_0402_25V6K
0.1U_0402_25V6
PRV172 0_0402_5%
EMI@ PCV83
EMI@ PCV84
EMI@ PCV85
EMI@ PCV86
PCV87
PCV88
@ PCV89
2 1 1
1
@ PCV90
PRV128
10U_0805_25VX7SK
10U_0805_25VX7SK
10U_0805_25VX7SK
10U_0805_25VX7SK
0_0402_5% 4.7_0603_5%
2200P_0402_50V7K
EMI@ PCV49
EMI@ PCV50
EMI@ PCV51
EMI@ PCV56
1U_0402_25V6K
1000P_0402_25V8J
0.1U_0402_25V6
@ PRV124
2
0_0402_5% 1 2 2
1
1
1
PCV57
PCV52
@ PCV53
@ PCV54
16
17
11
10
13
2
9
0_0402_5% 1 2 2 BST4_NVVDD_R
1
1 2 TMON2_NVVDD BST2_NVVDD +5VS
ZCD_EN
N/C
FAULT
VIN1
VIN
BOOT
103,104 TMON_NVVDD
10/13 For PWR modify PCV97
Use 0805 size
1/28 PWR PVT modify 0.22U_0603_25V7K
16
17
11
10
13
2
9
BST2_NVVDD_R 1
NC
1
+5VS
ZCD_EN
N/C
FAULT
VIN1
VIN
BOOT
1 PCV94 1 2 VCC4_NVVDD 3
NC 2.2U_0402_6.3VAM VCC
1 2 4 12 PHASE2_NVVDD PRV119 2
PVCC PHASE AGND Main: MAG LAYERS
1
2_0402_5%
PCV61 1 2 VCC2_NVVDD 3 PCV95 5 Package: 13.1 x 8.1 x 4
2.2U_0402_6.3VAM VCC PGND Idc=45A, Isat=77A
Main: MAG LAYERS 2.2U_0402_6.3VAM
2
2_0402_5% 2 20 ON@ PUV5 +NVVDD
AGND Package: 13.1 x 8.1 x 4 PGND2 Rdc=0.48mohm +/-5%
1
20
PGND2
ON@ PUV3
SH00001QL00 +NVVDD 103 PWM4_NVVDD 1 2 PWM4_NVVDD_R 14
PWM SW
8 LX4_NVVDD 1 2
1/28 PWR PVT modify NCP303152MNTWG_PQFN41_5X6 PRV120 0_0402_5%
1
SA0000DIL00 103,104 1 2 DISB4_NVVDD 15 0.22UH_MHT-MHDZIR22MEM3-RT_45A_20%
HBM (2~<4KV) PLV2 DRON_NVVDD DISB# EMI@
PRV121 0_0402_5% SH00001QL00
103 PWM2_NVVDD 1 2 PWM2_NVVDD_R 14 8 LX2_NVVDD 1 2 103 CSP4_NVVDD 18 PRV129
PRV102 0_0402_5% PWM SW IMON 4.7_1206_5%
1
1 2 DISB2_NVVDD 15 0.22UH_MHT-MHDZIR22MEM3-RT_45A_20% 1 2 19
PGND1
103,104 103,104
2
DRON_NVVDD PRV103 0_0402_5% DISB# EMI@ PRV104 SH00001QL00 CSREF_NVVDD PRV122 10_0402_1% REFIN SN4_NVVDD
GL2
18
GL
103 CSP2_NVVDD IMON 4.7_1206_5%
1
1 2 19 1 2 EMI@
PGND1
103,104
2
21
7
CSREF_NVVDD PRV105 10_0402_1% REFIN PCV98
2
GL2
SN2_NVVDD PCV96
1
1 2 .1U_0402_16V7K
6
21
EMI@ PCV64
9/24 For PWR modify 680P_0402_50V7K
2
PCV63
.1U_0402_16V7K
D D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_VGA_NCP30315
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K454P
Date: Wednesday, April 21, 2021 Sheet 104 of 121
1 2 3 4 5
A B C D
1 1
2 2
3 3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- Reserve for PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K453P
Date: Wednesday, April 21, 2021 Sheet 105 of 121
A B C D
A B C D
1 1
2 2
3 3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- Reserve for PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-K453P
Date: Wednesday, April 21, 2021 Sheet 106 of 121
A B C D
B
A
D
C
+NVVDD
2
1
+
330U_D2_2V_Y
PCV181
2
1
+
2 1 2 1 2 1 330U_D2_2V_Y
PCV182
1U_0402_6.3V7K 22U_0603_6.3VAM 10U_0603_6.3VAM
1
1
2
1
+
2 1 2 1 2 1
330U_D2_2V_Y
1U_0402_6.3V7K 22U_0603_6.3VAM 10U_0603_6.3VAM PCV183
PCV235 PCV220 PCV186
2
1
+
2 1 2 1 2 1
330U_D2_2V_Y
1U_0402_6.3V7K 22U_0603_6.3VAM 10U_0603_6.3VAM PCV184
PCV236 PCV221 PCV187
2 1 2 1 2 1
22U_0805_6.3VAM 10U_0603_6.3VAM
PCV232 PCV198
2 1 2 1
22U_0805_6.3VAM 10U_0603_6.3VAM
PCV233 PCV199
2 1
10U_0603_6.3VAM
PCV200
2 1
10U_0603_6.3VAM
2
2
PCV201
2 1
10U_0603_6.3VAM
PCV202
2 1
10U_0603_6.3VAM
PCV203
2 1
10U_0603_6.3VAM
PCV204
2 1
10U_0603_6.3VAM
PCV205
2 1
10U_0603_6.3VAM
PCV206
Place under GPU
2 1
10U_0603_6.3VAM
PCV207
2 1
10U_0603_6.3VAM
PCV208
2 1
10U_0603_6.3VAM
PCV209
2 1
10U_0603_6.3VAM
PCV210
2 1
10U_0603_6.3VAM
PCV211
2 1
10U_0603_6.3VAM
PCV212
2 1
10U_0603_6.3VAM
PCV213
2 1
+NVVDD
10U_0603_6.3VAM
PCV214
2 1
330uF X 4
10U_0603_6.3VAM
PCV215
2 1
1uF_0402 X 13
10uF_0603 X 34
10U_0603_6.3VAM
22uF_0805 X 15
PCV216
2 1
10U_0603_6.3VAM
3
3
PCV217
2 1
10U_0603_6.3VAM
PCV218
4
4
Issued Date
Security Classification
2019/04/19
Compal Secret Data
Deciphered Date
2020/04/19
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Title
Date:
5
5
Document Number
LA-K454P
Wednesday, April 21, 2021
Sheet
PWR_VGA_NCP30315
107
of
Compal Electronics, Inc.
121
Rev
0.1
B
A
D
C
5 4 3 2 1
12/16 PWR DVT2 modify
Main Func =+FBVDDQ PRW58
4.7K_0402_1%
1/21 PVT EE modify 12/16 PWR DVT2 modify
12/30 PWR DVT2 modify
+5VS +5VALW 1 2 ISEN1P_FBVDDQ
80W
1 2 2/1 PVT EE modify 12/30 PWR DVT2 modify PRW180 0_0402_5% PRW2
+3VALW
1
1 2 +5VALW 3.6K_0402_1% +FBVDDQ
1
2.2_0603_5%
@ PRW4
Vout = 1.2V - 1.25V
1
@PRW57
4.7K_0402_1% PRW1 @ PRW181 0_0402_5%
1
80W +3VS
1 2 2.2_0603_5% 1 2 +5VS PCW2
EDPc 15.9A
@ PRW3
Peak Current 21.3A
2
+FBVDDQ 10/12 EE modify 2/1 PVT EE modify FBVDD_B+ 2/1 PVT EE modify 1K_0402_1% 0.1U_0402_25V6
2
PVCC_FBVDDQ
Input Current:1.25*13/0.9/12=1.5A OCP=29.6A
2
DGPU_PWROK 1 2 ISEN1N_FBVDDQ
1
OVP 2.09 V (155%)
1
PCW1 PRW5
FSW=300KHz
1
100K_0402_1%
100K_0402_1%
PRW6 2.2U_0603_10V7K 0_0402_5%
1
PRW7
PRW8
91K_0402_1% @ PCW3
0.015U_0402_25V7K 2/22 DVT2 modify
17
2
2
1 2 FBVDDQ_N001
PVCC
+3VALW
LBSS139DW1T1G_SOT363-6
16 CSP1_FBVDDQ
2
CSP1
LBSS139DW1T1G_SOT363-6
D PRW9 D
10K_0402_1%
15 CSP2_FBVDDQ
CSP2
3
EN_FBVDDQ
6
+1.8VALW_GPU
PQW1B
PQW1A
D
5 G 1
PGOOD
0.22U_0402_25V6K
D
2 G S 14 CSP3_FBVDDQ
FBVDD/Q_EN CSP3
1
@ PCW42
S
4
PRW12 2
2
1 2 HBM 2KV EN/VINMON 13 CSN_FBVDDQ
15K_0402_1%
+3VS CSN
1
2
0_0402_5% PSI
10K_0402_1%
18
PWM3
10/13 For PWR modify PUW1
2
10K_0402_1%
REFIN_FBVDDQ 6 12 REFOUT_FBVDDQ 1 2
REFIN REFOUT
PRW19
2
1
5 11 COMP_FBVDDQ @ PRW54 10K_0402_1%
PRW20 REFADJ COMP PRW22
2
49.9K_0402_1% PRW21 PCW7 0_0402_5%
2/22 NV modify 8 10 FB_FBVDDQ 1 2 COMP_FBVDDQ_R 1 2 1 2
2200P_0402_50V7K
FS/OC/SS FB 30K_0402_1%
2
1U_0402_25V6K
FS_FBVDDQ 3300P_0402_25V7K
21 9 FBRTN_FBVDDQ @ PCW8
GND FBRTN
1
PRW23 1 2 FBVDDQ_N006
133K_0402_1%
PCW10
PCW9
PRW24 1K_0402_1% PRW25
1
16.9K_0402_1%
75K_0402_1% 1 2 0.015U_0402_25V7K 1 2
+FBVDDQ
PRW26
PRW27
100_0402_5%
2
2
PRW29
1 2 FBVDDQ_N005 1 2 FB_FBVDDQ_R 1 2
FB_VDDQ_SENSE
LBSS139DW1T1G_SOT363-6
+3VALW FBVDDQ_N002 @ PRW28 0_0402_5%
1
1K_0402_1% @ PCW11
C
Vout=2*[(PRW26//PRW27)/[PRW19+(PRW26//PRW27)] PRW30 0.015U_0402_25V7K @ PCW12 C
3
10K_0402_1% 0.015U_0402_25V7K
2
PQW2A
D
1 2 FBVDDQ_N003 5 G @PRW31
S 1 2
P0:high P8:low
4
LBSS139DW1T1G_SOT363-6
HBM 2KV 0_0402_5%
1
1 2 FBVDDQ_N004
MEM_VDD_CTL
PRW55 1 2
FB_GND_SENSE
PRW32 0_0402_5%
6
PQW2B
0_0402_5% D
@ PRW33
2 G 0_0402_5%
2
S
0.1U_0402_25V6
HBM 2KV
@ PCW13
+5VS
1
@0@
PRW34
0_0402_5%
teknisi-indonesia.com
2
+5VS +5VALW
@0@
1
1
1_0402_5%
PRW59
1
1_0402_5%
0_0402_5%
0_0402_5%
2
@PRW61
PRW62
PRW50 0_0402_5% 1
1 2 SMOD1_FBVDDQ 2 PWM
Main: MAG LAYERS
2
2
PRW38 2.2_0603_1% 4
AGND DISB#
17 DISB1_FBVDDQ 1 2 Idc=32A, Isat=55A
1