(T)EE2026

Digital Fundamentals
Introduction to Verilog

Massimo Alioto
Dept of Electrical and Computer Engineering
Email: [email protected]

1
Outline
• Introduction: Hardware Description
Languages
• Introduction to Verilog
– modules, inputs, outputs
– operators
– definition of Boolean expressions

2
Hardware Description Languages
• HDL = software programming language to model
the intended operation of a piece of hardware
• HDL vs programming languages
HDLs Programming languages
• concurrent execution • sequential execution
• account for timing • no timing information
• designed for HW modeling • permit HW modeling
• designed for HW synthesis • can be potentially used to
synthesize HW (difficult)

• Why using HDLs? Same language to...

– describe, verify/debug, designing a digital system 3
Automated Design Flows
• Automated translation of HDL into
programmable chip design (all steps are iterative)
clock
register
RTL synthesis Optimization
I O combinational Y=A*B*NOT(C) + NOT(A)*B*((A
(black box) logic XOR B)+E)+ (A+B) XOR (C+D)+
+ NOT(A)*NOT(B)*C

Behavioral
clock
register
combinational
description RTL description
expressions
directives (area,
time, resources)
Fitting
IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE I/O Element
(IOE)

Device Post-fitting IOE

IOE
Row
IOE

IOE
Local

programming simulation
Interconnect
EAB
Logic Element
(LE)
IOE IOE
Row
IOE IOE

Logic Array
EAB
Logic Array
Block (LAB)

Embedded
IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE Array Block
(EAB)
2K Bits RAM
4
Verilog

• Verilog was developed by Gateway Design

Automation as a simulation language in 1983
• Cadence purchased Gateway in 1989 and placed
the Verilog language in the public domain. Open
Verilog International (OVI) was created to develop
the Verilog language as an IEEE standard
• Verilog is a fairly simple language to learn,
especially if you are familiar with C
• References
– D. Harris, S. Harris, Digital Design and Computer
Architecture (1st ed.), Morgan Kaufmann
– http://www.asic-world.com/verilog/verilog_one_day.html
5
Commenting Code in Verilog
• Single line comments:
– begin with "//" and end with a carriage return
– may begin anywhere on the line

• Multiple line comments:

– begin with "/*" and end with a "*/"
– may begin and end anywhere on the line
– everything in between is commented out

• Coding style tip

– use single line comments for comments
– reserve multi-line comments for commenting out a
section of code
6
Example

module pound_one;
reg [7:0] a,a$b,b,c; // register declarations
reg clk;

initial
begin
clk=0; // initialize the clock
c = 1;
forever #25 clk = !clk;
end
/* This section of code implements
a pipeline */
always @ (posedge clk)
begin
a = b;
b = c;
end
endmodule

7
Identifiers in Verilog

• Verilog is case sensitive

Variable CASE_SENSITIVE = 0 different
Variable case_sensitive = 1 variables

• Identifiers = names assigned by the user to

Verilog objects (modules, variables, tasks...)
• Contain any sequence of letters, digits, a dollar
sign '$' , and the underscore '_' symbol.
– first character must be a letter or underscore
– escaped identifiers start with a backslash (\) and end
with white space
– examples: legal_identifier, _OK,OK_, OK_123,
CASE_SENSITIVE, case_sensitive; $_BAD,123_BAD
8
Logic Values

• Verilog has 4 logic values:

– ‘0’ represents zero, low, false, not asserted.

– ‘1’ represents one, high, true, asserted.

– ‘z’ or ‘Z’ represent a high-impedance value, which is

usually treated as an 'x' value.

– ‘x’ or ‘X’ represent an uninitialized or an unknown

logic value--an unknown value is either '1' , '0' , 'z' , or
a value that is in a state of change.

9
Data Types
• physical connections between devices
Nets • wire and tri (identical, typically: distinguish tristate nodes)
• no memory: continuously assigned (driven) by an assignment
wire a,b; // scalar wires
wire [7:0] in_bus; // multi-bit wire (bus)

• reg: storage devices, variables

Reg • on LHS of an assignment, reg is updated immediately and
holds its value until changed again
reg a; // scalar reg variable
reg [7:0] in_bus; // vectored reg variable

Parameters
• constants
parameter [2:0] a = 1; // 3-bit (little endian, [0:2] ok – big endian)
parameter width = 8; // default width for parameterizable design
10
Numbers
• Constant numbers are integer or real constants .
• Integers may be sized or unsized
– Syntax: <size>'<base><value> where:
• <size> is the number of bits
• <base is b or B (binary), o or O (octal), d or D (decimal), h or
H (hex)
• <value> is 0-9 a-f A-F x X z Z ? _
• Examples: 2'b01, 6'o243, 78, 4'ha

• Default radix is decimal, i.e. 1=1'd1

• underscores ( _ ) are ignored (use them like commas)
• When <size> is less than <value> - the upper bits are
truncated, e.g. 2'b101->2'b01, 4'hfcba->4'ha

11
Examples

• 3.14 decimal notation

• 6.4e3 scientific notation for 6400.0
• 16'bz 16 bit z (z is extended to 16 bits)
• 83 unsized decimal
• 8'h0 8 bits with 0 extended to 8 bits
• 2'ha5 2 bits with upper 6 bits truncated
(binary equivalent = 01)
• 2_000_000 2 million
• 16'h0x0z 16'b0000xxxx0000zzzz

12
Operators
• Verilog operators (in increasing order of precedence)
– ?: (conditional – cond_expr ? true_expr : false_expr)
– || (logical or – used when checking conditions)
– && (logical and – used when checking conditions)
– | (bitwise or)
– ~| (bitwise nor)
– ^ (bitwise xor)
– ^~ (or ~^) (bitwise xnor, equivalence) if bitwise operands have different bit width,
– & (bitwise and) the shorter one is zero-extended in MSBs
– ~& (bitwise nand)
– == (logical) != (logical) === (case – including x and z) !== (case – including x and
z)
– < (lower than)
– <= (lower than or equal to)
– > (greater than)
– >= (greater than or equal to)
– << (shift left)
– >> (shift right)
– + (addition), - (subtraction), * (multiply), / (divide), % (modulus)

13
Code Structure: Modules

• The module is the basic unit of code in the

Verilog language module name (port_names);

module port declarations

– describes any block of HW with
data type declarations
inputs/outputs
procedural blocks
– includes interfaces, functionality, continuous assignments
timing user defined tasks & functions

• Example primitive instances

module holiday_1(sat,sun,weekend); module instances

input sat, sun; specify blocks

output weekend; endmodule

assign weekend = sat | sun;

endmodule
14
Pictorial Summary of Module Structure

Module
Covers different
levels of
Ports abstraction
interfaces behavioral vs structural
description

Body always @ (posedge clk)....

Instances assign #3 out=(sel)?in0:in1;
Design partitioning
Concurrent blocks manages hierarchy (sub-
modules), enables
functionality
modularity (reusable) and
regularity (many times)

15
Module Port Declaration

• Scalar (1-bit) port declaration

– port_direction port_name, port_name...;
• Vector (multiple-bit) port declaration
– port_direction [port_size] port_name, port_name...;

– port_direction: input, inout (bi-directional) or output

– port_name: legal identifier
– port_size: is a range from [msb:lsb]

input a, into_here, george; // scalar ports

input [7:0] in_bus, data; //vectored ports
output [31:0] out_bus; //vectored port
inout [maxsize-1:0] a_bus; //parameterized port

16
Port Connection Rules
inputs need to be specified continuously
• Inputs (otherwise, value would be unclear)
– internally, must be of net data type
– externally, may be connected to reg or net data type

output may be generated by

• Outputs combinational or register
– internally may be of net or reg data type
– externally must be connected to a net data type.

• Inouts (most restrictive btwn inputs and outputs)

– internally must be of net data type
– externally must be connected to a net data type
17
Module Instantiation
• A module may be instantiated within another module,
there may be multiple instances of the same module
• ports of instances are either by order or by name
– use by order unless there are lots of ports, by name for libraries
and other peoples code (cannot mix the two in one instantiation)
syntax for instantiation with port order: just use same order as
module_name instance_name (signal, signal,...); module of the instance
syntax for instantiation with port name: explicit original names (+ actual signal)
module_name instance_name (.port_name(signal), .port_name (signal),... );
module example (a,b,c,d);
input a,b;
output c,d;
. . . .
endmodule
example ex_inst_1(in_1, in_2, w, z);
example ex_inst_2(in_1, in_2, , z); // skip a port (sets input to default value specified
within the instantiated module – ex.: input c = 1;)
example ex_inst_3 (.a(w), .d(x), .c(y), .b(z)); // w, x, y and z = wires around instance 18