Scribd
Upload
51 views

Computer Organization Exercise Answer5

The document discusses several topics related to computer architecture and pipelines. It contains questions and answers from multiple student groups. The key points are: 1) The document contains questions about pipeline concepts like branch prediction, exceptions, hazards and increasing instruction level parallelism. 2) Student groups selected correct and incorrect answer options for the questions and explained their reasoning. 3) Topics discussed included reducing branch penalties, dynamic scheduling, exception handling, increasing pipeline stages and static/dynamic multiple issue.

Uploaded by

RD
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
51 views

Computer Organization Exercise Answer5

The document discusses several topics related to computer architecture and pipelines. It contains questions and answers from multiple student groups. The key points are: 1) The document contains questions about pipeline concepts like branch prediction, exceptions, hazards and increasing instruction level parallelism. 2) Student groups selected correct and incorrect answer options for the questions and explained their reasoning. 3) Topics discussed included reducing branch penalties, dynamic scheduling, exception handling, increasing pipeline stages and static/dynamic multiple issue.

Uploaded by

RD
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 7

Computer Architecture

Fall, 2022
Week 13
2022.12.05

組別：

簽名：

◆ [group1]
Please select the correct options and explain the incorrect ones.
a. To reduce the delay of the taken branch, we can move branch execution earlier in
the pipeline.
b. Dynamic pipeline scheduling allows the CPU to execute instructions out of order
to avoid stalls but commit results to registers in order.
c. Interrupts and exceptions arise within the CPU and from external I/O controllers
respectively.
d. When an exception happens in a pipeline, we flush all instructions in the pipeline.
e. Exceptions are handled by the system control coprocessor in all instruction set
architectures.
Ans. a b
Explanation:
c. Should be the opposite.
d. Only the instruction and the subsequent instructions will be flushed.
e. It depends on the hardware design.
◆ [group11]
Select the correct statements.
(a) A superscalar processor is a CPU that implements instruction-level parallelism.
(b) We can reduce the delay of a taken branch by moving branch execution earlier from MEM to IF.
(c) Since the stall could be unpredictable, we solve this issue by using the concept of dynamic scheduling.
(d) As long as an exception happens in a pipeline, it still has to complete all the instructions which have
entered the pipeline.
(e) A superscalar processor tends to use compiler scheduled code. (If wrong, you should explain your
answer.)
(f) Both pipelining and static multiple issue employ instruction level parallelism.
(g) Compiler reordering instructions to execute is an example of the static multiple issue technique.
(h) Hardware can reorder instructions, while the compiler can look ahead for instructions to execute.

Ans: (A)(C)(F)

(B) IF -> ID. We can't fetch data in registers to compare in IF stage.


(D) Instructions after that exception might have to be flushed.
(E) (1) Not all stalls are predictable.
(2) Can’t always schedule around branches.
(3) Different implementations of ISA have different latencies and hazards.
(G) Compiler reordering instructions to execute is an example of the dynamic multiple issue technique.
(H) Compiler can reorder instructions, while hardware can look ahead for instructions to execute.

◆ [group13]
which following statement(s) are/is right?
A. In order to reduce the amount of penalty of flush, we move the execution of branch to ID in pipeline.
B. There are two kinds of unexpected events, exception arising from an external I/O controller and
interrupt from CPU.
C. With the prediction, we don’t need to know the target address of branch.
D. In MIPS, exceptions managed by a System Control Coprocessor(CP0).
E. In the process of handling the exceptions, we need to save PC of offending(or interrupted) instruction
at first, save indication of the problem secondly and jump to handler at 8000 00180 before jump to OS.
F. In the process of handling the exceptions, we don’t restart the program even if the program is
restartable in OS.
G. Pipelining is independent of the technology.
H. If we want to increase ILP(instruction-level parallelism), there are more stages.
ans:A, D, E, H
B. There are two kinds of unexpected events, exception arising from CPU and interrupt from an external
I/O controller.
C. We still need to calculate the target address of branch in prediction.
F. In the process of handling the exceptions, we would restart the program if the program is restartable.
G. Pipelining is dependent on the technology.
◆ [group10]
Choose the correct answers and also explain if it is false.
1. Branch prediction is more important when pipelines are longer.
2. In the dynamic prediction method, when branch prediction fails, we need to flush the pipeline and
keep the prediction unchanged.
3. With dynamic prediction, we don’t need additional cycles for a taken branch.
4. Compiler schedule applies to many situations including branches.
5. In the static multiple issue, the compiler groups instructions into “issue packets” and the group
of instructions that can be issued on a single cycle.
6. In the static multiple issue,there is no dependency in a packet and between packets.
7. In MIPS with static dual issue, it puts load/store instruction before ALU/branch in two issue packets.
8. In dynamic multiple issue, it allows the CPU to execute instructions out of order to avoid stalls.

A:
1. True.
2. False. We need to flip the prediction.
3. False. With dynamic prediction, we have a one cycle penalty for a branch taken.
4. False. The branches are excluded for the compiler wouldn’t know the result of branches in
advance.
5. True.
6. False. There would possibly has some dependencies between packets (This varies between ISAs)
7. False. The load/store instruction is put after ALU/branch in two issue packets.
8. True.

◆ [group12]
Datapath can be partitioned into several stages. Please organize the steps with correct
order for 4 instructions and calculate the total number of stages for each instruction.
(a) Instruction fetch
(b) Instruction decode
(c) Write the data back to the register file
(d) Execution
(e) Read/write data in Data Memory

1. Load
2. R-type
3. Beq
4. Store

Ans.
1. abdec, 5 stages
2. abdc, 4 stages
3. abd, 3 stages
4. abde, 4 stages
◆ [group4]
Please select the correct statement
a. ALUop requires 2 bits, 00, 01, 10 for R-type, lw/sw, beq respectively.
b. ALUctr2 = ALUop0 + ALUop1*func2*func1*func0’
c. We don’t care MemtoReg when the instruction is sw or beq, since RegWrite is 0.
d. RegDst = op5’*op4’*op3’*op2’*op1’*op0’
e. To add jump instruction, it doesn’t need an extra control.

Ans: c, d

a. 00, 01, 10 for lw/sw, beq, R-type respectively.


b. ALUctr2 = ALUop0 + ALUop1*func2’*func1*func0’
e. It needs.
◆ [group9]
Please select all correct answers, and explain if it is false
(a) we can increase the throughput by pipelining because the latency of each instruction is
shortened
(b) the concept behind pipeline is to increase hardware utilization
(c) in order to divide our MIPS datapath into 5 stages, adding 5 pipeline registers to original
structure is needed
(d) CISC is usually easier to pipeline compared to RISC
(e) it will take at least N-1 clocks to fill our pipeline with N stages
(f) one of the possible solutions of structural hazard is duplicating the resource
(g) pipeline with more stages always has better performance
(h) there are always multiple instructions in pipeline

ANS: (b)(e)(f)
(a) False, the instruction latency is unchanged
(b) True, overlapping the usage of hardware
(c) False, 4 pipeline registers is needed
(d) False, easier for RISC
(e) True
(f) True
(g) False, not necessarily
(h) False, not necessarily

You might also like