8051 Memory Organization

The 8051 microcontroller's memory is divided into Program Memory and Data
Memory.

Program Memory (ROM) is used for permanent saving program being executed, while
Data Memory (RAM) is used for temporarily storing and keeping intermediate results and
variables.

Program Memory (ROM)

 Program Memory (ROM) is used for permanent saving program (CODE) being
executed.

 The memory is read only. Depending on the settings made in compiler, program
memory may also used to store a constant variables.

 The 8051 executes programs stored in program memory only. Code memory type
specifier is used to refer to program memory.

 8051 memory organization allows external program memory to be added.

Internal ROM
 The 8051 has 4K (4096 locations) of on-chip ROM.
 This is used for storing the system program. 212 = 4096, therefore the internal ROM
address bus is 12 bits wide and internal ROM locations go from 000H to FFFH.

Internal Data Memory

Internal RAM
 There are 256 bytes of internal RAM on the 8051. 28 = 256, therefore the internal
RAM address bus is 8 bits wide and internal RAM locations go from 00H to FFH.
Register Banks
 There are four register banks from 00H to 1FH. On power-up, registers R0 to R7
are located at 00H to 07H.
Bit-addressable Locations
 The 8051 contains 210 bit-addressable locations of which 128 are at locations 20H
to 2FH while the rest are in the SFRs.
 Each of the 128 bits from 20H to 2FH have a unique number (address) attached to
them, as shown above.

General Purpose RAM

 These 80 bytes of Internal RAM memory are available for general-purpose data
storage.
 The general purpose RAM can be accessed using direct or indirect addressing mode
instructions.

Special Function Registers (SFRs)

 Locations 80H to FFH contain the special function registers.
 The 8051 provides 128 bytes of memory for Special Function Registers (SFRs).
 SFRs are bit, byte, or word-sized registers that are used to control timers, counters,
serial I/O, port I/O, and peripherals.

External Data Memory

 External Data Memory Access to external memory is slower than access to internal
data memory.
  There may be up to 64K Bytes of external data memory.
 Several 8051 devices provide on-chip XRAM space that is accessed with the same
instructions as the traditional external data space.
 This XRAM space is typically enabled via proper setting of SFR register and
overlaps the external memory space.

Calculate the number of address lines required to access 16 kB ROM.

Ans –

EXTRA –
How does the microcontroller handle external memory depends on the pin EA logical
state.
When EA = 0,
- then 8051 is completely ignored the internal program memory.
- It start the execution of a program stored in external memory.
When EA = 1,
- 8051 execute a program from internal ROM and
- After that execution is continued by executing the program from additional memory.
In both cases, P0 and P2 are used for data and address transmission, so they can not used
as normal I/O port.

8051 Boolean Processor –

  The CPU in each microcomputer is one of the industry's fastest and most efficient
for numerical calculations on byte operands.
 But controllers often deal with bits, not bytes: in the real world, switch contacts can
only be open or closed, indicators should be either lit or dark, motors are either
turned on or off, and so forth.
 For such control situations the most significant aspect of the MCS-51 architecture
is its complete hardware support for one-bit or Boolean variables
 The 8051 incorporates a number of special features which support the direct
manipulation and testing of individual bits and allow the use of single-bit variables
in performing logical operations. Taken together, these features are referred to as
the MCS-51 Boolean Processor.
 8051 microcontroller is a boolean processor. It means that even if 8051 is an 8 bit
microcontroller, it can process a single bit also. All the ports and few SFRs are bit
addressable. Some part of RAM is also bit addressable.
 8051 can process data on any bit of these SFRs. In instruction set, there are special
instructions for bit manipulation.

e.g., MOV C,P1.0; data on port pin P1.0 will be copied in carry flag

CLR C - means clear the carry bit

SETB PSW.0; PSW.0 (parity flag) will be set

Being Boolean processor, there are many advantages like:

 It can control individual I/O devices simultaneously without affecting others.

 It can manipulate a single bit/flag for specific applications.
 It can manipulate only some part of data, e.g., If you want to mask only lower
nibble of a port without affecting upper nibble.
 It can clear/reset a single flag.
 This enables 8051 to perform single bit logical operations.
 Using bit manipulation instructions reduces memory occupied by op codes as sizes
of these instructions are less.
 The Boolean Processor has:
 Its own instruction set.
 Its Accumulator: the carry flag.
 Bit Addressable RAM.
 Bit Addressable I/O.
 The 8051-microcontroller support bit addressable memory and bit manipulation for
Boolean processor.
Power Saving Options-idle and Power down mode –

 Power down and Idle mode features are used to save power in microcontrollers. 8051
has an inbuilt power-saving feature which is useful in embedded applications where
power consumption is the main constraint.
 There is a SFR ( last SFR in our list ) for power control mode in 8051. Only two bits in
the register are related to power saving mode in 8051 ( PD, IDL ).

PD IDL Status
0 0 Normal Power mode
0 1 Idle mode
1 0 Power down mode
1 1 Power down mode

Whenever the processor restarts by default it is in normal mode. The figure below depicts
the PCON ( power control ) register.
 8051 Power Control Logic

IDLE MODE
 In the Idle mode, the internal clock signal is cut from the CPU, but not to the
Interrupt, Timer and Serial Port functions.
 The CPU status is preserved in its entirety, the Stack Pointer, Program Counter,
Program Status Word, Accumulator, and all other registers maintain their data
during Idle.
 The port pins hold the logical state they had at the time idle mode was activated.
 ALE and PSEN hold at logic high levels.
 In this mode 80% of power is saved. The 20% power is used to get the
microcontroller from idle mode to normal mode.

There are two ways to terminate the idle mode.

1) Activation of any enabled interrupt will cause PCON.O to be cleared and idle
mode is terminated.
2) Hard ware reset: that is signal at RST pin clears IDEAL bit IN PCON register
directly. At this time, CPU resumes the program execution from where it left off.
POWER DOWN MODE

 In this mode, clock supply is cut from the whole system. In this power
saving mode maximum amount of power is saved.
 OR In the Power Down mode, the on-chip oscillator is stopped. With the clock
frozen, all functions are stopped, but the on-chip RAM and Special Function
Register are maintained held.
 The port pins output the values held by their respective SFRS. ALE and PSEN are
held low.

To Get out from idle mode:

1. Restart
In this method, the system is restarted, and the previous data is lost.

Difference between Power Down & Idle Mode

As shown in the above figure of 8051 power control logic, two control bits are there, IDL
and PD, which are used for Idle and Power-down mode respectively.

In Power Down mode, the oscillator clock provided to the system is OFF i.e. CPU and
peripherals clock remains inactive in this mode.

In Idle Mode, only the clock provided to the CPU gets deactivated, whereas the
peripherals clock will remain active in this mode.

Hence power saved in power-down mode is more than in idle mode.

The below table shows the power supply current required for 8051 family controllers in
Normal (Active), Idle and Power-down mode.
 Parameter Power Down Mode Idle Mode
Initialized by setting PCON.1 PCON.0
By Hardware Reset Any Enabled Interrupt or Hardware
Terminated By
Only Reset
Current 6.5mA 50uA
Condition of
Reinitialized Remain Unchanged
SFRs after Exit
Condition of Internal RAM Unchanged Unchanged
Condition of Ports during
Unchanged Unchanged
Sleep
On-Chip Oscillator Inactive Active
CPU status Inactive Inactive

As per the above table, it is clear that power consumption in power-down mode is less
than in Normal or idle mode.
8051 I/O port Structure –

I /O PORTS
 To communicate data with the external world the microcontroller needs ports.
 The ports may support either parallel or serial data transfer.
 It has 4 I/O ports namely, Port 0, Port 1, Port 2 & Port 3
 Port 1: is exclusively for input & output functions.
 Port 0, 2 & 3: perform functions other than parallel data transfer.
 All 4 ports are bidirectional.
 The 8 port pins are connected through 8 D type port latches.

Features of the four ports of 8051?

 Each port has 8 pins. Thus the four ports jointly comprise 32 pins.
 All ports are bidirectional.
 They are constructed with a D type output latch. They have output drivers and input
buffers.
 We can modify their functions using software and hardware that they connect to.
 All the ports are configured as input ports on Reset.
 To configure ports as an input port 1 must be written to that port
 To configure it as an output port 0 must be written to it.
PORT 0:

 Port -0 has 8 pins (P0.0-P0.7).

 Port-0 can be configured as a normal bidirectional I/O port or it can be
used for Address / data interfacing for accessing external memory.
 When control is '1', the port is used for address/data interfacing. When the control
is '0', the port can be used as a normal bi-directional I/O port.
 Port-0 latch is written to with 1's when used for external memory access.

Functions of Port 0 –

Port 0 of the 8051 has two main functions:

1) To be used as a simple input-output port and

2) To access external memory in conjunction with Port 2
Port 1:
Features of Port 1:

 Address is 90H
 Construction: Port 1 has one D latch, two unidirectional buffers, 1 FET,
and one internal pull-up resistor at each pin.
 It has only one function – to act as an Input-Output port.

Explanation -
 Port-1 has 8 pins (P1.1-P1.7)
 Port-1 does not have any alternate function i.e. it is dedicated only for I/O
interfacing.
 When used as output port, the pin is pulled up or down through internal pull-up.
 To use port-1 as input port, '1' has to be written to the latch. In this
input mode when '1' is written to the pin by the external device then it read
line.
 But when '0' is written to the pin by the external device then the
external source must sink current due to internal pull-up.
 If the external device is not able to sink the current the pin voltage may
rise, leading to a possible wrong reading.
Port 2 :
 Port-2 has 8-pins (P2.0-P2.7)
 Port-2 is used for higher external address byte or a normal input/output port.
The I/O operation is similar to Port-1.
Port-2 latch remains stable when Port-2 pin are used for external memory access.
 Here again due to internal pull-up there is limited current driving capability.

Functions of Port 2
Port-2 is used for higher external address byte or a normal input/output port. The I/O
operation is similar to Port-1.

PORT 3:
 Port-3 has 8 pin (P3.0-P3.7)
 Port-3 pins have alternate functions.
 Each pin of Port-3 can be individually programmed for I/O operation
or for alternate function.
  The alternate function can be activated only if the corresponding latch
has been written to '1'.
 To use the port as input port, '1' should be written.

Functions of Port 3-

Port 3 is multifunction part it can be used as a simple input/output port.

Alternate Functions of Port 3:

 P3.0 and P3.1 are used for the RxD (Receive Data) and TxD
(Transmit Data) serial communications signals.
 Bits P3.2 and P3.3 are meant for external interrupts.
Bits P3.4 and P3.5 are used for Timers 0 and 1 and P3.6 and P3.7 are used to
provide the write and read signals of external memories connected in 8031 based
systems
RXD: this is used for a serial input port
TXD: this is used for serial output port
INT0: this used for an external interrupt 0
INT1: this used for external interrupt 1
T0: Timer 0 external input
T1: Timer 1 external input
WR: external data memory write strobe
RD: external data memory Read strobe
All Department Student Association members and student Council
members are hereby informed that there will be meeting with respected
principal sir, scheduled on 31/03/2023 at 12:30pm in Seminal Hall (007)

Agenda of meeting is

1) Publicity of National Level Technical event Sanjivani Tech - Mantra 2K23

under ISTE student chapter.

2) Organization and smooth conduction of Sanjivani Tech - Mantra 2K23

Sanjivani Tech - Mantra 2K23 event.

Date: 31/03/2023

Time: 12:30pm

Venue : 007 (Conference Hall)

Note - It is compulsory to all.