+

William Stallings
Computer Organization
and Architecture
9th Edition
 2

+
Chapter 3
A Top-Level View of Computer
Function and Interconnection
+ 3

Computer Components

 Contemporary computer designs are based on concepts

developed by John von Neumann at the Institute for
Advanced Studies, Princeton

 Referred to as the von Neumann architecture and is based on

three key concepts:
 Data and instructions are stored in a single read-write memory
 The contents of this memory are addressable by location, without
regard to the type of data contained there
 Execution occurs in a sequential fashion (unless explicitly
modified) from one instruction to the next

 Hardwired program
 The result of the process of connecting the various components in
the desired configuration
+
Hardware
and Software
Approaches
 5

Software
• A sequence of codes or instructions Software
• Part of the hardware interprets each instruction and
generates control signals
• Provide a new sequence of codes for each new
program instead of rewiring the hardware
Major components:
• CPU I/O
• Instruction interpreter Components
• Module of general-purpose arithmetic and logic
functions
• I/O Components
+ • Input module
• Contains basic components for accepting data
and instructions and converting them into an
internal form of signals usable by the system
• Output module
• Means of reporting results
 6

Memory Memory buffer MEMORY

address register (MBR)
register (MAR) • Contains the data
• Specifies the to be written into
address in memory memory or
for the next read or receives the data
write read from memory

MAR

I/O address I/O buffer

register (I/OAR) register (I/OBR)
• Specifies a • Used for the
+ particular I/O exchange of data
device between an I/O
module and the
CPU MBR
 7

Computer
Components:
Top Level
View
+ 8

Basic Instruction Cycle

+ 9

Fetch Cycle
 At the beginning of each instruction cycle the processor
fetches an instruction from memory

 The program counter (PC) holds the address of the

instruction to be fetched next

 The processor increments the PC after each instruction

fetch so that it will fetch the next instruction in sequence

 The fetched instruction is loaded into the instruction

register (IR)

 The processor interprets the instruction and performs the

required action
Action Categories
10

•Data transferred from •Data transferred to or

processor to memory from a peripheral
or from memory to device by transferring
processor between the processor
and an I/O module

Processor- Processor-
memory I/O

Data
Control
processing

•An instruction may •The processor may

specify that the perform some
sequence of execution arithmetic or logic
be altered operation on data
+ 11
+
Example
of
Program
Execution
+ 13

Instruction Cycle State Diagram

+ 14

Classes of Interrupts
Program Flow Control 15
+ 16

Transfer of Control via Interrupts

+ 17

Instruction Cycle With Interrupts

+ 18

Program
Timing:
Short I/O
Wait
+ 19

Program
Timing:
Long I/O
Wait
Instruction Cycle State Diagram 20

With Interrupts
 21

Transfer of
Control

Multiple
Interrupts

+
+ Time Sequence of 22
E me
Multiple Interrupts x p
a l
+ 23

I/O Function
 I/O module can exchange data directly with the processor

 Processor can read data from or write data to an I/O module

 Processor identifies a specific device that is controlled by a
particular I/O module
 I/O instructions rather than memory referencing instructions

 In some cases it is desirable to allow I/O exchanges to occur

directly with memory
 The processor grants to an I/O module the authority to read from
or write to memory so that the I/O memory transfer can occur
without tying up the processor
 The I/O module issues read or write commands to memory
relieving the processor of responsibility for the exchange
 This operation is known as direct memory access (DMA)
 24
+ Computer
Modules
The interconnection structure must support the 25

following types of transfers:

Memory Processor I/O to or

I/O to Processor
to to from
processor to I/O
processor memory memory

An I/O
module is
allowed to
exchange
data
Processor Processor
directly
reads an Processor reads data Processor
with
instruction writes a from an I/O sends data
memory
or a unit of unit of data device via to the I/O
without
data from to memory an I/O device
going
memory module
through the
processor
using direct
memory
access
 26
A communication pathway Signals transmitted by any
connecting two or more one device are available for
devices reception by all other
• Key characteristic is that it is a devices attached to the bus
I
n
shared transmission medium • If two devices transmit during the
same time period their signals will
overlap and become garbled
n
e
Typically consists of multiple
t
communication lines Computer systems contain a
number of different buses B c
• Each line is capable of
transmitting signals representing
that provide pathways
between components at e
binary 1 and binary 0
various levels of the u t
r
computer system hierarchy

s i
c
System bus
o
o
• A bus that connects major The most common computer
computer components (processor,
memory, I/O) interconnection structures
are based on the use of one
or more system buses n
n
 27

Data Bus
 Data lines that provide a path for moving data among system
modules

 May consist of 32, 64, 128, or more separate lines

 The number of lines is referred to as the width of the data bus

 The number of lines determines how many bits can be

transferred at a time

 The width of the data bus

is a key factor in
determining overall
system performance
+ Address Bus Control Bus
28

 Used to designate the source or  Used to control the access and the
destination of the data on the use of the data and address lines
data bus
 If the processor wishes to  Because the data and address lines
read a word of data from are shared by all components there
memory it puts the address of must be a means of controlling their
the desired word on the use
address lines
 Control signals transmit both
 Width determines the maximum command and timing information
possible memory capacity of the among system modules
system
 Timing signals indicate the validity
 Also used to address I/O ports of data and address information
 The higher order bits are
used to select a particular  Command signals specify operations
module on the bus and the to be performed
lower order bits select a
memory location or I/O port
within the module
 29

Bus Interconnection Scheme

 30

C
o a
n t
B
f i
u
i o
s
g n
u s
r
+ 31

Elements of Bus Design

 32

Timing of
Synchronous
Bus
Operations
 33

Timing of
Asynchronous
Bus
Operations
+ 34

Point-to-Point Interconnect

Principal reason for change At higher and higher data

was the electrical rates it becomes
constraints encountered increasingly difficult to
with increasing the perform the synchronization
frequency of wide and arbitration functions in a
synchronous buses timely fashion

A conventional shared bus

on the same chip magnified
Has lower latency, higher
the difficulties of increasing
data rate, and better
bus data rate and reducing
scalability
bus latency to keep up with
the processors
 35
+Quick Path Interconnect
QPI
 Introduced in 2008

 Multiple direct connections

 Direct pairwise connections to other components
eliminating the need for arbitration found in shared
transmission systems

 Layered protocol architecture

 These processor level interconnects use a layered

protocol architecture rather than the simple use of
control signals found in shared bus arrangements

 Packetized data transfer

 Data are sent as a sequence of packets each of which

includes control headers and error control codes
 36

Multicore
Configuration
Using
QPI
 37

QPI Layers
+ 38

Physical Interface of the Intel QPI

Interconnect
+ 39

QPI Multilane Distribution

+ 40

QPI Link Layer

 Flow control function

 Performs two key  Needed to ensure that a
functions: flow control and sending QPI entity does not
error control overwhelm a receiving QPI
entity by sending data faster
 Operate on the level of than the receiver can process
the flit (flow control the data and clear buffers for
unit) more incoming data
 Each flit consists of a 72-
bit message payload
 Error control function
and an 8-bit error
control code called a  Detects and recovers from
cyclic redundancy check bit errors, and so isolates
(CRC) higher layers from
experiencing bit errors
+ 41

QPI Routing and Protocol Layers

Routing Layer Protocol Layer

 Packet is defined as the unit of
 Used to determine the course transfer
that a packet will traverse
across the available system  One key function performed at
interconnects this level is a cache coherency
protocol which deals with
 Defined by firmware and making sure that main
describe the possible paths memory values held in
that a packet can follow multiple caches are consistent

 A typical data packet payload

is a block of data being sent to
or from a cache
+ 42

Peripheral Component
Interconnect (PCI)
 A popular high bandwidth, processor independent bus that can
function as a mezzanine or peripheral bus

 Delivers better system performance for high speed I/O

subsystems

 PCI Special Interest Group (SIG)

 Created to develop further and maintain the compatibility of the PCI
specifications

 PCI Express (PCIe)

 Point-to-point interconnect scheme intended to replace bus-based
schemes such as PCI
 Key requirement is high capacity to support the needs of higher data rate
I/O devices, such as Gigabit Ethernet
 Another requirement deals with the need to support time dependent data
streams
+
PCIe
Configuration
+ 44

PCIe Protocol Layers

+ 45

PCIe Multilane Distribution

 46

PCIe
Transmit
and
Receive
Block
Diagrams
 Receives read and write requests from
+ 
the software above the TL and creates
request packets for transmission to a
destination via the link layer

PCIe  Most transactions use a split transaction

technique
Transaction Layer (TL)  A request packet is sent out by a
source PCIe device which then waits
for a response called a completion
packet
 TL messages and some write
transactions are posted transactions
(meaning that no response is
expected)

 TL packet format supports 32-bit

memory addressing and extended
64-bit memory addressing
+ 48

The TL supports four address

spaces:
 Memory  I/O
 The memory space includes  This address space is used
system main memory and
PCIe I/O devices
for legacy PCI devices, with
reserved address ranges
 Certain ranges of memory
addresses map into I/O used to address legacy I/O
devices devices

 Configuration  Message
 This address space enables  This address space is for
the TL to read/write control signals related to
configuration registers interrupts, error handling,
associated with I/O devices and power management
 49

PCIe TLP Transaction Types

+ 50

PCIe
Protocol
Data
Unit
Format
+ 51

TLP Memory Request Format

+ Summary
52
A Top-Level View of
Computer Function
and Interconnection
Chapter 3
 Point-to-point interconnect
 Computer components
 QPI physical layer
 Computer function
 QPI link layer
 Instruction fetch and
execute  QPI routing layer
 Interrupts  QPI protocol layer
 I/O function  PCI express
 Interconnection structures  PCI physical and logical
 Bus interconnection architecture
 Bus structure  PCIe physical layer
 Multiple bus hierarchies  PCIe transaction layer
 Elements of bus design  PCIe data link layer