Monte Carlo Analysis

with emphasis on Memory

L13, Part 1
The 3 Flavors of Chip Design
Integrated circuits have 3 essential types of components:
• Logic (circuits that “compute”)
• Memory (circuits that “store”)
• Analog (circuits that “interface”)
Analog
Designer

• Much of the progress in chips has been about computing faster

and storing more

• Our industry is unique in how long it has sustained exponential

growth: Moore’s Law
• You should be bragging about this to other engineers whose fields have
not had such a profound rate of progress

6/14/23 SS 2023 2
IBM Power 8

6/14/23 SS 2023 3
How to Make a Memory
• If it is about a loved one, a photo or a letter make wonderful
reminders and will last a long time
• If it is for a chip, we need a circuit that can reliably store a state

• With two inverters connected together, one can store a single

True/False value (a “bit”)

T F F T

• Sounds really simple, but…

6/14/23 SS 2023 4
How to Make LOTS of Memory
• Chips perform best when they have lots of data
• So we want a LOT of memory on a chip
• Example: Apple’s M1 chip has ~550 Million “bits”

• Solution: make devices very small

• Moore’s law is all about scaling devices
down after all!

• Problem: as we make the devices smaller,

the amount of 𝑉!" variability increases
very quickly
Eye from A. Asenov
🍬

6/14/23 SS 2023 5
An SRAM “Cell”
• Consists of the two cross-coupled Bit Line Bit Line Bar
inverters, plus two “access” devices Word Line

• Since it is desirable to have lots of

cells, a lot of engineering goes into
design and layout of the cell to
optimize it

• SRAM cell published by Intel with

0.346µm2 area in 45nm technology
• ~0.3µ x 1.2µ

6/14/23 SS 2023 6
From Cell to Memory
• We stack the cells so that they share word-lines horizontally and
share bit lines vertically
• The address decoder selects
cell cell cell cell cell cell cell cell

cell cell cell cell cell cell cell cell

one row of cells cell cell cell cell cell cell cell cell

cell cell cell cell cell cell cell cell

• The selected cells drive the

Address Decoder
cell cell cell cell cell cell cell cell

bit lines cell

cell
cell

cell
cell

cell
cell

cell
cell

cell
cell

cell
cell

cell
cell

cell

• A ”Sense Amplifier” at the cell

cell
cell

cell
cell

cell
cell

cell
cell

cell
cell

cell
cell

cell
cell

cell

bottom of the array senses cell cell cell cell cell cell cell cell

whether the cell is storing a cell

cell
cell

cell
cell

cell
cell

cell
cell

cell
cell

cell
cell

cell
cell

cell

0 or a 1 cell cell cell cell cell cell cell cell

cell cell cell cell cell cell cell cell

• The data read is then latched

at an output register
output data

6/14/23 SS 2023 7
Reading a Cell
• Pre-charge circuit charges Pre-Charge Circuit
the two bit lines to 𝑉## Bit Line Bit Line Bar

Word Line

• The word line is activated, so

one or the other bit line starts
going down in voltage

• When the voltage is low

enough, the sense amplifier Sense-Amplifier Circuit
triggers

6/14/23 SS 2023 8
Reading a Cell 𝑉!!
Pre-Charge

Bit Line Bit Line Bar

Word Line

Read Access Time

Sense-Amplifier Circuit

Output

6/14/23 SS 2023 9
Writing a Cell
Data
• Similar to the read,
except that the bit
Write Enable
lines are driven by
strong tri-state Bit Line Bit Line Bar
buffers which force
Word Line
the state of the cell to
the desired value

• We’re going to focus on

the read operation since
it is the one that is more
important for performance
Sense-Amplifier Circuit

Output

6/14/23 SS 2023 10
Sense Amps
𝑉!!
Pre-Charge
• Sense Amplifiers
are super important to
determining the speed Bit Line Bit Line Bar

of the SRAM Read operation Word Line

• Sense Amp could simply

be an inverter (but that does
not necessarily speed things
up)
• A +ve feedback clocked
inverter is one possibility → Output Output Bar

Sense Enable

6/14/23 SS 2023 11
Reading a 0 and a 1
Sense Enable

Bit Line Bar

0 1

Bit Line True 1 0

Word Line 2

Word Line 1

Pre-Charge

6/14/23 SS 2023 12
Parasitics and other Messy Things
• The cell exists in the company of many other cells
cell

cell

cell

• Cells in the same row share the same word line, while cell

cells in the same column share the same bit lines

cell

cell

cell

cell

• It is usually necessary to model the presence of the

cell

cell

other cells, as well as the R/C of the bit lines cell

cell
• We will model the presence of the other cells using our load cell

multiplier trick cell

6/14/23 SS 2023 13
Creating a Complete Column
Pre-Charge
• SRAMs are usually divided into
banks, and each bank is N×M cells
Bit Line Bit Line Bar
Word Line

• N is the number of columns

• M is the number of rows
125 other cells
Bit Line Bit Line Bar
Word Line

• It is common for M to be a power

of 2 (to simplify the addressing)
Bit Line Bit Line Bar
Word Line

• We’ll select M=128

• Larger arrays tend to be lower
performing
Output Output Bar

Sense
Enable

6/14/23 SS 2023 14
Creating a Complete Column
• We need one cell storing a 0 and another
cell storing a 1
• Because we want the access time for both Bit Line Bit Line Bar

cases
• We will use our “load multiplier” to create × ×
the other cells

• So we are reducing the number of devices Output Output Bar

we have to simulate from 775 to just 25 Sense

Enable

6/14/23 SS 2023 15
Implementation Details
cell cell cell cell cell cell cell cell

• If the SRAM cell is 0.3µ x 1.2µ cell cell cell cell cell cell cell cell

and our column is 128 bits high cell

cell
cell

cell
cell

cell
cell

cell
cell

cell
cell

cell
cell

cell
cell

cell
this means the height of the array

Address Decoder
cell cell cell cell cell cell cell cell

is 128 x 0.3µ = 38.4µ cell cell cell cell cell cell cell cell

cell cell cell cell cell cell cell cell

cell cell cell cell cell cell cell cell

cell cell cell cell cell cell cell cell

• For an 8K array, we will have 64 cell cell cell cell cell cell cell cell

cells across and the width of the

cell cell cell cell cell cell cell cell

cell cell cell cell cell cell cell cell

array is 64 x 1.2µ = 76.8µ cell cell cell cell cell cell cell cell

cell cell cell cell cell cell cell cell

• Depending on the technology, the wires

may play an important part in determining output data

the performance of the SRAM

6/14/23 SS 2023 16
Cells + Wires and Parasitics
• The well needs connections to 𝐵𝐿 𝐵𝐿
• Power, Ground

GND

GND
GND
VDD
• Word Line
• Bit Line and Bit Line Bar
WL Cell Cell

• The wires have both R and C

parasitics Cell
WL Cell
• The connections between M1
and the devices, as well as
between M1 and M2 also WL Cell Cell
Metal 1
have resistance

Metal 2
6/14/23 SS 2023 17
Aside: Estimating Parasitics
'(
• Resistance: 𝑅 = )*
𝜌+, = 0.017Ω𝜇

T A B

W S

6/14/23 SS 2023 18
Wiring Levels Example
This is an older 0.25µ
technology, current
“Last” Metal, X (and Y) processes have many
more layers of metal

M4, Y direction

The “X” and “Y”

M3, X direction directions are relative
to the PolySilicon
M2, Y direction
direction which is X

M1, X direction

Microns

“Local” interconnect layer

6/14/23 SS 2023 19
A Deeper Look
• Our basic cell is just two inverters

• What is exactly going on to make this be a “bit”?

Output
• DC transfer curve for an Yes… it inverts!
inverter →

• How does it look for the

two inverters together?

Input

6/14/23 SS 2023 20
Back to Back Inverters
• We can plot the forward and backward transfer curves together

B
• At the points where the
two lines intersect, the two
inverters are “in agreement” B A

• There appear to be three

agreement points?

• What is that about? This is A

supposed to be a bit, not
some sort of 3-values thing

6/14/23 SS 2023 21
Stability and Instability
• Not like my Ex-President

Unstable: will move away

with any perturbation

Stable: able to return

when moved away

6/14/23 SS 2023 22
Where are our Inverters Stable
• The middle point is not stable, any noise will cause the inverters to
go to one of the other of the stable points
B

• We can simulate this via this

circuit, points where the B A
current in the voltage source
is zero are stable

6/14/23 SS 2023 23
Stability and Noise
• The “butterfly curve” we plotted earlier is useful for understanding
how our SRAM cell responds to noise
B

• The largest rectangle that

can be embedded in each B A
“wing” is a measure of the
static noise margin of the
cell

• This can be done for the

static (DC) as well as dynamic SNM A
(transient) cases

6/14/23 SS 2023 24
Questions?

6/14/23 SS 2023 25
MOSFET Refresher
Source Gate Drain

• In Lecture 4 was looked at how a

MOSFET works, and mentioned the 0 +++

threshold voltage 𝑉!" as being the

needed amount of voltage on the gate
for the channel to begin conducting

accelerator
Ion
• We “set” the threshold voltage by
implanting dopant ions in the channel
to change it charge density and therefore
the ease with which the channel can be

Dopant Ions
made to conduct
• And in Lecture 5 we explained that
implantation is a random process in that the
location of the dopant ions is random

Source Drain
Channel
6/14/23 SS 2023 26
The Dope on Silicon
• Wafers are made from pure crystalline Silicon

• The nearest silicon atoms are 0.235nm apart

and a lattice constant of 0.543nm
• So a 5nm device is ~20 atoms

0.543nm
• Doping concentrations are in the range of
1013 to 1018 dopants / cm3 which works out to
be 10-8 to 10-3 dopants / nm3
5nm

20nm
• A device which is 5nm x 200nm x 20nm 200nm
will have ~20 dopant ions

6/14/23 SS 2023 27
Discrete vs. Average
• In a large device, the dopants are scattered all over and tend to
“average” out
• But as devices get
smaller, the averaging
disappears
• And therefore the
randomness of the
dopant locations is
much more visible
• And thus 𝑉!" is more
variable as devices are
made smaller!

6/14/23 SS 2023 28
Modeling & Simulation of 𝑉!" Variability
• Advanced Process Design Kits (PDK) Customer PDK Foundry
have information on the expected Design FAB
variability in threshold voltage Design Test
Chips Package

• Some advanced Spice version allow

easy access to enable adjustment of each device 𝑉*-
• We will do it in a simpler but more intuitive approach

• 𝑉*- is the voltage we have to overcome

in order to get the channel to conduct
• Adding a series voltage source on the Δ 𝑉"#
MOSFET gate accomplishes this

6/14/23 SS 2023 29
Simulating Stability
If you are at VDD the
current is zero, but if you
Current flowing reduce your voltage the
into source inverter fights you, giving
you current to bring you
back up

If you are here you

contemplate moving to
Canada or Europe

If you are at 0 the current

is zero, but if you increase
your voltage the inverter
fights you, taking current
from you to bring you
back down

Current flowing
out of source

6/14/23 SS 2023 30
Interpreting the Stability Curve

Safe

Safe

Noise Margin (Low) Noise Margin (High)

6/14/23 SS 2023 31
 Exploring our Stability Curve
* sram 32nm dc stability
OK * sram 32nm dc stability
.include 32nm_HP.pm
Better
.include 32nm_HP.pm
* make the DC voltage sources * make the DC voltage sources
VDD vdd 0 0.7 VDD vdd 0 0.7
VIN vin 0 0.0 VIN vin 0 0.0

v0 vin g0 0.0 .subckt nfet d g s b PARAMS: L=1.0 W=1.0 DVT=0.0

v1 vin g1 0.0 vx g gx {DVT}
v2 out g2 0.0 mx d gx s b NMOS L={L} W={W}
v3 out g3 0.0 .ends

M0 out g0 vdd vdd PMOS L=32n W=128n .subckt pfet d g s b PARAMS: L=1.0 W=1.0 DVT=0.0
M1 out g1 0 0 NMOS L=32n W=128n vx g gx {DVT}
M2 vin g2 vdd vdd PMOS L=32n W=128n mx d gx s b PMOS L={L} W={W}
M3 vin g3 0 0 NMOS L=32n W=128n .ends

.dc VIN 0.0 0.7 0.005 x0 out vin vdd vdd pfet PARAMS: L=32n W=128n
.print dc v(vin) i(VIN) x1 out vin 0 0 nfet PARAMS: L=32n W=128n
.end x2 vin out vdd vdd pfet PARAMS: L=32n W=128n
x3 vin out 0 0 nfet PARAMS: L=32n W=128n

.dc VIN 0.0 0.7 0.005

.print dc v(vin) i(VIN)
.end

6/14/23 SS 2023 32
Monte-Carlo Stability Curve
def write_spice_file(cktfile, P) :
f = open(cktfile, "w")
f.write(f"""* sram 32nm dc stability Write the spice file
.include 32nm_HP.pm with the 4 𝑉"# shifts
VDD vdd 0 0.7
VIN vin 0 0.0
.subckt nfet d g s b PARAMS: L=1.0 W=1.0 DVT=0.0
vx g gx {{DVT}}
mx d gx s b NMOS L={{L}} W={{W}}
.ends
.subckt pfet d g s b PARAMS: L=1.0 W=1.0 DVT=0.0
vx g gx {{DVT}}
mx d gx s b PMOS L={{L}} W={{W}}
.ends
x0 out vin vdd vdd pfet PARAMS: L=32n W=128n DVT={P[0]}
x1 out vin 0 0 nfet PARAMS: L=32n W=128n DVT={P[1]}
x2 vin out vdd vdd pfet PARAMS: L=32n W=128n DVT={P[2]}
x3 vin out 0 0 nfet PARAMS: L=32n W=128n DVT={P[3]}
.dc VIN 0.0 0.7 0.005
.print dc v(vin) i(VIN)
.end""")
f.close()

NMC = 1000 1000 Samples

PARAM = np.zeros(4)
rng = np.random.default_rng()
plt.figure(figsize=(10,10)) 𝜎$" = 0.06𝑉
for i in range(NMC) :
write_spice_file("y.ckt", rng.standard_normal(4)*0.06)
res = os.system("Xyce y.ckt >/dev/null 2>&1")
DATA = read_spice_file("y.ckt.prn") Run and plot
plt.plot(DATA[:,0], DATA[:,1], lw=0.5)

6/14/23 SS 2023 33
Results
• Art!

6/14/23 SS 2023 34
From Curve to Noise Margins
• Calculating the values
at which the minima
and maxima occur

• What is a reasonable
goal for the noise margin?
• A common rule of thumb
is 10% of 𝑉!!

• So we can consider a cell

that has less margin than
10% of 𝑉## as failing
0.07

6/14/23 SS 2023 35
Noise Margins are Correlated

Seems like we
have a lot of
room before cell
failure

Lower Limit = 10% 𝑉!!

6/14/23 SS 2023 36
Probabilities and Failures
• Let us assume that the probability of failure of an SRAM cell is 𝑝
• If we have 𝑁 cells in our array, then the probability that all 𝑁 are OK
is 𝑃56657 = 1 − 𝑝 8
𝑝
• Say we would like
99% of our arrays
to work, then we
0.99 = 1 − 𝑝 8 →
Type equation here.
To get a 1K bit array
working, 𝑝 has to be < 10-5!

6/14/23 SS 2023 37
Estimating the Failure Probability
• We can estimate the distribution, and from that estimate the
probability
• 𝑆𝑁𝑀" = 𝑁(0.24897,0.038872) and we want 𝑃𝑟𝑜𝑏(𝑆𝑁𝑀" ) < 0.07)

• How many sigma out is

that?
#.%&'()*#.#)
• 𝑧= = 4.6𝜎
#.#+'')%

• This corresponds to a
failure probability of
1.014×10-5
• Cannot do an array of more
than 1K with this cell 😳
6/14/23 SS 2023 38
ReReReDunDuncy
• In a large SRAM array, redundant rows and columns are added in
order to try and “fix” a broken array

• This has high overhead since you need to

add:
1. Built in self test (BIST) to find the failures
2. Extra rows and columns as “spares”
3. Complex logic to replace failed rows/columns

• OK for a large array, but not possible on a small one (< 32Kb)
• So we still have to deal with this problem

6/14/23 SS 2023 39
Questions?

6/14/23 SS 2023 40
 Project Feedback

• Plots, points, lines observations and models

• Histograms and histohellucination
• Information Gathering
• Jupyter and performance
• Too much of a black-box “don’t touch it” attitude
• Too much reading and writing of files
• Dictionary abuse

6/14/23 SS 2023 41
Plots, Points and Lines
• Most of you made plots like this →

• Recall: you know the points that

you simulated, but nothing about
the interval in between the points
• So: draw the points only

• And some said: It is observed that circuit activity varies in a

linear fashion with respect to input activity with a few outliers.
• In that case fit a line to the data and prove your point
• That is why we went over that in the modeling section ad nauseum
• When you have a model or equation, THEN you can draw the line

6/14/23 SS 2023 42
Histograms
• “The histogram
resembles a Gaussian
curve in all the cases”

• What are you smoking?

• This histogram does look

like a Gaussian… OK? →

6/14/23 SS 2023 43
Our Friend
• I was impressed that
some of you did a bit
of research on the
circuits and found out
what they are

• Then I got depressed

that so many of you did
no think to do so

• This literally was the first

hit in my google search →

6/14/23 SS 2023 44
P e r f o r m a n c e
• Many of you mentioned long CPU times for
running the various simulations

• A few used alternatives to Jupyter, like running

Python directly

• When computer time impacts “you” time,

you should look into options
• We’ll have a lecture about code performance if there is time

6/14/23 SS 2023 45
Black and White Boxes
• The intent of giving you the simulator in
source code was for you to feel free to
modify it
• Those who did Project 2 had no choice, but
many Project 1 teams did not “enter the code”

• Granted many of you were new to Python,

so…

• But this led to…

6/14/23 SS 2023 46
ReadWriteReadWriteReadWriteReadWriteReadWriteRea
• Because of not being willing to change the code, many were forced
to perform the tasks via files

500 Gb/s 500 Mb/s

• The bandwidth to Memory is 1000X faster than that to disc

• Don’t do that

6/14/23 SS 2023 47
Dictionary Abuse
• That poor poor Python dictionary it is so
so convenient

• There was much abuse of the dictionary

in the various submissions
• But some of you are new to Python and should be excused

• There are many alternatives that are worth learning, like in-memory
databases, data classes, etc…

6/14/23 SS 2023 48