VLSI LAB

Inverter

Source Code Testbench Code

module inver1(a, y); module inver3_v;
input a; reg a;
output y; wire y;
assign y=~a; inver1 uut (a,y);
initial begin
endmodule a = 0;
#5 a=1;
#5 a=0;
#5 a=1;
#5 a=0;
#5 a=1;
#5 a=0;
#5 a=1;
end
endmodule

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 VLSI LAB

Buffer

Source CodE Testbench code

module buff(a, y); module bu_v;
reg a;
input a;
wire y;
output y; buff uut (a,y);
initial begin
assign y=a;
a = 0;
endmodule #10 a=1;
#10 a=0;
#10 a=1;
#10 a=0;
#10 a=1;
#10 a=0;

end
endmodule

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 VLSI LAB

Transmission Gate

Source Code Testbench code

module trsg1(a, ctrl, y); module trsg2_v;

input a;
input ctrl; reg a;
output y; reg ctrl;
reg y; wire y;
always @(a,ctrl)
begin trsg1 uut (a,ctrl,y);
if (ctrl==1)
y<=a; initial begin
else a = 0;
y<=1'bz; #10 a=1;
end #10 a=0;
#10 a=1;
endmodule #10 a=0;

end
initial begin
ctrl=0;
#10 ctrl=1;
#10 ctrl=0;
#10 ctrl=1;
end
endmodule

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 VLSI LAB

Basic/Universal Gates

Source Code Testbench Code

module trfgate(a, b, c, d, e, module trfgate1_v;

f, g, h, i); reg a;
reg b;
input a;
wire c;
input b;
wire d;
output c; wire e;
output d; wire f;
output e; wire g;
output f; wire h;
output g; wire i;
trfgate uut (a, b, c, d, e, f,
output h;
g, h, i);
output i;
assign c=~a; initial begin
assign d=a|b; a = 0;
assign e=a&b; b = 0;
assign f=a^b;
#10 a=0;
assign g=~(a|b);
#10 b=0;
assign h=~(a&b);
#10 a=1;
assign i=~(a^b); #10 b=0;
#10 a=0;
endmodule #10 b=1;
#10 a=1;
#10 b=1;

end
endmodule

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 VLSI LAB

SR-Flip Flop

Source Code Testbench Code

module ssrff(s, r, clk, rst, module ssff_v;

q, qb); reg s;
reg r;
input s;
reg clk;
input r;
reg rst;
input clk; wire q;
input rst; wire qb;
output q; ssrff uut (s,r,clk,rst,q,qb);
output qb; initial begin
reg q; clk=1;
forever #5 clk=~clk;
always @(posedge clk)
end
begin initial begin
if(rst) rst=1;
q<=1'b0; #10 rst=0;
else #80 rst=1;
if (s==1'b0&& r==1'b0) #10 rst=0;
q<=q; end
else if(s==1'b0&& r==1'b1) initial begin
q<=1'b0;
else if(s==1'b1&& r==1'b0) s=0; r=0;
q<=1'b1; #15 s=0; r=1;
else if(s==1'b1&& r==1'b0) #15 s=1; r=0;
q<=1'bx; #15 s=1; r=1;
#30 s=0; r=0;
end
assign qb=~q; end
endmodule
endmodule

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 VLSI LAB

D-Flip Flop

Source Code Testbench Code

module dff1(d, clk, rst, q, qb); module dff_v;

input d;
input clk; reg d;
input rst; reg clk;
output q; reg rst;
output qb; wire q;
reg q; wire qb;
always@(posedge clk) dff1 uut (d,clk,rst,q,qb);
begin initial begin
if(rst) clk = 1;
q<=1'b0; forever #5 clk=~clk;
else end
q<=d; initial begin
end rst=1;
assign qb=~q; #10 rst=0;
#70 rst =1;
endmodule #10 rst=0;
#70 rst=1;

end
initial begin
d=0;
#10 d=1;
#10 d=0;
#10 d=1;
#10 d=0;

end
endmodule

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 VLSI LAB

T-Flip Flop

Source Code Testbench Code

module tff(t, clk, rst, q, qb); module tff1_v;

input t;
input clk; reg t;
input rst; reg clk;
output q; reg rst;
output qb;
reg tq; wire q;
always @(posedge clk) wire qb;
begin tff uut (t,clk,rst,q,qb);
if(rst) initial begin
tq<=1'b0; clk=1;
else forever #5 clk=~clk;
begin end
if(t==1'b1) initial begin
tq<=~tq; rst=1;
end #10 rst= 0;
end #80 rst= 1;
assign q=~tq; #10 rst = 0;
assign qb=~q; end
endmodule
initial begin
t=0;
#15 t=1;
#15 t=0;
#15 t=1;
#15 t=0;

end
endmodule

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 VLSI LAB

JK Flip Flop

Source Code Testbench Code

module jkf(j, k, clk, rst, q, module jkff_v;

qbar); reg j;
input j; reg k;
input k; reg clk;
input clk; reg rst;
input rst; wire q;
output q; wire qbar;
output qbar; jkf uut (j,k, clk,rst,q,qbar);
wire j,k,clk,rst,qbar; initial begin
reg q; clk=1;
always @ (posedge clk) forever #5 clk=~clk;
begin end
if(rst) initial begin
q<=1'b0; rst=1;
else if(j==0 && k==0) #10 rst=0;
q<=q; #80 rst=1;
else if(j==0 && k==1) #10 rst=0;
q<=1'b0; end
else if(j==1 && k==0) initial begin
q<=1'b1; j=0; k=0;
else if(j==1 && k==1) #10 j=0;k=1;
q<=~q; #10 j=1;k=0;
end #10 j=1;k=1;
assign qbar=~q; #10 j=0; k=0;
endmodule #10 j=0;k=1;
#10 j=1;k=0;
#10 j=1;k=1;
end
endmodule

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 VLSI LAB

4-bit Synchronous Counter

Source Code Testbench Code

module synch1(clk, rst, cout); module synch2_v;

input clk; reg clk;
input rst; reg rst;
output [3:0]cout; wire [3:0] cout;
reg[3:0]cout; synch1 uut (clk, rst, cout);
always @(posedge clk) initial begin
begin clk = 1;
if (rst) forever #5clk=~clk;
cout=4'b0000; end
else
cout<=cout+4'b0001; initial begin
end rst = 1;

endmodule //#100;
#5 rst=0;
#5 rst=1;
#5 rst=0;

end
endmodule

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 VLSI LAB

4-bit Asynchronous Counter

Source Code Testbench Code

module asyn(clk, rst, count); module asyn1_v;

input clk;
input rst; reg clk;
output [3:0] count; reg rst;
reg [3:0] count;
always @(negedge clk) wire [3:0] count;
if(rst)
count[0]=1'b0; asyn uut (.clk(clk),.rst(rst),
else .count(count));
count[0]=~count[0];
always @(negedge count[0]) initial begin
if(rst) clk=0; rst=0;
count[1]=1'b0; forever #5 clk=~clk;
else end
count[1]=~count[1]; initial begin
always @(negedge count[1]) rst=1;
if(rst) #10 rst=0;
count[2]=1'b0; #100 rst=1;
else #10 rst=0;
count[2]=~count[2];
always @(negedge count[2]) #200 $finish ;
if(rst) end
count[3]=1'b0;
else endmodule
count[3]=~count[3];
endmodule

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 VLSI LAB

Serial Adder

Source Code Testbench Code

module serialadd16(clk, rst, a, b, module serial162_v;

sum); reg clk;
input clk; reg rst;
input rst; reg [3:0] a;
input [3:0] a,b; reg [3:0] b;
output [4:0] sum; wire [4:0] sum;
reg[3:0] ina,inb;
reg[4:0]org; serialadd16 uut (.clk(clk),
wire s0,c0; .rst(rst),.a(a),.b(b),.sum(sum));
always @(posedge clk)
begin initial begin
if(rst) clk =1'b0;
begin forever #5 clk=~clk;
ina=a; end
inb=b; initial begin
org=5'b0; rst=1'b1;
end a=4'd9;
else b=4'd8;
begin #10 rst=1'b0;
ina={1'b0,ina[3:1]}; #30;
inb={1'b0,inb[3:1]}; #100;
org[4]=c0;
org [3:0]={s0,org [3:1]}; end
end endmodule
end
assign s0=ina[0]^inb[0]^org[4];
assign
c0=(ina[0]&inb[0]|(inb[0]&org[4])|
org[4]&ina[0]);
assign sum=org;
endmodule

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 VLSI LAB

Parallel Adder

Source Code Testbench Code

module par1(x, y, cin, sum, cout); module par2_v;

input [3:0] x,y; reg [3:0] x;
input cin; reg [3:0] y;
wire c1,c2,c3; reg cin;
output [3:0]sum;
output cout; wire [3:0] sum;
par stage0 (x[0], y[0], cin, sum[0], wire cout;
c1);
par stage1 (x[1], y[1], c1, sum[1], par1 uut (.x(x),.y(y),
c2); .cin(cin),.sum(sum),
par stage2 (x[2], y[2], c2, sum[2], .cout(cout));
c3);
par stage3 (x[3], y[3], c3, sum[3], initial begin
cout); x=4'b1001;
endmodule y=4'b1110;cin=0'b0;
module par (x,y,carryin,sum,carryout); #15
input x,y,carryin; x=4'b1111;y=4'b1010;cin=1'b1;
output sum,carryout; #15
assign sum=x^y^carryin; x=4'b1011;y=4'b0110;cin=1'b0;
assign #15
carryout=(x&y)|(y&carryin)|(carryin&x); x=4'b0111;y=4'b1110;cin=1'b0;
endmodule #15 $finish;

end
endmodule

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 VLSI LAB

Serial Adder Waveform

Parallel Adder Waveform

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 VLSI LAB

SAR (Successive Approximation Register)

Source Code
module controller(clk,go,valid,result,sample,value,cmp);
input clk; // clock input
input go; // go=1 to perform conversion
output valid; // valid=1 when conversion finished
output [7:0] result; // 8 bit result output
output sample; // to S&H circuit
output [7:0] value; // to DAC
input cmp; // from comparitor
reg [1:0] state; // current state in state machine
reg [7:0] mask; // bit to test in binary search
reg [7:0] result; // hold partially converted result
// state assignment
parameter sWait=0, sSample=1, sConv=2, sDone=3;
// synchronous design
always @(posedge clk) begin
if (!go) state <= sWait; // stop and reset if go=0
else case (state) // choose next state in state machine
sWait : state <= sSample;
sSample :
begin // start new conversion so
state <= sConv; // enter convert state next
mask <= 8'b10000000; // reset mask to MSB only
result <= 8'b0; // clear result
end
sConv :
begin
// set bit if comparitor indicates input larger than
// value currently under consideration, else leave bit clear
if (cmp) result <= result | mask;
// shift mask to try next bit next time
mask <= mask>>1;
// finished once LSB has been done
if (mask[0]) state <= sDone;
end
sDone :;
endcase
end
assign sample = state==sSample; // drive sample and hold
assign value = result | mask; // (result so far) OR (bit to try)
assign valid = state==sDone; // indicate when finished
endmodule

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 VLSI LAB

Testbench Code
module sar2_v;

// registers to hold inputs to circuit under test, wires for outputs

reg clk,go;
wire valid,sample,cmp;
wire [7:0] result;
wire [7:0] value;

// Instantiate the Unit Under Test (UUT)

controller uut (.clk(clk),.go(go),.valid(valid),.result(result),
.sample(sample),.value(value),.cmp(cmp));

// generate a clock with period of 20 time units

always begin
#10;
clk=~clk;
end
initial clk=0;
// simulate analogue circuit with a digital model
reg [7:0] hold;
always @(posedge sample) hold = 8'b01000110;
assign cmp =(hold >=value);
// monitor some signals and provide input stimuli
initial begin
#100; go=0;
#100; go=1;
#5000; go=0;
#5000; go=1;
#40; go=0;
#5000;
$stop;
end
endmodule

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 VLSI LAB

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