Low Cost, High Speed

Differential Driver
AD8131
FEATURES FUNCTIONAL BLOCK DIAGRAM
High speed
400 MHz, −3 dB full power bandwidth –DIN 1 8 +DIN
750Ω 750Ω
2000 V/μs slew rate VOCM 2 7 NC
Fixed gain of 2 with no external components
V+ 3 6 V–
Internal common-mode feedback to improve gain and phase 1.5kΩ 1.5kΩ

balance: −60 dB @ 10 MHz +OUT 4 5 –OUT

Separate input to set the common-mode output voltage AD8131

01072-001
Low distortion: 68 dB SFDR @ 5 MHz 200 Ω load NC = NO CONNECT
Power supply range +2.7 V to ±5 V
Figure 1.
APPLICATIONS
Video line driver
Digital line driver
Low power differential ADC driver
Differential in/out level shifting
Single-ended input to differential output driver

GENERAL DESCRIPTION
The AD8131 is a differential or single-ended input to –20

differential output driver requiring no external components for ΔVOUT, dm = 2V p-p

ΔVOUT, cm/ΔVOUT, dm
a fixed gain of 2. The AD8131 is a major advancement over op –30

amps for driving signals over long lines or for driving

BALANCE ERROR (dB)

differential input ADCs. The AD8131 has a unique internal –40

feedback feature that provides output gain and phase matching

that are balanced to −60 dB at 10 MHz, reducing radiated EMI –50

and suppressing harmonics. Manufactured on the Analog

VS = +5V
Devices, Inc. next generation XFCB bipolar process, the –60

AD8131 has a −3 dB bandwidth of 400 MHz and delivers a

differential signal with very low harmonic distortion. –70
VS = ±5V

01072-002
The AD8131 is a differential driver for the transmission of –80
1 10 100 1000
high-speed signals over low-cost twisted pair or coax cables. FREQUENCY (MHz)
The AD8131 can be used for either analog or digital video
Figure 2. Output Balance Error vs. Frequency
signals or for other high-speed data transmission. The AD8131
driver is capable of driving either Cat3 or Cat5 twisted pair or The AD8131’s differential output also helps balance the input
coax with minimal line attenuation. The AD8131 has for differential ADCs, optimizing the distortion performance of
considerable cost and performance improvements over discrete the ADCs. The common-mode level of the differential output is
line driver solutions. adjustable by a voltage on the VOCM pin, easily level-shifting the
input signals for driving single-supply ADCs with dual supply
The AD8131 can replace transformers in a variety of applications,
signals. Fast overload recovery preserves sampling accuracy.
preserving low frequency and dc information. The AD8131 does
not have the susceptibility to magnetic interference and hysteresis The AD8131 is available in both SOIC and MSOP packages for
of transformers. It is smaller, easier to work with, and has the high operation over −40°C to +125°C.
reliability associated with ICs.

Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
or otherwise under any patent or patent rights of Analog Devices. Trademarks and Tel: 781.329.4700 www.analog.com
registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2005 Analog Devices, Inc. All rights reserved.
AD8131

TABLE OF CONTENTS
Specifications..................................................................................... 3 Estimating the Output Noise Voltage ...................................... 16

±DIN to ±OUT Specifications...................................................... 3 Calculating the Input Impedance of an

Application Circuit..................................................................... 16
VOCM to ±OUT Specifications ..................................................... 4
Input Common-Mode Voltage Range in
±DIN to ±OUT Specifications...................................................... 5 Single-Supply Applications ....................................................... 17
VOCM to ±OUT Specifications ..................................................... 6 Setting the Output Common-Mode Voltage .......................... 17
Absolute Maximum Ratings............................................................ 7 Driving a Capacitive Load......................................................... 17
ESD Caution.................................................................................. 7 Applications..................................................................................... 18
Pin Configuration and Function Descriptions............................. 8 Twisted-Pair Line Driver........................................................... 18
Typical Performance Characteristics ............................................. 9 3 V Supply Differential A-to-D Driver.................................... 18
Operational Description................................................................ 15 Unity-Gain, Single-Ended-to-Differential Driver ................. 19
Theory of Operation ...................................................................... 16 Outline Dimensions ....................................................................... 20
Analyzing an Application Circuit............................................. 16 Ordering Guide .......................................................................... 20
Closed-Loop Gain ...................................................................... 16

REVISION HISTORY
6/05—Rev. A to Rev. B
Updated Format..................................................................Universal
Changed Upper Operating Limit .....................................Universal
Changes to Ordering Guide .......................................................... 20

Rev. B | Page 2 of 20
 AD8131

SPECIFICATIONS
±DIN TO ±OUT SPECIFICATIONS
25°C, VS = ±5 V, VOCM = 0 V, G = 2, RL, dm = 200 Ω, unless otherwise noted. Refer to Figure 5 and Figure 39 for test setup and label
descriptions. All specifications refer to single-ended input and differential outputs, unless otherwise noted.
Table 1.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Large Signal Bandwidth VOUT = 2 V p-p 400 MHz
−3 dB Small Signal Bandwidth VOUT = 0.2 V p-p 320 MHz
Bandwidth for 0.1 dB Flatness VOUT = 0.2 V p-p 85 MHz
Slew Rate VOUT = 2 V p-p, 10% to 90% 2000 V/μs
Settling Time 0.1%, VOUT = 2 V p-p 14 ns
Overdrive Recovery Time VIN = 5 V to 0 V Step 5 ns
NOISE/HARMONIC PERFORMANCE
Second Harmonic VOUT = 2 V p-p, 5 MHz, RL, dm = 200 Ω −68 dBc
VOUT = 2 V p-p, 20 MHz, RL, dm = 200 Ω −63 dBc
VOUT = 2 V p-p, 5 MHz, RL, dm = 800 Ω −95 dBc
VOUT = 2 V p-p, 20 MHz, RL, dm = 800 Ω −79 dBc
Third Harmonic VOUT = 2 V p-p, 5 MHz, RL, dm = 200 Ω −94 dBc
VOUT = 2 V p-p, 20 MHz, RL, dm = 200 Ω −70 dBc
VOUT = 2 V p-p, 5 MHz, RL, dm = 800 Ω −101 dBc
VOUT = 2 V p-p, 20 MHz, RL, dm = 800 Ω −77 dBc
IMD 20 MHz, RL, dm = 800 Ω −54 dBc
IP3 20 MHz, RL, dm = 800 Ω 30 dBm
Voltage Noise (RTO) f = 20 MHz 25 nV/√Hz
Differential Gain Error NTSC, RL, dm = 150 Ω 0.01 %
Differential Phase Error NTSC, RL, dm = 150 Ω 0.06 degrees
INPUT CHARACTERISTICS
Input Resistance Single-ended input 1.125 kΩ
Differential input 1.5 kΩ
Input Capacitance 1 pF
Input Common-Mode Voltage −7.0 to +5.0 V
CMRR ΔVOUT, dm/ΔVIN, cm; ΔVIN, cm = ±0.5 V −70 dB
OUTPUT CHARACTERISTICS
Offset Voltage (RTO) VOS, dm = VOUT, dm; VDIN+ = VDIN− = VOCM = 0 V ±2 ±7 mV
TMIN to TMAX variation ±8 μV/°C
VOCM = float ±4 mV
TMIN to TMAX variation ±10 μV/°C
Output Voltage Swing Maximum ΔVOUT; single-ended output −3.6 to +3.6 V
Linear Output Current 60 mA
Gain ΔVOUT, dm/ΔVIN, dm; ΔVIN, dm = ±0.5 V 1.97 2 2.03 V/V
Output Balance Error ΔVOUT, cm/ΔVOUT, dm; ΔVOUT, dm = 1 V −70 dB

Rev. B | Page 3 of 20
AD8131
VOCM TO ±OUT SPECIFICATIONS
25°C, VS = ±5 V, VOCM = 0 V, G = 2, RL, dm = 200 Ω, unless otherwise noted. Refer to Figure 5 and Figure 39 for test setup and label
descriptions. All specifications refer to single-ended input and differential outputs, unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth ΔVOCM = 600 mV 210 MHz
Slew Rate VOCM = −1 V to +1 V 500 V/μs
DC PERFORMANCE
Input Voltage Range ±3.6 V
Input Resistance 120 kΩ
Input Offset Voltage VOS, cm = VOUT, cm; VDIN+ = VDIN− = VOCM = 0 V ±1.5 ±7 mV
VOCM = float ±2.5 mV
Input Bias Current 0.5 μA
VOCM CMRR ΔVOUT, dm/ΔVOCM; ΔVOCM = ±0.5 V −60 dB
Gain ΔVOUT, cm/ΔVOCM; ΔVOCM = ±1 V 0.988 1 1.012 V/V
POWER SUPPLY
Operating Range ±1.4 ± 5.5 V
Quiescent Current VDIN+ = VDIN− = VOCM = 0 V 10.5 11.5 12.5 mA
TMIN to TMAX variation 25 μA/°C
Power Supply Rejection Ratio ΔVOUT, dm/ΔVS; ΔVS = ±1 V −70 −56 dB
OPERATING TEMPERATURE RANGE −40 +125 °C

Rev. B | Page 4 of 20
 AD8131
±DIN TO ±OUT SPECIFICATIONS
25°C, VS = 5 V, VOCM = 2.5 V, G = 2, RL, dm = 200 Ω, unless otherwise noted. Refer to Figure 5 and Figure 39 for test setup and label
descriptions. All specifications refer to single-ended input and differential outputs, unless otherwise noted.
Table 3.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Large Signal Bandwidth VOUT = 2 V p-p 385 MHz
−3 dB Small Signal Bandwidth VOUT = 0.2 V p-p 285 MHz
Bandwidth for 0.1 dB Flatness VOUT = 0.2 V p-p 65 MHz
Slew Rate VOUT = 2 V p-p, 10% to 90% 1600 V/μs
Settling Time 0.1%, VOUT = 2 V p-p 18 ns
Overdrive Recovery Time VIN = 5 V to 0 V Step 5 ns
NOISE/HARMONIC PERFORMANCE
Second Harmonic VOUT = 2 V p-p, 5 MHz, RL, dm = 200 Ω −67 dBc
VOUT = 2 V p-p, 20 MHz, RL, dm = 200 Ω −56 dBc
VOUT = 2 V p-p, 5 MHz, RL, dm = 800 Ω −94 dBc
VOUT = 2 V p-p, 20 MHz, RL, dm = 800 Ω −77 dBc
Third Harmonic VOUT = 2 V p-p, 5 MHz, RL, dm = 200 Ω −74 dBc
VOUT = 2 V p-p, 20 MHz, RL, dm = 200 Ω −67 dBc
VOUT = 2 V p-p, 5 MHz, RL, dm = 800 Ω −95 dBc
VOUT = 2 V p-p, 20 MHz, RL, dm = 800 Ω −74 dBc
IMD 20 MHz, RL, dm = 800 Ω −51 dBc
IP3 20 MHz, RL, dm = 800 Ω 29 dBm
Voltage Noise (RTO) f = 20 MHz 25 nV/√Hz
Differential Gain Error NTSC, RL, dm = 150 Ω 0.02 %
Differential Phase Error NTSC, RL, dm = 150 Ω 0.08 degrees
INPUT CHARACTERISTICS
Input Resistance Single-ended input 1.125 kΩ
Differential input 1.5 kΩ
Input Capacitance 1 pF
Input Common-Mode Voltage −1.0 to +4.0 V
CMRR ΔVOUT, dm/ΔVIN, cm; ΔVIN, cm = ±0.5 V −70 dB
OUTPUT CHARACTERISTICS
Offset Voltage (RTO) VOS, dm = VOUT, dm; VDIN+ = VDIN− = VOCM = 2.5 V ±3 ±7 mV
TMIN to TMAX variation ±8 μV/°C
VOCM = float ±4 mV
TMIN to TMAX variation ±10 μV/°C
Output Voltage Swing Maximum ΔVOUT; single-ended output 1.0 to 3.7 V
Linear Output Current 45 mA
Gain ΔVOUT, dm/ΔVIN, dm; ΔVIN, dm = ±0.5 V 1.96 2 2.04 V/V
Output Balance Error ΔVOUT, cm/ΔVOUT, dm; ΔVOUT, dm = 1 V −62 dB

Rev. B | Page 5 of 20
AD8131
VOCM TO ±OUT SPECIFICATIONS
25°C, VS = 5 V, VOCM = 2.5 V, G = 2, RL, dm = 200 Ω, unless otherwise noted. Refer to Figure 5 and Figure 39 for test setup and label
descriptions. All specifications refer to single-ended input and differential outputs, unless otherwise noted.
Table 4.
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth ΔVOCM = 600 mV 200 MHz
Slew Rate VOCM = 1.5 V to 3.5 V 450 V/μs
DC PERFORMANCE
Input Voltage Range 1.0 to 3.7 V
Input Resistance 30 kΩ
Input Offset Voltage VOS, cm = VOUT, cm; VDIN+ = VDIN− = VOCM = 2.5 V ±5 ±12 mV
VOCM = float ±10 mV
Input Bias Current 0.5 μA
VOCM CMRR ΔVOUT, dm/ΔVOCM; ΔVOCM = 2.5 V ±0.5 V −60 dB
Gain ΔVOUT, cm/ΔVOCM; ΔVOCM = 2.5 V ±1 V 0.985 1 1.015 V/V
POWER SUPPLY
Operating Range 2.7 11 V
Quiescent Current VDIN+ = VDIN− = VOCM = 2.5 V 9.25 10.25 11.25 mA
TMIN to TMAX variation 20 μA/°C
Power Supply Rejection Ratio ΔVOUT, dm/ΔVS; ΔVS = ±0.5 V −70 −56 dB
OPERATING TEMPERATURE RANGE −40 +125 °C

Rev. B | Page 6 of 20
 AD8131

ABSOLUTE MAXIMUM RATINGS

Table 5.1 Stresses above those listed under Absolute Maximum Ratings
Parameter Rating may cause permanent damage to the device. This is a stress
Supply Voltage ±5.5 V rating only, functional operation of the device at these or any
VOCM ±VS other conditions above those indicated in the operational
Internal Power Dissipation 250 mW section of this specification is not implied. Exposure to absolute
Operating Temperature Range −40°C to +125°C maximum rating conditions for extended periods may affect
Storage Temperature Range −65°C to +150°C device reliability.
Lead Temperature (Soldering 10 sec) 300°C
2.0
1
Thermal resistance measured on SEMI standard 4-layer board.
TJ = 150°C
8-lead SOIC: θJA = 121°C/W.

MAXIMUM POWER DISSIPATION (W)

8-lead MSOP: θJA = 142°C/W. 8-LEAD SOIC
PACKAGE
1.5

1.0

8-LEAD
MSOP
PACKAGE
0.5

01072-044
0
–50 –20 10 40 70 100 130
AMBIENT TEMPERATURE (°C)

Figure 3. Plot of Maximum Power Dissipation vs. Temperature

ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. B | Page 7 of 20
AD8131

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

–DIN 1 8 +DIN
750Ω 750Ω
VOCM 2 7 NC

V+ 3 6 V–
1.5kΩ 1.5kΩ
+OUT 4 5 –OUT

AD8131

01072-003
NC = NO CONNECT

Figure 4. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description
1 −DIN Negative Input.
2 VOCM Common-Mode Output Voltage. Voltage applied to this pin sets the common-mode output voltage with a ratio of
1:1. For example, 1 V dc on VOCM will set the dc bias level on +OUT and −OUT to 1 V.
3 V+ Positive Supply Voltage.
4 +OUT Positive Output. Note: the voltage at −DIN is inverted at +OUT.
5 −OUT Negative Output. Note: the voltage at +DIN is inverted at −OUT.
6 V− Negative Supply Voltage.
7 NC No Connect.
8 +DIN Positive Input.

Rev. B | Page 8 of 20
 AD8131

TYPICAL PERFORMANCE CHARACTERISTICS

12
VOUT = 2V p-p
VS = ±5V

1500Ω MSOP
6

GAIN (dB)
750Ω

49.9Ω AD8131 RL, dm = 200Ω SOIC

3
750Ω

24.9Ω
0

01072-004
1500Ω

01072-007
–3
1 10 100 1000
FREQUENCY (MHz)

Figure 5. Basic Test Circuit Figure 8. Large Signal Frequency Response

12 12
VOUT = 200mV p-p VOUT = 2V p-p
VS = ±5V
9 9

MSOP VS = ±5V
6 6
GAIN (dB)
GAIN (dB)

VS = +5V
3 3
SOIC

0 0

01072-008
01072-005

–3 –3
1 10 100 1000 1 10 100 1000
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 6. Small Signal Frequency Response Figure 9. Large Signal Frequency Response

12
VOUT = 200mV p-p

1500Ω
VS = ±5V 2:1 TRANSFORMER
6
GAIN (dB)

750Ω 300Ω HPF

LPF
ZIN = 50Ω
3 AD8131
49.9Ω 750Ω 300Ω
VS = +5V

24.9Ω
0
01072-009

1500Ω
01072-006

–3
1 10 100 1000
FREQUENCY (MHz)

Figure 7. Small Signal Frequency Response Figure 10. Harmonic Distortion Test Circuit (RL, dm = 800 Ω)

Rev. B | Page 9 of 20
AD8131
–50 –50
RL, dm = 800Ω VS = 5V
VOUT, dm = 1V p-p RL, dm = 800Ω
–60 –60
HD3 (F = 20MHz)
HD3 (V S = 3V)
DISTORTION (dBc)

DISTORTION (dBc)
–70 –70

HD3 (VS = 5V)

–80 –80 HD2 (F = 20MHz)

HD2 (V S = 3V) HD3 (F = 5MHz)

–90 –90
HD2 (VS = 5V)

–100 –100 HD2 (F = 5MHz)

01072-010

01072-013
–110 –110
0 10 20 30 40 50 60 70 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
FREQUENCY (MHz) DIFFERENTIAL OUTPUT VOLTAGE (V p-p)

Figure 11. Harmonic Distortion vs. Frequency Figure 14. Harmonic Distortion vs. Differential Output Voltage

–40 –50
RL, dm = 800Ω HD3 (VS = ±5V) VS = 3V
VOUT, dm = 2V p-p RL, dm = 800Ω HD3 (F = 5MHz)
–50
–60
HD3 (F = 20MHz)
–60 HD3 (VS = +5V)

DISTORTION (dBc)
DISTORTION (dBc)

–70

–70
–80
–80 HD2 (VS = ±5V) HD2 (F = 20MHz)

–90
HD2 (VS = +5V)
–90

–100 –100 HD2 (F = 5MHz)

01072-011

01072-014
–110 –110
0 10 20 30 40 50 60 70 0.25 0.50 0.75 1.0 1.25 1.5 1.75
FREQUENCY (MHz) DIFFERENTIAL OUTPUT VOLTAGE (V p-p)

Figure 12. Harmonic Distortion vs. Frequency Figure 15. Harmonic Distortion vs. Differential Output Voltage

–55 –50
VS = ±5V VS = ±5V
RL, dm = 800Ω HD3 (F = 20MHz) VOUT, dm = 2V p-p
–65 –60
HD2 (F = 20MHz) HD3 (F = 20MHz)
DISTORTION (dBc)

–70
DISTORTION (dBc)

–75

HD2 (F = 20MHz)
–85 –80

–95 –90 HD2 (F = 5MHz)

–105 –100
01072-015

HD2 (F = 5MHz) HD3 (F = 5MHz)

01072-012

HD3 (F = 5MHz)
–110
–115 200 300 400 500 600 700 800 900 1000
0 1 2 3 4 5 6
RLOAD (Ω)
DIFFERENTIAL OUTPUT VOLTAGE (V p-p)

Figure 13. Harmonic Distortion vs. Differential Output Voltage Figure 16. Harmonic Distortion vs. RLOAD

Rev. B | Page 10 of 20
 AD8131
–50 45
VS = 5V
RL, dm = 800Ω
VOUT, dm = 2V p-p
–60 40
HD2 (F = 20MHz)
HD3 (F = 20MHz)
DISTORTION (dBc)

–70

INTERCEPT (dBm)
35

VS = ±5V
–80 30

–90 25
HD2 (F = 5MHz) VS = +5V

–100 HD3 (F = 5MHz) 20

01072-016

01072-019
–110 15
200 300 400 500 600 700 800 900 1000 0 10 20 30 40 50 60 70 80
RLOAD (Ω) FREQUENCY (MHz)

Figure 17. Harmonic Distortion vs. RLOAD Figure 20. Third Order Intercept vs. Frequency

–50
VS = 3V
VOUT, dm = 1V p-p VS = ±5V
–60 HD3 (F = 20MHz)
HD2 (F = 20MHz)
VOUT, dm
DISTORTION (dBc)

–70

VOUT+
–80 VOUT–

–90

HD2 (F = 5MHz)
HD3 (F = 5MHz) V+DIN
–100
01072-017

01072-020
–110 1V 5ns
200 300 400 500 600 700 800 900 1000
RLOAD (Ω)

Figure 18. Harmonic Distortion vs. RLOAD

Figure 21. Large Signal Transient Response
10
0 fC = 500MHz
VS = ±5V
–10 RL, dm = 800Ω
VS = +5V
–20
–30
POUT (dBm)

–40
VS = ±5V
–50

–60
–70

–80

–90
01072-018

–100
–110
01072-021

49.5 50.0 50.5

40mV 5ns
FREQUENCY (MHz)

Figure 19. Intermodulation Distortion

Figure 22. Small Signal Transient Response

Rev. B | Page 11 of 20
AD8131

VS = +5V VOUT = 2V p-p

1500Ω

VS = ±5V
750Ω 24.9Ω

49.9Ω
AD8131 CL 150Ω
750Ω 24.9Ω

24.9Ω

01072-025
1500Ω

01072-022
400mV 5ns

Figure 23. Large Signal Transient Response Figure 26. Capacitor Load Drive Test Circuit

VOUT = 1.5V p-p CL = 5pF VS = ±5V

CL = 0pF
VS = 3V

CL = 20pF

01072-026
01072-023

300mV 5ns 400mV 1.25ns

Figure 24. Large Signal Transient Response Figure 27. Large Signal Transient Response for Various Capacitor Loads

0
ΔVOUT, dm
VS = ±5V
–10 ΔVS

–20

2mV/DIV –30
PSRR (dB)

VOUT, dm
–40 +PSRR
(VS = ±5V, +5V)
–50

1V/DIV –60
–PSRR
(VS = ±5V)
–70
01072-027

V+DIN
01072-024

4ns –80
1 10 100 1000
FREQUENCY (MHz)

Figure 25. 0.1% Settling Time Figure 28. PSRR vs. Frequency

Rev. B | Page 12 of 20
 AD8131

1500Ω 1500Ω

750Ω 100Ω 750Ω 100Ω

AD8131 VOUT, dm VOUT, cm AD8131

750Ω 49.9Ω 750Ω
24.9Ω
100Ω 100Ω
24.9Ω

01072-028

01072-031
1500Ω 1500Ω

Figure 29. CMRR Test Circuit Figure 32. Output Balance Error Test Circuit

–20 –20
VS = ±5V ΔVOUT, dm = 2V p-p
VIN, cm = 1V p-p ΔVOUT, cm/ΔVOUT, dm
–30 –30

BALANCE ERROR (dB)

–40 –40
CMRR (dB)

–50 ΔVOUT, dm/ΔVIN, cm –50

VS = +5V
–60 –60

–70 ΔVOUT, cm/ΔVIN, cm –70

VS = ±5V
01072-029

01072-032
–80 –80
1 10 100 1000 1 10 100 1000
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 30. CMRR vs. Frequency Figure 33. Output Balance Error vs. Frequency

100
15
SINGLE-ENDED OUTPUT

VS = ±5V
13
SUPPLY CURRENT (mA)

10
IMPEDANCE (Ω)

11
VS = +5V

9
1
VS = +5V

VS = ±5V 7
01072-030

0.1 01072-034
5
1 10 100 –50 –20 10 40 70 100 130
FREQUENCY (MHz) TEMPERATURE (°C)

Figure 31. Single-Ended ZOUT vs. Frequency Figure 34. Quiescent Current vs. Temperature

Rev. B | Page 13 of 20
AD8131
110 –20
VS = ±5V ΔVOUT, cm VS = ±5V
ΔVOCM
–30
90

–40 ΔVOCM = 600mV p-p

NOISE (nV/√Hz)

70

CMRR (dB)
–50

–60 ΔVOCM = 2V p-p

50

–70

30
–80

01072-037
01072-035
10 –90
0.1k 1k 10k 100k 1M 10M 100M 1 10 100 1000
FREQUENCY (Hz) FREQUENCY (MHz)

Figure 35. Voltage Noise vs. Frequency Figure 37. VOCM CMRR vs. Frequency

6
ΔVOUT, cm VS = ±5V
VS = 5V
ΔVOCM
VOCM = –1V TO +1V
VOUT, cm
3 ΔVOCM = 600mV p-p

0
GAIN (dB)

–3

ΔVOCM = 2V p-p
–6
01072-036

01072-038
–9 400mV 5ns
1 10 100 1000
FREQUENCY (MHz)

Figure 36. VOCM Gain Response Figure 38. VOCM Transient Response

Rev. B | Page 14 of 20
 AD8131

OPERATIONAL DESCRIPTION
RF
Common-mode voltage refers to the average of two node
voltages. The output common-mode voltage is defined as
RG +IN –OUT

VOUT ,cm = (V+OUT + V−OUT ) 2

+DIN –OUT
VOCM AD8131 RL, dm VOUT, dm
–DIN +OUT
RG –IN +OUT

01072-039
RF
Balance is a measure of how well differential signals are
matched in amplitude and exactly 180 degrees apart in phase.
Figure 39. Circuit Definitions Balance is most easily determined by placing a well-matched
resistor divider between the differential voltage nodes and
Differential voltage refers to the difference between two node
comparing the magnitude of the signal at the divider’s midpoint
voltages. For example, the output differential voltage (or
with the magnitude of the differential signal. By this definition,
equivalently output differential-mode voltage) shown in
output balance is the magnitude of the output common-mode
Figure 39 is defined as
voltage divided by the magnitude of the output differential-
VOUT ,dm = (V+OUT − V−OUT ) mode voltage.

V+OUT and V–OUT refer to the voltages at the +OUT and −OUT VOUT , cm
Output Balance Error =
terminals with respect to a common reference. VOUT , dm

Rev. B | Page 15 of 20
AD8131

THEORY OF OPERATION
The AD8131 differs from conventional op amps in that it has be assumed to be zero. Starting from these two assumptions,
two outputs whose voltages move in opposite directions. Like any application circuit can be analyzed.
an op amp, it relies on high open-loop gain and negative CLOSED-LOOP GAIN
feedback to force these outputs to the desired voltages. The
AD8131 behaves much like a standard voltage feedback op amp The differential mode gain of the circuit in Figure 39 can be
and makes it easy to perform single-ended-to-differential described by the following equation:
conversion, common-mode level-shifting, and amplification of
VOUT, dm RF
differential signals. = =2
V IN, dm RG
Previous discrete and integrated differential driver designs used
two independent amplifiers and two independent feedback where RF = 1.5 kΩ and RG = 750 Ω nominally.
loops, one to control each of the outputs. When these circuits
are driven from a single-ended source, the resulting outputs are ESTIMATING THE OUTPUT NOISE VOLTAGE
typically not well balanced. Achieving a balanced output Similar to the case of a conventional op amp, the differential
typically required exceptional matching of the amplifiers and output errors (noise and offset voltages) can be estimated by
feedback networks. multiplying the input referred terms, at +IN and −IN, by the
DC common-mode level shifting has also been difficult with circuit noise gain. The noise gain is defined as
previous differential drivers. Level shifting required the use of a
⎛R ⎞
third amplifier and feedback loop to control the output G N = 1 + ⎜⎜ F ⎟=3
⎟
common-mode level. Sometimes the third amplifier has also ⎝ RG ⎠
been used to attempt to correct an inherently unbalanced
circuit. Excellent performance over a wide frequency range has The total output referred noise for the AD8131, including the
proven difficult with this approach. contributions of RF, RG, and op amp, is nominally 25 nV/√Hz
at 20 MHz.
The AD8131 uses two feedback loops to separately control the
differential and common-mode output voltages. The differential CALCULATING THE INPUT IMPEDANCE OF AN
feedback, set by internal resistors, controls only the differential APPLICATION CIRCUIT
output voltage. The common-mode feedback controls only the The effective input impedance of a circuit such as that in
common-mode output voltage. This architecture makes it easy Figure 39, at +DIN and −DIN, will depend on whether the
to arbitrarily set the common-mode output level. It is forced, by amplifier is being driven by a single-ended or differential signal
internal common-mode feedback, to be equal to the voltage source. For balanced differential input signals, the input
applied to the VOCM input, without affecting the differential impedance (RIN, dm) between the inputs (+DIN and −DIN) is
output voltage.
R IN , dm = 2 × RG = 1.5 kΩ
The AD8131 architecture results in outputs that are very highly
balanced over a wide frequency range without requiring In the case of a single-ended input signal (for example if −DIN is
external components or adjustments. The common-mode grounded and the input signal is applied to +DIN), the input
feedback loop forces the signal component of the output impedance becomes
common-mode voltage to be zeroed. The result is nearly
perfectly balanced differential outputs, of identical amplitude ⎛ ⎞
⎜ ⎟
and exactly 180 degrees apart in phase. ⎜ R ⎟
R IN , dm =⎜ G
⎟ = 1.125 kΩ
RF
⎜⎜ 1 − ⎟
ANALYZING AN APPLICATION CIRCUIT
⎝ 2 × (RG + R F ) ⎟⎠
The AD8131 uses high open-loop gain and negative feedback to
force its differential and common-mode output voltages in such The input impedance is effectively higher than it would be for a
a way as to minimize the differential and common-mode error conventional op amp connected as an inverter because a
voltages. The differential error voltage is defined as the voltage fraction of the differential output voltage appears at the inputs
between the differential inputs labeled +IN and −IN in as a common-mode signal, partially bootstrapping the voltage
Figure 39. For most purposes, this voltage can be assumed to be across the input resistor RG.
zero. Similarly, the difference between the actual output
common-mode voltage and the voltage applied to VOCM can also

Rev. B | Page 16 of 20
 AD8131
INPUT COMMON-MODE VOLTAGE RANGE IN In cases where more accurate control of the output common-
SINGLE-SUPPLY APPLICATIONS mode level is required, it is recommended that an external
source, or resistor divider (made up of 10 kΩ resistors), be used.
The AD8131 is optimized for level-shifting ground referenced
input signals. For a single-ended input this would imply, for DRIVING A CAPACITIVE LOAD
example, that the voltage at −DIN in Figure 39 would be zero
A purely capacitive load can react with the pin and bondwire
volts when the amplifier’s negative power supply voltage (at V−)
inductance of the AD8131 resulting in high frequency ringing
was also set to zero volts.
in the pulse response. One way to minimize this effect is to
SETTING THE OUTPUT COMMON-MODE VOLTAGE place a small resistor in series with the amplifier’s outputs as
shown in Figure 26.
The AD8131’s VOCM pin is internally biased at a voltage
approximately equal to the midsupply point (average value of
the voltages on V+ and V−). Relying on this internal bias results
in an output common-mode voltage that is within about 25 mV
of the expected value.

Rev. B | Page 17 of 20
AD8131

APPLICATIONS
TWISTED-PAIR LINE DRIVER 3 V SUPPLY DIFFERENTIAL A-TO-D DRIVER
The AD8131 has on-chip resistors that provide for a gain of 2 Many newer ADCs can run from a single 3 V supply, which can
without any external parts. Several on-chip resistors are save significant system power. In order to increase the dynamic
trimmed to ensure that the gain is accurate, the common-mode range at the analog input, they have differential inputs, which
rejection is good, and the output is well balanced. This makes double the dynamic range with respect to a single-ended input.
the AD8131 very suitable as a single-ended-to-differential An added benefit of using a differential input is that the
twisted-pair line driver. distortion can be improved.

Figure 40 shows a circuit of an AD8131 driving a twisted-pair The low distortion and ability to run from a single 3 V supply make
line, like a Category 3 or Category 5 (Cat3 or Cat5), that is the AD8131 suited as an A-to-D driver for some 10-bit, single-
already installed in many buildings for telephony and data supply applications. Figure 41 shows a schematic for a circuit for an
communications. The characteristic impedance of such a AD8131 driving an AD9203, a 10-bit, 40 MSPS ADC.
transmission line is usually about 100 Ω. The outstanding
balance of the AD8131 output will minimize the common- The common mode of the AD8131 output is set at midsupply
mode signal and therefore the amount of EMI generated by by the voltage divider connected to VOCM, and ac-bypassed with
driving the twisted pair. a 0.1 μF capacitor. This provides for maximum dynamic range
between the supplies at the output of the AD8131. The 110 Ω
The two resistors in series with each output terminate the line at resistors at the AD8131 output, along with the shunt capacitors
the transmit end. Since the impedances of the outputs of the form a one pole, low-pass filter for lowering noise and
AD8131 are very low, they can be thought of as a short-circuit, antialiasing.
and the two terminating resistors form a 100 Ω termination at 3V
3V
the transmit end of the transmission line. The receive end is
+
directly terminated by a 100 Ω resistor across the line. 0.1 F 10 F 0.1 F
28 2
26 AVDD DRVDD
This back-termination of the transmission line divides the 3
110Ω
AINN
output signal by two. The fixed gain of 2 of the AD8131 will LPF 8 20pF
AD8131
create a net unity gain for the system from end to end. 49.9Ω 2
VOCM AD9203 DIGITAL
0.1 F OUTPUTS
1
In this case, the input signal is provided by a signal generator +3V 25
AINP
24.9Ω 6
with an output impedance of 50 Ω. This is terminated with a 110Ω 20pF AVSS DRVSS
10kΩ 27 1
49.9 Ω resistor near +DIN of the AD8131. The effective parallel
resistance of the source and termination is 25 Ω.The 24.9 Ω 10kΩ

01072-041
resistor from −DIN to ground matches the +DIN source
impedance and minimizes any dc and gain errors.
Figure 41. Test Circuit for AD8131 Driving an AD9203, 10-Bit, 40 MSPS ADC
If +DIN is driven by a low-impedance source over a short Figure 42 shows an FFT plot that was taken from the combined
distance, such as the output of an op amp, then no termination devices at an analog input frequency of 2.5 MHz and a 40 MSPS
resistor is required at +DIN. In this case, the −DIN can be directly sampling rate. The performance of the AD8131 compares very
tied to ground. favorably with a center-tapped transformer drive, which has
+5V typically been the best way to drive this ADC. The AD8131 has
+ the advantage of maintaining dc performance, which a
0.1μF 10μF
transformer solution cannot provide.
49.9Ω
3
8 5
49.9Ω 2 100Ω RECEIVER
AD8131
4
1 6
24.9Ω
49.9Ω

0.1μF 10μF
01072-040

+
–5V

Figure 40. Single-Ended-to-Differential 100 Ω Line Driver

Rev. B | Page 18 of 20
 AD8131
10
+5V
0
+ INPUT
–10 0.1 F 10 F
–20
–30
POUT (dBm)

3 –OUT
–40 8
5
–50 49.9Ω 2
AD8131
–60 1
4
–70 6
+OUT
–80
–90

01072-043
0.1 F 10 F
+
–100
–5V

01072-042
–110
–120 Figure 43. Unity Gain, Single-Ended-to-Differential Amplifier
2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0
FREQUENCY (MHz)

Figure 42. FFT Plot for AD8131/AD9203 As shown above, when −DIN is left floating, there is 100%
feedback of +OUT to −IN via the internal feedback resistor.
UNITY-GAIN, SINGLE-ENDED-TO-DIFFERENTIAL This contrasts with the typical gain of 2 operation where −DIN is
DRIVER grounded and one third of the +OUT is fed back to −IN. The
If it is not necessary to offset the output common-mode voltage result is a closed-loop differential gain of 1.
(via the VOCM pin), then the AD8131 can make a simple unity-
gain single-ended-to-differential amplifier that does not require Upon careful observation, it can be seen that only +DIN and VOCM
any external components. Figure 43 shows the schematic for are referenced to ground. The ground voltage at VOCM is the
this circuit. reference for this circuit. In this unity gain configuration, if a dc
voltage is applied to VOCM to shift the common-mode voltage, a
differential dc voltage will be created at the output, along with the
common-mode voltage change. Thus, this configuration cannot
be used when it is desired to offset the common-mode voltage of
the output with respect to the input at +DIN.

Rev. B | Page 19 of 20
AD8131

OUTLINE DIMENSIONS
5.00 (0.1968)
3.00
4.80 (0.1890) BSC

8 5
4.00 (0.1574) 6.20 (0.2440) 8 5
3.80 (0.1497) 1 4 5.80 (0.2284) 3.00 4.90
BSC BSC
1
4

1.27 (0.0500) 0.50 (0.0196)

BSC 1.75 (0.0688) × 45°
0.25 (0.0099) PIN 1
0.25 (0.0098) 1.35 (0.0532) 0.65 BSC
0.10 (0.0040)
0.51 (0.0201) 8° 1.10 MAX
0.15
COPLANARITY 0.25 (0.0098) 0° 1.27 (0.0500)
0.10 SEATING 0.31 (0.0122) 0.40 (0.0157)
0.00
PLANE 0.17 (0.0067) 0.80
0.38 8° 0.60
0.23
0.22 0° 0.40
COMPLIANT TO JEDEC STANDARDS MS-012-AA 0.08
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS COPLANARITY SEATING
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR 0.10 PLANE
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 44. 8-Lead Standard Small Outline Package [SOIC_N] Figure 45. 8-Lead Mini Small Outline Package [MSOP]
Narrow Body (RM-8)
(R-8) Dimensions shown in millimeters
Dimensions shown in millimeters and (inches)

ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
AD8131AR −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD8131AR-REEL −40°C to +125°C 8-Lead SOIC, 13” Tape and Reel R-8
AD8131AR-REEL7 −40°C to +125°C 8-Lead SOIC, 7” Tape and Reel R-8
AD8131ARZ 1 −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD8131ARZ-REEL1 −40°C to +125°C 8-Lead SOIC, 13” Tape and Reel R-8
AD8131ARZ-REEL71 −40°C to +125°C 8-Lead SOIC, 7” Tape and Reel R-8
AD8131ARM −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 HJA
AD8131ARM-REEL −40°C to +125°C 8-Lead MSOP, 13” Tape and Reel RM-8 HJA
AD8131ARM-REEL7 −40°C to +125°C 8-Lead MSOP, 7” Tape and Reel RM-8 HJA
AD8131ARMZ1 −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 HJA#
AD8131ARMZ-REEL1 −40°C to +125°C 8-Lead MSOP, 13” Tape and Reel RM-8 HJA#
AD8131ARMZ-REEL71 −40°C to +125°C 8-Lead MSOP, 7” Tape and Reel RM-8 HJA#
1
Z = Pb-free part, # denotes Pb-free part; may be top or bottom marked.

©2005 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
C01072–0–6/05(B)

Rev. B | Page 20 of 20