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INTRODUCTION TO SEMICONDUCTOR
RELIABILITY ENGINEERING and RELIABILITY LAB OPERATION

OSV, 26 – April – 2018

Prepared by Tam Vu

Internal Use Only

AGENDA

1 Introduction
2 Reliability Tests
3 Reliability Lab Operation
4 Reliability standards and Spec

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Introduction to Reliability

This training is designed with the idea of introducing new and experienced
engineers to the concepts in the area of reliability engineering in parallel of the
reliability lab established in OSV. Overview of the type of reliability stress tests
that are available within OSV for qualification/RAP monitoring.
 Meanwhile, it aims at improving awareness to product reliability and
subsequently instil a mind set to improve quality.

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Reliability and Quality

There is usually a confusion between Reliability and Quality.

Reliability, in a nutshell, is concerned with the performance of a product over
the course of its lifetime. This is subject to prescribed conditions according to
the product’s specification.
Quality on the other hand, is concerned with the performance of a product in
a particular point of time, usually during the manufacturing process.
Quality and reliability has some degree of correlation. As quality improves,
product consistency get better. This in turn also creates a more uniform
reliability. Quality issues are removed and this same problems, therefore,
cannot create defect-induced reliability failures. To some degree, high quality
can equate to high reliability.

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 1 Introduction
2 Reliability Tests
3 Reliability Lab Operation
4 Reliability standards and Spec

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Purpose
• Screening/Evaluation
– Suitable amount of stress (not enough to wear down or damage a device that has no latent defects) is
applied to products to wear down latent defects/early failures so that they can be detected and
removed by appropriate tests performed. Ex: 50x TC for wire short
– Electrical testing may be another type of screening without having to apply reliability stress. Ex :
Electrical test for defects that are screenable – broken wires
– Considerations in identifying screen:
• Failure mechanism, product application, history, customer returns
• must not have an adverse impact on non-defective products; must not reduce guaranteed life of
products
• Qualification – to evaluate and assess (qualify) new processes, BOM and products.
• Monitoring – performed periodically to assess and ensure that products maintain the performance and
functions throughout their life; continuously establish product performance
• Risk Assessment – performed to assess expected failure rate of products in the field over a given
period of time

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Types of Reliability Testing
• Intrinsic (Die or wafer level reliability)
 Test properties that are inherent to the process and materials. For example, dielectric strength,
resistance to metal migration, junction breakdown.
 These properties are typically tested using special structures that have been set up by NIST, JEDEC or
Sandia Labs. The testing stresses structures at highly elevated temperatures, voltages and currents to
cause rapidly accelerated failures typically in the wear out phase of the “Bath Tub Curve.”
 Typical tests performed: metal electromigration (EM), time dependent dielectric breakdown (TDDB),
stress migration (SM) and hot carrier injection (HCI). Most intrinsic reliability testing is currently sent to
outside labs. Normally used on IC technologies and Discrete technologies that are MOS based or have a
Gate structure. Not used on Zener, Rectifier, SST, SSD, BPT.

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Types of Reliability Testing
• Extrinsic (package level reliability)
 Test properties that are related to the final product that will involve the inter-relationships of the
material properties (mold compound, die attach, bonding wire), design, wafer fabrication,
manufacturing and final test.
 For the semiconductor market, JEDEC, AEC and the US Military have set up standards that define the
minimum testing required to ensure proper operation when components are integrated into large
systems. Most of the testing assumes an exponential distribution, i.e. it resides in the constant failure
rate portion of the bath tube curve. Most testing is performed for a set time, a given sample size and
an allowable failure rate. These tests are outlined in the reliability stress test slides.

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Reliability Tests – Accelerated Environment Stress Tests
Failure
Reliability Test Purpose Conditions Test Method
Mechanisms
Pre-Condition (PC) or Performed to determine Package crack Moisture Sensitivity Level: JSTD-020
Moisture moisture permeability of Die crack 24h Bake @125oC JESD22-
Preconditioning (if a non-hermetic solid- Lifted Ball Moisture Soak method A113
performed prior other state surface mount
stresses), MSL if device. Passivation Level 1: 85C, 85% RH, 168hr
performed alone to cracks Level 2: 85C, 60% RH, 168hr
determine MSL Level Popcorn effect Level 3: 30C, 60% RH, 192hr
Level 4: 30C, 60% RH, 96hr
Other Names: 3x Reflow
PCON

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Moisture Sensitivity Level
MSL: JSTD020, JESDA113 Moisture Level “Preconditioning” for Surface Mount Components
• Simulates the stress that the storage and mounting of devices may create.
• Determines Moisture Sensitivity Level of products and/or packages
• MSL: 1, 2, 3, 4, 5 indicate floor life of products
• Floor life = allowable time period after removal from a moisture barrier bag, dry storage,
or dry bake and before the solder reflow process.

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Moisture Sensitivity Level

Do not run MSL/preconditioning using accelerated conditions unless study was done
proving that the accelerated conditions do not cause spurious failure mechanisms
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(not normally detected when running at standard conditions).
Reliability Tests – Accelerated Environment Stress Tests

Reliability Test Purpose Failure Mechanisms Conditions Test Method

Autoclave Measures device resistance to Die corrosion or Pre-conditioned,

(AC) moisture penetration and the contaminants such as unbiased, JESD22-
resultant effects of galvanic foreign material on or Ta =121C, method A102
corrosion. Autoclave is an within the package 100%RH, 15 psig
Similar tests : accelerated and destructive material. Poor package
PCT – Pressure test. sealing.
Cooker Test 96 hours typically
PPoT – Pressure (extended for Cu)
Pot Test

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Reliability Tests – Accelerated Environment Stress Tests

AC Chamber

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Reliability Tests – Accelerated Environment Stress Tests

Corrosion on wire after AC Good wire after AC

Corrosion on die surface after AC 96hrs

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Reliability Tests – Accelerated Environment Stress Tests
Reliability Test Purpose Failure Conditions Test
Mechanisms Method
Unbiased Evaluates the reliability of non-hermetic Die corrosion or Pre-con,
Highly packaged solid-state devices in humid contaminants such unbiased JESD22-
Accelerated environments. It is a highly accelerated test as foreign material A118
Stress Test which employs temperature and humidity on or within the Ta = 130°C,
UHAST under non-condensing conditions to package materials. 85%RH, 18.8
accelerate the penetration of moisture through Poor package psig, 96hrs
the external protective material (encapsulant sealing.
Other names: or seal) or along the interface between the
uHAST external protective material and the metallic
uHST conductors which pass through it.
Bias is not applied in this test to ensure the
failure mechanisms potentially overshadowed
by bias can be uncovered (e.g. galvanic
corrosion).

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Reliability Tests – Accelerated Environment Stress Tests
Failure Test
Reliability Test Purpose Conditions
Mechanisms Method
Highly Accelerated Accelerates corrosion, particularly Die corrosion or Pre-conditioned, JESD-22
Stress Test (HAST) that of the die metal lines and thin contaminants such as Ta = 130C, 85% method
film resistors foreign material on or RH, 18.8 psig A110
within the package 96hrs
Measures the moisture resistance
materials. Poor
of plastic encapsulated devices. A
package sealing
bias is applied to create an Bias 80% rated
electrolytic cell necessary to voltage (100%
accelerate corrosion of the die (same fail mechs as VRWM for TVS)
metallization. With time, this is a THB and H3TRB but or 100V max.
catastrophically destructive test. at a more accelerated
HAST accelerates the same failure rate)
mechanisms as H3TRB (for
discretes)

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Reliability Tests – Accelerated Environment Stress Tests

HAST Chamber

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Reliability Tests – Accelerated Environment Stress Tests
Test
Reliability Test Purpose Failure Mechanisms Conditions
Method
Measures the moisture resistance Die corrosion or Pre-conditioned, JESD-22
H3TRB (High of plastic encapsulated devices. contaminants such as biased, method
Humidity High foreign material on or A101
A bias is applied to create an
Temp Reverse within the package Ta = 85°C, 85%
electrolytic cell necessary to
Bias) materials. RH, 1008hrs
accelerate corrosion of the die
metallization. With time, this is a Poor package sealing. Bias 80% rated
catastrophically destructive test voltage (100%
For discretes VRWM for TVS) or
only! 100V max.

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Reliability Tests – Accelerated Environment Stress Tests

Monitor:
- Water conductivity
- Temperature
- Humidity

H3TRB chambers
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Reliability Tests – Accelerated Environment Stress Tests

Reliability Test Purpose Failure Mechanisms Conditions Test Method

Temperature To evaluate the ability of Package crack, Pre-conditioned, unbiased JESD-22

Cycling the device to withstand Die crack, Lifted For Discrete: method A104
(TC) both exposure to extreme bonds, Wire Short, -55/ -650C to 1500C, and Appendix
temperatures and Lifted Die, Package 1000 cycles 3
transitions between defects, Hermetic Dwell time = 15mins.
temperature extremes. sealing defects, Load transfer time less
This test will also than 1 min.
accelerates the effects of Fractured/ Broken
thermal expansion wires
mismatch among the Dielectric/thin film
different components cracking
within a specific die and Solder fatigue
packaging system. (joint/bump/ ball),
Wire short

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Reliability Tests – Accelerated Environment Stress Tests

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Reliability Tests – Accelerated Environment Stress Tests

Broken wire after TC1000cyc Lateral crack die after TC500cyc

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Reliability Tests – Accelerated Environment Stress Tests
Test
Reliability Test Purpose Failure Mechanisms Conditions
Method
Determines the effect on devices Intermetallic compound, Unbiased JESD-22
High Temperature of long-term storage at elevated Stress migration, Junction For Discrete: method
Storage Life temperatures w/o any electrical degradation, Impurities Ta=T storage max A103.
(HTSL) stresses applied. deposit, Ohmic contact, (150/1750C)
or High Temp Measures stability of devices at bulk die and diffusion 1008hrs
Bake elevated temperatures defects.

Other names:
HTS

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Reliability Tests – Accelerated Environment Stress Tests

HTSL chambers

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Reliability Tests – Accelerated Environment Stress Tests

Intermetallic compound formation after HTSL 504hrs

Lifted wire after HTSL 1008hrs

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Reliability Tests – Life Stress Tests
Failure Test
Reliability Test Purpose Conditions
Mechanisms Method
Intermittent Accelerates the stresses Foreign material, Ta = 250C, ΔTj between on and off MIL
Operating Life on all bonds and crack and bulk state is a maximum of 100 deg C. STD750, M
(IOL) interfaces between the die defects, On and Off times vary based on 1037, AEC
chip and mounting face of metallization, package size and are specified as Q101
the devices subjected to wire and die follows:
For Discretes only! repeated turn on and off bond defects.
Small pkg (SMD SOTS thru D-pak
of equipment or devices
and all LEDS): 15000 cycles, 2 min
Other names: that have large power
on/off. (mid point 7500 cycles)
PRCL – Power dissipation (>1W).
Cycle Medium pkg (TO220, D2PAK):
8572 cycles, 3.5 min on/off. (mid
point 4286 cycles)
Large pkg ( TO-3, TO247): 6000
cycles, 5 min on/off. (mid point
3000 cycles)

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Reliability Tests – Life Stress Tests

IOL chamber

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Reliability Tests – Life Stress Tests

Solder die attach crack after IOL 7500cyc

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Reliability Tests – Life Stress Tests
Test
Reliability Test Purpose Failure Mechanisms Conditions
Method
To test the junction Ionic contamination on the Ta= Tjmax , 1008hrs JESD22-
High Temp integrity of the body diode, surface or under the Bias to 80% rated voltage A108
Reverse Bias crystal defects and ionic- metallization of the die. or 100% for automotive
(HTRB) contamination level. products.
(AEC Q101 rev. D)
For Discretes
only

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Reliability Tests – Life Stress Tests

HTRB chambers
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Reliability Tests – Life Stress Tests

Failure IDSS480 after 504hr HTRB (B160517-012)

The reduced breakdown voltage is created by a process defect nearby the
central gate feed. This process defect is resulting in missing oxide between
the source contact and the super junction.

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Reliability Tests – Life Stress Tests
Failure
Reliability Test Purpose Conditions Test Method
Mechanisms
SSOP (Steady State To operate the Ionic 1008 hrs at rated IZ MIL-STD-750-1
Operating Power) semiconductor device at contamination on max, Ta to rated TJ. M1038
specified conditions to the surface or Condition
In lieu of HTRB for reveal electrical failure under the B (Zeners)
Zeners modes that are time and metallization of
stress dependent. the die.

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Reliability Tests – Life Stress Tests

Reliability Test Purpose Failure Mechanisms Conditions Test Method

High Temperature The purpose of this test Random oxide defects Ta= 150 C, JESD22-A108
Gate Bias is to evaluate MOS gate and ionic contamination 100% rated gate
(HTGB) oxide capabilities. on the die surface, or on voltage.
oxide layer.
For Discretes only

Not applicable for

Bipolar device

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Reliability Tests – Life Stress Tests
A+B

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Reliability Tests – Life Stress Tests

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Reliability Tests – Package Integrity Tests

Reliability Test Purpose Failure Mechanisms Conditions Test Method

Wire Bond Pull or Determine adhesion strength of Lifted ball, lifted wedge due Pulling with MIL-STD-883
Bond Pull the wire bonding (ball and to corrosion or applied force Method 2011
Strength stitch), strength of wire to die, contaminants from foreign depending on
substrate, or package header material within the package wire diameter MIL-STD-750
Other names: connections. The wires may be or to wire bond issues; and material Method 2037
bonded by soldering, thermo- Silicon or metallization
WBP compression, ultrasonic, or defects.
BPS related bonding techniques.
WPS
WPT
BPULL

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Reliability Tests – Package Integrity Tests

Reliability Test Purpose Failure Mechanisms Conditions Test Method

Wire Bond Shear To determine adhesion Lifted ball due to Shearing or pushing AEC-Q100-001
strength of the wire/ball corrosion or ball bonds with AEC-Q101-003
Other names: bond to the bond pad contaminants from applied force
foreign material within depending on ball
WBS the package or wire diameter and material
BBS bond issues; Silicon or
BSHR metallization defects.

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Reliability Tests – Package Integrity Tests

Reliability Test Purpose Failure Mechanisms Conditions Test Method

Resistance to Measures the ability of a Shock failures – die Solder Temp: 265oC JESD22
Solder Heat device to withstand the cracking, package T= 10 seconds (5 A-111 (SMD)
(RSH) temperatures as may be seen crack, package-design seconds in flux prior B-106 (PTH)
in wave soldering operations. related to solder dipping)
Electrical testing is the
Other names: endpoint criterion for this
RSDH stress.

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Reliability Tests – Package Integrity Tests

RSH apparatus

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Reliability Tests – Package Integrity Tests

Reliability Test Purpose Failure Mechanisms Conditions Test Method

Solder Heat This test simulates Back metal structure defects, Immerse package 12MSV06288G
and Ice Test thermal shock. It is failures (applicable for devices in molten solder
(SHIT) performed by immersing with back side contact) (approx. 5-10s) and
the Pre and post electrical Indication of failure would be then immediately
test is performed to Vr, RDSon or VCEs shifts >10% into ice water.
ensure the part can (has to be manually observed
withstand the shock. by RE as ATE only looks at
>20%)

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Reliability Tests – Package Integrity Tests

SHIT apparatus

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Reliability Tests – Package Integrity Tests

Reliability Test Purpose Failure Mechanisms Conditions Test Method

Solderability Determines the wettability of Non-wetting, dewetting 1 hr or 8 hours steam J-STD-002
SD device package terminations due to poor plating or aging @ 93°C (±3) JESD22B102
by solder; ability of device contaminated leads depending on the lead
leads to be soldered after an finish
Other names: extended period of storage
SOLD or shelf life. Solder dip at required
temperature – 2450C,
10s.
Visual inspection.
Magnification 50x.

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Reliability Tests – Package Integrity Tests

Reliability Test Purpose Failure Mechanisms Conditions Test Method

Physical Determines whether the Incorrect dimensions Dimensions per JESD22-B100

Dimensions (PD) external physical dimensions due to package design device specific and B108
of the device are in issues or changes in LF, specs/package AEC Q003
Other names: accordance with the package components outline drawings
applicable procurement
PHYD document.

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Reliability Tests

Cavity Package Integrity Tests (Mechanical Shock,

Variable Frequency Vibration, Constant
Acceleration, Fine/Gross Leak, Package Drop,
Lead Torque, Die Shear, Internal Water Vapor), Die
Fabrication Reliability tests and electrical
verification tests are not included.

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Other Tests Required for Qualifications
There are also a series of tests that are normally required by reliability engineering but are the responsibility of
the PRODUCT ENGINEER to provide. These include but are not limited to:

TRI-TEMP CHARACTERIZATION: Electrical testing at high, low and room temperature obtained through the
characterization lab. This data will be required to complete the data sheet and to ensure that the device
operates properly at the extremes of the rated regions.

ESD CHARACTERIZATION: JS001, JS002, IEC61000-4-2 This test establishes the voltage range of electrical
discharge that the device can withstand without damage. Requirements for product release can be found in
12MSB17722C. There are several ESD tests that are performed by the characterization lab. Any of these may
be required by reliability depending on the technology and package size. Examples: ESD HBM (Human Body
Model), CDM (Charge Device Model)* and ESD per the instructions of the IEC61000-4-2. * CDM is required on
all packages greater than 7 mm x 7mm, except if TVS. CDM is then replaced by IEC61000-4-2. (reference
17722). MM (Machine Model) is now an obsolete test. Although it may be performed it is not normally
requested by rel.

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Other Tests Required for Qualifications
THERMAL RESISTANCE: The purpose of this test method is to measure the thermal impedance of the device
under the specified conditions of applied voltage, current and pulse duration. The data sheet will need to list
the thermal resistance values for use by the customer and the reliability lab in biasing up devices in known
thermal conditions. Note: for SCD components TjL (small signal) or TjC (larger components or PPD) will be
required prior to execution of IOL testing.

DIE SHEAR/DIE PUSH OFF: Used to test the die attach strength. Requested at the time of EBR. (often used (in
large sample sizes) as a rel information point when changing BM stuctures or techniques on devices with active
backside contact.

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Other Tests Required for Qualifications
AEC Q101 rev. D

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Summary of Reliability test and Failure Mechanism
Failure Mechanism
Reliability test Die and Crack or lifted Die Corrosion Poor Package Oxide Ionic
Die and
Foreign Metallization
Package Diffusion
wire bond or Contam. Sealing Defect Contam. Material Defects
Failures Defects
Thermal cycling test
Thermal shock
Autoclave/Pressure
Cooker Test
High Humidity High
Temperature Bias
High Accelerated
Stress Test
High Temperature
Forward Bias
High Temperature
Gate Bias
High Temperature
Reverse Bias
High Temperature
Storage Life
Intermittent
Operating Life
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Operating Life
Summary of Reliability test and Failure Mechanism

Failure Mechanism
Reliability test Contaminated Parameter Mechanical
Poor Plating
Leads Shifts Failures
Solderability
Solder Heat

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 1 Introduction
2 Reliability Tests
3 Reliability Lab Operation
4 Reliability standards and Spec

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Introduction to ONRMS

Is Primarily supports tracking of products processed in the

ON Semiconductor Reliability Labs. The system is also
used to view and notify associated parties of the product
reliability testing status.

http://myonweb.onsemi.com/?appId=RMS

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Introduction to ONRMS

2 TYPES OF RRF/RMS FLOW

FLOW 1: All process pertaining to the Reliability Plan EXECUTION FULLY done in a
LAB

FLOW 2: Process pertaining to the Reliability Plan require EXECUTION in few

intersites LABS
(Eg., SBN + GUNMA or SBN + OSPI or SBN + PHX)

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Introduction to ONRMS

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ONRMS – Stages of Activities

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Stages of Activities – Requestor Responsibility

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Stages of Activities – Requestor Responsibility

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Stages of Activities – Requestor Responsibility

Lot type:
Qual Lot: A, B, C, …
Control Lot: 2, 4, 6, …

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Stages of Activities – Requestor Responsibility

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Stages of Activities – Requestor Responsibility

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ONRMS – Stages of Activities

1. Reliability Engineer reviews information and accepts RRF. RRF Status

changes to “Accepted”.
2. Qual/Eval structure to be completed by Reliability Engineer prior to RTC
review.
3. Reliability Engineer submits RRF for RTC review. RTC status changes to “RTC
review”.
4. RTC group assigns Global Lab site, based on review of factory capability and
capacity. RTC status changes to “XXXX Lab Accept”

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ONRMS – Tools

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ONRMS – Tools

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ONRMS – Tools

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ONRMS – Tools

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 Receive units as per Typical Qual/Eval Flow (12MSV97571F)
ONRMS ID

Verify “Qual”/“Eval”
Load environment / life test
material
A:
Board mount Y
required ? A Board mounting Electrical Test
N (post test)

Sorting/Labelling
units per REL tests N Send to FA
Pass ? Depending on Rel
Electrical Test Eng disposition
(pre-test) Y

B: Complete Qual/Eval
Precon Y
or continue with next Lot disposition
required ? B Preconditioning
read-out
N
Electrical Test
(post Precon)

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 LOADING AND PRE CONDITIONING
OSV Reliability Lab Capability Update

HTxB IOL Vibration HAST/AC TC HTSL H3TRB

RESISTANCE to SOLDER
MOUNTING CAPABILITY INCLUDING PCB, STENCIL AND BIB CLEANING PROCESS
HEAT/SOLDERABILITY

BIB Dryer and PLATO SOLDER

SOLDERABILITY
Ionic STENCIL and PCB POT and
DEK PANASONIC PNP HELLER TESTER and STEAM
Contamination Cleaner BRANSON
Internal Use Only AGER
Tester CLEANER
 1 Introduction
2 Reliability Tests and Hardware
3 Reliability Lab Operation
4 Reliability standards and Spec

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Reliability Testing Standards and Specifications
Various semiconductor device testing methods have been standardized.
Performed according to industry standards and internal specifications:
• JEDEC specifications (Used for commercial and automotive)
http://www.jedec.org/
• Mil-Std 883 (Military ICs), 750 Discretes
• AEC-Q100 (Automotive ICs); Q101 (Automotive Discretes)
http://www.aecouncil.com/
• 12MSB17722C, Reliability Qualification Process (internal ON document)
Requirements and test methods/operating procedures are documented in internal
ON Rel Lab specifications

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Reliability Testing Standards and Specifications

Document no. Title

12MSV80750F OSV Reliability Audit Program (RAP)

12MSV97562F Reliability Laboratory Operating Procedure

12MSV97571F Reliability Procedure for Qualification and Evaluation Programs

12MSV97609F Reliability Electrical Testing Procedure

12MSV99465F Reliability Lab Control Of Non-Conforming Product/ Process/ Equipment

12MON49726E Reliability Corrective Action Request (RELCAR) Procedure

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 The end

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