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Chapter 03

This document contains 3 summaries of passages from a chapter on cache memory: 1) The first passage discusses a direct mapped cache with 232 bytes of main memory divided into 227 blocks of 32 bytes each. A memory address has a 17-bit tag, 10-bit block, and 5-bit offset. Address 0x000063FA maps to block 31F16. 2) The second passage describes a fully associative cache with 224 bytes of main memory in 218 blocks of 64 bytes each. A memory address has an 18-bit tag and 6-bit offset. Address 0x01D872 can map to any cache block. 3) The third passage shows a 2-way set associative

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22 views2 pages

Chapter 03

This document contains 3 summaries of passages from a chapter on cache memory: 1) The first passage discusses a direct mapped cache with 232 bytes of main memory divided into 227 blocks of 32 bytes each. A memory address has a 17-bit tag, 10-bit block, and 5-bit offset. Address 0x000063FA maps to block 31F16. 2) The second passage describes a fully associative cache with 224 bytes of main memory in 218 blocks of 64 bytes each. A memory address has an 18-bit tag and 6-bit offset. Address 0x01D872 can map to any cache block. 3) The third passage shows a 2-way set associative

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AMAN JOHN
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Chapter 3, Selected Questions, and Answers

May 28, 2022

2. Suppose a computer using direct mapped cache has 232 bytes of byte-addressable main memory, and
a cache of 1024 blocks, where each cache block contains 32 bytes.
(a) How many blocks of main memory are there?
(b) What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag,
block, and offset fields?
(c) To which cache block will the memory address 0x000063FA map?
Answer:
232 232
(a) 32 = 25 = 227 blocks (134,217,728)
(b) Breakdown of address values:
i. Offset = 32bytes = 25 → 5 bits
ii. Block = 1024bytes = 210 → 10 bits
iii. Tag = maximum address space = 232 → 32 − offset − block → 32 − 5 − 10 → 17 bits
(c) 0x000063F A → 000000000000000001100011111110102 → 00000000000000000 1100011111 11010
00000000000000000 1100011111 11010 → 79910 ≡ 31F16

5. Suppose a computer using fully associative cache has 224 bytes of byte-addressable main memory and
a cache of 128 blocks, where each cache block contains 64 bytes.
(a) How many blocks of main memory are there?
Answer:
224 /26 = 218
(b) What is the format of a memory address as seen by the cache, i.e., what are the sizes of the tag
and offset fields?
Answer:
24 bit addresses with 18 bits in the tag field and 6 in the offset field
(c) To which cache block will the memory address 0x01D872 map?
Answer:
Since it’s associative cache, it can map anywhere.
7. Assume a system’s memory has 128M bytes. Blocks are 64 bytes in length and the cache consists
of 32K blocks. Show the format for a main memory address assuming a 2-way set associative cache
mapping scheme and byte addressing. Be sure to include the fields as well as their sizes.
Answer:
Each address has 27 bits, and there are 7 in the tag field, 14 in the set field, and 6 in the offset field.

1
21. Suppose we have 210 bytes of virtual memory and 28 bytes of physical main memory. Suppose the
page size is 24 bytes.

(a) How many pages are there in virtual memory?


(b) How many page frames are there in main memory?
(c) How many entries are in the page table for a process that uses all of virtual memory?
Answer:
sizeOfVirtualMemory 210
(a) Number of pages in virtual memory pageSize = 24 = 26 = 64 pages in virtual memory
sizeOfPhysicalMemory 28
(b) Number of pages in physical memory pageSize = 24 = 24 = 16 page frames in physical
memory
(c) The page table must have an entry for each virtual page, so it must have 64 entries.

29. Name two ways that, as a programmer, you can improve cache performance.
Answer:
Programmers should focus on improving the reference locality.
(a) This can be done by using cache-conscious algorithms (for example, change a program’s data
access pattern to optimize locality in nested loops used in matrices by interchanging loops) or,
(b) A program’s data organization and layout (such as using cache-conscious data structures).

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