MICROCONTROLLER LAB: 18ECL48

NITTE MEENAKSHI INSTITUTE OF TECHNOLOGY

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

SUBJECT: MICROCONTROLLER LAB

SUBJECT CODE: 18ECL48

Deartment of ECE, NMIT 1

 MICROCONTROLLER LAB: 18ECL48

SYLLABUS
MICROCONTROLLER LAB

Course Code 21ECL47 Credits 01

Hours/Week(L-T-P) 0-0-2 CIE Marks 50
Total Hours 26(P) SEE Marks 50
Exam Hours 03 Course Type Core

COURSE CONTENTS
LIST OF EXPERIMENTS
PART- A
1. i) Assembly level programs on Arithmetic and Logical operations instructions
ii) Write an ALP to divide a 32bit numbers by four without using DIV instructions
iii) Write a program to multiply two 32bit numbers without using multiply instructions (MUL)
2. Write an ALP to find cube of 32 bit numbers
3. Find the frequency of occurrence of the number 99h in an array of ‘n’ 32 bit numbers.
4. i) Write an ALP to find largest number among ten, 32bit numbers.
ii) Write an ALP to find smallest number among ten, 32bit numbers
5. i) Write an ALP to sort ten, 32bit numbers in ascending order.
ii)Write an ALP to sort ten, 32bit numbers in descending order
6. Write an ALP to move a block of data from one memory location to another memory
Location
7. Assembly programs on execution of various special instruction of the processor (Reverse, Signed and
Unsigned Field extract ,Bit Field , Signed and Unsigned extension instructions and so on )
8. Assembly programs on multiple sours file

PART-B With the Board

Programming the device TM4C123GH6PM USING Embedded C for

1. Program External Interrupt via Switch SW1 to Glow LED

2. Interfacing of DC Motor
3. Interfacing of Stepper Motor
4. Interfacing of 7 segment LED
5. Controlling LED Buzzer using Switch (SW1)
6. Interfacing of RGB LED
CO-PO-PSO MAPPING
CO/PO PO PO PO PO PO PO PO PO PO PO PO PO PSO 1 PSO PSO B
1 2 3 4 5 6 7 8 9 10 11 12 2 3 T
CO1 3 1 2 2 3 1 1 3 3 1 3
CO2 3 1 1 1 3 2 2 2 2 1 3
CO3 3 2 2 2 3 2 2 2 2 1 3
CO4 3 3 3 3 3 3 3 3 3 2 3
CO5 3 3 3 3 3 3 3 3 3 3 3

Deartment of ECE, NMIT 2

MICROCONTROLLER LAB: 18ECL48

PART A

Deartment of ECE, NMIT 3

 MICROCONTROLLER LAB: 18ECL48

STARTUP FILE
STACK_ADDR_123G EQU 0X20008000
THUMB
AREA ANS, DATA, READONLY
EXPORT __Vectors
__Vectors
DCD STACK_ADDR_123G
DCD Reset_Handler

AREA ANS1, CODE, READONLY

ENTRY
EXPORT Reset_Handler
Reset_Handler
IMPORT __main
END

Deartment of ECE, NMIT 4

 MICROCONTROLLER LAB: 18ECL48
1. i) Assembly level programs on Arithmetic and Logical operations instructions
AREA ANS2,CODE,READONLY
THUMB
ENTRY
EXPORT __main
__main

MOV R1,#0X20000000
MOV R2,#0X40000000
ADDS R3,R2,R1
SUBS R4,R2,R1
DIV R5,R2,R1
MUL R6,R2,R1
STOP B STOP
END

INPUT : R1 = 0X20000000
R2 = 0X40000000

OUTPUT : R3 = 0X00000008
R4 = 0X 00000002
R5=0X 00000002
OUTPUT:

Deartment of ECE, NMIT 5

 MICROCONTROLLER LAB: 18ECL48
i) Assembly level programs on Logical operations instructions
AREA ANS3,CODE,READONLY
THUMB
ENTRY
EXPORT __main
__main
LDR R0,=0X20000000
LDR R1,=0X20000008
LDR R7,=0X20004008
LDR R8,=0X2000400C
LDR R9,=0X20004000
LDR R2,[R0]
LDR R3,[R1]
AND R4,R2,R3
ORR R5,R2,R3
EOR R6,R2,R3
STR R4,[R7]
STR R5,[R8]
STR R6,[R9]
STOP B STOP
END

INPUT :R0 :0X20000000= 0XFFFFFFFF

R1 : 0X20000008= 0X10001000
OUTPUT: R3 = 0X 10001000
R4 = 0X FFFFFFFF
R5 = 0X EFFFEFFF
INPUT

INPUT

Deartment of ECE, NMIT 6

 MICROCONTROLLER LAB: 18ECL48
OUTPUT

ii) Write an ALP to divide a 32bit numbers by four without using DIV instructions.
Deartment of ECE, NMIT 7
 MICROCONTROLLER LAB: 18ECL48

AREA ANS2,CODE,READONLY
THUMB
ENTRY
EXPORT __main
__main
LDR R0,=0X20000000
LDR R2,=0X20004000
LDR R1,[R0]
LSR R1,R1#2
STR R1, [R2]
STOP B STOP
END

INPUT : 0x20000000 = 0x00 00 00 08

OUTPUT :0x 20004000 = 00 00 00 02
INPUT:

OUTPUT:
OUTPUT:

Deartment of ECE, NMIT 8

 MICROCONTROLLER LAB: 18ECL48
iii) Write a program to multiply two 32bit numbers without using multiply instructions
(MUL)
AREA ANS2,CODE,READONLY
THUMB
ENTRY
EXPORT __main
__main

LDR R1,=0X20000000
LDR R2,=0X20000008
LDR R3,[R1]
LDR R4,[R2]
MOV R0,#0X00000000
LOOP
ADD R0,R0,R3
SUBS R4,R4,#1
CMP R4,#0
BNE LOOP
MOV R5,R0
STOP B STOP
END

INPUT: R1:0 X 20000000 = 0X5F 00 00 00

R2 : 0 X 20000008 = 0X05 00 00 00

OUTPUT : R5 =0 X 00 00 01 DB
INPUT:

OUTPUT:

2. Write an ALP to find cube of 32 bit numbers

Deartment of ECE, NMIT 9
 MICROCONTROLLER LAB: 18ECL48

AREA ANS3,CODE,READONLY
THUMB
ENTRY
EXPORT __main
__main

LDR R1,=0XABCDEF33
UMULL R3,R4,R1,R1
UMULL R5,R6,R1,R3
UMULL R8,R7,R1,R4
ADDS R6,R8
ADC R7,R7,#0
STOP B STOP
END

INPUT : R1: ABCDEF33

OUTPUT :

3. Find the frequency of occurrence of the number 99h in an array of ‘n’ 16 bit numbers.

AREA ANS3,CODE,READONLY
THUMB

Deartment of ECE, NMIT 10

 MICROCONTROLLER LAB: 18ECL48
ENTRY
EXPORT __main
__main
LDR R0, =0x20000000
LDR R3, =0x20002000
MOV R4,#0X05
LDR R2, =0X00000000
MOV R5,#0X099
BACK
LDRB R1, [R0]
CMP R1, R5
BNE NEXT
ADD R2, #01
NEXT
ADD R0, R0, #01
SUB R4, R4, #01
CMP R4, #00
BNE BACK
STR R2, [R3]
STOP B STOP
END

INPUT : 0x20000000 : 99 99 99 99 88
OUTPUT :0x20002000 : 04 00 00 00
INPUT:

OUTPUT:

4. i) Write an ALP to find largest number among ten 32bit numbers.

AREA ANS2,CODE,READONLY
THUMB
ENTRY
Deartment of ECE, NMIT 11
 MICROCONTROLLER LAB: 18ECL48

EXPORT __main
__main
MOV R5,#03
LDR R1,=0X20000000
LDR R2,=0X2000401C
LDR R3,[R1]
LOOP1
ADD R1, R1,#04
LDR R4,[R1]
CMP R3, R4
BHI LOOP2
MOV R3, R4
LOOP2
SUBS R5, R5,#01
CMP R5,#00
BNE LOOP1
STR R3, [R2]
STOP B STOP
END

INPUT : 0X20000000 = 00 00 00 44 00 00 00 22 00 00 00 33 00 00 00 55

OUTPUT: 0X 2000401C = 00 00 00 55
INPUT:

OUTPUT:

ii) Write an ALP to find Smallest number among ten 32bit numbers
AREA ANS2,CODE,READONLY
THUMB
ENTRY

Deartment of ECE, NMIT 12

 MICROCONTROLLER LAB: 18ECL48

EXPORT __main
__main
MOV R5,#03
LDR R1,=0X20000000
LDR R2,=0X2000401C
LDR R3,[R1]
LOOP
ADD R1, R1,#04
LDR R4,[R1]
CMP R3, R4
BLS LOOP1
MOV R3, R4
LOOP1
SUBS R5, R5,#01
CMP R5,#00
BNE LOOP
STR R3, [R2]
STOP B STOP
END

INPUT : 0X20000000 = 00 00 00 44 00 00 00 22 00 00 00 33 00 00 00 55
OUTPUT: 0X 2000401C = 00 00 00 22
INPUT:

OUTPUT:

Deartment of ECE, NMIT 13

 MICROCONTROLLER LAB: 18ECL48
5. i) Write an ALP to sort ten, 32bit numbers in ascending order.

AREA ANS3,CODE,READONLY
THUMB
ENTRY
EXPORT __main
__main

MOV R8,#04
LDR R2,=CVALUE
LDR R3,=DVALUE
LOOP0
LDR R1,[R2],#04
STR R1,[R3],#04
SUBS R8,R8,#01
CMP R8,#00
BNE LOOP0
START1
MOV R5,#03
MOV R7,#00
LDR R1,=DVALUE
LOOP
LDR R2,[R1],#04
LDR R3,[R1]
CMP R2,R3
BLT LOOP2
STR R2,[R1],#-4
STR R3,[R1]
MOV R7,#01
ADD R1,#04
LOOP2
SUBS R5,R5,#01
CMP R5,#00
BNE LOOP
CMP R7,#00
BNE START1
BACK B BACK
CVALUE
DCD 0X44444444
DCD 0X11111111
DCD 0X33333333
DCD 0X22222222
AREA DATA1,DATA,READWRITE
DVALUE DCD 0X00000000
END

INPUT : R2= 0x00000050 : 44444444 11111111 33333333 22222222

OUTPUT : 0x20000000: 11111111 22222222 33333333 44444444

Deartment of ECE, NMIT 14

 MICROCONTROLLER LAB: 18ECL48
INPUT :

OUTPUT :

Deartment of ECE, NMIT 15

 MICROCONTROLLER LAB: 18ECL48
ii)Write an ALP to sort ten, 32bit numbers in descending order

AREA ANS3,CODE,READONLY
THUMB
ENTRY
EXPORT __main
__main

MOV R8,#04
LDR R2,=CVALUE
LDR R3,=DVALUE
LOOP0
LDR R1,[R2],#04
STR R1,[R3],#04
SUBS R8,R8,#01
CMP R8,#00
BNE LOOP0
START1
MOV R5,#03
MOV R7,#00
LDR R1,=DVALUE
LOOP
LDR R2,[R1],#04
LDR R3,[R1]
CMP R2,R3
BGT LOOP2
STR R2,[R1],#-4
STR R3,[R1]
MOV R7,#01
ADD R1,#04
LOOP2
SUBS R5,R5,#01
CMP R5,#00
BNE LOOP
CMP R7,#00
BNE START1
BACK B BACK
CVALUE
DCD 0X44444444
DCD 0X11111111
DCD 0X33333333
DCD 0X22222222
AREA DATA1,DATA,READWRITE
DVALUE DCD 0X00000000
END

INPUT : R2= 0x00000050 : 44444444 11111111 33333333 22222222

OUTPUT : 0x20000000: 11111111 33333333 22222222 11111111

Deartment of ECE, NMIT 16

 MICROCONTROLLER LAB: 18ECL48
INPUT :

OUTPUT :

Deartment of ECE, NMIT 17

 MICROCONTROLLER LAB: 18ECL48
6. Write an ALP to move a block of data from one memory location to another memory
location
AREA ANS2,CODE,READONLY
THUMB
ENTRY
EXPORT __main
__main
LDR R1,=0X20000000
LDR R2,=0X20002000
MOV R3,#04
LOOP LDR R4,[R1]
STR R4,[R2]
ADD R1,#04
ADD R2,#04
sub R3,#01
CMP R3,#00
BNE LOOP

STOP B STOP
END

INPUT : 0X 20000000 : 46 00 00 00 47 00 00 00 69 00 00 00

OUTPUT: 0X 20002000 : 46 00 00 00 47 00 00 00 69 00 00 00

Deartment of ECE, NMIT 18

 MICROCONTROLLER LAB: 18ECL48

7. Assembly programs on execution of various special instruction of the processor (Reverse,

Signed and Unsigned Field extract ,Bit Field , Signed and Unsigned extension instructions
and so on
AREA ANS2,CODE,READONLY
THUMB
ENTRY
EXPORT __main
__main
LDR R0,=0X0123ABCD
UXTB R1,R0
SXTB R2,R0
REV R3,R0
REV16 R4,R0
REVSH R5,R0
UBFX R6,R0,#4,#4
SBFX R7,R0,#12,#4
LOOP B LOOP
END

INPUT: R1=0X0123ABCD
OUTPUT:

Deartment of ECE, NMIT 19

 MICROCONTROLLER LAB: 18ECL48

9. Assembly programs on multiple source file

AREA ANS2, CODE, READONLY

THUMB
ENTRY
IMPORT addnum
EXPORT __main
__main
MOV R0, #5
MOV R1, #0
BL addnum
NOP
STOP B STOP
END

AREA ANS3, CODE, READONLY

EXPORT addnum
addnum

LOOP
ADD R1, R0
SUBS R0, #01
BNE LOOP
BX LR
NOP
END
INPUT: R0: 05
OUTPUT: R1: 0F
INPUT: OUTPUT:

Deartment of ECE, NMIT 20

MICROCONTROLLER LAB: 18ECL48

PART B

Deartment of ECE, NMIT 21

MICROCONTROLLER LAB: 18ECL48

Lab Manual for TIVA Launch Pad

(TM4C123GH6PM)

Deartment of ECE, NMIT 22

 MICROCONTROLLER LAB: 18ECL48
⚫ TIVA C Series Launch Pad

⚫ Tiva TM4C123GH6PM Microcontroller

The Tiva™ C Series ARM Cortex-M4 microcontrollers provide top performance and advanced
integration. The product family is positioned for cost-conscious applications requiring significant control
processing and connectivity capabilities such as:

⚫ Low power, hand-held smart devices

⚫ Gaming equipment
⚫ Home and commercial site monitoring and control
⚫ Motion control
⚫ Medical instrumentation
⚫ Test and measurement equipment
⚫ Factory automation
⚫ Fire and security
⚫ Smart Energy/Smart Grid solutions
⚫ Intelligent lighting control
⚫ Transportation

For applications requiring extreme conservation of power, the TM4C123GH6PM microcontroller

features a battery-backed Hibernation module to efficiently power down the TM4C123GH6PM to a low-
power state during extended periods of inactivity. With a power-up/power-down sequencer, a real-time
counter (RTC), multiple wake-from-hibernate options, and dedicated battery-backed memory, the
Hibernation module positions the TM4C123GH6PM microcontroller perfectly for battery applications.

In addition, the TM4C123GH6PM microcontroller offers the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community.
Additionally, the microcontroller uses ARM's Thumb-compatible Thumb-2 instruction set to reduce memory
requirements and, thereby, cost. Finally, much of the TM4C123GH6PM microcontroller code is compatible
to the Tiva™ C Series product line, providing flexibility across designs.

Deartment of ECE, NMIT 23

 MICROCONTROLLER LAB: 18ECL48

Processor Core (ARM Cortex-M4)

Features:
• 32-bit ARM Cortex-M4F architecture optimized for small-footprint embedded applications
• 80-MHz operation; 100 DMIPS performance
• Outstanding processing performance combined with fast interrupt handling
• Thumb-2 mixed 16-/32-bit instruction set delivers the high performance expected of a 32-bit
ARM core in a compact memory size usually associated with 8- and 16-bit devices, typically
in the range of a few kilobytes of memory for microcontroller-class applications.
➢ Single-cycle multiply instruction and hardware divide
➢ Atomic bit manipulation (bit-banding), delivering maximum memory
Utilization and streamlined peripheral control
➢ Unaligned data access, enabling data to be efficiently packed into memory
• IEEE754-compliant single-precision Floating-Point Unit (FPU)
• 16-bit SIMD vector processing unit
• Fast code execution permits slower processor clock or increases sleep mode time
• Harvard architecture characterized by separate buses for instruction and data
Deartment of ECE, NMIT 24
 MICROCONTROLLER LAB: 18ECL48

• Efficient processor core, system and memories

• Hardware division and fast digital-signal-processing orientated multiply accumulate
• Saturating arithmetic for signal processing
• Deterministic, high-performance interrupt handling for time-critical applications
• Memory protection unit (MPU) to provide a privileged mode for protected operating
system Functionality
• Enhanced system debugs with extensive breakpoint and trace capabilities
• Serial Wire Debug and Serial Wire Trace reduce the number of pins required for
debugging and tracing

Processor core register

The processor has 32-registers that includes 13 general-purpose registers and several special-
purpose registers
The processor has the following 32-bit registers:
• 13 general-purpose registers, R0-R12
• Stack Pointer (SP), R13 alias of banked registers, SP Process and SP Main
• Link Register (LR), R14
• Program Counter (PC), R15
• Special-purpose Program Status Registers, (xPSR)

Figure shows the Processor Register Set

The general-purpose registers R0-R12 have no special architecturally-defined uses. Most

instructions that can specify a general-purpose register can specify R0-R12.

Low registers
Registers R0-R7 are accessible by all instructions that specify a general-purpose Register

Deartment of ECE, NMIT 25

 MICROCONTROLLER LAB: 18ECL48

High registers
Registers R8-R12 are accessible by all 32-bit instructions that specify a general-purpose register.
Registers R8-R12 are not accessible by most 16-bit instructions. Registers R13, R14, and R15 have the
following special functions:
The Rn registers are 32-bit general-purpose registers for data operations and can be accessed from
either privileged or unprivileged mode.

⚫ Special Function Registers

Register 13: Stack Pointer (SP)
Register R13 is used as the Stack Pointer (SP). In Thread mode, the function of this register changes
depending on the ASP bit in the Control Register (CONTROL) register. When the ASP bit is clear, this
register is the Main Stack Pointer (MSP). When the ASP bit is set, this register is the Process.
Stack Pointer (PSP). On reset, the ASP bit is clear, and the processor loads the MSP with the value
from address 0x0000.0000. The MSP can only be accessed in privileged mode; the PSP can be accessed in
either privileged or unprivileged mode.

Register 14: Link Register (LR)

The Link Register (LR) is register R14, and it stores the return information for subroutines, function
calls, and exceptions. The Link Register can be accessed from either privileged or unprivileged mode.

Register 15: Program Counter (PC)

The Program Counter (PC) is register R15, and it contains the current program address. On reset, the
processor loads the PC with the value of the reset vector, which is at address 0x0000.0004. Bit0 of the reset
vector is loaded into the THUMB bit of the EPSR at reset and must be 1. The PC register can be accessed
in either privileged or unprivileged mode.

Register 16: Program Status Register (PSR)

The Program Status Register (PSR) has three functions, and the register bits are assigned to the
different functions:

1. Application Program Status Register (APSR), bits 31:27, bits 19:16

2. Execution Program Status Register (EPSR), bits 26:24, 15:10
3. Interrupt Program Status Register (IPSR), bits 7:0

The PSR, IPSR, and EPSR registers can only be accessed in privileged mode; the APSR register can be
accessed in either privileged or unprivileged mode. APSR contains the current state of the condition flags
from previous instruction executions.
EPSR contains the Thumb state bit and the execution state bits for the If-Then (IT) instruction or the
Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction.
Attempts to read the EPSR directly through application software using the MSR instruction always return
zero. Attempts to write the EPSR using the MSR instruction in application software are always ignored.
Fault handlers can examine the EPSR value in the stacked PSR to determine the operation that faulted.

Deartment of ECE, NMIT 26

 MICROCONTROLLER LAB: 18ECL48

IPSR contains the exception type number of the current Interrupt Service Routine (ISR). These
registers can be accessed individually or as a combination of any two or all three registers, using the register
name as an argument to the MSR or MRS instructions. For example, all of the registers can be read using
PSR with the MRS instruction, or APSR only can be written to using APSR with the MSR instruction.

Bit/Field Name Description

APSR Negative or Less Flag
1- The previous operation result was negative or less than.
31 N 0-The previous operation result was positive, zero, greater than or equal.
APSR Zero Flag
1- The previous operation result was zero
30 Z 0- The previous operation result was non-zero
APSR Carry or Borrow Flag
1- The previous add operation resulted in a carry bit or the previous
29 C subtract operation did not result in a borrow bit
0- The previous add operation did not result in a carry bit or the
Previous subtract operation resulted in a borrow bit.
APSR Overflow Flag
1- The previous operation resulted in an overflow.
28 V 0- The previous operation did not result in an overflow.
APSR DSP Overflow and Saturation Flag
1-DSP Overflow or saturation has occurred when using a SIMD
27 Q
instruction.
0-DSP overflow or saturation has not occurred since reset or since
The bit was last cleared.
19:16 GE Greater Than or Equal Flags

Register 17: Priority Mask Register (PRIMASK)

The PRIMASK register prevents activation of all exceptions with programmable priority. Reset, non-
maskable interrupt (NMI), and hard fault are the only exceptions with fixed priority. Exceptions should be
disabled when they might impact the timing of critical tasks. This register is only accessible in privileged
mode. The MSR and MRS instructions are used to access the PRIMASK register, and the CPS instruction
may be used to change the value of the PRIMASK register.

Deartment of ECE, NMIT 27

 MICROCONTROLLER LAB: 18ECL48

Bit/Field Name Description

To provide compatibility with future
products, the value of a reserved bit
31:1 Reserved should be preserved across a read-
modify-write operation.
Priority Mask.
1-Prevents the activation of all
0 PRIMASK exceptions with configurable priority.
0- No effect.

Register 18: Fault Mask Register (FAULTMASK)

The FAULTMASK register prevents activation of all exceptions except for the Non-Maskable
Interrupt (NMI). Exceptions should be disabled when they might impact the timing of critical tasks. This
register is only accessible in privileged mode. The MSR and MRS instructions are used to access the
FAULTMASK register, and the CPS instruction may be used to change the value of the FAULTMASK
register.

Bit/Field Name Description

To provide compatibility with future
products, the value of a reserved bit
31:1 Reserved should be preserved across a read-
modify-write operation.
Fault Mask
1- Prevents the activation of all
0 FAULTMASK exceptions except for NMI.
0- No effect

Deartment of ECE, NMIT 28

 MICROCONTROLLER LAB: 18ECL48
Register 19: Base Priority Mask Register (BASEPRI)
The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is
set to a nonzero value, it prevents the activation of all exceptions with the same or lower priority level as the
BASEPRI value. Exceptions should be disabled when they might impact the timing of critical tasks. This
register is only accessible in privileged mode.

Bit/Field Name Description

To provide compatibility with future
products, the value of a reserved bit
31:8/4:0 Reserved should be preserved across a read-
modify-write operation.
Base Priority Value
Description
0x0- All exceptions are unmasked.
0x1- All exceptions with priority level 1-
7 are masked.
0x2 -All exceptions with priority level 2-
7 are masked.
7:5 BASEPRI 0x3- All exceptions with priority level 3-
7 are masked.
0x4 -All exceptions with priority level 4-
7 are masked.
0x5- All exceptions with priority level 5-
7 are masked.
0x6 -All exceptions with priority level 6-
7 are masked.
0x7- All exceptions with priority level 7
are masked

Register 20: Control Register (CONTROL)

The CONTROL register controls the stack used and the privilege level for software execution when
the processor is in Thread mode, and indicates whether the FPU state is active. This register is only accessible
in privileged mode.
Handler mode always uses the MSP (Main Stack Pointer), so the processor ignores explicit writes to
the ASP bit of the CONTROL register when in Handler mode. The exception entry and return mechanisms
automatically update the CONTROL register based on the EXC_RETURN value.

Deartment of ECE, NMIT 29

 MICROCONTROLLER LAB: 18ECL48

Bit/Field Name Description

To provide compatibility with
future products, the value of a
31:3 Reserved reserved bit should be preserved
across a read-modify-write
operation.
Floating-Point Context Active
Value Description
2 FPCA 1- Floating-point context active
0- No floating-point context
active
Active Stack Pointer
Value Description
1 ASP 1- The PSP is the current stack
pointer.
0- The MSP is the current stack
pointer
Thread Mode Privilege Level
Value Description
0 TMPL 1- Unprivileged software can be
executed in Thread mode.
0- Only privileged software can
be executed in Thread mode

Register 21: Floating-Point Status Control (FPSC)

The FPSC register provides all necessary user-level control of the floating-point system such as.

Deartment of ECE, NMIT 30

 MICROCONTROLLER LAB: 18ECL48

Bit/Field Name Description

31 N Negative Condition Code Flag

30 Z Zero Condition Code Flag

29 C Carry Condition Code Flag

28 V Overflow Condition Code Flag

27/21:8/6:5 Reserved To provide compatibility with future products, the value of a reserved
bit should be preserved across a read-modify-write operation.
26 AHP Alternative Half-Precision
When set, alternative half-precision format is selected. When clear,
IEEE half-precision format is selected
25 DN Default NaN Mode
When set, any operation involving one or more NaNs returns the
Default NaN. When clear, NaN operands propagate through to the
output of a floating-point operation
24 FZ Flush-to-Zero Mode
When set, Flush-to-Zero mode is enabled. When clear, Flush-to-Zero
mode is disabled and the behavior of the floating-point system is
fully
compliant with the IEEE 754 standard
23:22 RMODE Rounding Mode
The specified rounding mode is used by almost all floating-point
instructions.
Value Description
0x0 Round to Nearest (RN) mode
0x1 Round towards Plus Infinity (RP) mode
0x2 Round towards Minus Infinity (RM) mode
0x3 Round towards Zero (RZ) mode

7 IDC Input Denormal Cumulative Exception

When set, indicates this exception has occurred since 0 was last
written to this bit.
4 IXC Inexact Cumulative Exception
When set, indicates this exception has occurred since 0 was last
written to this bit.
3 UFC Underflow Cumulative Exception
When set, indicates this exception has occurred since 0 was last
written to this bit.
2 OFC Overflow Cumulative Exception
When set, indicates this exception has occurred since 0 was last
written to this bit.
1 DZC Division by Zero Cumulative Exception
When set, indicates this exception has occurred since 0 was last
written to this bit.
0 IOC Invalid Operation Cumulative Exception
When set, indicates this exception has occurred since 0 was last
written to this bit.

Deartment of ECE, NMIT 31

 MICROCONTROLLER LAB: 18ECL48
NOTE: For more details on Processor Architectural and core resisters Please Refer Data Sheet Page No.45

On-Chip Memory

Figure above Illustrates the internal SRAM, ROM, and Flash memory blocks and control logic.

The TM4C123GH6PM Microcontroller is integrated with the following set of on-chip memory
⚫ 32 KB single-cycle SRAM
⚫ 256 KB Flash memory
⚫ 2KB EEPROM
⚫ Internal ROM loaded with TivaWare for C Series software :
➢ TivaWare Peripheral Driver Library
➢ TivaWare Boot Loader
➢ Advanced Encryption Standard (AES) cryptography tables
➢ Cyclic Redundancy Check (CRC) error detection functionality

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 MICROCONTROLLER LAB: 18ECL48

Figure above Illustrates the internal EEPROM block and control logic. The EEPROM block is
connected to the AHB bus

SRAM
The internal SRAM of the TM4C123GH6PM device is located at address 0x2000.0000 of the device
memory map. To reduce the number of time consuming read-modify-write (RMW) operations, ARM
provides bit-banding technology in the processor. With a bit-band-enabled processor, certain regions in the
memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single,
atomic operation. The bit-band base is located at address 0x2200.0000.
The bit-band alias is calculated by using the formula:

Bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4)

For example, if bit 3 at address 0x2000.1000 is to be modified, the bit-band alias is calculated as:
0x2200.0000 + (0x1000 * 32) + (3 * 4) = 0x2202.000C
With the alias address calculated, an instruction performing a read/write to address 0x2202.000C allows
direct access to only bit 3 of the byte at address 0x2000.1000

ROM
The internal ROM of the TM4C123GH6PM device is located at address 0x0100.0000 of the device
memory map. Detailed information on the ROM contents can be found in the Tiva C Series
The ROM contains the following components:
• TivaWare Boot Loader and vector table
• TivaWare Peripheral Driver Library (DriverLib) release for product - specific
Peripherals and interfaces
• Advanced Encryption Standard (AES) cryptography tables
• Cyclic Redundancy Check (CRC) error detection functionality

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The boot loader is used as an initial program loader (when the Flash memory is empty) as well as an
application-initiated firmware upgrade mechanism (by calling back to the boot loader). The Peripheral
Driver Library APIs in ROM can be called by applications, reducing Flash memory requirements and freeing
the Flash memory to be used for other purposes (such as additional features in the application). Advance
Encryption Standard (AES) is a publicly defined encryption standard used by the U.S. Government and
Cyclic Redundancy Check (CRC) is a technique to validate if a block of data has the same contents as when
previously checked

TivaWare Peripheral Driver Library

The TivaWare Peripheral Driver Library contains a file called driverlib/rom.h that assists with calling
the peripheral driver library functions in the ROM. The detailed description of each function is available in
the Tiva C Series TM4C123x ROM User’s Guide driverlib/rom.h. The driverlib/rom_map.h header file is
also provided to aid portability when using different Tiva C Series devices which might have a different
subset of DriverLib functions in ROM. The driverlib/rom_map.h header file uses build-time labels to route
function calls to the ROM if those functions are available on a given device, otherwise, it routes to Flash-
resident versions of the functions.
A table at the beginning of the ROM points to the entry points for the APIs that are provided in the
ROM. Accessing the API through these tables provides scalability; while the API locations may change in
future versions of the ROM, the API tables will not. The tables are split into two levels; the main table
contains one pointer per peripheral which points to a secondary table that contains one pointer per API that
is associated with that peripheral. The main table is located at 0x0100.0010, right after the Cortex-M4F
vector table in the ROM.
Additional APIs are available for graphics and USB functions, but are not preloaded into ROM. The
TivaWare Graphics Library provides a set of graphics primitives and a widget set for creating graphical user
interfaces on Tiva C Series microcontroller-based boards that have a graphical display.
The TivaWare USB Library is a set of data types and functions for creating USB Device, Host or
On-The-Go (OTG) applications on Tiva C Series microcontroller-based boards

EEPROM
The TM4C123GH6PM microcontroller includes an EEPROM with the following features:
• 2Kbytes of memory accessible as 512 32-bit words
• 32 blocks of 16 words (64 bytes) each
• Built-in wear levelling
• Access protection per block
• Lock protection option for the whole peripheral as well as per block using 32-
bit to 96-bit unlock codes (application selectable)
• Interrupt support for write completion to avoid polling
• Endurance of 500K writes (when writing at fixed offset in every alternate
page in circular fashion) to 15M operations (when cycling through two pages)
per each 2-page block.

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Functional Description
The EEPROM module provides a well-defined register interface to support accesses to the EEPROM
with both a random access style of read and write as well as a rolling or sequential access scheme.
A protection mechanism allows locking EEPROM blocks to prevent writes under a set of
circumstances as well as reads under the same or different circumstances. The password model allows the
application to lock one or more EEPROM blocks to control access on 16-word boundaries.

Theory of Operation
The EEPROM operates using a traditional Flash bank model which implements EEPROM-type cells,
but uses sector erase. Additionally, words are replicated in the pages to allow 500K+ erase cycles when
needed, which means that each word has a latest version. As a result, a write creates a new version of the
word in a new location, making the previous value obsolete.

Each sector contains two blocks. Each block contains locations for the active copy plus six redundant
copies. Passwords, protection bits, and control data are all stored in the pages.

When a page runs out of room to store the latest version of a word, a copy buffer is used. The copy
buffer copies the latest words of each block. The original page is then erased. Finally, the copy buffer
contents are copied back to the page. This mechanism ensures that data cannot be lost due to power down,
even during an operation. The EEPROM mechanism properly tracks all state information to provide
complete safety and protection.

Memory Model
This section describes the processor memory map, the behaviour of memory accesses, and the bit-
banding features. The processor has a fixed memory map that provides up to 4 GB of addressable memory.
The Code, SRAM, and external RAM regions can hold programs. However, it is recommended that
programs always use the Code region because the Cortex-M4F has separate buses that can perform
instruction fetches and data accesses simultaneously.

Memory

Address Range Memory Region Description

This executable region is for program
0x0000.0000-0x1FFF.FFFF Code code. Data can also be stored here

This executable region is for data. Code

can also be stored here. This region
0x2000.0000 - 0x3FFF.FFFF SRAM includes bit band and bit band alias areas

This region includes bit band and bit

0x4000.0000 - 0x5FFF.FFFF Peripheral band alias areas

0x6000.0000 - 0x9FFF.FFFF External RAM This executable region is for data.

This region is for external device
0xA000.0000 - 0xDFFF.FFFF External device memory.

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This region includes the NVIC, system

0xE000.0000- 0xE00F.FFFF Private bus peripheral timer, and system control block timer,
and system control block

0xE010.0000- 0xFFFF.FFFF Reserved -----

Peripherals
START END Description
0x4000.1000 0x4000.1FFF Watchdog timer 1
0x4000.2000 0x4000.3FFF Reserved
0x4000.4000 0x4000.4FFF GPIO Port A
0x4000.5000 0x4000.5FFF GPIO Port B
0x4000.6000 0x4000.6FFF GPIO Port C
0x4000.7000 0x4000.7FFF GPIO Port D
0x4000.8000 0x4000.8FFF SSI0
0x4000.9000 0x4000.9FFF SSI1
0x4000.A000 0x4000.AFFF SSI2
0x4000.B000 0x4000.BFFF SSI3
0x4000.C000 0x4000.CFFF UART0
0x4000.6000 0x4000.6FFF GPIO Port C
0x4000.7000 0x4000.7FFF GPIO Port D
0x4000.8000 0x4000.8FFF SSI0
0x4000.9000 0x4000.9FFF SSI1
0x4000.A000 0x4000.AFFF SSI2
0x4000.B000 0x4000.BFFF SSI3
0x4000.C000 0x4000.CFFF UART0
0x4000.D000 0x4000.DFFF UART1
0x4000.E000 0x4000.EFFF UART2
0x4000.F000 0x4000.FFFF UART3
0x4001.0000 0x4001.0FFF UART4
0x4001.1000 0x4001.1FFF UART5
0x4001.2000 0x4001.2FFF UART6
0x4001.3000 0x4001.3FFF UART7
0x4001.4000 0x4001.FFFF Reserved
0x4002.0000 0x4002.0FFF I2C 0
0x4002.1000 0x4002.1FFF I2C 1
0x4002.2000 0x4002.2FFF I2C 2
0x4002.3000 0x4002.3FFF I2C 3
0x4002.4000 0x4002.4FFF GPIO Port E
0x4002.5000 0x4002.5FFF GPIO Port F
0x4002.6000 0x4002.7FFF Reserved
0x4002.8000 0x4002.8FFF PWM 0
0x4002.9000 0x4002.9FFF PWM 1
0x4002.A000 0x4002.BFFF Reserved
0x4002.C000 0x4002.CFFF QEI0
0x4002.D000 0x4002.DFFF QEI1
0x4002.E000 0x4002.FFFF Reserved
Deartment of ECE, NMIT 36
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0x4003.0000 0x4003.0FFF 16/32-bit Timer 0

0x4003.1000 0x4003.1FFF 16/32-bit Timer 1
0x4003.2000 0x4003.2FFF 16/32-bit Timer 2
0x4003.3000 0x4003.3FFF 16/32-bit Timer 3
0x4003.4000 0x4003.4FFF 16/32-bit Timer 4
0x4003.5000 0x4003.5FFF 16/32-bit Timer 5
0x4003.6000 0x4003.6FFF 32/64-bit Timer 0
0x4003.7000 0x4003.7FFF 32/64-bit Timer 1
0x4003.8000 0x4003.8FFF ADC0
0x4003.9000 0x4003.9FFF ADC1
0x4003.A000 0x4003.BFFF Reserved
0x4003.C000 0x4003.CFFF Analog Comparators
0x4003.D000 0x4003.FFFF Reserved
0x4004.0000 0x4004.0FFF CAN0 Controller
0x4004.1000 0x4004.1FFF CAN1 Controller
0x4004.2000 0x4004.BFFF Reserved
0x4004.C000 0x4004.CFFF 32/64-bit Timer 2
0x4004.D000 0x4004.DFFF 32/64-bit Timer 3
0x4004.E000 0x4004.EFFF 32/64-bit Timer 4
0x4004.F000 0x4004.FFFF 32/64-bit Timer 5
0x4005.0000 0x4005.0FFF USB
0x4005.1000 0x4005.7FFF Reserved
0x4005.8000 0x4005.8FFF GPIO Port A (AHB aperture)
0x4005.9000 0x4005.9FFF GPIO Port B (AHB aperture)
0x4005.A000 0x4005.AFFF GPIO Port C (AHB aperture)
0x4005.B000 0x4005.BFFF GPIO Port D (AHB aperture)
0x4005.C000 0x4005.CFFF GPIO Port E (AHB aperture)
0x4005.D000 0x4005.DFFF GPIO Port F (AHB aperture)
0x4005.E000 0x400A.EFFF Reserved
0x400A.F000 0x400A.FFFF EEPROM and Key Locker
0x400B.0000 0x400F.8FFF Reserved
0x400F.9000 0x400F.9FFF System Exception Module
0x400F.A000 0x400F.BFFF Reserved
0x400F.C000 0x400F.CFFF Hibernation Module
0x400F.D000 0x400F.DFFF Flash memory control
0x400F.E000 0x400F.EFFF System control
0x400F.F000 0x400F.FFFF µDMA
0x4010.0000 0x41FF.FFFF Reserved
0x4200.0000 0x43FF.FFFF Bit-banded alias of 0x4000.0000 through 0x400F.FFFF
0x4400.0000 0xDFFF.FFFF Reserved

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TIVA C Series Launch Pad

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TIVA C SERIES LAUNCH PAD PIN LAYOUT

LABLE J1 J3 LABLE
VCC 1 21 VBUS
CS(2) A11 PB5 2 22 GND
RX(1) PB0 3 23 PD0 A7 SCL(3) SCK(3)
TX(1) PB1 4 24 PD1 A6 SDA(3) CS(3)
RX(5) SCL(2) A9 PE4 5 25 PD2 A5 MISO(3)
TX(5) SDA(2) A8 PE5 6 26 PD3 A4 MOSI(3)
SCK(2) A10 PB4 7 27 PE1 PE1 A2 TX(7)
MOSI(0) PA5 8 28 PE2 PE2 A1
SCL(1) PA6 9 29 PE3 PE3 A0
SDA(1) PA7 10 30 PF1 PF1 RED_LIGHT MOSI(1)

LABLE J4 J2 LABLE
SCK(1) BLUE LED PF2 40 20 GND
CS(1) GREEN LED PF3 39 19 PB2 SCL(0)
SDA(0) PB3 38 18 PE0 A3
RX(1) PC4 37 17 PF0 PUSH2 MIS0(1)
TX(1) PC5 36 16 RESET
RX(3) PC6 35 15 PB7 MISI(2)
TX(3) PC7 34 14 PB6 MISO(2)
RX(2) PD6 33 13 PA4 MIS0(0)
TX(2) PD7 32 12 PA3 CS(0)
PUSH PF4 31 11 PA2 SCK(0)

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TIVA STARTER KIT

Features:
⚫ 12v dc voltage is used to power up the board
⚫ On board DAC with stereo output connector
⚫ On 16*2 LCD Module
⚫ On board module to connect wireless Devices such as Zigbee, Bluetooth, RF and Wi-Fi
⚫ Slot for micro SD card
⚫ Analog Hex keypad(4*4)
⚫ 7-Segment Display
⚫ LED Array
⚫ On board RTC with Battery module

⚫ On board 4 channel ADC

⚫ Port to connect External thermocouple

⚫ LDR
⚫ Motor Driver with connecting Pins
⚫ Potentiometer
⚫ Buzzer
⚫ Temperature sensor (LM35)
⚫ Port for UART Communication

Deartment of ECE, NMIT 40

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DIP SWITCHES FOR POWER CONTROLE MODE

DAC 16*2 LCD

POWER SUPPLY 12 V

PORTA
(Internally connected to 7-SEGMENT DISPLAY
all peripheral)
PORTD

ADC ADC 8 8
8 8
PORT E

UART LED ARRAY

PORTB ZEGBEE/
TM4C123GH6PM PORT B
BLUETOOT
H
PORT B RTC
BUZZE
PORT D rt-D
R
PORT D

KEYPAD
PORT B/C/F

PORT D
PORTD

POT
LDR

DIP SWITCHES FOR POWER

MOTOR DRIVER CONTROLE MODE
TEMPETRATU
E SENSOR

Software Required:
1. Install CCSv5 or CCSv6. (http://processors.wiki.ti.com/index.php/Download_CCS)

2. Install TivaWare 2.1.1.71(http://www.ti.com/tool/sw-tm4c ) (Optional)

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Tiva C Series and Evaluation Kits provide a low-cost way to start designing with Tiva microcontrollers using Keil
RealView Microcontroller Development Kit (MDK) for ARM controllers.

Requirements:
Hardware:

• PC with windows XP/7/8

• ARM CORTEX M4 Starter kit

Software:

• ICDI drivers
• Keil MDK 4
• TivaWare
1.0 Creating Project by Importing from TivaWare:

1.1 Start the Keil μVision IDE

1.2 From the Project menu, select Open Project

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1.3 Use the dialog box to navigate to the Project0 program in the directory appropriate for your board.
From the location where you installed TivaWare, the Hello project is located in:
c\ti\TivaWare_C_Seriesn.n\examples\boards\ek-TM4C123lxl\Project0

1.4 Select the Project0.uvproj project file and click Open. The project opens in the IDE

1.5 You can

view source files in the project by double-clicking a filename in the Project Workspace pane on the
left. For example, double-click Project0.c, and the source file opens in the editor

1.6 Build the Project

Select Project → Rebuild all target files, or click the Rebuild all button (icon)

All of
the

Deartment of ECE, NMIT 44

 MICROCONTROLLER LAB 18ECL48
source files are compiled and linked. The activity can be seen in the Build window at the bottom of the
μVision IDE. The process completes with an application named Project0.axf built with no errors and no
warnings

Deartment of ECE, NMIT 45

 MICROCONTROLLER LAB 18ECL48
1.7 Load the Hello Program into the Flash Memory
You can debug with either the on-board ICDI or you can use the Keil ULINK debug probe. Select
Download from the Flash menu, or click the Download button (icon)

The
process
takes a
few

seconds. A progress bar will show at the bottom of the IDE window as the device is programmed.
When it is finished, the Build window will show that th device was erased, programmed, and verified
OK.

1.8 Debug and Run the Program

Select Start/Stop Debug Session from the Debug menu or click the Debug button (icon)

To Run Program click on Run Icon in Debug Window

Deartment of ECE, NMIT 46

 MICROCONTROLLER LAB 18ECL48
2.0 Creating New Project

2.1 Create a New Project

To create a new project, perform the following steps:

In the Project menu, select Project → new uVision Project…

Save Project by creating a new folder anywhere in computer (preferred location c\ti\TivaWare_C_Series-
n.n\examples\boards\(user define folder))

2.2 Once the project file (.uvproj) is saved, a dialog window appears asking you to select the device
that you are using. Select the appropriate device under the Texas Instruments list
(TM4C123GH6PM)

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2.3 The tool asks whether you

want to add startup code to
the project You can click No, so you can add it externally provided by TivaWare tool

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 MICROCONTROLLER LAB 18ECL48

An empty project will be created as shown above

2.4 To add source file

Right click on Project select Add New Item to Group ‘Source Group1’…

It will open template window files select .c and name source file name and edit source file with
application code

Right click
on Project
tool (TivaWare) select Add
Existing File
to Group

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 MICROCONTROLLER LAB 18ECL48
‘Source Group1’… 2.5 Adding startup
code provided by

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 MICROCONTROLLER LAB 18ECL48

Brows to c\ti\TivaWare_C_Seriesn.n\examples\boards\ek-TM4C123gxl\Project0\ startup_rvmdk.s

2.6 Creating a New group under target (project) to add driver

lib Right click on Target click on “Add Groups….”

A new folder type option will be available under Target1 as shown below, name can be changed

2.7 adding driver library

Right click on New Group click on Add Existing File to Group ‘Source Group1’…

Browse to Driver library provided for Keil in TivaWare

Brows to c\ti\TivaWare_C_Seriesn.n\driverlib\rvmdk\driver.lib
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 MICROCONTROLLER LAB 18ECL48

After adding driver library the project look like above

2.8 option for target (Add TivaWare Hooks/ Configure Your Hardware/ Set up Debug)

Right click on Target 1 select ‘Option for Target 1’

Select C/C++ option and click on folder select option

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 MICROCONTROLLER LAB 18ECL48

Add the path of TivaWare by selecting new add path as shown below (Path:c/ti/tivaware c series xx.xx)

Click ok

For debugging connection need to be selected click on Debug Tab select use emulator option and select debugger
as stellaries ICDI and click OK and complete target option setting

2.9 Building Loading and Running:

Follow the procedure mentioned in 1.6, 1.7 and 1.8

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Interfacing of RGB LED

TM4C123GH6PM PF1 LED1

LED2

PF3
LED3

OUTPUT PORTS:
PORT F Pin1 – LED1
PORT F Pin2 – LED2
PORT F Pin3 – LED3

Expected Output: RED, GREEN & BLUE Lights in Launch Pad blinks in accordance with delay

Program

/* RGB LED */
#include <stdint.h>

#include "inc\tm4c123gh6pm.h"
void delayMs(int n);

int main(void)
{
/* enable clock to GPIOF/B/C at clock gating control register */
SYSCTL_RCGCGPIO_R |= SYSCTL_RCGCGPIO_R5;//PF

/* enable the GPIO pins for the PF2/PF3/PB3/PC4 as output */

GPIO_PORTF_DIR_R = 0x0E;//PF2/3

/* enable the GPIO pins for digital function */

GPIO_PORTF_DEN_R = 0x0E;

while(1)

{
GPIO_PORTF_DATA_R = 0x02;
delayMs(500);
GPIO_PORTF_DATA_R = 0x04;
delayMs(500);
GPIO_PORTF_DATA_R = 0x08;

delayMs(500);

}}
Deartment of ECE, NMIT 54

/* delay n milliseconds (16 MHz CPU clock) */

void delayMs(int n)

{
 MICROCONTROLLER LAB 18ECL48

Internal Circuit:

Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108

This register controls the clock gating logic in normal Run mode. Each bit controls a clock enable for a given interface,
function, or module. If set, the module receives a clock and functions. Otherwise, the module is unclocked and disabled
(saving power). If the module is unclocked, reads or writes to the module generate a bus fault. The reset state of these bits is
0 (unclocked) unless otherwise noted, so that all functional modules are disabled. It is the responsibility of software to enable
the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions,
or modules to control. This configuration is implemented to assure reasonable code compatibility with other family and
future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for
Deep- Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses
sleep modes. Note that there must be a delay of 3 system clocks after a module clock is enabled beforeany registers in that
module are accessed.

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 MICROCONTROLLER LAB 18ECL48

SYSCTL_RCGCGPIO_R |= SYSCTL_RCGCGPIO_R5;//Provide CLK to PORT F

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 MICROCONTROLLER LAB 18ECL48
Setting Direction of GPIO pins

GPIO Direction (GPIODIR), offset 0x400

The GPIODIR register is the data direction register. Setting a bit in the GPIODIR register configures the corresponding pin to
be an output, while clearing a bit configures the corresponding pin to be an input. All bits are cleared by a reset, meaning all
GPIO pins are inputs by default.

GPIO_PORTF_DIR_R = 0x0E;\\Enable pin PF1 PF2 & PF3

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 MICROCONTROLLER LAB 18ECL48
GPIO Digital Enable (GPIODEN), offset 0x51C

Note: Pins configured as digital inputs are Schmitt-triggered.

The GPIODEN register is the digital enable register. By default, all GPIO signals except those listedbelow are configured out
of reset to be undriven (tristate). Their digital function is disabled; they donot drive a logic value on the pin and they do not
allow the pin voltage into the GPIO receiver. Touse the pin as a digital input or output (either GPIO or alternate function),
the corresponding GPIODENbit must be set.

GPIO_PORTF_DEN_R = 0x0E;\\Digital enable PortF pin PF1 PF2 & PF3

Deartment of ECE, NMIT 58

 MICROCONTROLLER LAB 18ECL48
GPIO Data (GPIODATA), offset 0x000

The GPIODATA register is the data register. In software control mode, values written in theGPIODATA register are transferred
onto the GPIO port pins if the respective pins have beenconfigured as outputs through the GPIO Direction (GPIODIR) register
In order to write to GPIODATA, the corresponding bits in the mask, resulting from the address busbits [9:2], must be set.
Otherwise, the bit values remain unchanged by the write.Similarly, the values read from this register are determined for each
bit by the mask bit derived fromthe address used to access the data register, bits [9:2]. Bits that are set in the address mask
causethe corresponding bits in GPIODATA to be read, and bits that are clear in the address mask causethe corresponding bits
in GPIODATA to be read as 0, regardless of their value.A read from GPIODATA returns the last bit value written if the
respective pins are configured asoutputs, or it returns the value on the corresponding input pin when these are configured as
inputs.All bits are cleared by a reset.

GPIO_PORTF_DATA_R = 0x02;// move data 0x02 to Port F RED LED

// move data 0x04 to Port F Blue LED

//move data 0x08 to Port F Green LED

Deartment of ECE, NMIT 59

 MICROCONTROLLER LAB 18ECL48
Program External Interrupt via Switch SW1 to Glow LED

SW1 PF4 PF1 LED1

TMC123GH6PM

INPUTPORTS:
PORT F PIN 4

OUTPUT PORTS:
PORT F Pin 1 – LED1 Red LED

Expected Output:
By Pressing switch SW1 Corresponding Red LED glows

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Internal Circuit:

#include "TM4C123GH6PM.h"
int main(void)

unsigned int value;

GPIOF->DIR = 0x0E; /* set PORTF 1,2&3 pin as output(LED) pin */

GPIOF->DEN = 0x12;
GPIOF->PUR = 0x10; /* set PORTF pins 4&1 as digital pins */

while(1)

value = GPIOF->DATA; /* read data from PORTF */

value = ~value; /* switch is low active; LED is high active */
value = value >> 1; /* shift it right to display on red LED */
GPIOF->DATA = value; /* put it on red LED */

Deartment of ECE, NMIT 61

 MICROCONTROLLER LAB 18ECL48
GPIO Pull-Up Select (GPIOPUR), offset 0x510

The GPIOPUR register is the pull-up control register. When a bit is set, a weak pull-up resistor on the corresponding GPIO
signal is enabled. Setting a bit in GPIOPUR automatically clears the corresponding bit in the GPIO Pull-Down Select
(GPIOPDR) register (see page 679). Write access to this register is protected with the GPIOCR register. Bits in GPIOCR that
are cleared prevent writes to the equivalent bit in this register.

NVIC Register Descriptions

This section lists and describes the NVIC registers, in numerical order by address offset. The NVIC registers can only be
fully accessed from privileged mode, but interrupts can be pended while in unprivileged mode by enabling the
Configuration and Control (CFGCTRL) register. Any other unprivileged mode access causes a bus fault. Ensure software
uses correctly aligned register accesses. The processor does not support unaligned accesses to NVIC registers. An
interrupt can enter the pending state even if it is disabled. Before programming the VTABLE register to relocate the
vector table, ensure the vector table entries of the new vector table are set up for fault handlers, NMI, and all enabled
exceptions such as interrupts.

Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100

Register 5: Interrupt 32-63 Set Enable (EN1), offset 0x104
Register 6: Interrupt 64-95 Set Enable (EN2), offset 0x108
Register 7: Interrupt 96-127 Set Enable (EN3), offset 0x10C
Note: This register can only be accessed from privileged
mode.

The ENn registers enable interrupts and show which interrupts are enabled.Bit 0 of EN0 corresponds to Interrupt 0; bit
31 corresponds to Interrupt 31. Bit 0 of EN1 corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. Bit 0 of

Deartment of ECE, NMIT 62

 MICROCONTROLLER LAB 18ECL48
EN2 corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. Bit 0 of EN3 corresponds to Interrupt 96; bit 31
corresponds to Interrupt 127Bit 0 of EN4 corresponds to Interrupt 128; bit 10 corresponds to Interrupt 138.

If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled,
asserting its interrupt signal changes the interrupt state to pending, but the NVI never activates the interrupt, regardless
of its priority.

Deartment of ECE, NMIT 63

 MICROCONTROLLER LAB 18ECL48

NVIC->ISER[0] |= 0x40000000;// Enable Interrupt 30

Deartment of ECE, NMIT 40

 MICROCONTROLLER LAB 18ECL48
Interfacing of DC Motor Using L29DD

L293DD

TM4C123GH6PM PF2 IN1

DC

MOTOR

(TM4C123GH6PM)

⚫ PORTF Pin2 Input 1

⚫ PORTF Pin3 Input 2

INPUT PINS (L293DD)

⚫ IN1 (Pin No.2)

⚫ IN2 (Pin No.7)

OUTPUT PINS (L293DD)

⚫ L1
⚫ L2

/* DC_Motor _CLK*/

#include <stdint.h>

#include "inc\tm4c123gh6pm.h"
void delayMs(int n);

int main(void)
{
/* enable clock to GPIOF/B/C at clock gating control register */
SYSCTL_RCGCGPIO_R |= SYSCTL_RCGCGPIO_R5;//PF

/* enable the GPIO pins for the PF2/PF3/PB3/PC4 as output */

GPIO_PORTF_DIR_R = 0x0E;//PF2/3

/* enable the GPIO pins for digital function */

GPIO_PORTF_DEN_R = 0x0E;

while(1)
{
GPIO_PORTF_DATA_R = 0x08;
delayMs(500);
} }

/* delay n milliseconds (16 MHz CPU clock) */

void delayMs(int n) Deartment of ECE, NMIT 41

{
int i, j;
for(i = 0 ; i < n; i++)
 MICROCONTROLLER LAB 18ECL48

/* DC_Motor _AntiCLK*/

#include <stdint.h>

#include "inc\tm4c123gh6pm.h"

void delayMs(int n);

int main(void)
{
/* enable clock to GPIOF/B/C at clock gating control register */
SYSCTL_RCGCGPIO_R |= SYSCTL_RCGCGPIO_R5;//PF

/* enable the GPIO pins for the PF2/PF3/PB3/PC4 as output */

GPIO_PORTF_DIR_R = 0x0E;//PF2/3

/* enable the GPIO pins for digital function */

GPIO_PORTF_DEN_R = 0x0E;

while(1)
{
GPIO_PORTF_DATA_R = 0x04;
delayMs(500);

/* delay n milliseconds (16 MHz CPU clock) */

void delayMs(int n)
Hear L1 and L2 is connected to PF2 & PF3 via L293DD for driving load so if we move
{
int i, j;
For Clock wise:
for(i = 0 ; i < n; i++)
for(j = 0; j < 4180; j++)

0x08 to PF{}
then/*it do
willnothing
enable for
PF3 1and
ms */
disable PF2
}

PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0

X X X X 1 0 X X

Deartment of ECE, NMIT 42

 MICROCONTROLLER LAB 18ECL48
For Anti-Clock wise:

0x04 to PF then it will enable PF2 and disable PF3

PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0

X X X X 0 1 X X

Interfacing of Stepper Motor Using L29DD

PB3 IN1 OUT1

IN2 L293DD OUT2
STEEPER
TM4C123GH6PM PC4
MOTOR
IN4 OUT3
PF3
OUT4

(TM4C123GH6PM)

• PORTF Pin2 Input 1

• PORTF Pin3 Input 2
• PORTB Pin3 Input 3
• PORTC Pin4 Input 4

INPUT PINS (L293DD)

• IN1 (Pin No.2)

• IN2 (Pin No.7)
• IN3 (Pin No.10)
• IN4 (Pin No.15)

OUTPUT PINS (L293DD)

• OUT1 (Pin No.3)

• OUT2 (Pin No.6)
• OUT3 (Pin No.11) and OUT4 (Pin No.14)

EXPECTED OUTPUT:

Deartment of ECE, NMIT 43

 MICROCONTROLLER LAB 18ECL48
The Motor rotates in clock wise Step Angle depends on type of motor used.

Internal Circuit

L293DD (Motor Driver) :

Description
The Device is a monolithic integrated high voltage, high current four channel driver designed
to accept standard DTL or TTL logic levels and drive inductive loads (such as relays solenoids, DC and
stepping motors) and switching power transistors. To simplify use as two bridges each pair of channels is
equipped with an enable input. A separate supply input is provided for the logic, allowing operation at a
lower voltage and internal clamp diodes are included. This device is suitable for use in switching applications
at frequencies up to 5 kHz. The L293D is assembled in a 16 lead plastic package which has 4 centre pins
connected together and used for heat sinking The L293DD is assembled in a 20 lead surface mount which
has 8 centre pins connected together and used for heat sinking.
Benefits & Features:
1. 600mA OUTPUT CURRENT CAPABILITY PER CHANNEL
2. 1.2A PEAK OUTPUT CURRENT (non repetitive) PER CHANNEL
3. ENABLE FACILITY OVERTEMPERATURE PROTECTION
4. LOGICAL "0" INPUT VOLTAGE UP TO 1.5 V (HIGH NOISE IMMUNITY)
5. INTERNAL CLAMP DIODE

Deartment of ECE, NMIT 44

 MICROCONTROLLER LAB 18ECL48

/* Stepper Motor Interface */

#include <stdint.h>
#include "inc\tm4c123gh6pm.h"
void delayMs(int n);

int main(void)
{
/* enable clock to GPIOF/B/C at clock gating control register */
SYSCTL_RCGCGPIO_R |= SYSCTL_RCGCGPIO_R5;//PF
SYSCTL_RCGCGPIO_R |= SYSCTL_RCGCGPIO_R1;//PB
SYSCTL_RCGCGPIO_R |= SYSCTL_RCGCGPIO_R2;//PC

/* enable the GPIO pins for the PF2/PF3/PB3/PC4 as output */

GPIO_PORTF_DIR_R = 0x0E;//PF2/3

GPIO_PORTB_DIR_R = 0x08;//PB3
GPIO_PORTC_DIR_R = 0x10;//PC4

/* enable the GPIO pins for digital function */

GPIO_PORTF_DEN_R = 0x0E;

GPIO_PORTB_DEN_R = 0x08;
GPIO_PORTC_DEN_R = 0x10;

while(1)
{
GPIO_PORTF_DATA_R = 0x04; /* PF2 =1*/
delayMs(500);
GPIO_PORTF_DATA_R = 0;

delayMs(500);
GPIO_PORTF_DATA_R = 0x08; /* PF3 =1 */
delayMs(500);
GPIO_PORTF_DATA_R = 0;

delayMs(500);

GPIO_PORTB_DATA_R = 0x08; /* PB2 =3 */

delayMs(500);
GPIO_PORTB_DATA_R = 0;

delayMs(500);
GPIO_PORTC_DATA_R = 0x10; /* P2 =1*/ Deartment of ECE, NMIT 45
delayMs(500);
GPIO_PORTC_DATA_R = 0;

delayMs(500);
 MICROCONTROLLER LAB 18ECL48

Controlling LED, Buzzer using Switch (SW1)

TM4C123GH6PM

PF2 LED_G

Buzzer

/* LED_BUZZER_SW1 */

#include <stdint.h>
#include "inc\tm4c123gh6pm.h"
void delayMs(int n);

int value;
int main(void)
{

/* enable clock to GPIO F/D at clock gating control register *//* GPIO PORT D PIN 7 is
connected to Buzzer */

SYSCTL_RCGCGPIO_R |= SYSCTL_RCGCGPIO_R3;//PD
SYSCTL_RCGCGPIO_R |= SYSCTL_RCGCGPIO_R5;//PF

/* enable the GPIO pins for the PF2/PF3/PB3/PC4 as output */

GPIO_PORTD_LOCK_R = 0x4C4F434B; // unlock GPIO Port D
GPIO_PORTD_CR_R = 0x80; // allow changes to PD7-1 for GPIO
GPIO_PORTD_DIR_R = 0xf0;//PD7

GPIO_PORTD_DEN_R = 0xf0; /* enable the GPIO pins for digital function */

GPIO_PORTF_DIR_R = 0x08; /* set PORTF3 pin as output (LED) pin */

/* and PORTF4 as input, SW1 is on PORTF4 */

GPIO_PORTF_DEN_R = 0x18; /* set PORTF pins 4-3 as digital pins */
GPIO_PORTF_PUR_R = 0x10; /* enable pull up for pin 4 */

while (1)
{

value = GPIO_PORTF_DATA_R; /* read data from PORTF */

value = ~value; /* switch is low active; LED is high active */

value = value >> 1; /* shift it right to display on green LED */
GPIO_PORTF_DATA_R = value; /* put it on the green LED */

value = value << 1;

GPIO_PORTD_DATA_R = value;

Deartment of ECE, NMIT 46

 MICROCONTROLLER LAB 18ECL48

/* delay n milliseconds (16 MHz CPU clock) */

void delayMs(int n)

{
int i, j;
for(i = 0 ; i < n; i++)
for(j = 0; j < 4180; j++)
{} /* do nothing for 1 ms */
}

Deartment of ECE, NMIT 47

 MICROCONTROLLER LAB 18ECL48
GPIO Lock (GPIOLOCK)

The GPIOLOCK register enables write access to the GPIOCR register (see page 685). Writing 0x4C4F.434B to the
GPIOLOCK register unlocks the GPIOCR register. Writing any other value to the GPIOLOCK register re-enables the
locked state. Reading the GPIOLOCK register returns the lock status rather than the 32-bit value that was
previously written. Therefore, when write accesses are disabled, or locked, reading the GPIOLOCK register returns
0x0000.0001. When write accesses are enabled, or unlocked, reading the GPIOLOCK register returns 0x0000.0000.

Deartment of ECE, NMIT 48

 MICROCONTROLLER LAB 18ECL48

GPIO Commit (GPIOCR),

The GPIOCR register is the commit register. The value of the GPIOCR register determines which bits of the
GPIOAFSEL, GPIOPUR, GPIOPDR, and GPIODEN registers are committed when a write to these registers is performed.
If a bit in the GPIOCR register is cleared, the data being written to the corresponding bit in the GPIOAFSEL, GPIOPUR,
GPIOPDR, or GPIODEN registers cannot be committed and retains its previous value. If a bit in the GPIOCR register is
set, the data being written to the corresponding bit of the GPIOAFSEL, GPIOPUR, GPIOPDR, or GPIODEN registers is
committed to the register and reflects the new value. The contents of the GPIOCR register can only be modified if
the status in the GPIOLOCK register is unlocked. Writes to the GPIOCR register are ignored if the status in the
GPIOLOCK register is locked.

Deartment of ECE, NMIT 49

 MICROCONTROLLER LAB 18ECL48

GPIO Pull-Up Select (GPIOPUR)

The GPIOPUR register is the pull-up control register. When a bit is set, a weak pull-up resistor on the corresponding
GPIO signal is enabled. Setting a bit in GPIOPUR automatically clears the corresponding bit in the GPIO Pull- Down
Select (GPIOPDR) register Write access to this register is protected with the GPIOCR register. Bits in GPIOCR that are
cleared prevent writes to the equivalent bit in this register.

Deartment of ECE, NMIT 50

 MICROCONTROLLER LAB 18ECL48
/* ************************************************

*Interfacing of 7 segment LED

**************************************************/
#include <stdint.h>
#include "inc\tm4c123gh6pm.h"

void delayMs(int n);

void shift_out1(unsigned char str);
unsigned char a[16] =
{0xFC,0x60,0xDA,0xF2,0x66,0xB6,0xBE,0xE0,0xFE,0xF6,0xEE,0x3E,0x9C,0x7A,0x9E,0x8E};
unsigned int i;
int main(void)
{

ir
SYSCTL_RCGCGPIO_R = 0x10;
GPIO_PORTE_DIR_R = 0x1F;
GPIO_PORTE_DEN_R = 0x1F;

while(1){
for(i=0;i<=15;i++)
{
shift_out1(a[i]);
shift_out1(a[i]);
shift_out1(a[i]);
shift_out1(a[i]);
shift_out1(a[i]);

Deartment of ECE, NMIT 51

 MICROCONTROLLER LAB 18ECL48
delayMs(1000);
}
}
}
void shift_out1(unsigned char str)
{
unsigned char j=0,check;

for(j=0;j<=7;j++)
{
GPIO_PORTE_DATA_R = 0x00; //PE3 pin(sclk) is low (0000 0000)
check = (str &(1<<j));
if(check)
GPIO_PORTE_DATA_R = 0x04; //PE2 pin(sdat) is high (0000 0100)

else
GPIO_PORTE_DATA_R |= 0x00;
GPIO_PORTE_DATA_R |= 0x08; //PE3 pin(sclk) is high (0000 1000)
GPIO_PORTE_DATA_R |= 0x10;
}

}
void delayMs(int n)
{
int i, j;
for(i = 0 ; i < n; i++)
for(j = 0; j < 4180; j++)
{} /* do nothing for 1 ms */
}

Deartment of ECE, NMIT 52

 MICROCONTROLLER LAB 18ECL48

APPENDIX

TM4C123GH6PM Microcontroller
All members of the Tiva C Series, including the TM4C123GH6PM microcontroller, are designed
around an ARM Cortex-M processor core. The ARM Cortex-M processor provides the core for a high-
performance; low-cost platform that meets the needs of minimal memory implementation, reduced pin
count, and low power consumption, while delivering outstanding computational performance and
exceptional system response to interrupts.

Serial Communications Peripherals

The TM4C123GH6PM controller supports both asynchronous and synchronous serial
communications

Two CAN 2.0 A/B controllers

The TM4C123GH6PM microcontroller includes two CAN units with the following features:
• CAN protocol version 2.0 part A/B
• Bit rates up to 1 Mbps
• 32 message objects with individual identifier masks
• Maskable interrupt
• Disable Automatic Retransmission mode for Time-Triggered CAN (TTCAN)
applications
• Programmable loopback mode for self-test operation
• Programmable FIFO mode enables storage of multiple message objects
• Gluelessly attaches to an external CAN transceiver through the CANnTX and
CANnRX signals.

Universal Serial Bus (USB)

The TM4C123GH6PM microcontroller supports USB 2.0 full and low speed with three
configurations: USB Device, USB Host, and USB On-The-Go (OTG).The USB module has the following
features:
• Complies with USB-IF (Implementer's Forum) certification standards
• USB 2.0 full-speed (12 Mbps) and low-speed (1.5 Mbps) operation with integrated PHY
• 4 transfer types: Control, Interrupt, Bulk, and Isochronous
• 4 KB dedicated endpoint memory: one endpoint may be defined for double-buffered 1023-
byte isochronous packet size.

Deartment of ECE, NMIT 53

 MICROCONTROLLER LAB 18ECL48

TM4C123GH6PM Microcontroller Features

Deartment of ECE, NMIT 54