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DENEBOLA (See3CAM_CX3RDK) – CX3™ Reference Design Kit

Hardware User Manual
Revision 1.3

May 26, 2014

http://www.e-consystems.com/

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 Table of Contents

DENEBOLA (See3CAM_CX3RDK) – CX3™ Reference Design Kit ...............................................................................1

1. INTRODUCTION ................................................................................................................................................3
2. SCOPE ...............................................................................................................................................................3
3. PREREQUISITES .................................................................................................................................................3
4. FEATURES..........................................................................................................................................................3
5. BLOCK DIAGRAM ..............................................................................................................................................4
6. DENEBOLA CX3 RDK..........................................................................................................................................5
6.1 BASE BOARD .......................................................................................................................................................5
6.2 DENEBOLA CX3 RDK SETUP ................................................................................................................................6
7. ELECTRICAL SPECIFICATION ..............................................................................................................................7
8. BOARD SPECIFICATION .....................................................................................................................................7
8.1 USB3.0 CONNECTOR (CN2) .............................................................................................................................7
8.2 POWER SUPPLY ...................................................................................................................................................8
8.3 MIPI CSI-2 RX INTERFACE (CN10)........................................................................................................................9
8.4 GPIO EXPANSION HEADER (CN8) ..................................................................................................................... 10
8.5 RS232-DB9 CONNECTOR (CN3) ....................................................................................................................... 11
8.6 JTAG HEADER (CN4) ......................................................................................................................................... 11
8.7 BOOT MODE SWITCH (SW5) ............................................................................................................................ 12
8.7.1 USB BOOT ................................................................................................................................................. 13
8.7.2 I2C BOOT ................................................................................................................................................... 14
8.7.3 SPI BOOT ................................................................................................................................................... 17
8.8 CLOCK SCHEME OF THE CX3 RDK .................................................................................................................... 18
8.9 RESET SCHEME OF THE CX3 RDK ..................................................................................................................... 19
9. MECHANICAL SPECIFICATION ........................................................................................................................ 19
10. ASSEMBLY DRAWING ...................................................................................................................................... 20
11. LEARN MORE AT ........................................................................................................................................ 21

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1. INTRODUCTION
Denebola (See3CAM_CX3RDK) is a USB3.0 USB video class (UVC) reference design kit (RDK) developed by
e-con Systems using the EZ-USB® CX3 USB3.0 peripheral controller from Cypress® Semiconductor. The
Cypress EZ-USB® CX3 is a USB3.0 peripheral controller that enables developers to add USB3.0
connectivity to any image sensors compliant with the Mobile Industry Processor Interface (MIPI) Camera
Serial Interface Type 2 (CSI-2) standard.

The Denebola RDK developed using EZ-USB® CX3 is a complete RDK and has the OmniVision OV5640
CMOS image sensor interfaced to it through a two-lane MIPI CSI-2 interface. This is a fully functional
camera RDK that can stream uncompressed 720p60, 1080p30, and 5 MP at 15 fps. Denebola RDK is a two-
board solution containing a base board designed around the Cypress CX3 USB3.0 peripheral controller
and the camera daughter board designed using the OmniVision OV5640 CMOS image-sensor-based auto-
focus camera module.

2. SCOPE
This hardware user manual details the hardware features of the Denebola RDK; electrical and mechanical
specification; and provides detailed information about the interfaces available on the CX3 RDK.

3. PREREQUISITES
Please refer to the Cypress documentation for information on the CX3 SDK and the USB Control Center.

4. FEATURES
 Two-board solution containing a base board based on CX3 and a camera daughter board based on
e-CAM52_MI5640_MOD
 Samtec high-speed connector for a four-lane MIPI to support the Aptina demo3 image-sensor
board interface
 OmniVision OV5640 daughter board interfaced through a two-lane MIPI CSI-2 interface
 RS232-level UART port for debugging and other communication
 SPI Flash and I2C EEPROM for firmware storage
 User-configurable GPIOs from the GPIO header
 USB bus-powered and also powered by an external 5-V supply
 JTAG interface
 Maximum frame rates for Preview and Capture
o VGA - 60 fps
o HD (720p) - 60 fps
o Full HD (1080p) - 30 fps
o 5 MP (2592 x 1944) - 15 fps
o Preview format: YUV422 (16 bits per pixel)
 Still Image Capture
o 5 MP (2592 x 1944) resolution
o YUV422 (16 bits per pixel) format

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5. BLOCK DIAGRAM

Figure 5.1. CX3 RDK Functional Block Diagram

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6. DENEBOLA CX3 RDK
6.1 BASE BOARD

Figure 6.1. CX3 RDK Base Board: Top View

Osc 32.768 KHz
Osc 19.2 MHz

I2C
EEPROMs

UART
BUFFER
3.3V LDO

SPI FLASH
RS232
LINE
DRIVER

Figure 6.2. CX3 RDK Base Board: Bottom View

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6.2 DENEBOLA CX3 RDK SETUP

The DENEBOLA kit consists of two boards used to demonstrate the CX3 5MP MIPI Camera.

 EZ-USB CX3 Reference Design Kit (CX3 RDK) base board

 OV5640 sensor daughter board: e-CAM59CX3

By default, the CX3 RDK comes with the OV5640 daughter board fixed onto the CX3 RDK base board. The
CX3 RDK setup is shown in Figure6.3.

Figure 6.3. CX3 RDK Setup

The details about connecting the Image Sensor daughter board with the CX3 RDK base board are shown in
Figure 6.4.

Figure 6.4. CX3 RDK Board Interface

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7. ELECTRICAL SPECIFICATION
The recommended DC operating supply voltage specification is shown in Table 7.1.

PARAMETER DESCRIPTION MIN TYP MAX UNIT

USB 3.0 Cable Bus Power
VBUS / VCC_5V / External 5V power 4.75 5 5.25 V
Adaptor
Table 7.1. Recommended Operating Voltage

8. BOARD SPECIFICATION

8.1 USB3.0 CONNECTOR (CN2)

A standard USB3.0 Micro-B receptacle is used on the CX3_RDK. The part number is Hirose’s ZX360D-B-
10P. The USB3.0 pins (SS_TX_M, SS_TX_P, SS_RX_P, and SS_RX_M) and USB 2.0 pins (OTG_ID, D+, and D–)
with power (VBUS and GND) are available on the CN2 USB3.0 receptacle. CX3 is capable of operating in
Super-speed, High-speed and Full-speed protocols.

The USB3.0 and USB2.0 lines go through an ESD protection device for additional ESD protection. The CX3
RDK board can be bus-powered using the VBUS pin on the connector.

Figure 8.1. CX3 RDK USB3.0 Circuit

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8.2 POWER SUPPLY

The CX3 RDK board can be powered in two ways:

 Self power: Use the external DC 5-V, 1-A power adapter (not supplied with the RDK).

Figure 8.2. Center Positive Power Supply

 Bus power: The board can be powered using the USB3.0 cable by connecting to the PC host.

The Slide switch (SW3) is provided for power selection from either of the above sources, as explained
in the Table 8.1 and Figure 8.3.

SW3 POSITION POWERED THROUGH

1 USB RECEPTACLE (CN2) – Bus Powered
2 5V DC JACK (CN5) – Self Powered
Table 8.1. SW3 Settings

The green LED (D4) glows when the board is powered on.

USB3.0 Cable
[VBUS]

External Power
Adapter
[DC: 5V]

External 5V USB VBUS

Self-Powered Bus-Powered
Power Switch 2 1
(SW3)

Power -On
LED(D4)

Figure 8.3. Power-On Switch Configuration

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8.3 MIPI CSI-2 RX INTERFACE (CN10)

The four-lane MIPI CSI-2 interface from CX3 is routed to a Samtec high-speed interface connector (CN10).
The OmniVision OV5640 sensor-based daughter board is designed to plug in with this connector. The
daughter-board image data communication occurs through a two-lane MIPI CSI-2 interface.
This connector (CN10) interface is also compatible with the Aptina DEMO3 Sensor Head Board interface.

The I2C lines, a few GPIOs from the CX3, and power supplies (1.8 V, 2.8 V, and 3.3 V) are also terminated in
CN10 to support the Image Sensor daughter board interface.

The Figure 8.4 shows the high-speed interface connector.

Figure 8.4. MIPI Interface Connector

The pin-out of the MIPI Interface Connector (CN10) is provided in Table 8.2.

CN10 CN10
PIN SIGNAL NAME DESCRIPTION PIN SIGNAL NAME DESCRIPTION
NO NO
MIPI Data Lane 1 MIPI Data Lane2
1 MIPI_DAT1+ 2 MIPI_DAT2+
Differential Pair + Differential Pair +
MIPI Data Lane 1 MIPI Data Lane2
3 MIPI_DAT1- 4 MIPI_DAT2-
Differential Pair - Differential Pair -
Clock from camera MIPI Data Lane3
5 CLK_OUT 6 MIPI_DAT3+
head board Differential Pair +
MIPI Data Lane3
7 NC - 8 MIPI_DAT3-
Differential Pair -
General purpose IO
9 CX3_GPIO23** 10 GND Ground
‘23’ from CX3

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CN10 CN10
PIN SIGNAL NAME DESCRIPTION PIN SIGNAL NAME DESCRIPTION
NO NO
General purpose IO General purpose IO ‘18’
11 CX3_GPIO44 12 CX3_GPIO18**
‘44’ from CX3 from CX3
General purpose IO ‘24’
13 GND Ground 14 CX3_GPIO24**
from CX3
IO voltage of
15 VDDIO_OUT 16 NC -
head/daughter board
17 NC - 18 NC -
19 NC - 20 NC -
21 NC - 22 NC -
23 NC - 24 NC -
CX3 GPIO from base
25 NC - 26 MIPI_CAM_PWDN
board
27 NC - 28 NC -
29 NC - 30 NC -
Image sensor reset
31 MIPI_CAM_RST from CX3 MIPI bridge
32 NC -

33 NC - 34 NC -
35 NC - 36 NC -
Serial Data line of I2C
37 CAM_I2C_SDA from base board 38 VCC2P8 2.8 V from base board

39 VCC_SYS 5 V from base board 40 NC -

41 NC - 42 VCC1P8 1.8 V from base board
Serial Clock line of I2C Bridge clock output to
43 CAM_I2C_SCL 44 CLKM_CX3
from base board image sensor clock input
45 NC - 46 VCC1P2 1.2 V from base board
47 VCC_VIO4 3.3 V from base board 48 VCC2P8 2.8 V from base board
MIPI Data Lane 0 MIPI Clock lane
49 MIPI_DAT0+ 50 MIPI_CLK-
Differential Pair + Differential Pair -
MIPI Data Lane 0 MIPI Clock lane
51 MIPI_DAT0- 52 MIPI_CLK+
Differential Pair - Differential Pair +
Table 8.2. MIPI Connector Pin-out

**Highlighted GPIOs are shared in both the MIPI (CN10) and the GPIO Header (CN8)

8.4 GPIO EXPANSION HEADER (CN8)

The expansion header (CN8) hosts the GPIO lines, excluding the SPI, I2C signals, and CX3 interrupt signal.
The same SPI interface that is used for on-board Flash memory is terminated here. The 0 Ω series resistor
option is provided in the schematics, in case you need to isolate these signals from the on-board SPI Flash
chip. All the GPIOs in Table 8.3 are 3.3 V logic, according to the default settings of the CX3 RDK.

The pin-out of the GPIO Expansion Header (CN8) is shown in Table 8.3.

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CN8 CN8
PIN SIGNAL NAME DESCRIPTION PIN SIGNAL NAME DESCRIPTION
NO NO
DC 5V from RDK base General purpose IO from
1 VCC_SYS 2 CX3_GPIO17
board CX3
General purpose IO from
3 GND Ground 4 CX3_GPIO18**
CX3
SPI’s MISO input to CX3 General purpose IO from
5 CX3_SPI_MISO 6 CX3_GPIO19
from slave device CX3
General purpose IO from
7 CX3_SPI_SSN SPI’s SSN from CX3 8 CX3_GPIO20
CX3
SPI’s MOSI output from General purpose IO from
9 CX3_SPI_MOSI 10 CX3_GPIO21
CX3 as master CX3
General purpose IO from
11 CX3_SPI_SCK SPI clock from CX3 12 CX3_GPIO22
CX3
General purpose IO from General purpose IO from
13 CX3_GPIO26 14 CX3_GPIO23**
CX3 CX3
General purpose IO from General purpose IO from
15 CX3_GPIO57 16 CX3_GPIO24**
CX3 CX3
General purpose IO from General purpose IO from
17 CX3_GPIO52 18 CX3_GPIO25
CX3 CX3
General purpose IO from Active low interrupt
19 CX3_GPIO50 20 nINT_CX3
CX3 input to CX3
General purpose IO from
21 CX3_GPIO51 22 VCCIO Base board IO voltage
CX3
23 CAM_CX3_I2C_SCL I2C's serial clock 24 CAM_CX3_I2C_SDA I2C's serial data

25 GND Ground 26 GND Ground

Table 8.3. Expansion Header Pin-Out

**Highlighted GPIOs are shared in both the MIPI (CN10) and the GPIO Header (CN8).

8.5 RS232-DB9 CONNECTOR (CN3)

The four-wire UART signals (TX, RX, RTS and CTS) from CX3, level translated to RS232 standard are
terminated at DB9 connector. This RS232 port can be used as a debug port by connecting to a PC.

8.6 JTAG HEADER (CN4)

CX3's JTAG interface provides a standard five-pin interface for connecting to a JTAG debugger. The JTAG
circuit on the RDK board provides an option to debug the firmware through the CPU core's on-chip debug
circuitry. The CX3 RDK board provides a 20-pin connector (CN4) for the JTAG debugger that encompasses
the standard JTAG interface signals.

For details on how to perform JTAG configuration and debugging, refer to the Cypress FX3/CX3
programmer’s manual. The document can be downloaded from the SDK webpage. Figure 8.5 shows the
circuit diagram of schematic connections.

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 Figure 8.5. JTAG Connections Circuit Diagram

8.7 BOOT MODE SWITCH (SW5)

The EZ-USB CX3 RDK provides several boot options. The firmware to be loaded on CX3 can be selected
from various available sources. The boot option is determined by the PMODE[2:0] input pins. The
PMODE[2:0] pins can be configured using the combination of the three-positions SPST switch (SW5).

The RDK board is designed with a combination of appropriate resistors and the SPST Switch (SW5) for
hassle-free boot-mode settings, as shown in Figure 8.6.

Figure 8.6. Boot Option Circuit diagram

Table 8.4 provides the list of boot interfaces supported on the CX3 device for the corresponding
PMODE[2:0] pins configuration.
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 PMODE2 PMODE1 PMODE0 BOOT MODE
Float 1 1 USB
Float 1 Float I2C, with USB fallback
0 Float 1 SPI, with USB fallback
Table 8.4. Boot Mode Settings

Figure 8.7 shows the PMODE switch (SW5) of the RDK board. Move SW5 to the ON position for ‘0’ or ‘1’
selection, and to the OFF position for float selection. The board is, by default, set to PMODE[2:0]=[0Z1]
(SPI Boot).

NOTE: Z indicates high-impedance state (Float).

Figure 8.7. CX3 RDK’s Boot Mode Switch

8.7.1 USB BOOT

In this mode, the firmware image is downloaded into CX3’s RAM through the USB host. The CX3RDK
board boots in USB mode if the PMODE[2:0] pins are set as[Z11].

DOWNLOADING THE FIRMWARE IMAGE TO CX3 RAM

Follow the procedure outlined here to download the firmware image to CX3 RAM.
1. Enable USB boot by setting the PMODE[2:0] pins to [Z11] as shown in Table 8.5.

PMODE PINS REQUIRED STATE SW5 - SETTINGS

PMODE0 1 Set to SW5.4(ON position)
PMODE1 1 Set to SW5.5(ON position)
PMODE2 FLOAT Set to SW5.3(OFF position)
Table 8.5. USB Boot Mode Settings

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 PMODE[0]

PMODE[2]
PMODE[1]

PMODE[2]

Figure 8.8. USB Boot Mode Settings

2. When connected to a USB host, the CX3 device enumerates in the Cypress USB Control
Center**as "Cypress USBBootloader".
3. In the Control Center, select Program >FX3> RAM.
4. Browse to the firmware image (.img) path to be programmed into the CX3 RAM. Double-click
the .img file.
5. A Programming Succeeded message is displayed on the bottom left pane of the Control Center
and the CX3 device re-enumerates with the programmed firmware.

**Refer to Cypress documentation for information on the USB Control Center on the Cypress website.

8.7.2 I2C BOOT

In this mode, the firmware image is downloaded onto an external I2C EEPROM and on reset, the
bootloader executes the firmware over I2C. The board boots from the EEPROM if the PMODE [2:0] pins are
set as [Z1Z].

DOWNLOADING THE FIRMWARE IMAGE TO THE I2C EEPROM

Follow the procedure outlined here to download the firmware image to I2C EEPROM:
1. Enable USB boot by setting the PMODE[2:0] pins to [Z11], as shown in Table 8.5.
2. Connect the RDK to a PC host using the USB3.0 cable. The CX3 device enumerates in the Control
Center as Cypress USB Bootloader.
3. Select the CX3 device and choose Program >FX3 >I2C EEPROM. The CX3 device re-enumerates
as Cypress USB BootProgrammer.
4. Browse to the relevant firmware binary to be loaded on the EEPROM when prompted by the
Control Center.
NOTE: Before downloading, verify the firmware and EEPROM size and also ensure that the
address signals of the EEPROM are configured correctly.
5. The bottom left corner of the window displays Programming of I2C EEPROM Succeeded once
programming is completed.

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BOOTING FROM I2C EEPROM

Change the PMODE[2:0] pins on the CX3_RDK board to [Z1Z] to enable I2C boot, as shown in Table 8.6.
This is realized by moving the appropriate switches on SW5. Power on the board or press the RESET
button (SW4). The CX3_RDK board re-enumerates with the boot image in I2C EEPROM.

PMODE PINS REQUIRED STATE SW5 SETTINGS

PMODE0 FLOAT Set to SW5.1 (OFF position)
PMODE1 1 Set to SW5.5 (ON position)
PMODE2 FLOAT Set to SW5.3 (OFF position)
Table 8.6. I2C Boot Mode Settings

PMODE[0]

PMODE[1]

PMODE[2]

Figure 8.9. I2C Boot Mode Settings

I2C EEPROM CONFIGURATION:

The typical EEPROM consists of three address lines: A2, A1, and A0. Therefore, the CX3 RDK can address
up to eight EEPROM devices by using all possible combinations of the address lines (000-111). If the
firmware image size is less than the EEPROM size, then the corresponding address lines can be pulled
low/high. If the firmware size exceeds the EEPROM size, multiple EEPROMs can be cascaded with
sequential address lines assigned to them. The address selection can be done by mounting appropriate
resistors on the address input pins.

The CX3 RDK utilizes the ATMEL, AT24CM01 EEPROM for storing the firmware image. Atmel EEPROMs
use A2 and A1 for chip select and A0 is unused. Hence a maximum of four EEPROM devices can be
interfaced for firmware storage. In this RDK, two EEPROMs (U15 and U16) are interfaced and their
address lines are fixed in the schematics.

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 Figure 8.10. CX3 RDK I2C EEPROM Circuit

About AT24CM01

AT24CM01 is an I2C-compatible EEPROM. See Table 8.7 for specifications.

PROPERTY VALUE
Memory 1Mbit (131,072X8)
Clock Frequency, SCL 1000 KHz (max)
Table 8.7. AT24CM01 Specifications

Figure 8.11. ATMEL’s AT24C1024B Pin-Out

The address ranges are indicated in Table 8.8.

DEVICE NO ADDRESS RANGE A2 A1 A0 SIZE

1 0x00000 – 0x1FFFF 0 0 NC 128 KB
2 0x20000 – 0x3FFFF 0 1 NC 128 KB
Table 8.8. EEPROM Address Range
NOTE: NC- No Connection

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8.7.3 SPI BOOT
CX3 boots from SPI Flash/EEPROM devices through a four-wire SPI interface. CX3’s firmware image is
programmed onto an external SPI Flash or SPI EEPROM. On reset, CX3’s bootloader executes the firmware
over SPI. SPI Flash/EEPROM devices from 1 Kb to 32 Mb in size are supported for boot.

In this mode, the firmware image is downloaded onto an external SPI Flash. On reset, the bootloader
downloads the firmware over SPI. The board boots from Flash if the PMODE [2:0] pins are set as [0Z1].

DOWNLOADING THE FIRMWARE IMAGE TO SPI FLASH

Follow these steps to download the firmware into flash.

1. Enable USB boot by setting the PMODE[2:0] pins to [Z11] as shown in Table 8.5.
2. Connect the RDK to a PC host using the USB3.0 cable. The CX3 device enumerates in the Control
Center as Cypress USB Bootloader.
3. Select the CX3 device and choose PROGRAM > FX3 > SPI FLASH from the Control Center menu.
The CX3_RDK board re-enumerates as Cypress USB BootProgrammer.
4. Browse to the relevant firmware binary (.img), wait the prompt from Control Center, and select
the image.
5. The application then starts downloading the firmware to the flash memory. The bottom left
corner of the window displays Programming of SPI FLASH Succeeded once programming has
completed.

BOOTING FROM SPI FLASH:

After the firmware is programmed onto the SPI flash, change the PMODE[2:0] pins to [0Z1]. On the
CX3_RDK board, this is done using the configurations shown in Table 8.9.

PMODE PINS REQUIRED STATE SW5 SETTINGS

PMODE0 1 SET TO SW5.4 (ON position)
PMODE1 FLOAT SET TO SW5.2 (OFF position)
PMODE2 0 SET TO SW5.6 (ON position)
Table 8.9. SPI Boot Mode Settings

PMODE[0]

PMODE[1]

PMODE[2]

Figure 8.12. SPI Boot Mode Settings

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ABOUT CX3_RDK’S SPI FLASH:

The on-board flash on the CX3_RDK is Micron’s M25P40-VMN6TPB. It has 4 MB of flash memory and is SPI
serial bus compatible. It has write protect and hold pins that are hardware configurable. Options are fixed
for these pins on the CX3 RDK schematics.

Figure 8.13. CX3 RDK SPI Flash Circuit

8.8 CLOCK SCHEME OF THE CX3 RDK

The EZ-USB CX3 controller requires three clocks for normal operation.

 19.2 MHZ clock for Clock Input.

 19.2 MHZ clock as a reference clock.
 32.768 KHz clock is required for the watchdog timer.

The on-board 19.2 MHz clock is provided as an input for both the clock input and the reference. Table 8.10
provides the pin-out along with the clock frequencies applied.

CX3 PIN NO FUNCTION FREQUENCY

D6 CLKIN_32 32.768 KHZ
F2 REFCLK 19.2 MHZ.
D7 CLKIN 19.2 MHZ.
Table 8.10. Clock Signals

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Table 8.11 lists the oscillator components on the CX3_RDK.

PART
CLOCK FREQUENCY MANUFACTURING PART NO
REFERENCE
19.2 MHz Y2 KC5032A19.2000CM0E00
32.768KHz Y1 SG-3030LC 32.7680KB3: PURE SN
Table 8.11. CX3 RDK Clock

8.9 RESET SCHEME OF THE CX3 RDK

A supervisory IC from TI (TPS3808G01 - U22) is employed for the reset. It asserts an active low reset to
CX3 when either the SENSE or MR pins of the IC fall below the threshold voltage. The on-board push
button switch (SW4) is connected to the MR (Manual Reset) pin of TPS3808.

The external image sensor can be reset through the XRST (PIN F4) of the CX3 controller. The reset signal
for the image sensor is available on pin 31 of the MIPI Camera board connector (CN10).

9. MECHANICAL SPECIFICATION
The mechanical dimensions of the CX3 RDK are shown in Figure 9.1.
All dimensions are in millimeters.

Figure 9.1. CX3 RDK Mechanical Dimensions

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10. ASSEMBLY DRAWING
Figures 10.1 and 10.2 display the top and bottom assembly drawings of the CX3_RDK.

Figure 10.1. CX3 RDK – Assembly Top

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 Figure 10.2. CX3 RDK – Assembly Bottom

11. LEARN MORE AT

 Visit www.cypress.com/cx3 for additional learning resources, such as datasheets, the technical
reference manual, and application notes.
 Visit http://www.e-consystems.com/CX3-Reference-Design-Kit.asp for the latest information
about this kit and its documentation.

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