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Verilog Posts

Introduction

 What is Verilog?

 Introduction to Verilog

 Chip Design Flow

 Chip Abstraction Layers

Data Types

 Verilog Syntax

 Verilog Data types

 Verilog Scalar/Vector

 Verilog Arrays

Building Blocks

 Verilog Module

 Verilog Port

 Verilog Module Instantiations

 Verilog assign statements

 Verilog assign examples

 Verilog Operators

 Verilog Concatenation

 Verilog always block

 Combo Logic with always

 Sequential Logic with always

 Verilog initial block

 Verilog in a nutshell

 Verilog generate

Behavioral modeling

 Verilog Block Statements

 Verilog Assignment Types

 Verilog Blocking/Non-blocking

 Verilog Control Flow

 Verilog if-else-if

 Verilog Conditional Statements

 Verilog for Loop

 Verilog case Statement

 Verilog Functions

 Verilog Tasks

 Verilog Parameters

 Verilog `ifdef `elsif

 Verilog Delay Control

 Verilog Inter/Intra Delay

 Verilog Hierarchical Reference

 Verilog Coding Style Effect

Gate/Switch modeling

 Gate Level Modeling

 Gate Level Examples

 Gate Delays

 Switch Level Modeling

 User-Defined Primitives

Simulation

 Verilog Simulation Basics

 Verilog Testbench

 Verilog Timescale

 Verilog Scheduling Regions

 Verilog Clock Generator

System Tasks and Functions

 Verilog Display tasks

 Verilog Math Functions

 Verilog Timeformat

 Verilog Timescale Scope

 Verilog File Operations

Code Examples

 Hello World!

 Flops and Latches

 JK Flip-Flop

 D Flip-Flop

 T Flip-Flop

 D Latch
 Counters

 4-bit counter

 Ripple Counter

 Straight Ring Counter

 Johnson Counter

 Mod-N Counter

 Gray Counter

 Misc

 n-bit Shift Register

 Binary to Gray Converter

 Priority Encoder

 4x1 multiplexer

 Full adder

 Single Port RAM

 Verilog Pattern Detector

 Verilog Sequence Detector

Verilog syntax

1. Comments
2. Whitespace
3. Operators
4. Number Format
1. Sized
2. Unsized
3. Negative
5. Strings
6. Identifiers
7. Keywords
 8. Verilog Revisions

Lexical conventions in Verilog are similar to C in the sense that it

contains a stream of tokens. A lexical token may consist of one
or more characters and tokens can be comments, keywords,
numbers, strings or white space. All lines should be terminated
by a semi-colon ; .

Verilog is case-sensitive, so var_a and var_A are different.

Comments

There are two ways to write comments in Verilog.

1. A single line comment starts with // and tells Verilog

compiler to treat everything after this point to the end of
the line as a comment.
2. A multiple-line comment starts with /* and ends with
*/ and cannot be nested.

However, single line comments can be nested in a multiple line

comment.
 1 // This is a single line comment
2
3 integer a; // Creates an int variable called a,
4
5 /*
6 This is a
7 multiple-line or
8 block comment
9 */
10
11 /* This is /*
12 an invalid nested
13 block comment */
14 */
15
16 /* However,
17 // this one is okay
18 */
19
20 // This is also okay
21 ///////////// Still okay

Whitespace

White space is a term used to represent the characters for

spaces, tabs, newlines and formfeeds, and is usually ignored by
Verilog except when it separates tokens. In fact, this helps in the
indentation of code to make it easier to read.

module dut; // 'module' is a keyword,

// 'dut' is an identifie
reg [8*6:1] name = "Hello!"; // The 2 spaces in

However blanks(spaces) and tabs (from TAB key) are not ignored
in strings. In the example below, the string variable called addr
gets the value "Earth " because of preservation of spaces in
strings.

// There is no space in the beginning of this li

// but there's a space in the string
reg [8*6:1] addr = "Earth ";
endmodule
Operators

There are three types of operators: unary, binary, and ternary or

conditional.

Unary operators shall appear to the left of their operand

Binary operators shall appear between their operands
Conditional operators have two separate operators that
separate three operands

1 x = ~y; // ~ is a unary operator,

2 x = y | z; // | is a binary operator,
3 x = (y > 5) ? w : z; // ?: is a ternary operato

If the expression (y > 5) is true, then variable x will get the value
in w, else the value in z.

Number Format

We are most familiar with numbers being represented as

decimals. However, numbers can also be represented in binary,
octal and hexadecimal. By default, Verilog simulators treat
numbers as decimals. In order to represent them in a different
radix, certain rules have to be followed.

16 // Number 16 in decimal
0x10 // Number 16 in hexadecimal
10000 // Number 16 in binary
20 // Number 16 in octal

Sized

Sized numbers are represented as shown below, where size is

written only in decimal to specify the number of bits in the
number.

1 [size]'[base_format][number]

base_format can be either decimal ('d or 'D), hexadecimal

('h or 'H) and octal ('o or 'O) and specifies what base the
number part represents.
 number is specified as consecutive digits from 0, 1, 2 ... 9 for
decimal base format and 0, 1, 2 .. 9, A, B, C, D, E, F for
hexadecimal.

3'b010; // size is 3, base format is binary ('b

3'd2; // size is 3, base format is decimal (
8'h70; // size is 8, base format is hexadecima
9'h1FA; // size is 9, base format is hexadecima

4'hA = 4'd10 = 4'b1010 = 4'o12 // Decimal 10 can be

8'd234 = 8'D234 // Legal to use e
32'hFACE_47B2; // Underscore (_)

Uppercase letters are legal for number specification when

the base format is hexadecimal.

16'hcafe; // lowercase letters Valid

16'hCAFE; // uppercase letters Valid
32'h1D40_CAFE; // underscore can be used as sepa

Unsized

Numbers without a base_format specification are decimal

numbers by default. Numbers without a size specification have a
default number of bits depending on the type of simulator and
machine.

1 integer a = 5423; // base format is not spe

2 integer a = 'h1AD7; // size is not specified,

Negative

Negative numbers are specified by placing a minus - sign

before the size of a number. It is illegal to have a minus sign
between base_format and number.

-6'd3; // 8-bit negative number stored

-6'sd9; // For signed maths
8'd-4; // Illegal
Strings

A sequence of characters enclosed in a double quote " " is

called a string. It cannot be split into multiple lines and every
character in the string take 1-byte to be stored.

"Hello World!" // String with 12 characters

"x + z" // String with 5 characters

"How are you

feeling today ?" // Illegal for a string to be

Identifiers

Identifiers are names of variables so that they can be referenced

later on. They are made up of alphanumeric characters
[a-z][A-Z][0-9] , underscores _ or dollar sign $ and
are case sensitive. They cannot start with a digit or a dollar sign.

integer var_a; // Identifier contains alphab

integer $var_a; // Identifier starts with $ -
integer v$ar_a; // Identifier contains alphab
integer 2var; // Identifier starts with a
integer var23_g; // Identifier contains alphan
integer 23; // Identifier contains only

Keywords

Keywords are special identifiers reserved to define the language

constructs and are in lower case. A list of important keywords is
given below.
Verilog Revisions

Verilog has undergone a few revisions over the years and more
additions have been made from 1995 to 2001 which is shown
below.
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 Interview Questions

 Verilog Interview Set 1

 Verilog Interview Set 2

 Verilog Interview Set 3

 Verilog Interview Set 4

 Verilog Interview Set 5

 Verilog Interview Set 6

 Verilog Interview Set 7

 Verilog Interview Set 8

 Verilog Interview Set 9

 Verilog Interview Set 10

 Related Topics

 Digital Fundamentals

 Verilog Tutorial

 Verification

 SystemVerilog Tutorial

 UVM Tutorial

Verilog Testbench

Verilog Coding Style Effect

Verilog Conditional Statements

 Verilog Interview Set 10

Synchronous FIFO

SystemVerilog Interview Set 10

SystemVerilog Interview Set 9

SystemVerilog Interview Set 8

SystemVerilog Interview Set 7

SystemVerilog Interview Set 6

UVM Singleton Object

UVM Component [uvm_component]

UVM Object [uvm_object]

UVM Root [uvm_root]

UVM Interview Set 4

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