EEE415-Week03-Assembly Language Programming
EEE415-Week03-Assembly Language Programming
Week 3
1
DRAFT 6/17/2023
Branching
• Branches enable out of sequence instruction execution
• Types of branches:
• Branch (B)
– branches to another instruction
• Branch and link (BL)
– discussed later
• Both can be conditional or unconditional
2
DRAFT 6/17/2023
TARGET
SUB R1, R1, #78 ; R1 = R1 + 78
TARGET
SUB R1, R1, #78 ; R1 = R1 + 78
3
DRAFT 6/17/2023
4
DRAFT 6/17/2023
if Statement
C Code
if (i == j)
f = g + h;
f = f – i;
if Statement
C Code ARM Assembly Code
;R0=f, R1=g, R2=h, R3=i, R4=j
L1
f = f – i; SUB R0, R0, R2 ; f = f - i
10
5
DRAFT 6/17/2023
if Statement
C Code ARM Assembly Code
;R0=f, R1=g, R2=h, R3=i, R4=j
L1
f = f – i; SUB R0, R0, R2 ; f = f - i
11
12
6
DRAFT 6/17/2023
13
if/else Statement
14
7
DRAFT 6/17/2023
15
16
8
DRAFT 6/17/2023
CMP R0, R1
BLT ELSE
ADD R0, R0, R1
B DONE
ELSE SUB R0, R0, R1
DONE
17
CMP R0, R1
BLT ELSE
ADD R0, R0, R1
B DONE
ELSE SUB R0, R0, R1
DONE
CMP R0, R1
ADDGE R0, R0, R1
SUBLT R0, R0, R1
Dr. Sajid Muhaimin Choudhury 18
EEE 415 - Department of EEE, BUET Digital Design and Computer Architecture: ARM® Edition © 2015
18
9
DRAFT 6/17/2023
while Loops
C Code ARM Assembly Code
// determines the power ; R0 = pow, R1 = x
// of x such that 2x = 128 MOV R0, #1 ; pow = 1
int pow = 1; MOV R1, #0 ; x = 0
int x = 0;
WHILE
CMP R0, #128 ; R0-128
while (pow != 128) { BEQ DONE ; if (pow==128)
; exit loop
pow = pow * 2; LSL R0, R0, #1 ; pow=pow*2
x = x + 1; ADD R1, R1, #1 ; x=x+1
} B WHILE ; repeat loop
DONE
19
for Loops
for (initialization; condition; loop operation)
statement
20
10
DRAFT 6/17/2023
for Loops
C Code ARM Assembly Code
// adds numbers from 1-9 ; R0 = i, R1 = sum
int sum = 0 MOV R0, #1 ; i = 1
MOV R1, #0 ; sum = 0
DONE
21
22
11
DRAFT 6/17/2023
23
Arrays
• Access large amounts of similar data
Index: access to each element
Size: number of elements
24
12
DRAFT 6/17/2023
Arrays
• 5-element array
Base address = 0x14000000 (address of first
element, scores[0])
Array elements accessed relative to base address
25
Accessing Arrays
C Code
int array[5];
array[0] = array[0] * 8;
array[1] = array[1] * 8;
26
13
DRAFT 6/17/2023
27
FOR
LDR R2, [R0, R1, LSL #2] ; R2 = array(i)
LSL R2, R2, #3 ; R2 = R2<<3 = R3*8
STR R2, [R0, R1, LSL #2] ; array(i) = R2
SUBS R1, R1, #1 ; i = i – 1
; and set flags
decreament er BPL
khetrei
FOR
normally ; if (i>=0) repeat loop
Dr. Sajid Muhaimin Choudhury 28
EEEkomano
evabe instruction lines 415 - Department
easy hoy of EEE, BUET Digital Design and Computer Architecture: ARM® Edition © 2015
28
14
DRAFT 6/17/2023
Memory
array thakle
memory base
address declare
kore dite hobe
Instead of the LSL and LDR instruction sequence in Code Example 6.18, we can use a single instruction:
LDR R3, [R0, R1, LSL #2]
R1 is scaled (shifted left by two) then added to the base address (R0). Thus, the memory address is R0 + (R1 × 4)
29
Memory
• In addition to scaling the index register, ARM provides offset, pre- indexed, and post-
indexed addressing to enable dense and efficient code for array accesses and function
calls.
In each case, the base register is R1 and the offset is R2. The offset can be subtracted by writing –R2.
The offset may also be an immediate in the range of 0–4095 that can be added (e.g., #20) or
subtracted (e.g., #-20)
30
15
DRAFT 6/17/2023
Memory
• Code Example 6.19 shows the for loop from Code Example 6.18
rewritten to use post-indexing, eliminating the ADD to increment i.
31
Memory
• ARM provides load byte (LDRB), load signed byte (LDRSB), and store byte
(STRB) to access individual bytes in memory.
• LDRB zero-extends the byte, whereas LDRSB sign-extends the byte to fill the
entire 32-bit register. STRB stores the least significant byte of the 32-bit
register into the specified byte address in memory.
32
16
DRAFT 6/17/2023
Week 3
33
ASCII Encoding
34
17
DRAFT 6/17/2023
Related to ASCII
encoding
35
36
18
DRAFT 6/17/2023
37
38
19
DRAFT 6/17/2023
39
5 instructions
3 instructions
40
20
DRAFT 6/17/2023
41
Function Calls
• Caller: calling function (in this case, main)
• Callee: called function (in this case, sum)
C Code
void main()
{
int y;
y = sum(42, 7);
...
}
42
21
DRAFT 6/17/2023
Function Conventions
• Caller:
• passes arguments to callee
• jumps to callee
43
Function Conventions
• Caller:
• passes arguments to callee
• jumps to callee
• Callee:
• performs the function
• returns result to caller
• returns to point of call
• must not overwrite registers or memory needed by caller
44
22
DRAFT 6/17/2023
45
Function Calls
C Code ARM Assembly Code
int main() { 0x00000200 MAIN BL SIMPLE
simple(); 0x00000204 ADD R4, R5, R6
a = b + c; ...
}
0x00401020 SIMPLE MOV PC, LR
void simple() {
return;
}
46
23
DRAFT 6/17/2023
Function Calls
C Code ARM Assembly Code
int main() { 0x00000200 MAIN BL SIMPLE
simple(); 0x00000204 ADD R4, R5, R6
a = b + c; ...
}
0x00401020 SIMPLE MOV PC, LR
void simple() {
return;
}
BL branches to SIMPLE
LR = PC + 4 = 0x00000204
MOV PC, LR makes PC = LR
(the next instruction executed is at 0x00000200)
47
48
24
DRAFT 6/17/2023
49
50
25
DRAFT 6/17/2023
51
The Stack
• Memory used to temporarily
save variables
• Like stack of dishes, last-in-
first-out (LIFO) queue
• Expands: uses more memory
when more space needed
• Contracts: uses less memory
when the space no longer
needed
Dr. Sajid Muhaimin Choudhury 52
EEE 415 - Department of EEE, BUET Digital Design and Computer Architecture: ARM® Edition © 2015
52
26
DRAFT 6/17/2023
The Stack
• Grows down (from higher to lower memory
addresses)
• Stack pointer: SP points to top of the stack
53
54
27
DRAFT 6/17/2023
55
56
28
DRAFT 6/17/2023
57
58
29
DRAFT 6/17/2023
R4-R11 R12
59
60
30
DRAFT 6/17/2023
https://developer.arm.com/documentation/dui0552/a/the-cortex-m3-instruction-set/memory-access-instructions/push-and-pop
Dr. Sajid Muhaimin Choudhury 61
EEE 415 - Department of EEE, BUET Digital Design and Computer Architecture: ARM® Edition © 2015
61
62
31
DRAFT 6/17/2023
63
important
64
32
DRAFT 6/17/2023
65
66
33
DRAFT 6/17/2023
67
Week 3
68
34
DRAFT 6/17/2023
69
Preserving Registers
• Caller save rule: Before a function call, the caller must save any non-preserved registers
(R0–R3 and R12) that it needs after the call. After the call, it must restore these
registers before using them.
• Callee save rule: Before a callee disturbs any of the preserved registers (R4–R11 and LR),
it must save the registers. Before it returns, it must restore these registers.
70
35
DRAFT 6/17/2023
71
72
36
DRAFT 6/17/2023
73
Recursive Function
• A recursive function is a nonleaf function that calls itself. Recursive functions
behave as both caller and callee and must save both preserved and
nonpreserved registers.
• Example:
74
37
DRAFT 6/17/2023
75
76
38
DRAFT 6/17/2023
77
78
39
DRAFT 6/17/2023
• Callee
• Saves registers that might be disturbed (R4-R7)
• Performs function
• Puts result in R0
• Restores registers
• Returns: MOV PC, LR
79
80
40
DRAFT 6/17/2023
81
82
41
DRAFT 6/17/2023
83
84
42
DRAFT 6/17/2023
; R1 = result; R2 = prevresult
BBB MOV R1, #1 ; R1 = result = fib(0)
MOV R2, #0 ; R2 = prevresult = fib(-1)
CMP R0, #0 ; n == 0?
BEQ DONE
LOOP
ADD R1, R1, R2 ; result = result + prevresult
SUB R2, R1, R2 ; prevresult = result – prevresult
SUBS R0, R0, #1 ; n = n - 1
BPL LOOP
DONE
MOV R0, R2 ; return result
MOV PC, LR
END
Dr. Sajid Muhaimin Choudhury 85
EEE 415 - Department of EEE, BUET Digital Design and Computer Architecture: ARM® Edition © 2015
85
R0 = 55
86
43
DRAFT 6/17/2023
87
88
44
DRAFT 6/17/2023
89
90
45
DRAFT 6/17/2023
91
92
46
DRAFT 6/17/2023
93
94
47
DRAFT 6/17/2023
95
48