ARMv7 Quick Reference Bitwise and Move Instructions Load and Store Instructions

AND{S} rx, ry, op2 rx = ry & op2 LDMDA rx{!}, rlist rlist = [rx−4×cnt+4]; if(!) rx−=4×cnt A
Arithmetic Instructions ASR{S} rx, ry, #j5 ¯ j
rx = ry  LDMDB rx{!}, rlist rlist = [rx − 4×cnt]; if(!) rx−=4×cnt
ADC{S} rx, ry, op2 rx = ry + op2 + C ASR{S} rx, ry, Rs ¯ Rs
rx = ry  LDMIA rx{!}, rlist rlist = [rx]; if(!) rx += 4×cnt
ADD{S} rx, ry, op2 rx = ry + op2 BFC rx, #p, #n rxp+n−1:p = 0n 6t LDMIB rx{!}, rlist rlist = [rx + 4]; if(!) rx += 4×cnt A
ADDW rx, ry, #i12 rx = ry + i∅ T BFI rx, ry, #p, #n rxp+n−1:p = ryn−1:0 6t LDR{T} rx, [addr] rx = [addr]
ADR rx, ±rel12 rx = PC ± rel BIC{S} rx, ry, op2 rx = ry & ∼op2 LDRB{T} rx, [addr] rx = [addr]∅8
CMN rx, op2 rx + op2 CLZ rx, ry rx = CountLeadingZeros(ry) LDRD rx, ry, [addr] ry:rx = [addr]
CMP rx, op2 rx − op2 EOR{S} rx, ry, op2 rx = ry ⊕ op2 LDRH{T} rx, [addr] rx = [addr]∅16
QADD rx, ry, rz rx = SATS(ry + rz, 32) D LSL{S} rx, ry, #i5 rx = ry  i LDRSB{T} rx, [addr] rx = [addr]±
8
QDADD rx, ry, rz rx = SATS(ry + SATS(2×rz, 32), 32) D LSL{S} rx, ry, Rs rx = ry  Rs LDRSH{T} rx, [addr] rx = [addr]±
16
QDSUB rx, ry, rz rx = SATS(ry − SATS(2×rz, 32), 32) D LSR{S} rx, ry, #j5 rx = ry  j POP rlist rlist = [SP]; SP += 4×cnt
QSUB rx, ry, rz rx = SATS(ry − rz, 32) D LSR{S} rx, ry, Rs rx = ry  Rs PUSH rlist SP −= 4×cnt; [SP] = rlist
RSB{S} rx, ry, op2 rx = op2 − ry MOV{S} rx, op2 rx = op2 STMDA rx{!}, rlist [rx−4×cnt+4] = rlist; if(!) rx−=4×cnt A
RSC{S} rx, ry, op2 rx = op2 − (ry + C) A MOVT rx, #i16 rx31:16 = i 6t STMDB rx{!}, rlist [rx − 4×cnt] = rlist; if(!) rx−=4×cnt
SBC{S} rx, ry, op2 rx = ry − (op2 + C) MOVW rx, #i16 rx = i∅ STMIA rx{!}, rlist [rx] = rlist; if(!) rx += 4×cnt
SDIV rx, ry, rz ¯ rz
rx = ry ÷ 7 MVN{S} rx, op2 rx = ∼op2 STMIB rx{!}, rlist [rx+4] = rlist; if(!) rx += 4×cnt A
SSAT rx, #j5 , ry{slr} rx = SATS(ry   ¯ sh, j)± 6 ORN{S} rx, ry, op2 rx = ry | ∼op2 T STR{T} rx, [addr] [addr] = rx
SSAT16 rx, #j4 , ry rx = SATS(ry± ± ±
H1 , j) :SATS(ryH0 , j)
±
6,D ORR{S} rx, ry, op2 rx = ry | op2 STRB{T} rx, [addr] [addr]8 = rxB0
SUB{S} rx, ry, op2 rx = ry − op2 RBIT rx, ry rx = ReverseBits(ry) 6t STRD rx, ry, [addr] [addr] = ry:rx
SUBW rx, ry, #i12 rx = ry − i∅ T REV rx, ry rx = ryB0 :ryB1 :ryB2 :ryB3 6 STRH{T} rx, [addr] [addr]16 = rxH0
UDIV rx, ry, rz rx = ry ÷ rz 7 REV16 rx, ry rx = ryB2 :ryB3 :ryB0 :ryB1 6
rx = 3n=0 (ABS(ry∅Bn )−rz∅Bn )
P
USAD8 rx, ry, rz 6,D REVSH rx, ry rx = ry±
B0 :ryB1 6 ARM LDR/STR Addressing Modes
rx = rw + 3n=0 (ABS(ry∅Bn )−rz∅Bn ) [rz{, #±i8 }]{!} addr = rz ± i; if(!) rz = addr
P
USADA8 rx, ry, rz, rw 6,D ROR{S} rx, ry, #i5 rx = ry ≫ i non-T
USAT rx, #j5 , ry{slr} rx = SATU(ry  ¯ sh, j)± 6 ROR{S} rx, ry, Rs rx = ry ≫ Rs xxR{,B} [rz{, #±i12 }]{!} addr = rz ± i; if(!) rz = addr
USAT16 rx, #i4 , ry rx = SATU(ry± ± ±
H1 , i) :SATU(ryH0 , i)
±
6,D RRX{S} rx, ry rx = C:ry31:1 ; C = ry0 any [rz]{, #±i8 } addr = rz; rz ±= i

rx = ry± xxR{,B}{T} [rz], #±i12 addr = rz; rz ±= i

SBFX rx, ry, #p, #n p+n−1:p 6t
Operand 2 non-T [rz, ±rw]{!} addr = rz ± rw; if(!) rz = addr
TEQ rx, op2 rx ⊕ op2
#i32 i8 ≫ i4 :0 A xxR{,B} [rz, ±rw{AS}]{!} addr = rz ± AS(rw); if(!) rz = addr
TST rx, op2 rx & op2
#i32 024 :i8 , 08 :i8 08 :i8 , i8 :08 i8 :08 or i8 :i8 i8 :i8 T any [rz], ±rw addr = rz; rz ±= rw
UBFX rx, ry, #p, #n rx = ry∅p+n−1:p 6t
#i32 1:i7  {1..24} T xxR{,B}{T} [rz], ±rw{AS} addr = rz; rz ±= AS(rw)
rz rz Branch and Jump Instructions LD non-T ±rel8 addr = PC ± rel
LDR{,B} ±rel12 addr = PC ± rel
rz, LSL #n rz  {1..31} B rel26 PC = PC + rel±25:2 :01:0 A
rz, LSR #n rz  {1..32} B rel25 PC = PC + rel±24:1 :0 T
Thumb2 LDR/STR Addressing Modes
¯ {1..32}
rz, ASR #n rz  if(cc) PC = PC + rel±
Bcc rel21 20:1 :0 I
any [rz{, #i8 }] addr = rz + i
rz, ROR #n rz ≫ {1..31} BKPT #i16 BreakPoint(i) I
xxR{,B,H,SB,SH} [rz, #i12 ] addr = rz + i
rz, RRX C:rz31:1 ; C = rz0 BL rel26 LR=PC31:1 :0; PC+=rel±
25:2 :01:0 A
xxR{,B,H,SB,SH} [rz, #±i8 ]{!} addr = rz ± i; if(!) rz = addr
rz, LSL rw rz  rw A BL rel25 LR=PC31:1 :1; PC+=rel±
24:1 :0 T xxR{,B,H,SB,SH} [rz], #±i8 addr = rz; rz ±= i
rz, LSR rw rz  rw A BLX rel26 LR=PC31:1 :0; Set=1; PC+=rel±
25:1 :0 A xxR{,B,H,SB,SH} [rz,rw{,LSL #i2 }] addr = rz + rw  i
rz, ASR rw ¯ rw
rz  A LR=PC31:1 :1; Set=0; PC+=rel±
BLX rel25 24:2 :01:0 T LDR{,B,H,SB,SH} ±rel12 addr = PC ± rel
rz, ROR rw rz ≫ rw A BLX rx LR=PC31:1 :0; Set=rx0 ; PC=rx31:1 :0 A xxRD [rz{, #±i10 }]{!} addr=rz±i9:2 :01:0 ; if(!) rz=addr
BX rx Set = rx0 ; PC = rx31:1 :0 A xxRD [rz], #±i10 addr = rz; rz ±= i±
9:2 :01:0
TBB [rx, ry] PC = PC + 2 × [rx + ry]∅8 T LDRD ±rel10 addr = PC ± rel9:2 :01:0
TBH [rx, ry, LSL #1] PC = PC + 2 × [rx + 2 × ry]∅16 T

ARMv7 version 8 page 1

Multiplication Instructions Packing and Unpacking Instructions Special Instructions
MLA rx, ry, rz, rw rx = rw + ry × rz PKHBT rx, ry, rz{sl} rx = (rz  sh)H1 :ryH0 6,D DBG #i4 DebugHint(i) 7
MLA{S} rx, ry, rz, rw rx = rw + ry × rz A PKHTB rx, ry, rz{sr} ¯ sh)H0
rx = ryH1 :(rz  6,D DMB option DataMemoryBarrier(option) I,7
MLS rx, ry, rz, rw rx = rw − ry × rz 6t SXTAB rx, ry, rz{rb} rx = ry + (rz ≫ sh)±
B0 6,D DSB option DataSynchronizationBarrier(option) I,7
MUL rx, ry, rz rx = ry × rz SXTAB16 rx, ry, rz{rb} for(n=0..1) rxHn =ryHn +(rz≫sh)±
B2n 6,D ISB SY InstructionSynchronizationBarrier(SY) I,7
MUL{S} rx, ry, rz rx = ry × rz A SXTAH rx, ry, rz{rb} rx = ry + (rz ≫ sh)±
H0 6,D NOP 6k
SMLAxy rx, ry, rz, rw rx = rw + ry± ¯ ±
Hx × rzHy D SXTB rx, ry{rb} rx = (ry ≫ sh)±
B0 6 PLD{W} [addr] PreloadData(addr)
SMLaD rx, ry, rz, rw rx = rw + ryH0 ×rzH0 ± ry±
± ¯ ± ¯ ±
H1 ×rzH1 6,D SXTB16 rx, ry{rb} for(n=0..1) rxHn = (ry ≫ sh)±
B2n 6,D PLI [addr] PreloadInstr(addr) 7
± ¯ ± ± ¯ ±
SMLaDX rx, ry, rz, rw rx = rw + ry ×rz ± ry ×rz
H0 H1 H1 H0 D SXTH rx, ry{rb} rx = (ry ≫ sh)±
H0 6 SETEND {BE/LE} EndianState = {BE/LE} I,6
SMLaLD rx, ry, rz, rw ry:rx += rz± ¯ ± ± ¯ ±
H0 ×rwH0 ± rzH1 ×rwH1 6,D UXTAB rx, ry, rz{rb} rx = ry + (rz ≫ sh)∅B0 6,D SEV SendEvent() 6k
SMLaLDX rx, ry, rz, rw ry:rx += rz± ¯ ± ± ¯ ±
H0 ×rwH1 ± rzH1 ×rwH0 D UXTAB16 rx, ry, rz{rb} for(n=0..1) rxHn =ryHn +(rz≫sh)∅B2n 6,D SVC #i24 CallSupervisor() A
SMLAL rx, ry, rz, rw ¯
ry:rx += rz × rw UXTAH rx, ry, rz{rb} rx = ry + (rz ≫ sh)∅H0 6,D UDF #i16 UndefinedException()
SMLAL{S} rx, ry, rz, rw ¯ rw
ry:rx += rz × A UXTB rx, ry{rb} rx = (ry ≫ sh)∅B0 6 WFE WaitForEvent() 6k
SMLALxy rx, ry, rz, rw ry:rx += rz± ׯ rw±
Hx Hy D UXTB16 rx, ry{rb} for(n=0..1) rxHn = (ry ≫ sh)∅B2n 6,D WFI WaitForInterrupt() 6k
SMLAWy rx, ry, rz, rw ¯ rz±
rx = rw + ry × D UXTH rx, ry{rb} rx = (ry ≫ sh)∅H0 6 YIELD HintYield() 6k
Hy
SMMLa rx, ry, rz, rw ¯ rz)63:32
rx = rw ± (ry × 6,D
SMMLaR rx, ry, rz, rw ¯ + 0x80000000)63:32
rx = rw ± (ry×rz D Exclusive Load and Store Instructions Keys
SMMUL rx, ry, rz ¯
rx = (ry × rz)63:32 6,D CLREX ClearExclusiveLocal() I,6k {S} Optional suffix, if present update flags
SMMULR rx, ry, rz ¯ rz + 0x80000000)63:32
rx = (ry × D LDREX rx, [ry] rx = [ry]; SetExclusiveMonitor 6k {t} Conditional for additional instructions (T or E)

SMUaD rx, ry, rz rx = ry± ׯ rz± ± ry± × ¯ rz± 6,D LDREX rx, [ry, #i10 ] rx = [ry+i∅9:2 :01:0 ]; SetExclusiveMonitor T,6k {T} LDR/STR instruction uses user privileges.
H0 H0 H1 H1
SMUaDX rx, ry, rz rx = ry± ¯
× rz± ± ry± ¯
× rz± D LDREXB rx, [ry] rx = [ry]∅8 ; SetExclusiveMonitor 6k a A or S to add or subtract operand.
H0 H1 H1 H0
ry:rx = [rz]; SetExclusiveMonitor x, y Selects bottom (B) or top (T) half of register(s)
SMULxy rx, ry, rz rx = ry±
Hx
¯
× rz±
Hy D LDREXD rx, ry, [rz] 6k
¯ rw LDREXH rx, [ry] rx = [ry]∅16 ; SetExclusiveMonitor 6k cc Condition code (can suffix most ARM instructions)
SMULL rx, ry, rz, rw ry:rx = rz ×
STREX rx,ry,[rz] if(Pass) [rz] = ry; rx = Pass ? 1 : 0 6k di DA, DB, IA or IB for decrease/increase before/after.
SMULL{S} rx, ry, rz, rw ¯ rw
ry:rx = rz × A
if(Pass) [rz+i∅9:2 :01:0 ]=ry; rx=Pass?1:0 i, j Immediate operand, range 0..max / 1..max+1
SMULWy rx, ry, rz ¯
rx = (ry × rz±
Hy )47:16 D STREX rx,ry,[rz,#i10 ] T,6k
if(Pass) [rz]8 = ryB0 ; rx = Pass?1:0 rx, ry, rz, rw General register
UMAAL rx, ry, rz, rw ry:rx = ry + rx + rz × rw D STREXB rx,ry,[rz] 6k
Rbanked Banked register
UMLAL rx, ry, rz, rw ry:rx += rz × rw STREXD rx,ry,rz,[rw] if(Pass) [rw] = rz:ry; rx = Pass?1:0 6k
rlist Comma separated list of registers within { }.
UMULL rx, ry, rz, rw ry:rx = rz × rw STREXH rx,ry,[rz] if(Pass) [rz]16 = ryH0 ; rx = Pass?1:0 6k
op2 Immediate or shifted register
System Instructions xPSR APSR, CPSR or SPSR
Parallel Instructions
SAT{S,U}(x,b) Saturated signed/unsigned b bit value
pADD16 rx, ry, rz for(n=0..1) rxHn = p(ryHn + rzHn ) 6,D CPSI{D,E} {aif}{, #mode} {a}{i}{f} = (E ? 1: 0); MODE = mode 6
B{0,1,2,3} Selected byte (bits 7:0, 15:8, 23:16 or 31:24)
pADD8 rx, ry, rz for(n=0..3) rxBn = p(ryBn + rzBn ) 6,D CPS #mode MODE = mode 6
H{0,1} Selected half word (bits 15:0 or 31:16)
pASX rx, ry, rz rx = p(ryH1 + rzH0 ):p(ryH0 − rzH1 ) 6,D ERET PC = LR; CPSR = SPSR 7
{rb} Optional rotate (ROR 8, ROR 16 or ROR 24)
pSAX rx, ry, rz rx = p(ryH1 − rzH0 ):p(ryH0 + rzH1 ) 6,D HVC #i16 CallHypervisor(i) 7
{slr} Optional shift (LSL #{1..31} or ASR #{1..32})
pSUB16 rx, ry, rz for(n=0..1) rxHn = p(ryHn − rzHn ) 6,D MRS rx, xPSR rx = {CPSR,SPSR}
{sl} Optional left shift (LSL #{1..31})
pSUB8 rx, ry, rz for(n=0..3) rxBn = p(ryBn − rzBn ) 6,D MRS rx, Rbanked rx = Rbanked 7
{sr} Optional right shift (ASR #{1..32})
SEL rx, ry, rz for(n=0..3) rxBn = (GEn ? ry : rz)Bn 6,D MSR xPSR, rx {CPSR,SPSR} = rx
{AS} ARM shift or rotate (LSL/ROR #{1..31}, LSR/ASR
MSR Rbanked, rx Rbanked = rx 7 #{1..32} or RRX)
Parallel Instruction Prefixes MSR xPSR {cxsf}, i {CPSR,SPSR}f;s;x;c = if;s;x;c A value± , value∅ Value is sign/zero extended
Q Signed operation, Results are saturated MSR xPSR {cxsf}, rx {CPSR,SPSR}f;s;x;c = rxf;s;x;c ¯ ÷
× ¯ 
¯ Operation is signed
S Signed operation, Results are truncated RFEdi rx{!} LDMdi rx{!}, {PC, CPSR}
SH Signed operation, Results are right shifted by one SMC #i4 CallSecureMonitor() 6k
U Unsigned operation, Results are truncated SRSdi SP{!}, #mode STMdi SP mode{!}, {LR, SPSR} 6
UH Unsigned operation, Results are right shifted by one
UQ Unsigned operation, Results are saturated
ARMv7 version 8 page 2
General Registers Thumb16 Bitwise and Move Instructions Thumb16 Arithmetic Instructions
R0-R3 Arguments and return values (useable by Thumb16) AND{S} rx, ry rx = rx & ry S ADC{S} rx, ry rx = rx + ry + C S
R4-R7 General purpose (must be preserved, useable by Thumb16) ASR{S} rx, ry, #j5 ¯ j
rx = ry  S ADD{S} rx, ry, #i3 rx = ry + i∅ S
R8-R11 General purpose registers (must be preserved) ASR{S} rx, ry ¯ ry
rx = rx  S ADD{S} rx, #i8 rx = rx + i∅ S
R12 IP Intra-procedure-call scratch register BIC{S} rx, ry rx = rx & ∼ry S ADD{S} rx, ry, rz rx = ry + rz S
R13 SP Stack pointer EOR{S} rx, ry rx = rx ⊕ ry S ADD rx, ry rx = rx + ry H
R14 LR Return address LSL{S} rx, ry, #i5 rx = ry  i S ADD rx, SP, #i8 rx = SP + i∅
R15 PC Program counter LSL{S} rx, ry rx = rx  ry S ADD SP, #i9 SP = SP + i∅8:2 :01:0
LSR{S} rx, ry, #j5 rx = ry  j S ADR rx, rel10 rx = PC + rel∅9:2 :01:0
Condition Codes
LSR{S} rx, ry rx = rx  ry S CMN rx, ry rx + ry
EQ Equal Z
MOV rx, ry rx = ry H CMP rx, #i8 rx − i∅
NE Not equal !Z
MOVS rx, ry rx = ry CMP rx, ry rx − ry H
CS/HS Carry set, Unsigned higher or same C
MOV{S} rx, #i8 rx = i∅ S MUL{S} rx, ry rx = rx × ry S
CC/LO Carry clear, Unsigned lower !C
MVN{S} rx, ry rx = ∼ry S RSB{S} rx, ry, #0 rx = 0 − ry S
MI Minus, Negative N
ORR{S} rx, ry rx = rx | ry S SBC{S} rx, ry rx = rx − (ry + C) S
PL Plus, Positive or zero !N
REV rx, ry rx = ry7:0 :ry15:8 :ry23:16 :ry31:24 6 SUB{S} rx, ry, #i3 rx = ry − i∅ S
VS Overflow V
VC No overflow !V REV16 rx, ry rx = ry23:16 :ry31:24 :ry7:0 :ry15:8 6 SUB{S} rx, #i8 rx = rx − i∅ S
HI Unsigned higher C & !Z REVSH rx, ry rx = ry±
7:0 :ry15:8 6 SUB{S} rx, ry, rz rx = ry − rz S
LS Unsigned lower or same !C | Z ROR{S} rx, ry rx = rx ≫ ry S SUB SP, #i9 SP = SP − i∅8:2 :01:0
GE Signed greater than or equal N=V SXTB rx, ry rx = ry±
7:0

LT Signed less than N 6= V SXTH rx, ry rx = ry±

15:0
Thumb16 Load and Store Instructions

GT Signed greater than !Z & N = V TST rx, ry rx & ry LDMIA rx{!}, rlist rlist = [rx]; if(!) rx += 4×cnt

LE Signed less than or equal Z | N 6= V UXTB rx, ry rx = ry∅7:0 6 LDMIA SP!, rlist rlist = [SP]; SP += 4×cnt
AL Always (default) 1 UXTH rx, ry rx = ry∅15:0 6 LDR rx, [ry{, #i7 }] rx = [ry + i∅6:2 :01:0 ]
LDR rx, [SP{, #i10 }] rx = [SP + i∅9:2 :01:0 ]
DMB and DSB Options Thumb16 Branch and Special Instructions LDR rx, rel10 rx = [PC + rel∅9:2 :01:0 ]
SY Full system, Read and write B rel12 PC = PC + rel±
11:1 :0 LDR rx, [ry, rz] rx = [ry + rz]
(SY)ST Full system, Write only Bcc rel9 if(cc) PC = PC + rel±
8:1 :0 I LDRB rx, [ry{, #i5 }] rx = [ry + i∅ ]∅8
ISH Inner shareable, Read and write BKPT #i8 BreakPoint(i) I LDRB rx, [ry, rz] rx = [ry + rz]∅8
ISHST Inner shareable, Write only BL rel23 LR=PC31:1 :1; PC+=rel±
22:1 :0 LDRH rx, [ry{, #i6 }] rx = [ry + i∅5:1 :0]∅16
NSH Non-shareable, Read and write BLX rel23 LR=PC31:1 :1; Set=0; PC+=rel±
22:2 :01:0 LDRH rx, [ry, rz] rx = [ry + rz]∅16
NSHST Non-shareable, Write only BLX rx LR=PC31:1 :1; Set=rx0 ; PC=rx31:1 :0 LDRSB rx, [ry, rz] rx = [ry + rz]±
8
OSH Outer shareable, Read and write BX rx Set=rx0 ; PC = rx31:1 :0 LDRSH rx, [ry, rz] rx = [ry + rz]±
16
OSHST Outer sharable, Write only CBNZ rx, rel7 if(rx 6= 0) PC += rel∅6:1 :0 I,6t POP rlist rlist = [SP]; SP += 4×cnt
CBZ rx, rel7 if(rx = 0) PC += rel∅6:1 :0 I,6t PUSH rlist SP −= 4×cnt; [SP] = rlist
Notes for Instruction Set
CPSI{D,E} {aif} {a}{i}{f} = (E ? 1 : 0) 6 STMIA rx!, rlist [rx] = rlist; rx += 4×cnt
6,6k,6t,7 Introduced in ARMv6, ARMv6k, ARMv6T2, or ARMv7
IT{t{t{t}}}cc if(cc) NextInstruction I,6t STMDB SP!, rlist SP −= 4×cnt; [SP] = rlist
A Only available in ARM mode
NOP 6k STR rx, [ry{, #i7 }] [ry + i∅6:2 :01:0 ] = rx
D Not available on ARM-M without DSP extension
SETEND {BE/LE} EndianState = {BE/LE} I,6 STR rx, [SP{, #i10 }] [SP + i∅9:2 :01:0 ] = rx
H Thumb16 instruction can use high registers
SEV SendEvent() 7 STR rx, [ry, rz] [ry + rz] = rx
I Can’t be conditional
SVC #i8 CallSupervisor() STRB rx, [ry{, #i5 }] [ry + i∅ ]8 = rx7:0
S Thumb16 instruction must have S suffix unless in IT block
T Only available in Thumb mode UDF #i8 UndefinedException() STRB rx, [ry, rz] [ry + rz]8 = rx7:0
WFE WaitForEvent() 7 STRH rx, [ry{, #i6 }] [ry + i∅5:1 :0]16 = rx15:0
WFI WaitForInterrupt() 7 STRH rx, [ry, rz] [ry + rz]16 = rx15:0
YIELD HintYield() 7
ARMv7 version 8 page 3
 ARMv7-A & ARMv7-R System System Control Register (SCTLR) Secure Configuration Register (SCR)
M 0x00000001 MMU enabled B NS 0x001 System state is non-secure unless in Monitor mode
Current Program Status Register (CPSR) A 0x00000002 Alignment check enabled B IRQ 0x002 IRQs taken to Monitor mode
M 0x0000001f Processor Operating Mode C 0x00000004 Data and unified caches enabled B FIQ 0x004 FIQs taken to Monitor mode
T 0x00000020 Instruction set (JT: 00=ARM, 01=Thumb) CP15BEN 0x00000020 CP15 barrier enable 7,B EA 0x008 External aborts taken to Monitor mode
F 0x00000040 FIQ exception masked SW 0x00000400 Enable SWP and SWPB instructions 6,B FW 0x010 CPSR.F writeable in non-secure state
I 0x00000080 IRQ exception masked Z 0x00000800 Program flow prediction enabled B AW 0x020 CPSR.A writeable in non-secure state
A 0x00000100 Asynchronous abort masked 6 I 0x00001000 Instruction cache enabled B nET 0x040 Disable early termination
E 0x00000200 Big-endian operation 6 V 0x00002000 High exception vectors B SCD 0x080 Secure monitor call disable V
IT 0x0600fc00 IT state bits 6t RR 0x00004000 Round Robin select (Non-Secure RO) HCE 0x100 Hyp Call enable V
GE{3..0} 0x000f0000 SIMD Greater than or equal to 6 HA 0x00020000 Hardware access flag enable B,S SIF 0x200 Secure instruction fetch V
J 0x01000000 Instr set (JT: 10=Jazelle, 11=ThumbEE) 6 BR 0x00020000 Background region enable 7,R
Q 0x08000000 Cumulative saturation bit WXN 0x00080000 Write force to XN V Non-Secure Access Control Register (NSACR)
V 0x10000000 Overflow condition flag DZ 0x00080000 Divide by zero causes undefined instruction 7,R CP{0..13} 1  {0..13} CP{0..13} can be accessed in non-secure state
C 0x20000000 Carry condition flag UWXN 0x00100000 Unprivileged write forced to XN for PL1 V NSD32DIS 0x00004000 CPACR.D32DIS is fixed 1 in non-secure state
Z 0x40000000 Zero condition flag FI 0x00200000 Fast Interrupts (Non-Secure RO) 6 NSASEDIS 0x00008000 CPACR.ASEDIS is fixed 1 in non-secure state
N 0x80000000 Negative condition flag VE 0x01000000 Interrupt Vectors Enable 6,B RFR 0x00080000 Reserve FIQ mode for non-secure
EE 0x02000000 Exception Endianess 6,B NSTRCDIS 0x00100000 Disable non-secure access to CP14 trace regs
Processor Operating Modes
NMFI 0x08000000 Non-maskable FIQ support (RO) 6
usr 0x10 User CP15 Memory System Fault Registers
TRE 0x10000000 TEX remap functionality enabled B,S
fiq 0x11 FIQ DFSR c5,0,c0,0 Data Fault Status Register B
AFE 0x20000000 Access flag enable B,S
irq 0x12 IRQ IFSR c5,0,c0,1 Instruction Fault Status Register 6,B
TE 0x40000000 Thumb exception enable 6t,B
svc 0x13 Supervisor ADFSR c5,0,c1,0 Auxiliary DFSR 7,B
IE 0x80000000 Big-endian byte order in instructions 7,R
mon 0x16 Monitor (Secure only) S AIFSR c5,0,c1,1 Auxiliary IFSR 7,B
abt 0x17 Abort Coprocessor Access Control Register (CPACR) DFAR c6,0,c0,0 Data Fault Address Register B
hyp 0x1a Hypervisor (Non-secure only) V CP{0..13} 3(2×{0..13}) CP{0..13} access (00=denied, 01=privileged IFAR c6,0,c0,2 Instruction Fault Address Register 6,B
und 0x1b Undefined mode only, 11=privileged or user mode) DRBAR c6,0,c1,0 Data Region Base Address Register R
sys 0x1f System TRCDIS 0x10000000 Disable CP14 access to trace registers IRBAR c6,0,c1,1 Instruction Region Base Address Register R
D32DIS 0x40000000 Disable use of D16-D31 registers DRSR c6,0,c1,2 Data Region Size and Enable Register R
Vectors ASEDIS 0x80000000 Disable advanced SIMD functionality IRSR c6,0,c1,3 Instruction Region Size and Enable Register R
0x00 Reset DRACR c6,0,c1,4 Data Region Access Control Register R
0x04 Undefined instruction CP15 System Control Registers IRACR c6,0,c1,5 Instruction Region Access Control Register R
0x08 Supervisor Call / Secure Monitor Call / Hypervisor Call SCTLR c1,0,c0,0 System Control Register RGNR c6,0,c2,0 MPU Region Number Register R
0x0c Prefetch abort ACTLR c1,0,c0,1 Auxiliary Control Register 6,B
0x10 Data abort CPACR c1,0,c0,2 Coprocessor Access Control Register 6 CP15 Generic Timer Registers
0x14 Hyp trap SCR c1,0,c1,0 Secure Configuration (Secure only) S CNTFRQ c14,0,c0,0 Counter Frequency Reg (Non-Secure RO) 7
0x18 IRQ interrupt SDER c1,0,c1,1 Secure Debug Enable (Secure only) S CNTKCTL c14,0,c1,0 Timer PL1 Control Register 7
0x1c FIQ interrupt NSACR c1,0,c1,2 Non-Secure Access Control (Non-Secure RO) S CNTP TVAL c14,0,c2,0 PL1 Physical TimerValue Register 7,B
CNTP CTL c14,0,c2,1 PL1 Physical Timer Control Register 7,B
Notes for System Registers and Tables CP15 Security Extension Registers (ARM-A Only) CNTV TVAL c14,0,c3,0 Virtual TimerValue Register 7
6,6k,6t,7 Introduced in ARMv6, ARMv6k, ARMv6T2, or ARMv7 VBAR c12,0,c0,0 Vector Base Register B CNTV CTL c14,0,c3,1 Virtual TimerControl Register 7
A Only present on ARM-A MVBAR c12,0,c0,1 Monitor Vector Base Address (Secure only) CNTPCT c14,0 Physical Count Register (RO) 7
B Banked between secure and non-secure usage ISR c12,0,c1,0 Interrupt Status Register (RO) CNTVCT c14,1 Virtual Count Register (RO) 7
R Only present on ARM-R CNTP CVAL c14,2 PL1 Physical Timer CompareValue Register 7,B
S Only present with security extensions (Implies 6k,A) CNTV CVAL c14,3 Virtual Timer CompareValue Register 7
V Only present with virtualization extensions (Implies 7,A)

ARMv7 version 8 page 4

CP15 ID Registers (Read-Only) CP15 Memory Protection and Control Registers (ARM-A only) CP15 Process, Context, and Thread ID Registers
MIDR c0,0,c0,0 Main ID Register TTBR0 c2,0,c0,0 Translation Table Base 0 B FCSEIDR c13,0,c0,0 FSCE PID Register A,B
CTR c0,0,c0,1 Cache Type Register TTBR1 c2,0,c0,1 Translation Table Base 1 6,B CONTEXIDR c13,0,c0,1 Context ID Register 6,B
TCMTR c0,0,c0,2 TCM Type Register TTBCR c2,0,c0,2 Translation Table Base Control 6,B TPIDRURW c13,0,c0,2 User Read/Write Thread ID 6,B
TLBTR c0,0,c0,3 TLB Type Register A TTBR0 c2,0 Translation Table Base 0 (LPAE only) 7,B TPIDRURO c13,0,c0,3 User Read-only Thread ID 6,B
MPUIR c0,0,c0,4 MPU Type Register R TTBR1 c2,1 Translation Table Base 1 (LPAE only) 7,B TPIDRPRW c13,0,c0,4 PL1 only Thread ID 6,B
MPIDR c0,0,c0,5 Multiprocessor Affinity Register DACR c3,0,c0,0 Domain Access Control Register B
REVIDR c0,0,c0,6 Revision ID CP15 Virtualization Extension Registers (ARM-A Only)
ID PFR{0..1} c0,0,c1,{0..1} Processor Feature Registers 6 CP15 TLB Maintenance Operation Regs (Write Only, ARM-A Only) VPIDR c0,4,c0,0 Virtualization Processor ID Register
ID DFR0 c0,0,c1,2 Debug Feature Register 0 6 TLBIALLIS c8,0,c3,0 Invalidate entire TLB IS 7 VMPIDR c0,4,c0,5 Virtualization Multiproc ID Register
ID AFR0 c0,0,c1,3 Auxiliary Feature Register 0 6 TLBIMVAIS c8,0,c3,1 Invalidate unified TLB by MVA and ASID IS 7 HSCTLR c1,4,c0,0 Hyp System Control Register
ID MMFR{0..3} c0,0,c1,{4..7} Memory Model Feature Regs 6 TLBIASIDIS c8,0,c3,2 Invalidate unified TLB by ASID match IS 7 HACTLR c1,4,c0,1 Hyp Auxiliary Control Register
ID ISAR{0..5} c0,0,c2,{0..5} Instruction Set Attribute Regs 6 TLBIMVAAIS c8,0,c3,3 Inv unified TLB entry by MVA all ASID IS 7 HCR c1,4,c1,0 Hyp Configuration Register
CCSIDR c0,1,c0,0 Cache Size ID Register 7 ITLIALL c8,0,c5,0 Invalidate instruction TLB HDCR c1,4,c1,1 Hyp Debug Configuration Register
CLIDR c0,1,c0,1 Cache Level ID Register 7 ITLIMVA c8,0,c5,1 Inv instr TLB entry by MVA all ASID IS HCPTR c1,4,c1,2 Hyp Coprocessor Trap Register
AIDR c0,1,c0,7 Auxiliary ID Register 7 ITLIASID c8,0,c5,2 Invalidate instruction TLB by ASID match 6 HSTR c1,4,c1,3 Hyp System Trap Register
CSSELR c0,2,c0,0 Cache Size Selection Register (RW) 7,B DTLBIALL c8,0,c6,0 Invalidate data TLB HACR c1,4,c1,7 Hyp Auxiliary Configuration Register
DTLBIMVA c8,0,c6,1 Invalidate data TLB entry by MVA and ASID HTCR c2,4,c0,2 Hyp Translation Control Register
CP15 Cache Maintenance Registers (Write Only) DTLBIASID c8,0,c6,2 Invalidate data TLB by ASID match 6 VTCR c2,4,c1,2 Virtualization Translation Control Reg
CP15WFI c7,0,c0,4 Wait for interrupt operation TLBIALL c8,0,c7,0 Invalidate unified TLB HTTBR c2,4 Hyp Translation Table Base Reg
ICIALLUIS c7,0,c1,0 Inv all instr caches to PoU Inner Sharable 7 TLBIMVA c8,0,c7,1 Inv unified TLB entry by MVA and ASID VTTBR c2,6 Virt Translation Table Base Reg
BPIALLIS c7,0,c1,6 Inv all branche predictors Inner Sharable 7 TLBIASID c8,0,c7,2 Invalidate unified TLB by ASID match 6 HADFSR c5,4,c1,0 Hyp Auxiliary DFSR
PAR c7,0,c4,0 Physical Address Register (RW) 7,A,B TLBIMVAA c8,0,c7,3 Inval unified TLB entries by MVA all ASID 6 HAIFSR c5,4,c1,1 Hyp Auxiliary IFSR
ICIALLU c7,0,c5,0 Invalidate all instruction caches to PoU HSR c5,4,c2,0 Hyp Syndrome Register
ICIMVAU c7,0,c5,1 Inv instruction caches by MVA to PoU CP15 Performance Monitor Registers (ARM-R Only) HDFAR c6,4,c0,0 Hyp Data Fault Address Register
CP15ISB c7,0,c5,4 Instruction Sync Barrier operation 7 PMCR c9,0,c12,0 PM Control Register HIFAR c6,4,c0,2 Hyp Instruction Fault Address Register
BPIALL c7,0,c5,6 Invalidate all branch predictors PMCNTENSET c9,0,c12,1 PM Count Enable Set Register HPFAR c6,4,c0,4 Hyp IPA Fault Address Register
BPIMVA c7,0,c5,7 Invalidate MVA from branch predictors PMCNTENCLR c9,0,c12,2 PM Count Enable Clear Register ATS1HR c7,4,c8,0 Addr Tran Stage 1 Hyp mode Read (WO)
DCIMVAC c7,0,c6,1 Inv data cache line my MVA to PoC PMOVSR c9,0,c12,3 PM Overflow Flag Status Register ATS1HW c7,4,c8,1 Addr Tran Stage 1 Hyp mode Write (WO)
DCISW c7,0,c6,2 Invalidate data cache line by set/way PMSWINC c9,0,c12,4 PM Software Increment Register TLBIALLHIS c8,4,c3,0 Inv entry hyp unif TLB IS (WO)
ATS1CPR c7,0,c8,0 PL1 read translation (Current state) 7,A PMSELR c9,0,c12,5 PM Event Counter Selection Register TLBIMVAHIS c8,4,c3,1 Inv hyp unif TLB entry by MVA IS (WO)
ATS1CPW c7,0,c8,1 PL1 write translation (Current state) 7,A PMCEID0 c9,0,c12,6 PM Common Event Identification Register 0 TLBIALLNSNHIS c8,4,c3,4 Inv non-sec/hyp uni TLB IS (WO)
ATS1CUR c7,0,c8,2 Unpriv read translation (Current state) 7,A PMCEID1 c9,0,c12,7 PM Common Event Identification Register 1 TLBIALLH c8,4,c7,0 Inv hyp unified (WO)
ATS1CUW c7,0,c8,3 Unpriv write translation (Current state) 7,A PMCCNTR c9,0,c13,0 PM Cycle Count Register TLBIMVAH c8,4,c7,1 Inv hyp unif TLB by MVA (WO)
ATS12NSOPR c7,0,c8,4 PL1 read translation (NS state) 7,S PMXEVTYPER c9,0,c13,1 PM Event Type Select Register TLBIALLNSNH c8,4,c7,4 Inv non-sec/hyp unif TLB (WO)
ATS12NSOPW c7,0,c8,5 PL1 write translation (NS state) 7,S PMXEVCNTR c9,0,c13,2 PM Event Count Register HMAIR0 c10,4,c2,0 Hyp Mem Attribute Indirection Reg 0
ATS12NSOUR c7,0,c8,6 Unprivileged read translation (NS state) 7,S PMUSERENR c9,0,c14,0 PM User Enable Register HMAIR1 c10,4,c2,1 Hyp Mem Attribute Indirection Reg 1
ATS12NSOUW c7,0,c8,7 Unprivileged write translation (NS state) 7,S PMINTENSET c9,0,c14,1 PM Interrupt Enable Set Register HAMAIR0 c10,4,c3,0 Hyp Aux Mem Attr Indirection Reg 0
DCCMVAC c7,0,c10,1 Clean data cache line my MVA to PoC PMINTENCLR c9,0,c14,2 PM Interrupt Enable Clear Register HAMAIR1 c10,4,c3,1 Hyp Aux Mem Attr Indirection Reg 1
DCCSW c7,0,c10,2 Clean data cache line by set/way HVBAR c12,4,c0,0 Hyp Vector Base Address Register
CP15DSB c7,0,c10,4 Data Synchronization Barrier operation 7 CP15 Memory Mapping Registers (ARM-A Only) HTPIDR c13,4,c0,2 Hyp Read/Write Thread ID
CP15DMB c7,0,c10,5 Data Memory Barrier operation 7 PRRR c10,0,c2,0 Primary Region Remap Register 6,B CNTHCTL c14,4,c1,0 Timer PL2 Control Register
DCCMVAU c7,0,c11,1 Clean data cache line by MVA to PoU NMRR c10,0,c2,1 Normal Memory Remap Register 6,B CNTHP TVAL c14,4,c2,0 PL2 Physical TimerValue Register
DCCIMVAC c7,0,c14,1 Clean and inv data c-line by MVA to PoC AMAIR0 c10,0,c3,0 Aux Memory Attribute Indirection Reg 0 7 CNTHP CTL c14,4,c2,1 PL2 Physical Timer Control Register
DCCISW c7,0,c14,2 Clean and inv data c-line by set/way AMAIR1 c10,0,c3,1 Aux Memory Attribute Indirection Reg 1 7 CNTVOFF c14,4 Virtual Offset Register
PAR c7,0 Physical Address Register (RW) 7,A,B CNTHP CVAL c14,6 PL2 Physical Timer CompareValue Register

ARMv7 version 8 page 5

 ARMv7-M System Interrupt Control and State Register (ICSR) System Timer Registers
VECTACTIVE 0x000001ff Current executing exception (RO) SYST CSR 0xe000e010 SysTick Control and Status Register
Special Registers RETTOBASE 0x00000800 No active exceptions (except by IPSR) (RO) SYST RVR 0xe000e014 SysTick Reload Value Register
{I}{E}{A}PSR Program Status Registers VECTPENDING 0x001ff000 Highest pending and enabled exception (RO) SYST CVR 0xe000e018 SysTick Current Value Register
XPSR Alias for IEAPSR ISRPENDING 0x00400000 External interrupt is pending (RO) SYST CALIB 0xe000e01c SysTick Calibration Value Register
MSP Main Stack Pointer ISRPREEMPT 0x00800000 Will service exception on debug exit (RO)
PSP Process Stack Pointer PENDSTCLR 0x02000000 Clear pending SysTick exception External Interrupt Controller Registers
PRIMASK Exceptions Mask Register PENDSTSET 0x04000000 Make SysTick exception pending NVIC ISER{0..15} 0xe000e1{00..3c} Interrupt Set-Enable Registers
BASEPRI Base Priority Register PENDSVCLR 0x08000000 Clear pending PendSV exception NVIC ICER{0..15} 0xe000e1{80..bc} Interrupt Clear-Enable Registers
BASEPRI MAX Alias for BASEPRI that ignores writes of lower value PENDSVSET 0x10000000 Make PendSV exception pending NVIC ISPR{0..15} 0xe000e2{00..3c} Interrupt Set-Pending Registers
FAULTMASK Raise exception priority to HardFloat NMIPENDSET 0x80000000 Make NMI exception active NVIC ICPR{0..15} 0xe000e2{80..bc} Interrupt Clear-Pending Registers
CONTROL Special-Purpose Control Register NVIC IABR{0..15} 0xe000e3{00..3c} Interrupt Active Bit Registers
SysTick Control and Status Register (SYST CSR) NVIC IPR{0..123} 0xe000e{400..5ec} Interrupt Priority Registers
Program Status Register (xPSR) ENABLE 0x00000001 Counter is operating
0x000001ff Exception number (RO) TICKINT 0x00000002 SysTick exception on counter zero Memory Protection Unit Registers
IT 0x0600fc00 IT state bits CLKSOURCE 0x00000004 SysTick uses processor clock MPU TYPE 0xe000ed90 MPU Type Register (RO)
GE{3..0} 0x000f0000 SIMD Greater than or equal to (DSP extension only) COUNTFLAG 0x00010000 Timer has reached zero since last read (RO) MPU CTRL 0xe000ed94 MPU Control Register
Q 0x08000000 Cumulative saturation bit MPU RNR 0xe000ed98 MPU Region Number Register
V 0x10000000 Overflow condition flag System Control Registers MPU RBAR 0xe000ed9c MPU Region Base Address Register
C 0x20000000 Carry condition flag ICTR 0xe000e004 Interrupt Controller Type Register MPU RASR 0xe000eda0 MPU Region Attribute and Size Register
Z 0x40000000 Zero condition flag ACTLR 0xe000e008 Auxiliary Control Register
N 0x80000000 Negative condition flag ICSR 0xe000ed04 Interrupt Control and State Register SW Trigger Interrupt Registers
VTOR 0xe000ed08 Vector Table Offset Register STIR 0xe000ef00 Software Triggered Interrupt Register (WO)
Vector Table AIRCR 0xe000ed0c App Interrupt and Reset Ctrl Reg FPCCR 0xe000ef34 Floating Point Context Control Register
0 Main SP register value at reset SCR 0xe000ed10 System Control Register FPCAR 0xe000ef38 Floating Point Context Address Register
1 Reset CCR 0xe000ed14 Configuration and Control Register FPDSCR 0xe000ef3c Floating Point Default Status Control Reg
2 NMI SHPR{1..3} 0xe000ed{18..20} System Handler Priority Registers MVFR{0..2} 0xe000ef4{0..8} Medial and FP Feature Registers (RO)
3 HardFault SHCSR 0xe000ed24 System Handler Control and State Reg
4 MemManage CFSR 0xe000ed28 Configurable Fault Status Register Cache and Branch Predictior Maintenance (Write-Only)
5 BusFault HFSR 0xe000ed2c HardFault Status Register ICIALLU 0xe000ef50 I-cache invalidate all to PoU
6 UsageFault DFSR 0xe000ed30 Debug Fault Status Register ICIMVAU 0xe000ef58 I-cache invalidate by MVA to PoU
11 SVCall MMFAR 0xe000ed34 MemManage Fault Address Registers DCIMVAC 0xe000ef5c D-cache invalidate by MVA to PoC
12 DebugMonitor BFAR 0xe000ed38 BusFault Address Register DCISW 0xe000ef60 D-cache invalidate by set-way
14 PendSV AFAR 0xe000ed3c Auxiliary Fault Status Register DCCMVAU 0xe000ef64 D-cache clean by MVA to PoU
15 SysTick CPACR 0xe000ed88 Coprocessor Access Control Register DCCMVAC 0xe000ef68 D-cache clean by MVA to PoC
16+{n} External interrupt {n} DCCSW 0xe000ef6c D-cache clean by set-way
CPUID Registers (Read Only) DCCIMVAC 0xe000ef70 D-cache clean and invalidate by MVA to PoC
Address Map CPUID 0xe000ed00 CPUID Base Register DCCISW 0xe000ef74 D-cache clean and invalidate by set-way
0x00000000-0x1fffffff On-chip ROM or flash memory ID PFR{0..1} 0xe000ed4{0..4} Processor Feature Registers BPIALL 0xe000ef78 Branch predictor invalidate all
0x20000000-0x3fffffff On-chip SRAM ID DFR0 0xe000ed48 Debug Feature Register
0x40000000-0x5fffffff On-chip Peripherals ID AFR0 0xe000ed4c Auxiliary Feature Register Microcontroller-specific ID Registers
0x60000000-0x7fffffff RAM with write-back cache ID MMFR{0..3} 0xe000ed5{0..c} Memory Model Feature Registers PID{4..7} 0xe000efd{0..c} Peripheral Identification Registers
0x80000000-0x9fffffff RAM with write-through cache ID ISAR{0..4} 0xe000ed{60..70} Instruction Set Attribute Regs PID{0..3} 0xe000efe{0..c} Peripheral Identification Registers
0xa0000000-0xbfffffff Shared device space ID CLIDR 0xe000ed78 Cache Level ID Register CID{0..3} 0xe000eff{0..c} Component Identification Registers
0xc0000000-0xdfffffff Non-shared device space ID CTR 0xe000ed7c Cache Type Register
0xe0000000-0xffffffff System segment ID CCSIDR 0xe000ed80 Cache Size ID Register
ID CSSELR 0xe000ed84 Cache Size Selection Register
ARMv7 version 8 page 6