DIGITAL AND HDL LAB REPORT

EXPERIMENTS (1-10)

VARANASI THANUSRI
119EI0897
Exp.no Experiment Name Date of Date of
Experiment Submission

1 Realization of logic functions using 24/12/20 31/12/20

Universal gates -
NAND and
NOR

2 Design and Implementation of 31/12/20 7/1/21

Half/full adder and Half/full
subtractor using X-OR and basic
gates

3 Design and implementation of code 7/1/21 20/1/21

converters using logic gates

4 Design & Implementation of 20/1/21 27/1/21

Magnitude Comparator

5 Design and Implementation of 27/1/21 28/1/21

Multiplexer and De-multiplexer

6 study and verification of State table of 28/1/21 10/2/21

different Flip-Flops

7 Design and Implementation of 4-bit 10/2/21 17/2/21

ripple counter and M od-10 counters
using flip flop and gates

8 Design and Implementation of 3-bit 17/2/21 24/2/21

synchronous up/down counter

9 Design and Implementation of the 24/2/21 6/3/21

various shift Registers using flip flops

10 Digital to analog converter using R 2R 6/3/21 18/3/21

ladder network and 741 op amp
 EXPERIMENT 1
Aim of the experiment: Realization of logic functions using Universal gates -
NAND and NOR
Apparatus/Components used:
 Components Development System (breadboard)
 Digital ICs:
7400: Quad 2 input NAND---2pcs
7402: Quad 2 input NOR ----2pcs
 Connecting Wires
 Patch Cords(7pcs)
Theory in Brief:
A Digital Logic Gate is an electronic device that makes logical decisions
based on the different combinations of digital signals present on its inputs. Logic
gates are the building blocks of digital circuits. Combinations of logic gates form
circuits designed with specific tasks in mind. They are fundamental to the design
of computers. Digital logic using transistors is often referred as Transistor-
Transistor Logic or TTL gates. These gates are the AND, OR, NOT, NAND, NOR,
EXOR and EXNOR gates
These basic logic gates are implemented as small-scale integrated
circuits (SSICs) or as part of more complex medium scale (MSI) or very large-
scale (VLSI) integrated circuits. Digital IC gates are classified not only by their
logic operation, but also the specific logic-circuit family to which they belong.
Each logic family has its own basic electronic circuit upon which more complex
digital circuits and functions are developed. The following logic families are the
most frequently used.
TTL Transistor-transistor logic.
ECL Emitter-coupled logic.
MOS Metal-oxide semiconductor.
 CMOS Complementary metal-oxide semiconductor.
Digital circuits are frequently constructed with NAND or NOR gates rather
than with AND and OR gates. NAND and NOR gates are easier to fabricate with
electronic components and are the basic gates used in all IC digital logic
families.

Procedure:
Observation:
Results:
Realization of logic gates using NAND universal gates have the following
results:

1) NOT: Output is inverted for corresponding input.

2) AND: Output is HIGH only when both the inputs are HIGH.
3) OR: Output is LOW only when both the inputs are LOW.
4) Ex-OR: Output is HIGH when either of the inputs is HIGH (Not both the
inputs).

5) Ex-NOR: Output is HIGH only when either both the inputs are LOW or
both the inputs are HIGH.

6) NOR: Output is HIGH when both the inputs are LOW.

Realization of logic gates using NOR universal gates have the following
results:

1) NOT: Output is inverted for corresponding input.

2) AND: Output is HIGH only when both the inputs are HIGH.
3) OR: Output is LOW only when both the inputs are LOW.
4) Ex-OR: Output is HIGH when either of the inputs is HIGH (Not
both the inputs).
5) Ex-NOR: Output is HIGH only when either both the inputs are LOW or
both the inputs are HIGH.

6) NAND: Output is LOW when both the inputs are HIGH.

Discussion and Conclusion:
From the above experiment, it can be seen that all the basic logic gates
were implemented successfully through IC7400, IC7402. Therefore, the
realization of logic functions using Universal gates was successful.
Precautions:
▪ Check all the connections carefully.
▪ Check if the IC is properly biased or not.
▪ Verify the results with the theoretical truth tables.
 EXPERIMENT 2
Aim of the experiment: Design and Implementation of Half/full adder and
Half/full subtractor using X-OR and basic gates.
Apparatus/Components used:
 IC 7400, IC 7408, IC 7486, IC 7432,
 Wires and Patch Cords
 Component Development System
Theory in Brief:
Half-Adder: A combinational logic circuit that performs the addition of two
data bits, A and B, is called a half-adder. Addition will result in two output
bits; one of which is the sum bit, S, and the other is the carry bit, C. The
Boolean functions describing the half-adder are:
S =A⊕B C = A B
Full-Adder: The half-adder does not take the carry bit from its previous
stage into account. This carry bit from its previous stage is called carry-in
bit. A combinational logic circuit that adds two data bits, A and B, and a
carry-in bit, Cin, is called a full-adder. The Boolean functions escribing the
full-adder are:
S = (x⊕y) ⊕Cin C = xy + Cin (x ⊕y)
Half Subtractor: Subtracting a single-bit binary value B from another A
(i.e. A -B) produces a difference bit D and a borrow out bit B-out. This
operation is called half subtraction and the circuit to realize it is called a
half subtractor. The Boolean functions describing the half-Subtractor are:
S =A⊕B C = A’ B
Full Subtractor: Subtracting two single-bit binary values, B, Cin from a
single-bit value A produces a difference bit D and a borrow out Br bit. This
is called full subtraction. The Boolean functions describing the full-
subtractor are:
D = (x⊕y) ⊕Cin Br=A’B + A’(Cin) + B(Cin)
Half Adder:

Full Adder:
Half Subtractor:

TRUTH TABLES FOR ADDERS AND SUBTRACTORS

Half Adder:
Full Adder:

Half Subtractor:

Full Subtractor:
PROCEDURE:
(i) Connect the elements of circuit as given according to circuit diagram.
(ii) Give logical inputs as per circuit diagram.
(iii) Observe the output and verify with the truth table.
OBSERVATION:
Result and Analysis: Verified the truth table as follows.
Half Adder: Verified the truth table of Half Adder as S = 1 i.e. LED which is
connected to S terminal glows when inputs are A B = (0,1) or (1,0).
Verified the truth table of Half Adder as C = 1 i.e. LED which is connected to
C terminal glows when inputs are A B = (1,1)

Full Adder: Verified the truth table of Full Adder as S = 1 i.e. LED which is
connected to S terminal glows when inputs are A B Ci = (1,0,0); (0,0,1);
(0,1,0); (1,1,1).
Verified the truth table of Full Adder as Co = 1 i.e. LED which is connected
to Co terminal glows when inputs are A B Co = (1,1,0); (1,0,1); (0,1,1); (1,1,1).

Half Subtractor: Verified the truth table of Half Subtractor as D = 1 i.e. LED
which is connected to D terminal glows when inputs are x y. = (0,1)
Verified the truth table of Half Subtractor as B = 1 i.e. LED which is
connected to B terminal glows when inputs are x y = (0,1); (1,0)

Full Subtractor: Verified the truth table of Full Subtractor as D = 1 i.e. LED
which is connected to D terminal glows when inputs are X Y Bin= (1,0,0);
(0,1,0); (0,0,1); (1,1,1)
Verified the truth table of Full Subtractor as BORROW out = 1 i.e. LED
which is connected to BORROW out terminal glows when inputs are X Y
BORROW in= (0,0,1); (0,1,0), (0,1,1); (1,1,1)

Discussion:
1. To add two bits we require one EXOR gate (IC 7486) to generate Sum and
one AND (IC 7408) to generate carry.
2. To add three bits we require two half adders
3. To add two bits we require one EXOR gate (IC 7486) to generate
Difference and one AND (IC 7408) and NOT Gate(IC7432) to generate
Borrow.
4. To add three bits we require two half subtractor.

Conclusion:
Therefore, the design of half/ full adders/subtarctors are successfully
implemented and verified.
 EXPERIMENT 3
Aim of the experiment: Design and Implementation of code converters using
logic gates.
Objectives:
▪ Binary to Gray code converter.
▪ Gray to Binary code converter.
▪ BCD to Excess-3 code converter.
▪ Excess-3 to BCD code converter.
Apparatus/Components used:
➔ Components Development System
➔ Connecting Wires and Patch Cords
➔ Digital ICs:
1. 7404: Hex Inverter - 1No
2. 7408: Quad 2 input AND - 1No
3. 7432: Quad 2 input OR - 1No
4. 7486: Quad 2 input Ex-OR - 1No

Theory in Brief:
Code Converters: The availability of a large variety of codes for the same
discrete elements of information results in the use of different codes by
different digital systems. It is some time necessary to use the output of
one system as the input to the other. The conversion circuit must be
inserted between the two systems if each uses different codes for the
same information. Thus a code converter is a circuit that makes the two
systems compatible even though each uses the different code
Binary Codes: A symbolic representation of data/ information is called
code. The base or radix of the binary number is 2. Hence, it has two
independent symbols. The symbols used are 0 and 1. A binary digit is
called as a bit. A binary number consists of sequence of bits, each of
which is either a 0 or 1. Each bit carries a weight based on its position
relative to the binary point. The weight of each bit position is one power of
2 greater than the weight of the position to its immediate right. e. g. of
binary number is 100011 which is equivalent to decimal number 35.
 BCD Codes: Numeric codes represent numeric information i.e. only
numbers as a series of 0’s and 1’s. Numeric codes used to represent
decimal digits are called Binary Coded Decimal (BCD) codes. A BCD code
is one, in which the digits of a decimal number are encoded-one at a time
into group of four binary digits. There are a large number of BCD codes in
order to represent decimal digits0, 1, 2……9, it is necessary to use a
sequence of at least four binary digits. Such a sequence of binary digits
which represents a decimal digit is called code word.
Gray Codes: It is a non-weighted code; therefore, it is not a suitable for
arithmetic operations. It is a cyclic code because successive code words
in this code differ in one-bit position only i.e. it is a unit distance code.
Applications of Gray Code:
1. In instrumentation and data acquisition system where linear or angular
displacement is measured.
2. In shaft encoders, input-output devices, A/D converters and the other
peripheral equipment.
Excess-3 code: It is a non-weighted code. It is also a self-complementing
BCD code used in decimal arithmetic units. The Excess-3 code for the
decimal number is performed in the same manner as BCD except that
decimal number 3 is added to each decimal unit before encoding it to
binary.
TRUTH TABLES AND LOGIC GATES OF CONVERTORS:
1) Binary to Gray code convertor:
 Binary I/P Gray code O/P

2)Gray to Binary code convertor:

 Gray Code Binary Code

3)BCD to Excess-3 code convertor:

 BCD code Excess-3 code

4)Excess-3 to BCD code convertor:

 Excess-3 i/p BCD o/p

Observation:
Input Variable- B3 B2 B1 B0
Output Variable- G3 G2 G1 G0
LED ON = LOGIC 1; LED OFF = LOGIC 0.
Binary to Gray Code Converter:
Procedure:
1)Make the connections according to the circuit diagrams.
2)Give various logical inputs as per truth tables.
3)Observe obtained logical outputs and verify them with the truth tables
Discussions:
Binary to Gray Code:
The binary to gray code converter is used since two systems use two different
codes but they need to use the same information. Binary to gray code
converter converts binary 0000 to 1111 into gray codes. The circuit diagram is
very simple and only uses a 74886 IC, i.e, EX-OR Gate. Unless the K-Map is
used many gates may be used, but the result of K-Map minimization, it can
work only using EX-OR Gate. Gray code is a weighted, cyclic and reflective
code, used in instrumentation and acquisition systems where linear or
angular displacement is measured, shaft encoders, I/O Devices, A/D
converters and outer peripheral devices.
Conclusion: Binary to gray code converter has been designed using EX-OR
Gate and its truth table was verified.
Gray to Binary Code:
The gray to binary code converter is used since two systems use two different
codes but they need to use the same information. Binary to gray code
converters convert correctly gray 0000 into binary 1111 codes. The circuit
diagram is very simple and only uses a 74886 IC, i.e, EX-OR Gate. Unless the
K-Map is used many gates may be used, but the result of K-Map minimization,
it can work only using EX-OR Gate. Gray code is a weighted, cyclic and
reflective code, used in instrumentation and acquisition systems where linear
or angular displacement is measured, shaft encoders, I/O Devices, A/D
converters and outer peripheral devices.
Conclusion:
Gray to binary code converter has been designed using EX-OR Gate and its
truth table was verified.

BCD to Excess-3 Code Converter

Excess-3 code is a 4-bit unweighted code and can be obtained from the
corresponding value of BCD code by adding three to each coded number.
Excess-3 code is a self-complementing in nature because 1's complement of
the coded number yields 9's complement of number itself.
Conclusion: BCD to Excess-3 code converter has been designed using EX-OR
Gate and its truth table was verified.
 EXPERIMENT 4
Aim of the experiment: Design and implementation of magnitude
comparator.
Objectives:
 2 Bit magnitude comparator using logic gates
 4 Bit magnitude comparator using IC7485
Apparatus/Components used:

Sl.no Component Specification Quantity

1 AND Gate IC7408 2

2 XOR Gate IC7486 1

3 OR Gate IC7432 1

4 NOT Gate IC7404 1

5 4 Bit IC7485 1
Comparator
6 CDs (Bread - 1
Board)
7 Wires And Patch - As per
cord requirement

Theory: A magnitude digital Comparator is a combinational circuit that

compares two digital or binary numbers in order to find out whether
one binary number is equal, less than or greater than the other binary
number. We logically design a circuit for which we will have two inputs
one for A and other for B and have three output terminals, one for A >
B condition, one
for A = B condition and one for A < B condition.
 A = A3 A2 A1 A0
B = B3 B2 B1 B0
The equality of the two numbers A and B is displayed in a combinational
circuit designated by the symbol(A=B). This indicates A greater than B,
then inspect the relative magnitude of pairs of significant digits starting
from the most significant position. A is 0 and that of B is 0.
We have A<B, the sequential comparison can be expanded as,
A>B = A3B3’ + X3A2B2’ + X3X2A1B1’ + X3X2X1A0B0’
A<B = A3’B3 + X3A2’B2 + X3X2A1’B1 + X3X2X1A0’B0.
The same circuit can be used to compare the relative magnitude of two
BCD digits. Where A=B is expanded as,
A = B = (A3 + B3) (A2 + B2) (A1 + B1) (A0 + B0)
x3 x2 x1 x0

2 Bit Magnitude Comparator Logic Circuit:

4 Bit Magnitude Comparator Pin Diagram and logic circuit:
Procedure:

1. Check all the components if they are working.

2. Insert the right IC into the appropriate IC base.
3. Make connections using IC chips of particular required gates as
shown in the circuit diagram.
4. Give the logical inputs according to the truth table.
5. Verify the truth table and observe the outputs taken.
6. Inputs given and Outputs are to be compared and verified.

Observation:
Result Table for 2 Bit Magnitude Comparator:
A1 A0 B1 B0 A>B A=B A<B

0 0 0 0 0 1 0

0 0 0 1 0 0 1

0 0 1 0 0 0 1

0 0 1 1 0 0 1

0 1 0 0 1 0 0

0 1 0 1 0 1 0

0 1 1 0 0 0 1

0 1 1 1 0 0 1

1 0 0 0 1 0 0

1 0 0 1 1 0 0

1 0 1 0 0 1 0
 1 0 1 1 0 0 1

1 1 0 0 1 0 0

1 1 0 1 1 0 0

1 1 1 0 1 0 0

1 1 1 1 0 1 0

Result table for 4 Bit Magnitude comparator:

A3 A2 A1 A0 B3 B2 B1 B0 A<B A=B A>B

0 0 0 1 0 0 0 0 0 0 1

0 0 0 1 0 0 0 1 0 1 0

0 0 0 0 0 0 0 1 1 0 0

1 0 1 0 1 0 1 1 1 0 0

0 1 0 1 0 1 0 1 0 1 0

1 1 0 0 0 0 1 1 0 0 1

1 1 1 1 0 1 1 1 0 0 1

0 1 1 1 1 0 0 1 0 0
Discussion and Conclusion: The 2-bit and 4-bit magnitude comparator
data have been compared. Hence, this experiment has been
implemented successfully.
Precautions:
1)Check all the connections carefully.
2)Check if the IC is properly biased or not.
3)Connections on the bread board must be tight.
4)Identify the pins of IC properly.
5)Take care while inserting or removing the IC pins of the bread board.
 EXPERIMENT 5

Aim of the experiment: Design and Implementation of Multiplexer and

Demultiplexer.

Objectives:

1) To design and set up a 4:1 Multiplexer (MUX) using only NAND gates.
2) To design and set up a 1:4 Demultiplexer (DE-MUX) using only NAND
gates.
3) To verify the truth table of IC 74153(MUX) and IC 74139(DEMUX).

Apparatus/Components used:

1. IC 7400, IC 7420, IC 74153, IC74139

2. Wires and Patch Cords
3. Component Development System

Theory in Brief:

Multiplexers are very useful components in digital systems. They

transfer a large number of information units over a smaller number
of channels, (usually one channel) under the control of selection
signals. Multiplexer means many to one. A multiplexer is a circuit with
many inputs but only one output. By using control signals (select
lines) we can select any input to the output.
Multiplexer is also called as data selector because the output bit
depends on the input data bit that is selected. The general multiplexer
circuit has 2n input signals, n control/select signals and 1 output
signal.
De-multiplexers perform the opposite function of multiplexers.
They transfer a small number of information units (usually one unit)
over a larger number of channels under the control of selection
signals. The general de-multiplexer circuit has 1 input signal, n
control/select signals and 2n output signals. De-multiplexer circuit
can also be realized using a decoder circuit with enable.
LOGIC DIAGRAM:
1) MUX Realization using NAND Gates

2) DEMUX Realization using NAND gates

 PIN DIAGRAM:

Procedure:

1. Collect the components necessary to accomplish this experiment.

2. Plug the IC chip into the breadboard.
3. Connect the supply voltage and ground lines to the chips. PIN7 =
Ground and PIN 14 = +5V.
4. Make connections as shown in the respective circuit diagram.
5. Connect the inputs of the gate to the input switches of the LED.
6. Connect the output of the gate to the output LEDs.
7. Once all connections have been done, turn on the power switch of the
breadboard
8. Operate the switches and fill in the truth table (Write "1" if LED is ON
and "0" if L1 is OFF) Apply the various combination of inputs according
to the truth table and observe the condition of Output LEDs.
Observation:
Result Table of MUX using NAND Gates:
Select Enable INPUTS Output
Input
Inputs

S1 S0 E I0 I1 I2 I3 Y

X X 1 X X X X 0

0 0 0 0 X X X 0

0 0 0 1 X X X 1

0 1 0 X 0 X X 0

0 1 0 X 1 X X 1

1 0 0 X X 0 X 0

1 0 0 X X 1 X 1

1 1 0 X X X 0 0

1 1 0 X X X 1 1

Result Table of DE-MUX using NAND Gates:

Enable Select Inputs Data Outputs
inputs inputs

E S1 S0 D Y3 Y2 Y1 Y0

1 X X 0 X X X X

0 0 0 1 0 0 0 1
 0 0 1 1 0 0 1 0

0 1 0 1 0 1 0 0

0 1 1 1 1 0 0 0

Discussion and Conclusion:

Multiplexer and de-multiplexer help in reducing the cost of
transmission of digital signals. Logic design is simple and Boolean
expressions need not be simplified. MUX and DEMUX act as rotary
switches.
The experiment has been executed and data has been verified. Hence,
the experiment can be concluded to be successful.

Precautions:
1)Check all the connections carefully.
2)Check if the IC is properly biased or not.
3)Connections on the bread board must be tight.
4)Identify the pins of IC properly.
5)Take care while inserting or removing the IC pins of the breadboard.
 EXPERIMENT 6
Aim of the experiment: To study and verify state tables of different flip-flops.
Objectives: To verify different State tables and State diagram.

1.
S-R flip-flop
2.
D flip-flop
3.
J-K flip-flop
4.
T flip-flop
Apparatus/Components used:
 IC 7400, IC 7404, IC 7410 -- 1 Each
 Patch Cords and Single Stand Wire
 Components Development System.

Theory in Brief:
S R Flip-Flop: The clocked RS flip-flop consists of NAND gates and
the output changes its state with respect to the input application of
clock pulse. When the clock pulse is high the S and R inputs reach
the second level
NAND gates in their complementary form. The flip-flop is reset
when the R input is high and S input is low. The flip-flop is set
when the S input is high and R input is low. When both the
inputs are high the output is in an indeterminate state.

D Flip-Flop: D flip flop is actually a slight modification of the above

explained clocked SR flip-flop. From the figure you can see that the
D input is connected to the S input and the complement of the D
input is connected to the R input. The D input is passed on to the flip
flop when the value of CP is ‘1’. When CP is HIGH, the flip flop moves
to the SET state. If it is ‘0’, the flip flop switches to the CLEAR state.

JK Flip-Flop: A J-K flip flop can also be defined as a modification of

the S-R flip flop. The only difference is that the intermediate state is
more refined and precise than that of a S-R flip flop. The behavior of
inputs J and K is the same as the S and R inputs of the S-R flip flop.
The letter J stands for SET and the letter K stands for CLEAR. When
both the inputs J and K have a HIGH state, the flip-flop switches to
the complement state. So, for a value of Q = 1, it switches to Q=0 and
for a value of Q = 0, it switches to Q=1.

T Flip-Flop: This is a much simpler version of the J-K flip flop. Both
the J and K inputs are connected together and thus are also called a
single input J-K flip flop. When the clock pulse is given to the flip
flop, the output begins to toggle. Here also the restriction on the
pulse width can be eliminated with a master-slave or edge-
triggered construction.

State Table: The state table representation of a sequential circuit

consists of three sections labeled present state, next state and
output. The present state designates the state of flip-flops before
the occurrence of a clock pulse. The next state shows the states
of flip-flops after the clock pulse, and the output section lists the
value of the output variables during the present state.

State Diagram: In addition to graphical symbols, tables or equations,

flip-flops can also be represented graphically by a state diagram. In
this diagram, a state is represented by a circle, and the transition
between states is indicated by directed lines (or arcs) connecting the
circles.
Diagrams (Including Circuit Diagrams):
S-R , D, J-K , T Flip flops:
 State Diagrams of different flip-flops:

Procedure:
1. Connect IC pins to the bread board as per the given circuit
diagrams.
2. All PIN 7’s are to be grounded and all PIN 14’s are to be
connected to the +5V supply.
3. Make the connections according to the circuit diagrams.
4. Give various logical inputs as per the truth tables.
5. Give the respective inputs and verify the status of all the flip-
flops.
Results and Analysis:
State Table of clocked S-R flip-flop:

Clock Inputs Present Next state Status

pulse state Name
S R

1 0 0 0 X Invalid

2 0 0 1 X Invalid

3 0 1 0 1 Set

4 0 1 1 1 Set

5 1 0 0 0 Reset

6 1 0 1 0 Reset

7 1 1 0 0 NC

8 1 1 1 1 NC

State Table of D flip-flop:

Clock pulse Input D Present Next State Status

State Name

1 0 0 0 Reset

2 0 1 0 Reset
 3 1 0 1 Set

4 1 1 1 Set

State Table of T flip-flop:

Clock pulse Input T Present Next state Status

state Name

1 0 0 0 Toggle

2 0 1 1 Toggle

3 1 0 1 No change

4 1 1 1 No change
Discussion:

Each of these flip-flops can be uniquely described by its graphical

symbol, its characteristic table, its characteristic equation or
excitation table. All flip-flops have output signals Q and Q’. During the
design process we usually know the transition from present state to
the next state and wish to find the flip-flop input conditions that will
cause the required inputs for a given change of state. Such a list is
called the excitation table.

Conclusion:
We have verified the tables and hence can conclude that the
experiment has been successful.

Precautions:
1.Remove and connect the IC pins to the breadboard properly.

2.Check for all safety measures.

 EXPERIMENT 7
Aim of the experiment: Design and Implementation of 4-bit ripple counter
and Mod-10 counter using flip flop and gates.

Objective:
a. To design a 4- bit Ripple Counter using J-K Flip flop (IC7476).
b. Verify the timing diagram and truth Table.
c. To design a Mod-10 Counter using J-K Flip flop (IC7476) and AND
gate.
d. Verify the timing diagram and truth Table of Mod-10 counter.

Apparatus/Components used:

1. Components Development System

2. Discrete Components - IC7476 Dual JK Flip-flop 2Nos
3. AND Gate (IC7408) 1No.
4. Patch Cord- 7Nos
5. wires As required

Theory in Brief:

Asynchronous Counter is sequential circuit that is used to count the

number of clock input signal. The output of one flip flop is given as a clock
input to another flip-flop, so it is called as Serial Counter. A ripple counter
is an asynchronous counter where only the first flip flop is clocked by an
external clock. All subsequent flip-flops are clocked by the output of the
preceding flip-flop. Asynchronous counters are also called ripple-
counters because of the way the clock pulse ripples it way through the
flip-flops. The MOD of the ripple counter or asynchronous counter is 2n if
n flip-flops are used. A four-bit asynchronous counter is shown on the
below figure. The external clock is connected to the clock input of the first
flip -flop (FFA) only. So, FFA changes state at the falling edge of each
clock pulse, but FFB changes only when triggered by the falling edge of
the QA output of FFA similarly FFC changes only when triggered by the
falling edge of the QB output of FFB. Because of the inherent propagation
delay through a flip-flop, the transition of the input clock pulse and a
transition of the QA output of FFA can never occur at exactly the same
time. Therefore, the flip-flops cannot be triggered simultaneously,
producing an asynchronous operation. Usually, all the CLEAR inputs are
connected together, so that a single pulse can clear all the flip-flops
before counting starts. The clock pulse fed into FFA is rippled through the
other counters after propagation delays, like a ripple on water, hence the
name Ripple Counter.

Circuit diagram:
 4 BIT RIPPLE COUNTER

MOD 10 RIPPLE COUNTER

Procedure:
1) Collect all the components necessary to do the experiment.
2) Insert the IC chips onto the breadboard.
3) According to the logic diagram, make connections using wires.
4) Give the logic inputs as per circuit diagram and perform the experiment.
5) Observe the output and verify with the truth tables.
6) Carry out the same process for both the counters.

Observation:
4-Bit Ripple counter
CLK QA QB QC QD
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
 Mod-10 counter
CLK QA QB QC QD
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
Discussion: In a ripple counter, different flip-flops are triggered with
different clock pulses and not simultaneously. A decade counter requires
resetting to zero when the output count reaches the decimal value of
10. The 4-bit counter has a reset pin that enables it to enter an all-zero
state i.e. the output of the counter is '0' if the reset is '1' irrespective of the
clock and the current state of the flip flops.
Conclusion:
Therefore, the two different types of Asynchronous counters, 4-bit Ripple
and Mod 10 counters are successfully implemented.
Precautions:
1. Check all the connections carefully.
2. Check if the IC is properly biased or not.
3. Connections on the bread board must be tight.
4. Identify the pins of IC properly.
5. Take care while inserting or removing the IC pins of the bread boar
 EXPERIMENT 8
Aim of the experiment: Design and Implementation of 3-bit synchronous
up/down counter

Objectives:
a. To learn the design of synchronous counter.
b. Verify the truth table in both the direction (up and down)

Apparatus/Components used:
1. IC 7476, / OR IC 74107 2NOS
2. IC 7408, IC7404, IC7432 1NOS/each
3. Patch Cords 8pcs
4. Components Development System

Theory in Brief:
A counter is a register capable of counting number of clock pulse arriving
at its clock input. Counter represents the number of clock pulses arrived.
An up/down counter is one that is capable of progressing in increasing
order or decreasing order through a certain sequence. An up/down
counter is also called bidirectional counter. Usually up/down operation of
the counter is controlled by up/down signal. When this signal is high
counter goes through up sequence and when up/down signal is low
counter follows reverse sequence. The circuit above is of a simple 3-bit
Up/Down synchronous counter using JK flip-flops configured to operate
as toggle or T-type flipflops giving a maximum count of zero (000) to
seven (111) and back to zero again. Then the 3-Bit counter advances
upward in sequence (0,1,2,3,4,5,6,7) or downwards in reverse sequence
(7,6,5,4,3,2,1,0).

Circuit Diagrams:
LOGIC DIAGRAM OF 3 BIT UP/DOWN SYNCHRONOUS COUNTER
 STATE DIAGRAM

CHARACTERESTIC TABLE

Q Q(t+1) J K

0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0

Procedure:
1. Collect all the components necessary to do the experiment.
2. Insert the IC chips onto the breadboard.
3. According to the logic diagram, make connections using wires.
4. Give the logic inputs as per circuit diagram and perform the experiment.
5. Observe the output and verify with the truth tables.
Observation:

Input Present State Next State

Up/Down
Qa Qb Qc Qa+1 Qb+1 Qc+1

0 0 0 0 0 0 1

0 0 0 1 0 1 0

0 0 1 0 0 1 1

0 0 1 1 1 0 0

0 1 0 0 1 0 1

0 1 0 1 1 1 0

0 1 1 0 1 1 1

0 1 1 1 0 0 0

1 0 0 0 1 1 1

1 0 0 1 0 0 0

1 0 1 0 0 0 1

1 0 1 1 0 1 0

1 1 0 0 0 1 1

1 1 0 1 1 0 0
1 1 1 0 1 0 1

1 1 1 1 1 1 0

Discussion:
The similarities between the implementation of a binary up counter and a
binary down counter leads to the possibility of a binary up/down counter,
which is a binary up counter and a binary down counter combined into
one. Since the difference is only in which output of the flip-flop to use, the
normal output or the inverted one, we use two AND gates for each flip-
flop to "choose" which of the output to use.
Conclusion: Therefore, the 3-bit synchronous Up/Down counter was
successfully implemented.

Precautions:
1. Check all the connections carefully.
2. Check if the IC is properly biased or not.
3. Connections on the bread board must be tight.
4. Identify the pins of IC properly.
5. Take care while inserting or removing the IC pins of the bread board.
 EXPERIMENT 9
Aim of the experiment: Design and Implementation of the various shift
Registers using flip flops

Objectives:
To design and implement
1. Serial in serial out shift register (SISO).
2. Serial in parallel out shift register (SIPO).
3. Parallel in serial out shift register (PISO).
4. Parallel in parallel out shift register (PIPO).

Apparatus/Components used:
Sl.no COMPONENT SPECIFICATION QTY
1. D flip flop IC7474 2
2. OR Gate IC7432 1
3. Components Development 1
system
4. Patch cords and wires As required

Theory in Brief: The Shift Register is another type of sequential logic

circuit that can be used for the storage or the transfer of data in the form
of binary numbers. This sequential device loads the data present on its
inputs and then moves or “shifts” it to its output once every clock cycle,
hence the name “shift register”.
Shift register IC’s are generally provided with a clear or reset
connection so that they can be “SET” or “RESET” as required. Generally,
shift registers operate in one of four different modes with the basic
movement of data through a shift register being:
 Serial-in to Parallel-out (SIPO) - The register is loaded with serial data,
one bit at a time, with the stored data being available at the output in
parallel form.
 Serial-in to Serial-out (SISO) - The data is shifted serially “IN” and “OUT”
of the register, one bit at a time in either a left or right direction under
clock control.
 Parallel-in to Serial-out (PISO) - The parallel data is loaded into the
register simultaneously and is shifted out of the register serially one bit at
a time under clock control.
 Parallel-in to Parallel-out (PIPO) - The parallel data is loaded
simultaneously into the register, and transferred together to their
respective outputs by the same clock pulse.

The effect of data movement from left to right through a shift register can
be presented graphically as:

Also, the directional movement of the data through a shift register can be
either to the left, (left shifting) to the right, (right shifting) left-in but right-
out, (rotation) or both left and right shifting within the same register
thereby making it bidirectional. In this manual, it is assumed that all the
data shifts to the right, (right shifting).
Circuit Diagrams:
PIN DIAGRAM OF IC7474
 LOGIC DIAGRAMS OF DIFFERENT SHIFT REGISTERS:
1) Serial in Serial out (SISO):

2) Serial in Parallel out (SIPO):

3) Parallel in Serial out (PISO):

4) Parallel in Parallel out (PIPO):

Procedure:
1. Collect all the components necessary to do the experiment.
2. Insert the IC chips onto the breadboard.
3. According to the logic diagram, make connections using wires.
4. Give the logic inputs as per circuit diagram and perform the
experiment.
5. Observe the output and verify with the truth tables.
 Observation:
TRUTH TABLE FOR SISO:
CLK Serial in Serial Data out
1 1 0
2 0 0
3 1 0
4 0 1
5 0 0
6 0 1
7 0 0

TRUTH TABLE FOR SIPO:

CLK Data I/p Output

Q3 Q2 Q1 Q0
1 1 1 0 0 0
2 0 0 1 0 0
3 1 1 0 1 0
4 0 0 1 0 1

TRUTH TABLE FOR PISO:

CLK Data I/P Output
Q3 Q2 Q1 Q0
0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 1

TRUTH TABLE FOR PIPO:

CLK Data Input Output
DA DB DC DD Q3 Q2 Q1 Q0
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0

Discussion:
Shift Registers are used for data storage or for the movement of data and
are therefore commonly used inside calculators or computers to store
data such as two binary numbers before they are added together, or to
convert the data from either a serial to parallel or parallel to serial format
Conclusion: From the experiment, we can conclude that the Shift Register
was successfully implemented and observed for different data inputs.
SISO, SIPO, PISO, PIPO type shift registers were studied and the
corresponding truth tables were filled.

Precautions:
1. Check all the connections carefully.
2. Check if the IC is properly biased or not.
3. Connections on the bread board must be tight.
4. Identify the pins of IC properly.
5. Take care while inserting or removing the IC pins of the bread board.
 EXPERIMENT 10
Aim: To construct an analog to digital convertor by using R 2R Ladder
network and 741 Opamp.
Objectives:
1. Design the circuit diagram
2. Measure the DC output voltage (Op-Amp pin 6)
3. Demonstrate the digital input and analog output using LED
4. Draw the D/A transfer curve.

Components required:
1. Resistors (1KΩx4, 2.2 KΩx5)
2. 741 Op Amp
3. Patch Cord -10pcs
Theory:
Digital-to-Analog Converter: An electronic device, often an integrated
circuit, that converts a digital number into a corresponding analog voltage
or current. Digital to analog converter (DAC) is used to get analog voltage
corresponding to an input digital data. Data in binary digital form can be
converted to corresponding analog form by using a R-2R ladder network
and a summing amplifier. It is more common and practical. Below is the
circuit and output simulated waveform of R-2R ladder network DAC. This
circuit also uses an op amp (741) summing amplifier circuit. You can learn
how to build a Digital to Analog converter using the simple technique
explained in this page. Actually different types of Digital to Analog
converter ICs are available commercially based on this same principle.
The R-2R ladder network is built by a set of resistors of two values. It
makes the circuit simpler and economical for different applications.
General DAC Characteristics There are six key parameters you should
consider when choosing a DAC.
• Reference Voltage
• Resolution
• Linearity
• Speed
• Settling Time
• Error
Working of R-2R ladder network DAC with R =1kΩ, 2R = 2kΩ:
R-2R weighted resistor ladder network uses only 2 set of resistors- R and
2R. If you want to build a very precise DAC, be precise while choosing the
values of resistors that will exactly match the R-2R ratio.
 This is a 4 bit DAC. Let us consider the digital data D3D2D1D0= 0001 is
applied to the DAC, then the Thevenin equivalent circuit reduction is shown
below. (If R=1K, and 2R=2K)
 Vref is nothing but the input binary value reference voltage, that is for
binary 1, Vref=5V and for binary 0, Vref=0V.
 For 0001 only D0=Vref, all other inputs are at 0V and can be treated as
ground. So finally Vref/16 volt is appearing as the input to op amp. This
value gets multiplied by the gain of op amp circuit – (Rf/Ri).
 If we proceed in this manner (Thevenin equivalent reduction), we will
get
Vout = -(Rf/Ri) Vref [(D0/16) +(D1/8) +(D2/4) +(D3/2)]
Circuit Diagrams:

Procedure:
1. Collect all the components necessary to do the experiment.
2. Insert the IC chip onto the breadboard.
3. According to the logic diagram, make connections using wires.
4. Give the logic inputs as per circuit diagram and perform the
experiment.
5. Observe the output and verify with the truth tables.

Observation:
Digital Input (4 Bit Binary) Analog O/P O/P
DC Voltage Voltage
D3 D2 D1 D0 Practical
0 0 0 0 0 -0.133
0 0 0 1 -0.625 -0.75
0 0 1 0 -1.25 -1.33
0 0 1 1 -1.875 -1.997
0 1 0 0 -2.50 -2.42
0 1 0 1 -3.125 -3.08
0 1 1 0 -3.75 -3.367
0 1 1 1 -4.375 -4.35
1 0 0 0 -5 -4.47
1 0 0 1 -5.625 -5.12
1 0 1 0 -6.25 -5.68
1 0 1 1 -6.875 -6.36
1 1 0 0 -7.5 -6.78
1 1 0 1 -8.125 -7.45
1 1 1 0 -8.75 -8.04
1 1 1 1 -8.75 -8.05

Output Waveform:
Discussion:
 Note that you can build a DAC with any number of bits you want, by
simply enlarging the resistor network, by adding more R-2R resistor
branches.
 In this circuit the 7493 IC simply provides digital inputs to DAC. It is a
counter IC and not an integral part of the DAC circuit. You can apply
any combinations of binary inputs to D3 D2 D1 D0
Conclusion: Therefore, the Digital to Analog convertor using R 2R ladder
network is successfully designed and verified.
Precautions:
1. Check all the connections carefully.
2. Check if the IC is properly biased or not.
3. Connections on the bread board must be tight.
4. Identify the pins of IC properly.
5. Take care while inserting or removing the IC pins of the bread board.