An Improved Strong Arm Comparator With Integrated Static Preamplifier

This article has been accepted for publication in IEEE Access.
This is the author's version which has not been fully edited and
content may change prior to final publication. Citation information: DOI 10.1109/ACCESS.2023.3308447
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Digital Object Identifier 10.1109/ACCESS.2023.0322000
An Improved Strong Arm Comparator with

Integrated Static Preamplifier
VALERIO SPINOGATTI, RICCARDO DELLA SALA, CRISTIAN BOCCIARELLI,FRANCESCO
CENTURELLI(Senior Member, IEEE), ALESSANDRO TRIFILETTI
Sapienza, University of Rome, Italy, Rome, Via Eduossiana 18, 00184
Corresponding author: Francesco Centurelli (e-mail: [email protected]).
ABSTRACT This paper presents a novel Strong Arm comparator in which the input pair is reused as a
static amplifier to preamplify the input signal during the precharge phase. The proposed approach relaxes
the main trade-offs that characterize the Strong Arm latch: compared to the conventional topology, the
enhanced comparator achieves better input-referred noise and offset, without penalizing delay nor power
consumption. In fact, the proposed topology is even more efficient than its conventional counterpart as it
exhibits lower power consumption when the two circuits are sized to have the same delay. The operation
of the new topology is analyzed in detail through a comprehensive theoretical analysis, providing useful
design criteria. The enhanced Strong Arm comparator is validated by means of post-layout simulations in
a 55 nm CMOS technology with 1 V supply. The simulations show that the proposed approach improves
noise, offset and energy-delay product (EDP) respectively by 28.5%, 33.8% and 5.24% compared to the
conventional Strong Arm latch.
INDEX TERMS Strong Arm, High speed, Dynamic comparator, Analog-to-digital conversion (ADC)
I. INTRODUCTION increase in power consumption. The authors of [6] propose

Due to the inherent robustness of digital processing, modern to modify the topology so that a pair of reset devices can be
communication systems are usually designed to perform most removed, which results in smaller delay and power consump-
of the processing in the digital domain. This trend, combined tion. In [3], instead, an improvement in comparison speed is
with the demand for systems that are capable of handling achieved by creating several additional current paths during
high bit rates, makes the development of fast, power efficient the evaluation phase; such paths discharge asymmetrically the
mixed-signal building blocks a research topic of fundamental output nodes according to the input differential signal, thus
importance. helping improve the regeneration time. Similarly, [2] pro-
Dynamic comparators are an essential part of most mixed- poses to ease regeneration by unbalancing the outputs. Differ-
signal applications, such as analog-to-digital converters ently from the previous reference, however, they achieve this
(ADC) and digital low drop-out regulators (DLDO) and thus result by creating static current paths during the comparator’s
enhancing the figures of merit of these components is crucial precharge phase.
for improving the performance of the systems they belong to Another (significant) part on the literature focuses on de-
[1]–[3]. veloping strategies for increasing the preamplification gain in
Among dynamic comparators, the Strong Arm latch is one order to improve the performance in terms of input-referred
of the most popular topologies in high-speed applications at offset and noise. The technique known as dynamic bias, for
medium-to-high supply voltages because of its many attrac- instance, boosts the gm /Id ratio of the transistors involved
tive features, namely low power consumption, limited input- in dynamic preamplification by limiting their gate-source
referred offset, rail-to-rail output swing and minimal circuit voltages [7]–[9]. The main limitation of dynamic bias consists
complexity [4]. Owing to such popularity, numerous efforts in the fact that it increases significantly the delay of the
have been made in the literature with the intent of further comparator because it increases the duration of the pream-
improving the performance of this topology. Numerous pro- plification phase [7]. Charge-pump based dynamic bias [10],
posals focus on relaxing the trade-off between speed and [11] addressess this issue by coupling a negative voltage
power consumption: in [1], [5], for instance, forward body- step to the source node of the dynamic preamplifier, which
bias (FBB) is exploited to improve speed with a negligible increases temporarily the overdrive voltage of the differential
VOLUME 11, 2023 1
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Spinogatti et al.: An Improved Strong Arm Comparator with Integrated Static Preamplifier
pair and speeds up preamplification. However, this comes offset as the asymmetry that had been created by the
at the cost of an increase in power consumption. There are previous decision is canceled.
also alternative approaches that investigate the use of static • Evaluation (CLK = VDD ): M7 turns on and S1 through
preamplifiers to relax the comparator’s specifications. The S4 turn off. M1 and M2 discharge asymmetrically nodes
traditional approach consists in cascading one or more static P and Q. When VPQc ≜ (VP + VQ )/2 drops to ≈ VDD −
amplifiers, usually implemented as simple differential pairs, Vth,n (Vth,n being the threshold voltage of the NMOS
before the dynamic comparator [12]. In this way, noise and transistors) M3 and M4 turn on and start discharging
offset are suppressed and the delay improves, but power asymmetrically the output nodes. Even though M3 -M4
consumption and area occupation increase significantly. In form a positive feedback loop, they provide little regen-
[13], the input differential pair is removed and the positive eration in this phase because their drain terminals are
feedback loop is unbalanced in the proper direction by driving connected to the comparator’s load capacitance. When
the body terminals of the latch’s devices. This minimizes Voc ≜ (Vop + Von )/2 reaches ≈ VDD − Vth,p (Vth,p being
the number of devices in the dynamic comparator. A CMOS the threshold voltage of the PMOS devices) the pair of
static preamplifier with common-mode feedback (CMFB) cross-coupled inverters formed by M3 through M6 starts
is added to compensate for the reduction in preamplifica- to regenerate the signal to full swing.
tion gain, which is caused by the fact that gmb (the body The main strengths of the Strong Arm comparator are
transconductance) is several times lower than gm . As a result, summarized below:
the comparator achieves very high speed operation without
• Delay and power consumption are low because of the
impairing preamplification, as demonstrated by the low input-
limited number of transistors.
referred noise.
• Static power consumption is virtually zero thanks to the
This paper introduces an improved Strong Arm comparator
CMOS configuration used in the latch.
where the preamplification gain is boosted by amplifying the
• The input-referred offset is limited as it mainly depends
input difference during the precharge phase. This is achieved
on the mismatch of the input differential pair. In fact, the
by adding a clocked resistive load to the drain nodes of the
offset contributions from transistors M3 through M6 are
input differential pair and a static tail generator biased by a
attenuated because these devices turn on when the signal
current mirror. This results in a significant improvement in
has been already partially amplified.
terms of noise and input-referred offset with no penalty on
• The pair of cross-coupled latches regenerates the signal
delay nor power consumption. Indeed, our simulations show
to full swing: therefore, the comparator’s outputs can be
that the energy-delay product (EDP) improves as well, albeit
connected to CMOS digital blocks without the need for
by a smaller extent. Therefore, the proposed technique relaxes
interface blocks.
the trade-offs that affect the Strong Arm latch at the only cost
of a slight increase in area and layout complexity. In addition,
a detailed theoretical analysis is provided, showing that the A. STRONG ARM LATCH WITH PREAMPLIFIER
performance of the proposed comparator can be optimized by The delay, noise and input-referred offset of the Strong Arm
varying the explicit load resistance and the static bias current. latch (and, in general, of a dynamic comparator) can be
The theoretical analysis is then validated through circuit-level improved by adding a static preamplifier before the compara-
simulations. tor’s input, as shown in Figure 2.
This work is organized as follows: section II briefly recalls The preamplifier usually consists of a simple differential
the operating principle and the properties of the conven- pair biased at constant current. If a resistive load is used (as
tional Strong Arm latch. Section III introduces the proposed shown in the Figure) no common-mode feedback (CMFB)
topology and describes its operating principle. In section IV, is required. To a first approximation, a static preamplifier
a theoretical analysis of the proposed topology is carried with gain equal to Av reduces the comparator’s noise and
out. Section V describes the sizing that has been adopted offset contribution by a factor equal to Av . Delay, on the other
to simulate the proposed and the conventional Strong Arm hand, scales logarithmically with Vid : this implies that the
comparator. In section VI the theoretical analysis is validated delay tdpreamp of the comparator with a preamplifier can be
by means of pre-layout simulations and the performance of computed as td − ln(Av ), where td is the delay that the com-
the proposed comparator is evaluated through post-layout parator would exhibit if no preamplifier was used. Clearly,
simulations. A comparison with the recent state of the art is these improvements come at the expense of an increase in
also provided. Finally, section VII concludes the paper. power consumption. Indeed, the minimum bias current of the
preamplifier is bounded below by the specification on the
II. CONVENTIONAL STRONG ARM LATCH bandwidth that, in turn, depends on fCLK .
Figure 1 shows the schematic of the conventional Strong Arm
latch. The operation of the comparator is as follows: III. PROPOSED TOPOLOGY
• Precharge (CLK = GND): M7 is in off state, while The power consumption and area overhead that come with
devices S1 through S4 precharge the output and interme- the addition of a static preamplifier can be minimized by
diate nodes to VDD . This eliminates the signal-dependent reusing the input pair transistors M1 -M2 to preamplify the
2 VOLUME 11, 2023
FIGURE 1. Schematic of the conventional Strong Arm latch.
FIGURE 2. Schematic of the conventional Strong Arm latch with preamplifier.
VOLUME 11, 2023 3
input difference during the precharge phase, as shown in already unbalanced according to the input difference
Figure 3. More specifically, there are three key points to this during precharge. This increases the differential voltage
topology: that builds up at nodes P and Q until M3 and M4 turn
• During the precharge phase, the tail current for M1 -M2 on, and ultimately results in improved performance in
is provided by an additional static generator that can be terms of delay, offset, and noise. Note that there is no
implemented as a current mirror. This way, the signal is need to switch off the static generator during evaluation,
preamplified with limited power consumption because because the CMOS latch formed by M3 -M4 -M5 -M6 cuts
Ib is set by a reference branch. the path between VDD and GND as soon as the outputs
• The preamplifer’s load is represented by a pair of saturate. Moreover, the static generator helps improve
clocked devices connected in series to resistors R1 -R2 . delay because it increases the total tail current.
Hereafter we will assume that R1 = R2 = R. Adding a It is important to remark that the proposed topology con-
resistive load boosts the preamplification gain because strains the setup time of the input signal. Specifically, if
the load resistance seen by M1 -M2 increases. the input difference does not settle sufficiently in advance
• The output nodes are reset with a modified scheme with respect to the rising clock edge the comparator might
that combines the approach used in the original Strong produce a wrong output because preamplification is impaired.
Arm latch [14] with the pull-up based configuration However, this issue also exists when a static preamplifier is
employed in the Razavi Strong Arm [4]. Thanks to this added before the comparator’s input; therefore the proposed
configuration, only S5 is responsible for eliminating the preamplification technique does not add constraints with re-
signal-dependent offset. Transistors S3 and S4 , on the spect to the conventional one.
other hand can be made much smaller. Note that S3
and S4 cannot be eliminated completely: indeed, the IV. THEORETICAL ANALYSIS
comparator performs better if the outputs are precharged A. ANALYSIS OF THE LOAD RESISTANCE
close to VDD , because the circuit has more time to pream- a: Existence of the optimum
plify the signal before the latch takes over. Moreover,
The load seen by M1 -M2 during the reset/preamplification
these devices ensure that S5 turns on completely. The
phase depends on the nonlinear interaction between the load
combination of S3 -S4 -S5 helps reducing power con-
resistance R and M3 (or M4 ). In this subsection we show that
sumption without increasing the reset time because the
there exists an optimal choice of R that maximizes the total
overall parasitic capacitance is smaller.
small-signal load resistance.
It should be noted that a similar approach, based on us- During the reset phase S5 short-circuits the output nodes
ing the comparator’s devices for preamplification, has been and M5 -M6 turn off. M3 -M4 become diode-connected. There-
already devised in [2]. However, our comparator achieves fore, the behavior of the total load resistance as a function
better performance in terms of power consumption thanks to of R can be investigated by considering the equivalent half-
the additional tail generator that limits current consumption circuit depicted in Figure 4a. In the circuit Ih represents the
during the reset phase. Furthermore, the clocked resistive load bias current and RD is the explicit load resistance in parallel
causes higher differential voltages to build up during the reset to M3 . The series resistance associated to the switches S1 -S2 -
phase, which improves noise and offset. S3 -S4 is neglected, which implies RD = R. Moreover, a small-
The operation of the proposed comparator is as follows: signal test current iT is added to compute the load resistance.
• Precharge/preamplification (CLK = GND): During The conductance associated to each resistance will be denoted
precharge, the output nodes are equalized by the reset by the letter G (with the same pedix). Now let Vgs = VgsQ +vgs ,
transistor S5 while S3 -S4 pull them up to ≈ VDD . The where VgsQ denotes the bias point and vgs represents the small-
clocked tail transistor M7 is off. At the same time M1 signal component. Then, we can write
and M2 , biased by the static tail generator, preamplify vgs
the input difference thanks to the clocked load (S1 -S2 - iT = −(gm3,4 + GD )vgs = − (1)
RPQ
R1 -R2 ). It should be noted that the total load seen by
M1 and M2 is given by the parallel of the clocked load where gm3,4 is the small-signal transconductance of M3 and
resistance and the source resistance of M3 -M4 . The key RPQ ≜ 1/(gm3,4 + GD ). The drain-source conductancegds3
aspect is that the explicit load resistors R1 -R2 can act as is neglected. Now we note that gm3,4 = gm3,4 VgsQ (RD ) . To
a weak pull up network that limits the Vgs of M3 -M4 and, prove that RPQ has a maximum, it is sufficient to demonstrate
consequently, their transconductance. Hence, a proper that VgsQ is a strictly increasing function of RD . Indeed, if
choice of R can prevent the active devices from limiting this is true, GPQ = 1/RPQ is the sum of a strictly decreasing
the preamplifier’s load resistance. This idea is discussed function that goes to infinity as RD → 0 and tends to 0 as
in greater detail in section IV. RD → ∞ (i.e., the function GD = 1/RD ), and a strictly
• Evaluation (CLK = VDD ): M7 is on while S1 through increasing function whose limit for RD → 0 is finite (i.e., the
S5 are off. The comparator works like a conventional function gm3,4 ).This means that GPQ has a (unique) minimum
Strong Arm, except for the fact that VP and VQ have been point.
4 VOLUME 11, 2023
FIGURE 3. Schematic of the proposed enhanced Strong Arm latch.
a) b)
FIGURE 4. Equivalent circuits for analyzing the load resistance as a function of RD a) and the evolution of VPQd as a function of time b).
The relationship between VgsQ and RD can be studied by when VgsQ > Vth :
setting iT = 0 (which implies vgs = 0) and writing Kirch- ( Vgs −Vth Vgs
Q Q
hoff’s law at node P: Id3,4 (VgsQ ) = Id0 e nUT (1 − e UT ) VgsQ ≤ Vth (3)
Id3,4 (VgsQ ) = k(VgsQ − Vth )2 VgsQ > Vth
GD VgsQ + Id3,4 (VgsQ ) = Ih (2)
where UT is the thermal voltage, Vth is the transistor’s thresh-
old voltage and k ≜ 12 µCox WL is the transconductance factor
where Id3,4 represents the drain current of M3 . In this analysis, of the device. It should be noted that equation (2) does not
we adopt the exponential model to describe Id3,4 in the sub- have a closed-form solution when VgsQ < Vth . This is not an
threshold region and the square law to describe its behavior issue, however, because we can prove that ∂gm3,4 /∂RD > 0
VOLUME 11, 2023 5
without solving equation (2) in the unknown VgsQ . First, we Recalling that GPQ = gm3,4 (RD ) + 1/RD and using equation
solve the equation for RD , obtaining (9), we obtain
1
VgsQ R∗PQ = q (10)
RD (VgsQ ) = (4)
Ih − Id3,4 (VgsQ ) 2 k(Ih − Ĩ )
We then take the first derivative of RD with respect to VgsQ : If V ∗ < Vth , the drain current follows an exponential
∂RD Ih − Id3,4 (VgsQ ) + Vgs gm3,4 (VgsQ ) law and equation (6) does not have a closed-form solution.
= 2 (5) However, the analysis we performed in the previous subsec-
∂VgsQ Ih − Id3,4 (Vgs ) Q tion guarantees that RPQ (RD ) has a unique maximum point.
Now we observe that Ih = Id3,4 + GD VgsQ ≥ Id3,4 and In addition, we can carry out an approximated analysis by
that gm3,4 (VgsQ ) > 0. Hence, the right side of equation making the following assumptions:
(5) must be positive as well. But RD (VgsQ ) is the inverse • The drain current of the active device is small when
function of VgsQ (RD ), so its derivative must have
the same RD = R∗D , i.e., we have Id3,4 (V ∗ ) << Ih .
sign as ∂VgsQ /∂RD . This means gm3,4 VgsQ (RD ) is a strictly • The exponential behavior of Id3,4 (Vgs ) is approximated
increasing function, because it is the composition of two as a on-off behavior: more precisely, we suppose that M3
strictly increasing functions. We have thus demonstrated that does not conduct any current for Vgs ≤ V ∗ and it turns
RPQ (RD ) has a maximum point. We will denote by R∗D the on abruptly when Vgs > V ∗ .
value of RD that maximizes RPQ . If these hypotheses are verified the equation
b: Evaluation of the optimum Vgs ≈ RD Ih (11)
In order to compute analytically the value of RD that maxi-
represents a reasonable approximation for Vgs ≤ V ∗ . It
mizes RPQ , we make an assumption on the transistor’s oper-
follows that
ating region and solve the equation V∗
R∗PQ ≈ R∗D ≈ (12)
∂GD (VgsQ ) ∂gm3,4 (VgsQ ) Ih
+ =0 (6)
∂VgsQ ∂VgsQ because we assume that RPQ starts to decrease as soon as
The solution of equation (6), which we call V , represents ∗ Vgs exceeds V ∗ . Clearly, the analysis we just presented is
the voltage drop across the load when RD = R∗D . Once the limited in that it does not provide an expression for V ∗ ;
analytical expression of V ∗ is known, R∗D may be computed nonetheless equation (12) is useful because it describes with
by letting VgsQ = V ∗ in equation (4). reasonable accuracy the behavior of R∗PQ as a function of Ih .
Assume that V ∗ > Vth , i.e., the transistor is biased above This point will be clarified in subsection IV-C, where we
the threshold when RD = R∗D . Then, using equations (3) and study the compromise between power consumption and static
(4), equation (6) can be rewritten as preamplification gain in the proposed topology.
2k(VgsQ − Vth )VgsQ + Ih − k(VgsQ − Vth )2 B. ANALYSIS OF THE PREAMPLIFICATION GAIN
2k − =0 (7)
Vgs2 Q In this subsection we derive an expression for the preampli-
By solving for VgsQ we get fication gain of the proposed comparator. In the analysis that
r s follows we denote by VPQd and VPQc the output differential
I − kV 2 Ih − Ĩ mode voltage and the output common mode voltage of the
h
V∗ = th
= (8) preamplifier, respectively. The duration of the reset phase will
k k
be denoted by trst ≜ tready + ts , with tready ≥ 0 being the
where Ĩ represents the drain current of the diode-connected worst-case settling time of the input signal (measured from
transistor M3 when VgsQ = 2Vth . Note that Ĩ is an intrinsic the beginning of the reset phase) and ts > 0 being the time
property of the device. Equation (8) is useful in two ways: available for VPQd to settle. Furthermore, we denote by td the
∗
• It provides an analytical expression of V in the case duration of the dynamic preamplification phase, that starts
∗
V > Vth with the rising edge of the clock. Finally, we assume that Vid
∗
• It provides a criterion to establish whether V > Vth or is a step function:
∗
V < Vth . Indeed,qthe solution we found has a physical (
Vid = 0, t < tstep
meaning only if Ih − k
Ĩ
> Vth , which is equivalent to (13)
Vid = Vs , t ≥ tstep
Ih > 2Ĩ . If Ih < 2Ĩ , there is no meaningful solution
to equation (7), which means that M3 must be in the where Vs is a small constant voltage. For the sake of conve-
subthreshold region when RD = R∗D . nience, the origin of the time axis is set at the instant in which
By substituting V ∗ into equation (4) and simplifying the Vid changes its value, which implies tstep = 0. With these
resulting expression we obtain hypotheses, the falling clock edge that marks the beginning
1 of the reset phase occurs at t = −tready and the rising clock
R∗D = (9) edge that marks the end of the reset phase occurs at t = ts .
2kVth
6 VOLUME 11, 2023
As a starting point, we observe that during the interval [0, ts ] shortly after turning on and its current varies significantly
the input differential voltage Vs is amplified by the subcircuit during dynamic preamplification. With this hypothesis, Id1
consisting of the active devices M1 -M2 -M3 -M4 , the resistors and Id2 are also constant and we may write
R1 -R2 and the static generator Ib . This creates a non-zero
initial condition for the subsequent phase, that takes place Id1 td
∆VP = (18)
during the interval [ts , ts + td ]. During this phase, nodes P and CPQ
Q are discharged asymmetrically and their voltages drop by
different amounts, which we call ∆VP and ∆VQ , respectively. Id2 td
We can thus write ∆VQ = (19)
CPQ
VPQd (td )
VP (ts + td ) = VPQc (ts ) + − ∆VP (14) Subtracting the two equations we obtain
2
VPQd (td ) (Id1 − Id2 )td g′m1,2 td Vs
VQ (ts + td ) = VPQc (ts ) − − ∆VQ (15) ∆VP − ∆VQ = = (20)
2 CPQ CPQ
Subtracting equation (15) from equation (14) we obtain
If, as it is usually done, we assume that the end of the pream-
VPQd (ts + td ) = VPQd (ts ) − (∆VP − ∆VQ ) (16) plification phase coincides with the time instant in which VPQc
Now we will derive analytical expressions for VPQd (ts ), ∆VP falls below VDD − Vth [4], we may express td as
and ∆VQ .
CPQ (VPQc (ts ) − Vth )
We start by computing VPQd (ts ). To this end, we linearize td = (21)
the circuit, based on the following observations: Itail
• The differential input signal Vs is assumed to be small. Then, equation (20) can be rewritten as
• The differential signal starts to be preamplified tready
seconds after the beginning of the reset phase. If tready g′m1,2 (VPQc (ts ) − Vth )Vs
is greater than zero and represents a significant fraction ∆VP − ∆VQ = (22)
Itail
of trst (e.g. at least 1/3 of the reset time), we can assume
VPQc to have settled at least partially by the time VPQd The preamplification gain is defined as
begins to settle. This hypothesis is verified in several
applications, such as SAR ADCs, and it allows us to ne- VPQd (ts + td )
Apre ≜ (23)
glect the variation of the small signal parameters caused Vs
by the settling of VPQc . If the condition we just described
Hence, we have
does not hold, the circuit may still be analyzed by using
small signal parameters averaged over the preamplifier’s
Apre = Apre,s + Apre,d (24)
output common mode swing. In this case, of course, the
error associated to the small signal approximation will
where
be higher. ( ts
Within the linear approximation, the gain error can be com- Apre,s = −gm1,2 RPQ (1 − e− τ )
g′m1,2 (VPQc (ts )−Vth ) (25)
puted by referring to the equivalent small-signal circuit de- Apre,d = − Itail
picted in Figure 4. By analyzing the circuit in the Laplace
domain, it is straightforward to show that We now recall the expression of the preamplification gain of
ts the conventional Strong Arm [4]:
VPQd (ts ) = −gm1,2 RPQ (1 − e− τ )Vs (17)
g′m1,2 (VDD − Vth )
where τ = RPQ CPQ . Note that the quantity gm1,2 RPQ repre- Aconv
pre = − (26)
sents the steady state gain A∞ Itail
vd .
In order to compute ∆VP and ∆VQ we have to take into Comparing equations (24) and (26), we notice that the pro-
account that M7 is on during the interval [ts , ts + td ]. This posed topology improves the preamplification gain with the
implies that: addition of the term Apre,s , but this comes at the expense of a
• The total tail current is given by Itail = Id7 + Ib , with decrease in the magnitude of the dynamic term Apre,d because
Id7 >> Ib . VPQc (ts ) is less than VDD . Despite this, the total gain can be
• The transconductance of M1 -M2 increases significantly expected to improve compared to the conventional Strong
because their drain current increases. We denote by g′m1,2 Arm because the static preamplifier can achieve a higher gain
the transconductance of the input pair during dynamic compared to a purely dynamic one. This is confirmed by the
preamplification. simulations, which show that the enhanced Strong Arm has
For the sake of simplicity, Id7 is assumed to be constant: this better performance in terms of input-referred noise and offset
is obviously an approximation, as M7 enters the triode region with respect to its conventional counterpart.
VOLUME 11, 2023 7
C. TRADE-OFF BETWEEN SETTLING ERROR AND ENERGY as it is relatively convoluted and offers limited insight on the
EFFICIENCY operation of the circuit.
a: Energy-settling trade-off as trst changes At this point, it should be remarked that usually the de-
The presence of the static current generator Ib gives rise to signer is not allowed to choose trst , because the frequency and
a trade-off between the energy efficiency and the settling duty cycle of the clock signal are both fixed. In this case, we
error affecting the static preamplification gain. Assume that can rewrite R as a function of Ib and RPQ and formulate a
it is possible to change the duration of the reset phase trst . A constrained optimization problem in which RPQ = R∗PQ . This
shorter reset time results in smaller power consumption, at the requires us to distinguish between the case in which V ∗ > Vth
expense of the static preamplification gain Apre,s . If, instead, and the case in which V ∗ < Vth .
we increase trst the gain improves because the preamplifier
is given more time to settle. However, power consumption in- b: Energy-settling trade-off as Ib changes and V ∗ > Vth
creases because the tail generator draws more charge from the As shown inqsubsection IV-A, the condition V ∗ > Vth implies
supply. After a certain point, increasing the preamplification R∗PQ = 1/2 k(Ih − Ĩ ), where Ih = Ib /2. By substituting this
time becomes counterproductive because the gain saturates. relationship into the expression of R we obtain
To formalize this reasoning we propose the following reward q
Ib
− C2ts k( −Ĩ )
function: 1−e 2 PQ
trst −tready
R(Ib ) = (29)
|Apre,s (trst )| 1 − e− τ Edyn + VDD Ib trst
R(trst ) = = (27)
A∞pre,s E Edyn + VDD Ib trst where we used the fact that ts = trst − tready to simplify the
expression. Similarly to the previous paragraph, the equation
where Edyn is the energy absorbed to charge and discharge the ∂R(Ib )/∂Ib = 0 does not have a closed-form solution, but
parasitic capacitances during a clock cycle and VDD Ib (trst ) is we can prove the existence of at least one maximum point.
the energy absorbed by the static tail generator during a clock Indeed, the numerator of the derivative ∂R(Ib )/∂Ib consists
cycle. The quantity E(trst ) ≜ Edyn + VDD Ib trst represents the of two terms, which we denote by A(Ib ) and B(Ib ), whose
total energy absorbed by the circuit to perform a comparison expressions are reported below:
(reset phase included). Hence, R(trst ) is the ratio between q
I
the (normalized) static preamplification gain and the energy − 2Cts k( 2b −Ĩ )
2ktpre e PQ Ib
per comparison. Three important observations must be done A(Ib ) = q (Edyn + VDD trst ( − Ĩ )) (30)
CPQ Ib
− Ĩ 2
before carrying on with the analysis: 2
• The dynamic term is assumed to be constant because we q
VDD trst − ts
I
k( 2b −Ĩ )
hypothesize that trst is long enough for VPQc to achieve B(Ib ) = − (1 − e 2CPQ ) (31)
2
at least a rough settling and, in general, that the clock
period is enough for all the main charge/discharge tran- Clearly, A(Ib ) > 0 for every Ib ≥ 0 and limIb →∞ A(Ib ) = 0.
sients to settle. The transient of VPQd is not included in Moreover, we have that B(Ib ) < 0 for every Ib > 0, B(Ib =
this hypothesis because the energy consumption associ- 0) = 0 and limIb →∞ B(Ib ) < 0. Hence, R(Ib ) has at least one
ated to it is negligible (recall that Vid is small). maximizer.
• Apre,s has been rewritten as a function of trst by using the
relation ts = trst − tready . c: Energy-settling trade-off as Ib changes and V ∗ < Vth
When V ∗ < Vth there is no closed-form expression for
We now wish to study the behavior of R(trst ) in the interval
V ∗ . However, as explained in subsection IV-A, we may
[tready , ∞). To this end, we take its first derivative:
carry out an approximated analysis if we hypothesize that
trst −tready trst −tready Id3,4 (V ∗ ) << Ih and that Id3,4 starts to increase abruptly
∂R e− τ E(trst ) − VDD Ib (1 − e− τ )
= (28) when Vgs > V ∗ . With these assumptions, we have that
∂trst E(trst )2 R∗PQ ≈ 2V ∗ /Ib . In addition, we approximate V ∗ as indepen-
In order to maximize R(trst ) we should solve the transcenden- dent from Ib . This assumption is not backed by mathematical
tal equation ∂R(trst )/∂trst = 0. Although this equation does considerations, but it works well in practice, as we shall
not have a closed-form solution, we can prove that R(trst ) has demonstrate in section VI. By substituting the relationship
a maximum. Indeed, by inspecting the numerator of equation R∗PQ = 2V ∗ /Ib in the expression of R we obtain
(28) it is easy to recognize that it is the sum of a strictly −
Ib ts
positive term and a negative term. The positive term, that is, 1 − e Vth CPQ
trst −tready R(Ib ) = (32)
e− τ E(trst ), vanishes as trst → ∞. The negative term, Edyn + VDD Ib trst
trst −tready
that is, −VDD Ib (1 − e− τ ), is null when trst = tready and In this case, the function R(Ib ) has the same form as R(trst ),
tends to a finite negative value as trst → ∞. Therefore R(trst ) which means the considerations we made for R(trst ) also hold
must have at least a maximum point in the interval [tready , ∞) for R(Ib ). Specifically, for a given trst and a given tready there
because it is a continuous function. It is also possible to prove exists an optimum choice of the tail current, which denote as
that the maximum is unique, however the proof is omitted Ib∗ , that maximizes the objective function.
8 VOLUME 11, 2023
V. SIZING TABLE 1. Sizing of the conventional and proposed comparators. All

transistors have minimum channel length, that is, L = 60 nm.
To assess the effectiveness of the proposed approach, the
enhanced Strong Arm comparator was designed and laid out W [µm]
Device
in Cadence Virtuoso in a 55 nm CMOS technology with Conventional Proposed
M1 8 8
1 V supply. A standard Strong Arm comparator was also M2 8 8
designed and laid out in the same technology to provide a M3 2 2
reliable benchmark. Both layouts were carefully optimized M4 2 2
M5 2 2
so as to maximize symmetry, in order to limit the systematic M6 2 2
input-referred offset, and are shown in Figure 5. The area M7 16 6
occupation of the conventional Strong Arm latch is about S1 , s2 0.5 0.2
S3 , s4 0.5 0.15
12.38 µm × 9.44 µm ≈ 116.9 µm²; the enhanced comparator, S5 - 0.4
instead, occupies an area of approximately 14.2 µm × 10.26
µm ≈ 145.7 µm². All the results reported in section VI have
been obtained from post-layout simulations, except where a: Load resistance optimization
otherwise stated. Table 1 shows the sizing of the active This section contains a validation of the analysis developed
devices in the conventional and in the proposed comparator. in subsection IV-A. The validation is based on pre-layout
The two circuits were sized in such a way to obtain the same simulations because it requires a sweep on the value of R.
delay. The channel widths of the active devices are almost As already explained in section V, in our sizing RD does not
identical for the two circuits, the only exceptions being S1 , coincide with R because the on resistance of S3 -S4 is not
S2 , S3 , S4 and M7 . In the proposed topology the width of negligible; specifically we have RD = R+Rswitch where Rswitch
M7 is smaller because VPQc is precharged to VDD − VPQc (ts ), is comprised between ≈ 6 kΩ and 9 kΩ. In the discussion
which causes the latch to turn on earlier. For this reason, the that follows we assume Rswitch ≈ 7.5 kΩ. Because Ĩ is several
tail current is reduced in order to slow down the discharge of hundreds of µA and Ih = 20 µA we have Ih < 2Ĩ , which
the intermediate nodes and ensure that the two comparators implies that M3 -M4 are biased in the subthreshold region for
have the same delay. RD = R∗D .
A small aspect ratio is chosen for S1 -S2 in order to use their Figure 6 shows the simulated behavior of the small-signal
equivalent resistance as part of the load; in other words, we resistance of the preamplifier load as a function of R. In
have RD = Rswitch + R, where Rswitch is the on resistance of the accordance with the theory, RPQ has a unique maximum point
switches. This helps reduce the area and the parasitic capaci- in R = R∗ ≜ 8 kΩ, which implies R∗D = 15 kΩ. It should be
tance associated to the resistive load because the same value noted that R∗D does not have an analytical expression because
of RD can be achieved with a smaller R. The aspect ratio of the optimum falls in the subthreshold region. Despite this, we
S3 -S4 is also small because in the proposed comparator these can compare the results of the simulation to the approximated
transistors are not responsible for equalizing the outputs. analysis developed in section IV-A because Id3,4 (R∗D ) ≈
The proposed topology also features additional compo- 0.62 µA << Ih . The simulation yields V ∗ ≈ 280 mV, which
nents, namely S5 , R1 and R2 . The value of R1 and R2 , which is implies R∗PQ ≈ R∗D ≈ V ∗ /Ih = 14kΩ and, consequently,
not reported in the table, is 10 kΩ for both resistors. As it will R∗ ≈ 6.5 kΩ. It is also interesting to notice that for R < R∗
be shown in section VI, this value is suboptimal compared the curve RPQ (R) is well approximated by a line whose slope
to the one that would maximize RPQ . This choice was made is 1. Obviously the curve is shifted upwards because of the
because it led to slightly better performance in terms of power series resistance of the switch (RPQ (R = 0) = 6 kΩ, which
consumption and settling error compared to R∗D . Nonetheless, coincides with the switch resistance).
R∗D is generally worth estimating because it represents a good
starting point from which the designer can iterate. The static b: Energy-settling trade-off
tail generator is implemented as a MOS device with W = 1 This section validates the theory developed in subsection
µm and L = 60 nm, biased by a current mirror. The static tail IV-C regarding the trade-off between energy efficiency and
current Ib is 40 µA. settling error affecting the preamplification gain. Figures 7
It is worth mentioning that the conventional Strong Arm and 8 compare the simulated behavior of the reward function
latch with a preamplifier (as shown in figure 2) was not R with the variation of trst and Ib , respectively. In both cases
simulated because the proposed topology has a smaller EDP the simulated curves have been obtained from pre-layout
compared to the conventional Strong Arm. Therefore, if a simulations. In order to plot the theoretical behavior of R,
stand-alone static preamplifier was added to both topologies, the constants Edyn and CPQ were extracted from the simulator.
the proposed comparator would still perform better. Their values are 11.5 fJ and 6 fF, respectively.
The figures confirm the existence of an optimum when
R is varied both as a function of trst and as a function of
VI. SIMULATIONS Ib . The theoretical curve in Figure 8 was obtained by using
A. VALIDATION OF THE THEORETICAL ANALYSIS the approximation RPQ ≈ V ∗ /Ih and assuming V ∗ to be
VOLUME 11, 2023 9
a) b)
FIGURE 5. Layout of the proposed a) and conventional b) comparator.
FIGURE 6. Simulated (pre-layout) small-signal load resistance RPQ as a FIGURE 7. Theoretical and simulated (pre-layout) behavior of R as a
function of R. function of trst , with Ib = 40 µA.
TABLE 2. Optimum values of trst and Ib based on the theoretical and

independent from Ib . The agreement between theoretical and simulated reward function R.
simulated curve demonstrates that this hypothesis works well

Theoretical Simulated
in practice, at least for Id3,4 (V ∗ ) << Ih . ∗ [ps]
trst 275 263
Table 2 summarizes the optimum values obtained from Ib∗ [µA] 40 45
the theoretical and simulated curves shown in Figures 7 and
8, again highlighting good agreement between theory and
simulations. It is worth noticing that the function R does not somewhat arbitrarily. Its relevance lies especially in the fact
represent an actual physical quantity and has been defined that it allows visualizing the trade-off between settling error
10 VOLUME 11, 2023
B. PERFORMANCE OF THE COMPARATOR

The comparator was tested at 2 GHz clock frequency by
applying an input differential voltage Vid such that |Vid | =
1 mV. An input common mode of VDD /2 = 0.5V was used
for all the simulations. The sign of Vid toggled every 2 cycles
during the central part of the reset/preamplification phase. By
using the notation introduced in section IV, this means that
tready = Tck /4. A static differential voltage was superimposed
to the signal to compensate the residual systematic offset
caused by parasitics, which was estimated to be ≈ 1 mV in the
proposed topology and ≈ 0.6 mV in the conventional Strong
Arm latch. Each output of the comparator was loaded with a
2 fF capacitor.
Figure 10 compares the transient behavior of the output
voltages in the proposed and in the conventional Strong Arm
latch. The figure highlights that, as expected, the delays of
FIGURE 8. Theoretical and simulated (pre-layout) behavior of R as a
function of Ib , with trst = TCLK /2 = 250 ps.
and energy and it provides a useful criterion to size the circuit.

Finally, in order to showcase the importance of optimizing the
energy-settling trade-off, we report in Figure 9 the behavior
of noise, offset and energy consumption as the duty cycle (and
hence trst ) varies. When the duty cycle of the comparator is
FIGURE 10. Transient behavior of the output signals of the proposed and
conventional Strong Arm comparator.
the two comparators are almost identical. Specifically, the

simulated delay is about 80.0 ps for the proposed comparator
and 79.4 ps for the conventional comparator. It should be
noted that the choice of sizing the comparators to have the
same delay is arbitrary, and that the designer could choose to
obtain an advantage in terms of speed at the expense of power
consumption, for instance by increasing the aspect ratio of
FIGURE 9. Noise, offset and energy absorption of the proposed M7 . Figure 10 also shows that VP and VQ diverge slightly
comparator versus duty cycle at fCLK = 2 GHz (post-layout). A higher duty
cycle implies a shorter trst . during the reset phase. It is important to highlight that this
phenomenon, which is caused by the capacitive feedthrough
of the outputs’ reset transient, can ease preamplification or
increased, Etot decreases linearly at the expense of the input- penalize it depending on the sign of the input differential
referred noise and offset which, to a first approximation, voltage. In order to clarify this point, suppose that at a given
are inversely proportional to the preamplification gain. Con- clock cycle Vid > 0. If, at the subsequent clock cycle,
versely, the energy absorption can be traded to improve noise the sign of the input differential voltage remains unchanged,
and offset by giving the preamplifier more time to settle. The preamplification starts from a disfavorable condition because
proposed reward function provides an immediate and intuitive the capacitive coupling causes VPQd to be positive at the be-
way to manage this compromise. By using a simulation-aided ginning of the reset phase (note that Vid > 0 implies that VPQd
approach to maximize R as a function of either trst or Ib , the should be negative). If, instead, the sign of Vid toggles with
designer can easily find an optimal (or near-optimal) sizing. respect to the previous decision, preamplification is favored
because the capacitive feedthrough causes VPQd to be already
VOLUME 11, 2023 11
negative when the reset phase begins. All the results reported is initially positive due to capacitive feedthrough. Around
below have been obtained by considering the less favorable t = 0.56 ns the sign toggles because the input differential
case. voltage is positive, which implies that VPQd should converge
Figure 11 compares the output differential voltages in the to a negative value. The maximum value reached by |VPQd |
proposed and in the conventional comparator during the reset before the beginning of the evaluation phase is approximately
phase. The combination of equalization and pull up transistors 2.4 mV, which corresponds to a gain of about 7.6 dB. The
allows the proposed comparator to cancel the memory effect discontinuity in the slope of the two curves around t = 0.64
faster than the conventional topology. At the same time, the ns is due clock feedthrough (caused by the rising edge of the
total channel width of S3 -S4 -S5 in the proposed topology is clock).
only 0.7 µm while in the conventional Strong Arm the total Table 3 compares the performance of the proposed com-
width of S3 -S4 amounts to 1 µm. As a consequence, the parator to that of the conventional Strong Arm. Overall, noise
total parasitic capacitance associated to the reset switches is
smaller in the proposed topology because all transistors have TABLE 3. Performance comparison between the conventional Strong Arm
comparator and proposed topology.
the same channel length, which in turn results in lower power
consumption. Conventional Proposed Improvement
EDP [fJ/GHz] 3.53 3.38 4.25%
σoffset [mV] 8.09 5.36 33.8%
σIRN [mV] 1.13 0.808 28.5%
and offset experience the largest improvement: this is in ac-

cordance with the theory because noise and offset suppression
are enhanced as the preamplification gain increases. The EDP
also decreases, which means the proposed topology relaxes
all the main trade-offs despite the additional power consumed
by the static tail generator. We summarize below the three
aspects that contribute to improving the energy efficiency:
• Nodes P and Q are precharged only partially, because
during the reset phase VPQc settles to VDD − VPQc (ts ) <
VDD . This reduces dynamic power consumption.
• If the comparator is sized to achieve the same delay as
the conventional Strong Arm latch, the aspect ratio of
FIGURE 11. Transient behavior of the output differential voltage in the
proposed and in the conventional comparator during the reset phase. the clocked tail transistor M7 can be reduced because
the partial precharge of nodes P and Q causes the latch
Figure 12 shows a detail of the transient behavior of VP to turn on earlier. This reduces the parasitic capacitance
and VQ during static preamplification. It should be noted that at the source node and thus power consumption.
• The reset technique implemented at the output nodes
this plot has been obtained from the pre-layout version of the
comparator because in the post-layout version the presence helps saving power consumption because the total para-
of systematic offset makes it more difficult to intepret the sitic capacitance of the reset switches can be smaller.
behavior of the two voltages. The differential signal VPQd The only cost of such improvements is a small increase in area
occupation due to the addition of R1 , R2 and S5 .
Table 4 shows the performance of the enhanced Strong
Arm comparator under process, voltage and temperature
(PVT) variations. The comparator shows good robustness
under a wide range of operating conditions. The offset of the
TABLE 4. Performance summary of the proposed Strong Arm comparator

with integrated preamplifier under PVT variations. In the table
max min
VDD = VDD + 10%VDD , VDD = VDD − 10%VDD , T max = 80 °C and T min = 0
°C.
VDDmin max
VDD T min T max FF SS FS SF
Pavg [µW] 65.5 106.1 82.1 89.4 88.8 81.7 84.3 84.6
td [ps] 105.8 65.3 80.3 81.0 69.0 113.9 77.5 87.7
EDP [fJ/GHz] 3.46 3.47 3.30 3.62 3.06 4.65 3.29 3.71
σIRN [mV] 0.84 0.79 0.75 0.92 0.84 0.80 0.90 0.73
proposed comparator was evaluated over 200 Monte Carlo

mismatch iterations. Figure 13 shows the resulting histogram.
FIGURE 12. Transient behavior of VPQd in the proposed comparator.
As already reported in table 3, the input-referred offset of
12 VOLUME 11, 2023
reset phase. An additional tail transistor, biased by a current

mirror, limits static power consumption while allowing for
current to flow through the switched load resistors. This ben-
efits the comparator’s performance in two ways. Firstly, the
input differential signal is amplified at the comparator’s in-
termediate nodes, improving noise, offset and, to a lesser ex-
tent, EDP with respect to the conventional Strong Arm latch.
Secondly, the intermediate nodes are never fully charged
during preamplification. This characteristic, combined with
the fact that the clocked tail device can be made smaller,
causes power consumption to improve with respect to the
conventional topology. Additionally, we showed that resetting
FIGURE 13. Histogram of the input-referred offset of the proposed the outputs with a combination of pull up and equalizing
comparator under mismatch variations.
devices allows to reduce the total area of the reset devices
with respect to the conventional Strong Arm topology, which
the proposed comparator exhibits a standard deviation of 5.36 instead only uses pull up devices. This results in a further
mV. The histogram shows that the offset remains within the improvement in power consumption. In order to provide a
[−15mV, 15mV] range. The offset distribution of the conven- benchmark, a conventional Strong Arm latch was sized and
tional Strong Arm comparator, on the other hand, has higher simulated. Our simulations show that the proposed approach
variance and covers the [−20mV, 20mV] range. relaxes the all the main trade-offs that characterize dynamic
comparators: EDP, offset and noise are reduced respectively
C. COMPARISON WITH STATE OF THE ART by about 5.24%, 33.8% and 28.5% compared to the conven-
Table 5 compares the performance of the proposed compara- tional Strong Arm latch.
tor to the recent state of the art. As the table shows, our
topology achieves the best performance in terms of input- REFERENCES
referred noise and energy per comparison, the only exceptions [1] A. Alshehri, M. Al-Qadasi, A. S. Almansouri, T. Al-Attar, and H. Fariborzi,
being [13], which has better energy efficiency, and [10], that ‘‘Strongarm latch comparator performance enhancement by implementing
clocked forward body biasing,’’ in 2018 25th IEEE International Confer-
exhibits lower input-referred noise. The input-referred offset ence on Electronics, Circuits and Systems (ICECS), pp. 229–232, 2018.
of the enhanced Strong Arm comparator is the highest among [2] X. Zhang, S. Li, R. Siferd, and S. Ren, ‘‘High-sensitivity high-speed
those reported in the table; however the comparison with the dynamic comparator with parallel input clocked switches,’’ AEU - Inter-
conventional Strong Arm latch demonstrates that the pro- national Journal of Electronics and Communications, vol. 122, p. 153236,
2020.
posed approach is also beneficial in terms of offset, as already [3] R. K. Siddharth, Y. Jaya Satyanarayana, Y. B. Nithin Kumar, M. H. Vasan-
highlighted in the previous subsection. Overall, the proposed tha, and E. Bonizzoni, ‘‘A 1-v, 3-ghz strong-arm latch voltage comparator
technique allows for a considerable improvement in terms of for high speed applications,’’ IEEE Transactions on Circuits and Systems
II: Express Briefs, vol. 67, no. 12, pp. 2918–2922, 2020.
noise and input-referred offset compared to the conventional [4] B. Razavi, ‘‘The strongarm latch [a circuit for all seasons],’’ IEEE Solid-
Strong Arm latch. This is even more interesting if we consider State Circuits Magazine, vol. 7, no. 2, pp. 12–17, 2015.
that these benefits do not come at the expense of EDP, which [5] V. Spinogatti, C. Bocciarelli, F. Centurelli, R. D. Sala, and A. Trifiletti,
‘‘Robust body biasing techniques for dynamic comparators,’’ in 2023
on the contrary experiences a significant improvement. 18th Conference on Ph.D Research in Microelectronics and Electronics
(PRIME), pp. 25–28, 2023.
TABLE 5. Comparison between recent literature and the topologies that [6] A. Almansouri, A. Alturki, A. Alshehri, T. Al-Attar, and H. Fariborzi,
have been simulated in this work. ‘‘Improved strongarm latch comparator: Design, analysis and performance
evaluation,’’ in 2017 13th Conference on Ph.D. Research in Microelectron-
This Work Literature ics and Electronics (PRIME), pp. 89–92, 2017.
Prop. Conv. [15] [13] [2] [3] [10] [7] H. S. Bindra, C. E. Lokin, A.-J. Annema, and B. Nauta, ‘‘A 30fj/comparison
Year 2023 2023 2019 2021 2020 2020 2022 dynamic bias comparator,’’ in ESSCIRC 2017 - 43rd IEEE European Solid
Technology [nm] 55 55 65 22 90 65 22
State Circuits Conference, pp. 71–74, 2017.
VDD [V] 1 1 1.2 0.8 1.2 1 0.8
Vid [mV] 1 1 10 1 0.03 2 0.174 [8] H. S. Bindra, C. E. Lokin, D. Schinkel, A.-J. Annema, and B. Nauta, ‘‘A
fck [GHz] 2 2 6 4 2 1 1 1.2-v dynamic bias latch-type comparator in 65-nm cmos with 0.4-mv input
Pavg [µW] 84.4 89.1 381 144 106 157 75 noise,’’ IEEE Journal of Solid-State Circuits, vol. 53, no. 7, pp. 1902–1912,
td [ps] 80.0 79.4 57.7 36 190 167 280 2018.
EDP [fJ/(GHz)] 3.38 3.53 2.16 1.40 10.07 26.2 21 [9] X. Tang, L. Shen, B. Kasap, X. Yang, W. Shi, A. Mukherjee, D. Z. Pan, and
E [fJ/comp] 42.2 44.6 63.5 36.0 53.0 78.5 75 N. Sun, ‘‘An energy-efficient comparator with dynamic floating inverter
σIRN [mV] 0.808 1.13 - 1.4 - - 0.174
σoffset [mV] 5.36 8.28 3.87 - - 2.05 -
amplifier,’’ IEEE Journal of Solid-State Circuits, vol. 55, no. 4, pp. 1011–
1022, 2020.
[10] H. S. Bindra, J. Ponte, and B. Nauta, ‘‘A 174µvrms input noise, 1 gs/s
comparator in 22nm fdsoi with a dynamic-bias preamplifier using tail
VII. CONCLUSIONS charge pump and capacitive neutralization across the latch,’’ in 2022 IEEE
In this paper a new enhanced Strong Arm latch is introduced International Solid- State Circuits Conference (ISSCC), vol. 65, pp. 1–3,
2022.
and validated. The proposed topology exploits the input dif- [11] C. Bocciarelli, F. Centurelli, R. D. Sala, V. Spinogatti, and A. Trifiletti, ‘‘A
ferential pair to preamplify the input difference during the 2.5 ghz, 0.6 v body driven dynamic comparator exploiting charge pump
VOLUME 11, 2023 13
based dynamic biasing,’’ in 2023 18th Conference on Ph.D Research in FRANCESCO CENTURELLI was born in Roma in
Microelectronics and Electronics (PRIME), pp. 37–40, 2023. 1971. He received the laurea degree (cum laude)
[12] B. P. Ginsburg and A. P. Chandrakasan, ‘‘Dual time-interleaved successive and the Ph.D. degree in Electronic Engineer-
approximation register adcs for an ultra-wideband receiver,’’ IEEE Journal ing from the University of Roma “La Sapienza”,
of Solid-State Circuits, vol. 42, no. 2, pp. 247–257, 2007. Roma, Italy, in 1995 and 2000 respectively. In 2006
[13] H. Zhuang, H. Tang, X. Peng, and Y. Li, ‘‘A back-gate-input clocked he became an Assistant Professor at the DIET de-
comparator with improved speed and reduced noise in 22-nm soi cmos,’’ partment of the University of Roma La Sapienza.
in 2021 IEEE International Symposium on Circuits and Systems (ISCAS),
His research interests were initially focused on
pp. 1–5, 2021.
system-level analysis and design of clock recovery
[14] T. Kobayashi, K. Nogami, T. Shirotori, and Y. Fujimoto, ‘‘A current-
controlled latch sense amplifier and a static power-saving input buffer for circuits and high-speed analog integrated circuits,
low-power architecture,’’ IEEE Journal of Solid-State Circuits, vol. 28, and now concern the design of analog-to-digital converters and very low-
no. 4, pp. 523–527, 1993. voltage circuits for analog and RF applications. He has published more than
[15] H. Ghasemian, R. Ghasemi, E. Abiri, and M. R. Salehi, ‘‘A novel high- 100 papers on international journals and refereed conferences, and has been
speed low-power dynamic comparator with complementary differential also involved in R&D activities held in collaboration between Università “La
input in 65 nm cmos technology,’’ Microelectronics Journal, vol. 92, Sapienza” and some industrial partners.
p. 104603, 2019.
VALERIO SPINOGATTI was born in Rome (Italy) ALESSANDRO TRIFILETTI was born in Rome
in 1997. He received the Master Degree in Elec- (Italy) on October 4, 1959. In 1991 he joined Elec-
tronic engineering from University of Rome “La tronic Engineering Department of “La Sapienza”
Sapienza”, Rome, Italy, in 2021. He’s currently University in Rome as research assistant, where
a PhD student at the Department of Informa- he was involved in research activities dealing with
tion Engineering, Electronics, and Telecommuni- analogue, RF and microwave IC’s design. In 2001
cations of University of Rome “La Sapienza”. he became assistant professor and in 2005 he got
His research interests include dynamic compara- the position of associate professor and in 2019
tors, high-speed analog-to-digital converters, digi- the position of Full Professor at the Engineering
tal calibration techniques based on adaptive filters Faculty of the same University. Prof. Trifiletti has
for communication systems and fast digitizers, and analog wideband filters. worked in the field of Microelectronics, both from the point of view of
He is also working in the field of hardware security, where he is focusing on design methodologies and circuit topologies. On these subjects, Prof. Tri-
side channel attacks on implementations of cryptographic primitives. filetti has (co-)authored over 210 publications, of which about 80 published
on international Journals, the others published on the proceedings of major
international Conferences (a large part of these sponsored by the IEEE). He
is presently reviewer for some IEE and IEEE reviews, among them: IEEE
Transaction on Microwave Theory and Techniques, IEEE Transaction on
Circuit and Systems (part I and II), IEE Proceedings on Circuits, Devices and
RICCARDO DELLA SALA was born on April 23th Systems, IEE Electronic letters. In last 20 years he has been engaged in the
1996. He received the Bachelor degree (summa coordination of research teams from DIET (previously DIE) in the frame-
cum laude) and the M.S. degree (summa cum work of national and international programs, involving both industrial and
laude) in Electronics Engineering from the Univer- academic partners. From an industrial perspective, Prof. Trifiletti expertise
sity of Rome ‘‘La Sapienza” (Italy) respectively in covers topics about analogue and RF microelectronics, Radar and ESM sys-
2018 and 2020. His main research interests include tems, high-speed communication systems, security issues in cryptographic
the design and development of PUFs and TRNGs algorithms implementation, and embedded system design.
for hardware security. Furthermore, in the context
of analog design, his research activity is focused
on ultra-low voltage ultra-low power topology for
IOT and biomedical applications such as OTAs and Comparators.
CRISTIAN BOCCIARELLI was born in Febraury

1998, in Narni (TR). He received the bachelor’s
and M.S. degrees (summa cum laude) in electron-
ics engineering from the University of Rome La
Sapienza, Italy, in 2019 and 2021, respectively. on
November 2021 he started his PhD at the Depart-
ment of Information Engineering, Electronics, and
Telecommunications of University of Rome “La
Sapienza”. in electronic engineering. His research
interests include the design and development of
high speed ADC, dynamic comparators, wide band Filters and digital cali-
bration techniques of analog circuits. Furthermore, in the context of hardware
security, his research activity is focused on SCA on cryptography primitive.
14 VOLUME 11, 2023

An Improved Strong Arm Comparator With Integrated Static Preamplifier

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This article has been accepted for publication in IEEE Access.

An Improved Strong Arm Comparator with

I. INTRODUCTION increase in power consumption. The authors of [6] propose

VOLUME 11, 2023 1

FIGURE 1. Schematic of the conventional Strong Arm latch.

FIGURE 2. Schematic of the conventional Strong Arm latch with preamplifier.

VOLUME 11, 2023 3

FIGURE 3. Schematic of the proposed enhanced Strong Arm latch.

V. SIZING TABLE 1. Sizing of the conventional and proposed comparators. All

FIGURE 5. Layout of the proposed a) and conventional b) comparator.

TABLE 2. Optimum values of trst and Ib based on the theoretical and

simulated curve demonstrates that this hypothesis works well

B. PERFORMANCE OF THE COMPARATOR

and energy and it provides a useful criterion to size the circuit.

the two comparators are almost identical. Specifically, the

and offset experience the largest improvement: this is in ac-

TABLE 4. Performance summary of the proposed Strong Arm comparator

proposed comparator was evaluated over 200 Monte Carlo

reset phase. An additional tail transistor, biased by a current

VOLUME 11, 2023 13

CRISTIAN BOCCIARELLI was born in Febraury

14 VOLUME 11, 2023

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