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Verilog Synthesis Examplesx2

This document provides an overview of Verilog synthesis examples. It discusses behavioral modeling using continuous assignments, bitwise operators that act on vectors, reduction operators that apply an operator to a single vector, and conditional operators like muxes. It also covers using internal signals, operator precedence, specifying constants, hierarchy, tristates, bit swizzling, registers including using resets and enables, counters, combinational and sequential logic with always blocks, decoders, seven segment displays, memories, shift registers, finite state machines, Mealy vs Moore machines, parameterized modules, and a Verilog style guide.

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20001003067lokesh
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22 views

Verilog Synthesis Examplesx2

This document provides an overview of Verilog synthesis examples. It discusses behavioral modeling using continuous assignments, bitwise operators that act on vectors, reduction operators that apply an operator to a single vector, and conditional operators like muxes. It also covers using internal signals, operator precedence, specifying constants, hierarchy, tristates, bit swizzling, registers including using resets and enables, counters, combinational and sequential logic with always blocks, decoders, seven segment displays, memories, shift registers, finite state machines, Mealy vs Moore machines, parameterized modules, and a Verilog style guide.

Uploaded by

20001003067lokesh
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Verilog Synthesis Examples

CS/EE 3710
Fall 2010

Mostly from CMOS VLSI Design


by Weste and Harris

Behavioral Modeling
 Using continuous assignments
 ISE can build you a nice adder
 Easier than specifying your own

1
Bitwise Operators
 Bitwise operations act on vectors (buses)

More bitwise operators

2
Reduction Operators
 Apply operator to a single vector
 Reduce to a single bit answer

Conditional Operator
 Classic mux
 Can be confusing if you get crazy

3
Using internal signals
 Internal wires and regs can be used inside a
module

Using internal signals


 Internal wires and regs can be used inside a
module

4
Operator Precedence

Constants
 Specified in binary, octal, decimal, or hex
 Note use of underscore in long binary numbers

5
Hierarchy
 Instantiate other modules in your module

Tristates
 Assign the value z
 Just say NO!
 No on-board tri-states on Spartan3e FPGAs
 Use MUXs instead!

6
Bit Swizzling
 Sometimes useful to work on part of a bus, or
combine different signals together
 Use bus (vector) notation

Bit Swizzling
 Sometimes useful to work on part of a bus, or
combine different signals together
 Use concatenation {} operator

7
Registers
 Edge-triggered flip flops
 Always use reset of some sort!

Registers
 Can also add an enable signal
 Only capture new data on clock and en

8
Counters
 Behavioral

Counters
 Structural

9
Comb Logic with Always blocks
 Always blocks are often sequential
 But, if you have all RHS variables in the
sensitivity list it can be combinational
 Remember that you still must assign to a reg
type

Comb Logic with Always blocks


 Always blocks are often sequential
 But, if you have all RHS variables in the
sensitivity list it can be combinational
 Remember that you still must assign to a reg
type

10
Decoder example (combinational)

Decoder example (combinational)

Continuous assignment version


is not as readable

Same circuit though…

11
Seven Segment Decoder

Memories
 Generally translates to block RAMs on the
Spartan3e FPGA

12
Shift Register?

Blocking vs. Non-Blocking


 Shift Register?

13
Blocking vs. Non-Blocking
 Shift Register?

Finite State Machines


 Divide into three sections
 State register
 Next state logic
 output logic
 Use parameters for state encodings

14
Example
 Three states, no inputs, one output, two state
bits

Example

15
Mealy vs. Moore

Mealy example

Output is true if
input is the same as
it was on the last
two cycles

16
Mealy Example

Parameterized Modules

17
Verilog Style Guide
 Use only non-blocking assignments in
always blocks
 Define combinational logic using assign
statements whenever practical
 Unless if or case makes things more readable
 When modeling combinational logic with
always blocks, if a signal is assigned in one
branch of an if or case, it needs to be assigned
in all branches

Verilog Style Guide


 Include default statements in your case
statements
 Use parameters to define state names and
constants
 Properly indent your code
 Use comments liberally
 Use meaningful variable names
 Do NOT ignore synthesis warnings unless
you know what they mean!

18
Verilog Style Guide
 Be very careful if you use both edges of the
clock
 It’s much safer to stick with one
 I.e. @(posedge clock) only
 Be certain not to imply latches
 Watch for synthesis warnings about implied
latches
 Provide a reset on all registers

Verilog Style Guide


 Provide a common clock to all registers
 Avoid gated clocks
 Use enables instead

19

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