Analog and Digital

• Two ways of representing information

– ANALOG and DIGITAL

• How are they distinguished ?

– distinguished by the nature of the values that they allow
the information variables to assume.

• Basic idea
· The values that an analog variable can take are smooth
and seamless continuous
· they are not separated by gaps.
1

Comparison: Digital vs Analog

Number System and logic gates

3 4

1
 Numeric Data Representation Radix Number Systems
Each number system has a number of
Deals with the representation of numbers in a different digits which is called the radix
computer. or the base of the number system.
In digital computers, the most commonly used
number systems are: • Decimal Base = 10
• binary • Binary Base = 2
• octal • Octal Base = 8
• hexadecimal
• Hexadecimal (Hex) Base = 16
5 6

Numeric Data Representation (Continued)

Numeric Data Representation (Continued)

Numeric data can be

Numeric data can be • Integers - fixed-point numbers (no fractional part)
• Integers - fixed-point numbers (no fractional part) • Unsigned integers
• Unsigned integers • signed integers
• signed integers • Floating-point numbers - numbers with fractional
• Floating-point numbers - numbers with fractional components
components

7 8

2
 Decimal Number System
Unsigned Integers Base (Radix) 10
Digits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9
No distinction is made between positive and negative numbers. e.g. 747510
An unsigned integer S can be represented as:
The magnitude represented by a digit is decided by
S = sn-1 sn-2 ..... s1 s0 r
the position of the digit within the number.
where si = digits allowed in the corresponding number system for S
1000 100 10 1
n = number of integer digits
r = radix (base) of the number system

Examples: S = 56210 S = 1011102 For example the digit 7 in the left-most position of
S = 42578 S = 2CD5916 7475 counts for 7000 and the digit 7 in the second
position from the right counts for 70.
9 10

Binary Number System Octal Number System

Base (Radix) 2 Base (Radix) 8
Digits 0, 1 Digits 0, 1, 2, 3, 4, 5, 6, 7
e.g. 11102 e.g. 16238
8=23 4=22 2=21 1=20 512=83 64=82 8=81 1=80

The digit 1 in the third position from the right The digit 2 in the second position from the right
represents the value 4 and the digit 1 in the represents the value 16 and the digit 1 in the
fourth position from the right represents the fourth position from the right represents the value
value 8. 512.
11 12

3
 Hexadecimal Number System
Base (Radix) 16
Number Base Conversions
Digits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, Two techniques available
A, B, C, D, E, F
e.g. 2F4D 16 § Repeated division
4096=163 256=162 16=161 1=160
§ Bit grouping

The digit F in the third position from the right

represents the value 3840 and the digit D in the
first position from the right represents the value 1.
13 14

Number Base Conversions (Continued) Number Base Conversions (Continued)

Repeated Division Technique Bit Grouping Technique

Employed for conversion between octal and
To convert a number in base  to the equivalent number in base , binary and for the conversion between
divide the given number by base  using base  arithmetic. hexadecimal and binary.

Each hexadecimal digit corresponds to a group of

four binary bits.

Each octal digit corresponds to a group of three

binary bits.
15 16

4
 Bit grouping Number Base Conversions (Continued)

Binary to Octal and Octal to Binary

To convert a binary number to octal, simply split

up the binary number into 3-bit groups starting
from the least significant bit and get the
corresponding octal digits.

To convert an octal number to binary, for each

octal digit, get the equivalent 3-bit binary
representation.
18

Number Base Conversions (Continued)

Binary to hex and hex to binary

To convert a binary number to hexadecimal,

simply split up the binary number into 4-bit
groups starting from the least significant bit and
get the corresponding hexadecimal digits.

To convert a hexadecimal number to binary, for

each hexadecimal digit, get the equivalent 4-bit
binary representation.
19

5
 Fractions
• We can extend our unsigned representational
system of binary to include a decimal point
– After the decimal point, the i exponent, in 2i, becomes
negative
Data Representation • So, we now have the ½ column, the ¼ column, etc
– 1101.1001 =
– 1*23 + 1*22 + 0*21 + 1*20 + 1*2-1 + 0*2-2 + 0*2-3 + 1*2-4 =
Chap-1, Session-3 – 8 + 4 + 0+1 + ½ + 0 + 0 + 1/16 =
– 13 9/16 = 13.5625
• What is .4304? Use 8-bits with 4 fraction bits
– .4304 has a .25, .125, .03125, .015625, and more fractions, but this
exceeds the number of fraction bits so the number is 0000.0110
– But 0000.0110 = .125 + 0.3125 = .375, we have a loss in precision!
• In the fraction representation, our decimal point is typically
fixed, so this is often known as fixed point representation

Signed Integers Signed Magnitude

• So far we have treated all of our numbers as • The first signed integer format is signed
unsigned (or positive only) magnitude where we add a bit to the front of our
– To implement signed integers (or signed fractions),
numbers that represents the sign
we need a mechanism to denote the sign itself – In 4 bits, 3 = 0011 and –3 = 1011
(positive or negative) • Notice in 4 bits, we can store 16 numbers in unsigned
• Unfortunately, this introduces new problems, so we will see magnitude (0000 to 1111, or decimal 0 to 15) but in signed
3 different approaches, all of which add a special bit known magnitude we can only store 15 numbers (between –7, or
as the sign bit 1111, and +7, 0111), so we lose a number
– If the sign bit is 0, the number is positive – Two problems:
• 0 is now represented in two ways: 0000, 1000, so we lose
– If the sign bit is 1, the number is negative the ability to store an extra number since we have two 0s
• If we have an 8 bit number, does this mean that we now • We cannot do ordinary arithmetic operations using signed
need 9 bits to store it with one bit used exclusively for the magnitude
sign? – we have to “strip” off the sign bit, perform the operation, and
insert the sign bit on the new answer – this requires extra hardware

1
 One’s Complement Binary Complement
• An alternative approach to signed magnitude is one’s (1s Complement) Operation
complement where the first bit is again a sign bit
• But negative numbers are stored differently from positive 1 0
numbers
– Positive number stored as usual 0 1
– Negative number – all bits are inverted Example
• 0s become 1s, 1s become 0s
– Example: +19 in 6 bits = 010011, -19 = 101100 110010110
• The first bit is not only the sign bit, but also part of the number
– Notice that we still have two ways to represent 0, 000000 and
111111
• So, we won’t use one’s complement
001101001
6

Two’s Complement
Two’s Complement • Positive numbers remain the same 4-bit Two’s Complement
Binary Decimal
The Two’s complement of a binary number • Negative numbers: derived by flipping 1000 -8
is obtained by first complementing the each bit and then adding 1 to the result 1001
1010
-7
-6
number and then adding 1 to the result. – +19 in 6 bits = 010011, 1011
1100
-5
-4
– -19 in 6 bits = 101101 1101 -3
• 010011  101100 +1  101101 1110 -2
1001110 – To convert back, flip all bits and add 1 1111 -1
0000 0
• 101101  010010 + 1  010011
0110001 One’s Complement 0001
0010
1
2
– While this is harder, it has two advantages
+ 1 • Only 1 way to represent 0 (000000) so we can
0011
0100
3
4
store 1 extra value that we lost when we tried 0101 5
Two’s Complement signed magnitude and one’s complement 0110 6
0110010 • Arithmetic operations do not require “peeling” 0111 7

7 off the sign bit

2
 Some Examples
Represent 83 and –83 using 8 bits in all 3 signed representations:
Binary Arithmetic
+83 = 64 + 16 + 2 + 1 = 01010011 (in all 3 representations)

-83: • Addition
Signed magnitude = 11010011 (sign bit is 1 for negative)
One’s complement = 10101100 (flip all bits from +83)
Two’s complement = 10101101 (flip all bits from +83 and add 1)
•Complements
Convert 11110010 into a decimal integer in all 4 representations •Subtraction
Unsigned magnitude = 128 + 64 + 32 + 16 + 2 = 242
Signed magnitude = -114 (negative, 1110010 = 114)
One’s complement = -13 (leading bit = 1, the number is negative,
flip all bits 00001101 = 13)
Two’s complement = -14 (negative, so flip all bits and add 1 
10
00001101 + 1 = 00001110 = 14)

Arithmetic Operations (Additions and Binary Addition

Subtractions) Using 2’s Complement 0 (b) 0
(a)
Number System +0 +1
Steps to be followed: 0 1
1. Express the given binary numbers in the 2’s
complement number system (c) 1 (d) 1
2. Add the numbers obtained step 1 +0 +1
3. Discard the end carry, if any 1 10
4. Express the result in sign-magnitude notation
Carry Bit
11 12

3
 Addition
• This operation is much like decimal addition
Binary Addition Examples
except that you are only adding 1s and 0s (a) 1011 (b) 1010 (c) 1011
• Add each column as you would in decimal, write down the + 1100 + 100 + 101
sum and if the sum > 1, carry a 1 to the next column
• Four possibilities: 10111 1110 10000
– Sum of the two digits (and any carry in) = 0, write 0, carry 0
– Sum = 1, write 1, carry 0
(d)
–
–
Sum = 2, write 0, carry 1 (this represents 10 = 2)
Sum = 3, write 1, carry 1 (this represents 11 = 3)
101 (e) 10011001
Examples:
+ 1001 + 101100
01000101
1 + 1 = 2, write 0, carry 1
11111111 The carry out of this
1110 11000101
+ 00001111 + 10101010 last bit causes overflow
01010100 110101001
14

Overflow Rules
Subtraction • In unsigned magnitude addition
– a carry out of the left-most bit is also an overflow
• There are two ways we could perform subtraction
– As normal, we subtract from right to left with borrows now
• In unsigned magnitude subtraction
being 2 instead of 10 as we move from one column to the next – overflow will occur in subtraction if we must borrow prior to the
– Or, we can negate the second number and add them together left-most bit
(36 – 19 = 36 + -19) • In two’s complement addition/subtraction
• We will use the latter approach when implementing a subtraction – if the two numbers have the same sign bit and the
circuit as it uses the same circuit as addition sum/difference has a different sign bit, then overflow
Examples:
borrow 2 from the previous
11010100 column 11010100  11010100
Below we see examples of four signed additions
- 00110011 - 00110011 + 11001101
10100001 110100001

Notice the overflow in this case too, but it differs from the
last example because we are using two’s complement

4
 Binary Subtraction
Binary subtraction is implemented by adding
the Two’s complement of the number to be
subtracted.
Two’s
Example complement
of 1001
1101 1101
-1001 +0111
10100
If there is a carry then it is ignored. Thus,
the answer is 0100.
17

5
 Binary Arithmatic Rules

Addition Subtraction Multiplication Division

Binary Arithmatic....
0+0 = 0 0-0 = 0 0*0 = 0 0÷0 = 0

Chap-1: Session-4 0 -1 = 1 (1 is
0+1 = 1 0*1 = 0 0÷1 = 0
borrowed)
05 April 2021
1+0 = 1 1- 0 = 1 1*0 = 0 1÷1 = 1
1+1 = 0 (1 is
1-1 = 0 1*1 = 1
carry forward)

Multiplication Example
First, load the multiplicand
• Multiplication is much like as you do it in decimal in M and the multiplier in Q
– Line up the numbers and multiply the multiplicand by one digit
of the multiplier, aligning it to the right column, and then A is an accumulator along
adding all products together with the left side of Q
• but in this case, all values are either going to be multiplied by 0 or 1
– So in fact, multiplication becomes a series of shifts and adds: As we shift C/A/Q, we
begin to write over part of Q
110011 (but it’s a part that we’ve
* 101001
already used in the
110011
000000
multiplication)
000000
110011 For each bit in Q, if 0 then
000000 merely shift C/A/Q,
110011 otherwise add M to C/A
Add these values Need 8 bit location to store result of
two 4 bit multiplications
Notice that A/Q stores the
We will use a tabular approach for simplicity (see next slides) resulting product, not just A

1
 NOTE: this algorithm works only if both
Multiplication numbers are positive. If we have negative
values in two’s complement, we will use a

Algorithm different algorithm

A is the accumulator Binary Multiplication:

M and Q are temporary
registers Booth’s Algorithm
C is a single bit storing the DLD: Chap-1 Session-5
carry out of the addition of
A and M

The result is stored in the

combination of registers
A and Q (A storing the upper
half of the product, Q the
lower half)

Booth's Multiplication Algorithm

This algorithm is a multiplication algorithm for two signed

binary integers in 2's complement, respectively.

1. Speeds up the performance of the multiplication process,

and
2. Very efficient too.

2
Booth’s Algorithm for Binary Multiplication Example...... Booth’s Algorithm
Compare rightmost bit of
We will use Q (that is, Q0) with the
Booth’s algorithm previous rightmost bit
if either or both from Q (which is stored
numbers are in a single bit Q-1)
negative

The idea is based Q-1 is initialized to 0

on this observation:
If this sequence is 0 – 1
0011110 = then add M to A
0100000 –
0000010 If this sequence is 1 – 0
then sub M from A
So, in Booth’s,
we look for
If this sequence is 0 – 0
transitions of 01
and 10, and ignore or 1 – 1 then don’t add
00 and 11 sequences
in our multiplier After each iteration, shift
A >> Q >> Q-1

Example of Using Booth’s Algorithm

Q = Multiplier = 0011, M = Multiplicand = 0111
-M = 1001 (2’s complement of 0111)

Initialize A to 0
Initialize Q to 0011
Initialize M to 0111
Initialize Q-1 to 0

1) Q/Q-1=10, AA–M,
Shift
2) Q/Q-1=11, Shift

3) Q/Q-1=01,AA+M,
Shift

4) Q/Q-1=00, Shift

Done, Answer = 00010101

3
 Codes and its classification?
A binary code is a group of n bits that assume up to 2n distinct
combinations of 1’s and 0’s with each combination representing one
element of the set that is being coded.
Binary Codes
Classification of binary codes
DLD: Chap-1 The codes are broadly categorized into following four categories.
• Weighted Codes
• Non-Weighted Codes (Excess-3 code and Gray code)
• Binary Coded Decimal Code (BCD or 8421 code)
• Alphanumeric Codes (ASCII, EBECDIC)
• Error Detecting and Correcting Codes (Parity codes)

BCD – Binary Coded Decimal

Non-weighted Codes Decimal BCD
Number Number
In this type of binary codes, the
positional weights are not assigned. When the decimal numbers are
0 0000
The examples of non-weighted represented in BCD, each 1 0001
codes are decimal digit is represented by 2 0010
• Excess-3 code and the equivalent BCD code. 3 0011
4 0100
Example :BCD Representation 5 0101
of Decimal 6349 6 0110
7 0111
6 3 4 9 8 1000
9 1001
• Gray code. 10 ~ 15 not VALID
0110 0011 0100 1001
4

1
 Rules for BCD addition BCD addition example

1. At first the given numbers are added using the

rule of binary.
2. If the result of addition is greater than 9 (not
valid) and if a carry bit is present in the result,
add “6” (0110)

6 is added to the addition result instead of any other

numbers to skip the six invalid states of binary
coded decimal i.e from 10 to 15 and again return to
the BCD codes.

BCD subtraction
BCD Subtraction
Subtraction by addition 9= 1001
Negatige DECIMAL representation -5 = (+) 0100 (nine’s complement of 5)
• 9’s complement 1101 (invalid)
• 10’s complement
Example: add 0110
-5= in 9’s complement - 0100 10011
= in 10’s complement - 0101
1 Add end around carry (EAC)
0100 = +4
8

2
 BCD arithmetic counted…. BCD arithmetic of fraction
9.3 = 1001.0011
4= 0100 -5.1 = (+) 0100.1000 (nine’s complement of 5.1)
-8 = (+) 0001 (Nine’s complement of 8) 1101.1011 (invalid)
0101 (No carry, “-ve” number) add 0110 .0110
Nine’s complement of 0101 = 4 10011 .10001
The answer is -4 1. 1 Add end around carry (EAC)
0100. 0010 = +4.2
9 10

Error Codes
Alphanumeric codes
Error-Detecting codes
The alphanumeric codes are the codes that represent numbers Whenever a message is transmitted, it may get scrambled by noise or
and alphabetic characters. It Represent other characters such as data may get corrupted. To avoid this, we use error-detecting codes
symbol and various instructions necessary for conveying information. which are additional data added to a given digital message to help us
An alphanumeric code should at least represent 10 digits and 26 detect if an error occurred during transmission of the message. A
letters of alphabet i.e. total 36 items. simple example of error-detecting code is parity check.

• American Standard Code for Information Interchange (ASCII). Error-Correcting codes

• Extended Binary Coded Decimal Interchange Code (EBCDIC). Along with error-detecting code, we can also pass some data to figure
out the original message from the corrupt message that we received.
ASCII code is a 7-bit code whereas EBCDIC is an 8-bit code. This type of code is called an error-correcting code. Error-correcting
ASCII code is more commonly used worldwide while EBCDIC is codes also deploy the same strategy as error-detecting codes but
used primarily in large IBM computers. additionally, such codes also detect the exact location of the corrupt
bit.

3
 How to Detect and Correct Errors?
To detect and correct the errors, additional bits are added to the
data bits at the time of transmission.
• The additional bits are called parity bits. They allow
detection or correction of the errors.
The data bits along with the parity bits form a code word.

• Even parity -- Even parity means the number of 1's in the

given word including the parity bit should be even (2,4,6,....).
• Odd parity -- Odd parity means the number of 1's in the given
word including the parity bit should be odd (1,3,5,....).

4
 Boolean Algebra
• Developed by George Boole in the 1850s
Boolean Algebra • Mathematical theory of logic.

DLD: Chap-1 • Shannon was the first to use Boolean

Algebra to solve problems in electronic
Session-8
circuit design. (1938)

1 2

Variables & Operations Operators: OR

• All variables have the values 1 or 0 • The result of the OR operator is 1 if either
– sometimes we call the values TRUE / FALSE of the operands is a 1.
• Three operators: • The only time the result of an OR is 0 is
– OR written as , as in A  B when both operands are 0s.
– AND written as , as in A B • OR is like our old pal addition, but operates
– NOT written as an overline, as in A only on binary values.

3 4

1
 Operators: AND Operators: NOT
• The result of an AND is a 1 only when both • NOT is a unary operator – it operates on
operands are 1s. only one operand.
• If either operand is a 0, the result is 0. • NOT negates it’s operand.
• If the operand is a 1, the result of the NOT
is a 0.
• AND is like our old nemesis multiplication, • If the operand is a 0, the result of the NOT
but operates on binary values. is a 17.678.
just kidding – it’s a 1 (wake up)!
5 6

Quiz (already?)
Equations
What is the value of each X:
Boolean algebra uses equations to express
relationships. For example:
X 1  1  (0  1)
X2  A A
X  A  (B  C)
X3  A A
This equation expressed a relationship X 4  X 4 1
between the value of X and the values of A,
B and C. Go to ZOOM’s CHAT option and TEXT me (HOST)
7
your answer within 3 minutes 8

2
 Basic Postulates of Boolean
Laws of Boolean Algebra
Algebra
Just like in good old algebra, Boolean • Using just the basic postulates – everything
Algebra has postulates and identities. else can be derived.
–Commutative laws
We can often use these laws to reduce –Distributive laws
expressions or put expressions in to a –Identity
more desirable form. –Inverse

9 10

Identity Laws Inverse Laws

A0  A A A 1

A 1  A
A A  0
11 12

3
 Commutative Laws Distributive Laws

A B  B  A A  ( B  C )  ( A  B)  ( A  C )

A B  B  A A  ( B  C )  ( A  B)  ( A  C )

13 14

Other Identities Zero and One Laws

Can be derived from the basic postulates.
A 1  1 Law of Ones
Laws of Ones and Zeros

Associative Laws A0  0 Law of Zeros

De Morgan’s Theorems
15 16

4
 Associative Laws DeMorgan’s Theorems

A  ( B  C )  ( A  B)  C A  B  A B
A  ( B  C )  ( A  B)  C
A B  A  B
17 18

Other Operators
• Boolean Algebra is defined over the 3 operators
AND, OR and NOT.
– this is a functionally complete set. Boolean Functions
• There are other useful operators:
– NOR: is a 0 if either operand is a 1
– NAND: is a 0 only if both operands are 1
– XOR: is a 1 if the operands are different.
• NOTE: NOR is (by itself) a functionally complete
set!

19 20

5
 Question
• How many Boolean functions of 1 variable
• Boolean functions are functions that operate are there?
on a number of Boolean variables. • We can answer this by listing them all!
• The result of a Boolean function is itself f1 ( x)  x
either a 0 or a 1.
f 2 ( x)  x
• Example: f(a,b) = a+b f 3 ( x)  0
f 4 ( x)  1
21 22

Tougher Question Alternative Representation

• How many Boolean functions of 2 variables • We can define a Boolean function by
are there? showing it using algebraic operations.

• We can also define a Boolean function by

• It’s much harder to list them all, but it is listing the value of the function for all
still possible… possible inputs.

23 24

6
 OR as a Boolean Function
for(a,b)=a+b Truth Tables
a b OR AND NOR NAND XOR
d a b for(a,b)
calle e” 0 0 0 0 1 1 0
s abl
is i t 0 0 0
Th ruth 0 1 1 0 0 1 1
t
a“ 0 1 1
1 0 1 0 0 1 1
1 0 1
1 1 1 1 0 0 0
1 1 1

25 26

Truth Table for (X+Y)·Z

X Y Z (X+Y)·Z
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
27

7
 Logic Conventions
• Binary information is represented in digital
computers by physical quantities called signals.
• Two different electrical voltage levels such as 3
Logic Gates volts and 0.5 volts may be used to represent binary 1
and 0.
DLD: Chap-1, Session-9 • Binary logic deals with binary variables and with
operations that assume a logical meaning.

Positive logic convention: If the signal has for its high (1)
level a voltage more positive than for its low (0) level
Negative logic convention: If the signal has for its high (1)
level a voltage more negaitive than for its low (0) level 2

Logic Gates Logic Gates ……

• A particular logic operation can be described in an
algebraic or tabular form. • Each gate has a distinct graphics symbol and it’s
operation can be described by means of an algebraic
• The manipulation of binary information is done by
expression or in a form of a table called the truth
the circuits called logic gates which are blocks of
table.
hardware that produce signals of binary 1 or 0 when
input logic requirements are satisfied. • Each gate has one or more binary inputs and one
binary output.

3 4

1
 A Gate Logic Gates
– AND
– OR
A Output – NOT (Inverter)
Inputs
B
??? f(A,B) – NAND (Not AND)
– NOR (Not OR)
– XOR (Exclusive-OR)
– Exclusive-NOR

5 6

Logic Gates Cont. Logic Gates Cont.

•AND Logic Gate Truth •OR Logic Gate Truth

Table Table
A AB x A AB x
x x
B 0 0 0 B 0 0 0
0 1 0 0 1 1
x=A.B 1 0 0 1 0 1
1 1 1 x=A+B 1 1 1
A, B Binary Input Variables
This is read as x
x Binary Output Variable equals A or B.

7 8

2
Logic Gates Cont. Logic Gates Cont.
•NOT Logic Gate Truth •NAND Logic Gate Truth
Table Table
A x A
A x x AB x
0 1 B
1 0 0 0 1
0 1 1
x=A.B
x=A 1 0 1
1 1 0

9 10

Logic Gates Cont. Logic Gates Cont.

•NOR Logic Gate Truth •XOR Logic Gate Truth
Table Table
A AB x A AB x
x x
B 0 0 1 B 0 0 0
0 1 0 0 1 1
x=A+B 1 0 0 1 0 1
x=A+B
1 1 0 1 1 0

11 12

3
Logic Gates Cont. Gates compute something!
•Exclusive-NOR Logic Gate Truth
Table
A AB x
x
B
0 0 1
0 1 0
x=A+B 1 0 0
1 1 1

13 14

Combinational Circuits A Simple Circuit

• We can put gates together into circuits
A
– output from some gates are inputs to others.
?
• We can design a circuit that represents any
Boolean function! B

15 16

4
 Truth Table for our circuit Alternative Representations
a b a b a•b a•b

0 0 1 1 1 0
0 1 1 0 0 1
1 0 0 1 0 1
1 1 0 0 0 1

17 18

Implementation Function Implementation

• A logic diagram is used to design an • Given a Boolean function expressed as a
implementation of a function. truth table or Boolean Equation, there are
• The implementation is the specific gates and many possible implementations.
the way they are connected. • The actual implementation depends on what
kind of gates are available.
• We can buy a bunch of gates, put them • In general we want to minimize the number
together (along with a power source) and
build a machine. of gates.

19 20

5
 One Implementation
Example: f  A B  A B
A B A B A B f f  A B  A B
0 0 0 0 0 A
0 1 0 1 1
1 0 1 0 1 f
1 1 0 0 0
B
21 22

Homework:
Another Implementation
Proof it’s the same function
A

f  A  B  A  B  A  B A  B  
f
Hint: One solution may be the use of the
following laws on the LHS of the equation
B
DeMorgan's Law

 
Distributive
f  A  B  A  B  A  B A  B Inverse, Identity
DeMorgan's Laws
23

6
 Proof it’s the same function
A B  A B 

A  B  A  B   DeMorgan's Law
A  B  A  B   DeMorgan's Laws

A  B  A A  B  B   Distributive

A  A  B  A A  B  B  B   Distributive
 B  A   A  B   Inverse, Identity

 B  A   A  B   DeMorgan's Law

B  A  A  B  DeMorgan's Laws 25

7
 Can you guess the Logic
functions?

light/load
DLD: Chap-1: Session-10 light/load
Electronic Logic gates
AND OR

Logic Gates: Diode Logic (DL): AND Logic Gates: Diode Logic: OR
The simples gates are AND and OR. They can be built from switches
or using the simplest form of electronic logic - diode logic.

When A = 0 , B = 0  both diodes are forward biased, why?

A = 0 , B = 0  both diodes are reverse biased  does not conduct out is LOW  0.
 both diodes conduct  output is LOW  0.
A = 0 , B = 1  DA is reverse biased  does not conduct,
A = 0 , B = 1  Diode B is reverse biased  does not conduct, DB is forward biased  conducts out is HIGH  1.

Diode A is forward biased  conducts  A = 1 , B = 0  DB is reverse biased  does not conduct,

output is LOW  0. DA is forward biased  conducts out is HIGH  1.

A = 1 , B = 1  both diodes are reverse biased 

both the diodes conduct  out is HIGH  1.
NJIT ECE271 Dr.Serhiy Levkov Topic 7 - 4

1
 DL Gates: Limitations Logic Gates: NAND & NOR
• The simple diode logic allows AND and OR, but not inverters • Any gate can be built from
NAND or NOR gates. This
 an incomplete form of logic.
enables a circuit to be built
from just one type of gate,
• Also, without some kind of amplification it is not possible to either NAND or NOR.
have such basic logic operations cascaded as required for more • To build NAND or NOR
complex logic functions. inverter is required 
transistors needed.

Conclusion.
• To build a functionally complete logic systems transistors are
used.
NJIT ECE271 Dr.Serhiy Levkov Topic 7 - 5 • The most basic digital building block is the inverter.

Diode-Transistor Logic (DTL) Gate Diode-Transistor Logic (DTL) Gate

The inversion and level-restoration problem associated with diode
logic can be solved by adding a diode and transistor to form the
diode-transistor logic (DTL) gate

On the left, diodes D1 and D2 are both off, whereas D3 and Q1 are
on. Node 1 is at 1.3 V:
V1 = VD3 + VBE = 0.6 V + 0.7 V = 1.3 V
The current I through resistor RB and diode D3 becomes the base
current IB of transistor Q1.
The value of IB is designed to cause Q1 to saturate so that vO =
VCESAT (for example, 0.05 to 0.1 V).

2
Diode-Transistor Logic (DTL) Gate The Ideal Inverter
The ideal inverter has the following voltage transfer characteristic
(VTC) and is described by the following symbol

On the right, input B is now at 0 V, corresponding to a logical 0. Diode

D2 is conducting, holding node 1 at 0.6 V. Now diode D3 and transistor
Q1 must both be off, because the voltage at node 1 is now less than the
two diode voltage drops required to turn on both D3 and Q1. The base
current of Q1 is now zero; Q1 will be off with IC = 0, and the output
voltage will be at +3.3 V, corresponding to a logical 1.

A similar situation holds for the circuit if both inputs are low.

What’s the Boolean Function the gate implements?

The Ideal Inverter

The ideal inverter has the following voltage transfer characteristic
Basic MOS inverter
(VTC) and is described by the following symbol
• MOS or Metal Oxide Semiconductor logic uses
nmos and pmos to implement logic gates. One
need to know operation of FET, MOS transistors
to understand the operation of MOS logic
circuits.
• The basic NMOS invertor is shown below, when
input is LOW, NMOS transistor does not conduct,
and thus output is HIGH. But when input is HIGH,
NMOS transistor conducts and thus output is
V+ and V- are the supply rails
LOW.
VH and VL describe the high and low logic levels at the output
12

3
 Inverter - circuit Inverter - circuit
An inverter operating with power supplies at V+ and 0 V An inverter operating with power supplies at V+ and 0 V
can be implemented using a switch with a resistive load. can be implemented using a switch with a resistive load.

MOSFET
Q-point

Inverter - circuit Inverter - circuit

An inverter operating with power supplies at V+ and 0 V An inverter operating with power supplies at V+ and 0 V
can be implemented using a switch with a resistive load. can be implemented using a switch with a resistive load.

Q-point

4
 Feature of logic families
Logic Families The feature to be concerned of IC logic families:
– fan-out
• The no. of standard loads can be connected to the output of the
gate without degrading its normal operation
• Sometimes the term loading is used
– fan-in
DLD: Chap-1, Session-12 • The number of inputs that the gate can handle properly with out
disturbing the output level.
– Power dissipation
• The power needed by the gate (Expressed in mW)
– Propagation delay
• The average transition-delay time for the signal to propagate
from input to output when the binary signal changes in value
– Noise margin
• Noise margin is the maximum noise added to an input signal of a
digital circuit that does not cause an undesirable change in the
circuit output

Typical npn Silicon Transistor

Parameters Noise margin
Region VBE (V) VCE (V) Current
Relation
Cutoff < 0.6 Open IB=IC=0
circuit
Active 0.6-0.7 > 0.8 IC =hFEIB

Saturation 0.7-0.8 0.2 IB ≥IC/hFE

1
Resistance-Transistor Logic (RTL)
RTL....
In RTL (resistor transistor logic), all the
logic are implemented using resistors
• The basic circuit of the RTL logic family is the NOR.
and transistors. One basic thing about
• Each input is associated with one resistor and one transistor.
the transistor (NPN), is that HIGH at
• The collector of the transistor are tied together at the output
input causes output to be LOW (i.e. like
• The voltage levels for the circuit are 0.2v for the low level and from
a inverter).
1 to 3.6v for the high level

When either input X or Y is driven

HIGH, the corresponding transistor
goes to saturation and output Z is
pulled to LOW.

What’s the logic function implemented by the gate? 5

Transistor-Transistor Logic
Charracteristics (TTL)
•  It has a fan-out of 5.
In Transistor Transistor logic or
•  Propagation delay is 25 ns. just TTL, logic gates are built only
•  Power dissipation is 12 mw. around transistors. Through the
•  Noise margin for low signal input is 0.4 v. years basic TTL has been
•  Low speed improved to meet performance
requirements. There are many
versions or families of TTL.

Standard TTL.
High Speed TTL
Low Power TTL.
Schhottky TTL.
8

2
 Totem-pole TTL
TTL TTL families have three configurations for outputs.
• It can perform many digital function and have achieved the most
Totem - Pole output.
popularity.
• TTL IC are given the numerical designation as 5400 and 7400 series Open Collector Output.
Tristate Output.
• The basic circuit of TTL with totem pole output stage is NAND
gate
• TTL uses a multi-miter transistor at the input and is fast saturation This extra output stage is known
logic circuit. as totem-pole stage because three
output components Q3 and Q4
and Diode are stacked on one
another.

10

Totem-pole output of TTL

Totem-pole
Output Stage
Output stage is called Totem-Pole because transistor Q3 sits upon Q4. Q2
Wikipedia........ provides complementary voltages for the output transistors Q3 and Q4,
Totem poles are monumental which stack one above the other in such a way that while one of these
conducts, the other is in cut-off.
carvings, a type of Northwest
Coast art, consisting of poles, posts Q4 is called pull-down transistor, as it pulls the output voltage down, when
it saturates and the other is in cut-off (i.e. Q3 is in cut-off). Q3 is called
or pillars, carved with symbols or
pull-up transistor, as it pulls the output voltage up, when it saturates and
figures. the other is in cut-off (i.e. Q4 is in cut-off).
Diodes in input are protection diodes which conduct when there is large
negative voltage at input, shorting it to the ground.

12

3
 ECL operation
Emitter-coupled logic (ECL) • Emitter coupled logic (ECL) is a non saturated logic, which means
that transistors are prevented from going into deep saturation, thus
eliminating storage delays. Preventing the transistors from going into
saturation is accomplished by using logic levels whose values are so
close to each other that a transistor is not driven into saturation when
its input switches from low to high. In other words, the transistor is
switched on, but not completely on. This logic family is faster than
TTL.
• Voltage level for high is -0.9 Volts and for low is -1.7V; thus biggest
problem with ECL is a poor noise margin.
• When any input is HIGH (-0.9v), its connected transistor will conduct,
and hence will make Q3 off, which in turn will make Q4 output
HIGH.When both inputs are LOW (-1.7v), their connected transistors
will not conduct, making Q3 on, which in turn will make Q4 output
13 LOW. 14

Dis/Advantages of ECL Pseudo NMOS inverter

• There are several disadvantages associated with ECL. It VD
uses a negative power supply so that the logic levels are D
not compatible with any other logic family, and makes
analysis and measurement inconvenient.
• ECL requires large currents and the noise margins are
small.
Output
• On the other hand, power supply currents remain much
more stable when the logic switches compared to TTL,
thus reducing noise on the power leads. Input
• In practice, ECL is used only when necessary for its high
speed.
15

4
 Pseudo NMOS inverter Pseudo-nMOS NOR
• Normally it is difficult to fabricate resistors VDD
inside the chips, so resistor is replaced with
NMOS gate as shown below. This new
NMOS transistor acts as resistor
Output

Input 1 Input 2 Input 3

17

What is this circuit?

VDD
CMOS inverter

Output

Input 1 Pseudo-nMOS NAND

Input 2

20

5
 CMOS inverter
• CMOS or Complimentary Metal Oxide
Semiconductor logic is built using both NMOS and
PMOS. Below is the basic CMOS inverter circuit,
which follows following rules.
– NMOS conducts when its input is HIGH.
– PMOS conducts when its input is LOW.
• So when input is HIGH, NMOS conducts, and thus
output is LOW, when input is LOW PMOS conducts
and thus output is HIGH.
21