Chap-1 DLD
Chap-1 DLD
• Basic idea
· The values that an analog variable can take are smooth
and seamless continuous
· they are not separated by gaps.
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Numeric Data Representation Radix Number Systems
Each number system has a number of
Deals with the representation of numbers in a different digits which is called the radix
computer. or the base of the number system.
In digital computers, the most commonly used
number systems are: • Decimal Base = 10
• binary • Binary Base = 2
• octal • Octal Base = 8
• hexadecimal
• Hexadecimal (Hex) Base = 16
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Decimal Number System
Unsigned Integers Base (Radix) 10
Digits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9
No distinction is made between positive and negative numbers. e.g. 747510
An unsigned integer S can be represented as:
The magnitude represented by a digit is decided by
S = sn-1 sn-2 ..... s1 s0 r
the position of the digit within the number.
where si = digits allowed in the corresponding number system for S
1000 100 10 1
n = number of integer digits
r = radix (base) of the number system
Examples: S = 56210 S = 1011102 For example the digit 7 in the left-most position of
S = 42578 S = 2CD5916 7475 counts for 7000 and the digit 7 in the second
position from the right counts for 70.
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The digit 1 in the third position from the right The digit 2 in the second position from the right
represents the value 4 and the digit 1 in the represents the value 16 and the digit 1 in the
fourth position from the right represents the fourth position from the right represents the value
value 8. 512.
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Hexadecimal Number System
Base (Radix) 16
Number Base Conversions
Digits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, Two techniques available
A, B, C, D, E, F
e.g. 2F4D 16 § Repeated division
4096=163 256=162 16=161 1=160
§ Bit grouping
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Bit grouping Number Base Conversions (Continued)
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Fractions
• We can extend our unsigned representational
system of binary to include a decimal point
– After the decimal point, the i exponent, in 2i, becomes
negative
Data Representation • So, we now have the ½ column, the ¼ column, etc
– 1101.1001 =
– 1*23 + 1*22 + 0*21 + 1*20 + 1*2-1 + 0*2-2 + 0*2-3 + 1*2-4 =
Chap-1, Session-3 – 8 + 4 + 0+1 + ½ + 0 + 0 + 1/16 =
– 13 9/16 = 13.5625
• What is .4304? Use 8-bits with 4 fraction bits
– .4304 has a .25, .125, .03125, .015625, and more fractions, but this
exceeds the number of fraction bits so the number is 0000.0110
– But 0000.0110 = .125 + 0.3125 = .375, we have a loss in precision!
• In the fraction representation, our decimal point is typically
fixed, so this is often known as fixed point representation
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One’s Complement Binary Complement
• An alternative approach to signed magnitude is one’s (1s Complement) Operation
complement where the first bit is again a sign bit
• But negative numbers are stored differently from positive 1 0
numbers
– Positive number stored as usual 0 1
– Negative number – all bits are inverted Example
• 0s become 1s, 1s become 0s
– Example: +19 in 6 bits = 010011, -19 = 101100 110010110
• The first bit is not only the sign bit, but also part of the number
– Notice that we still have two ways to represent 0, 000000 and
111111
• So, we won’t use one’s complement
001101001
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Two’s Complement
Two’s Complement • Positive numbers remain the same 4-bit Two’s Complement
Binary Decimal
The Two’s complement of a binary number • Negative numbers: derived by flipping 1000 -8
is obtained by first complementing the each bit and then adding 1 to the result 1001
1010
-7
-6
number and then adding 1 to the result. – +19 in 6 bits = 010011, 1011
1100
-5
-4
– -19 in 6 bits = 101101 1101 -3
• 010011 101100 +1 101101 1110 -2
1001110 – To convert back, flip all bits and add 1 1111 -1
0000 0
• 101101 010010 + 1 010011
0110001 One’s Complement 0001
0010
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– While this is harder, it has two advantages
+ 1 • Only 1 way to represent 0 (000000) so we can
0011
0100
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store 1 extra value that we lost when we tried 0101 5
Two’s Complement signed magnitude and one’s complement 0110 6
0110010 • Arithmetic operations do not require “peeling” 0111 7
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Some Examples
Represent 83 and –83 using 8 bits in all 3 signed representations:
Binary Arithmetic
+83 = 64 + 16 + 2 + 1 = 01010011 (in all 3 representations)
-83: • Addition
Signed magnitude = 11010011 (sign bit is 1 for negative)
One’s complement = 10101100 (flip all bits from +83)
Two’s complement = 10101101 (flip all bits from +83 and add 1)
•Complements
Convert 11110010 into a decimal integer in all 4 representations •Subtraction
Unsigned magnitude = 128 + 64 + 32 + 16 + 2 = 242
Signed magnitude = -114 (negative, 1110010 = 114)
One’s complement = -13 (leading bit = 1, the number is negative,
flip all bits 00001101 = 13)
Two’s complement = -14 (negative, so flip all bits and add 1
10
00001101 + 1 = 00001110 = 14)
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Addition
• This operation is much like decimal addition
Binary Addition Examples
except that you are only adding 1s and 0s (a) 1011 (b) 1010 (c) 1011
• Add each column as you would in decimal, write down the + 1100 + 100 + 101
sum and if the sum > 1, carry a 1 to the next column
• Four possibilities: 10111 1110 10000
– Sum of the two digits (and any carry in) = 0, write 0, carry 0
– Sum = 1, write 1, carry 0
(d)
–
–
Sum = 2, write 0, carry 1 (this represents 10 = 2)
Sum = 3, write 1, carry 1 (this represents 11 = 3)
101 (e) 10011001
Examples:
+ 1001 + 101100
01000101
1 + 1 = 2, write 0, carry 1
11111111 The carry out of this
1110 11000101
+ 00001111 + 10101010 last bit causes overflow
01010100 110101001
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Overflow Rules
Subtraction • In unsigned magnitude addition
– a carry out of the left-most bit is also an overflow
• There are two ways we could perform subtraction
– As normal, we subtract from right to left with borrows now
• In unsigned magnitude subtraction
being 2 instead of 10 as we move from one column to the next – overflow will occur in subtraction if we must borrow prior to the
– Or, we can negate the second number and add them together left-most bit
(36 – 19 = 36 + -19) • In two’s complement addition/subtraction
• We will use the latter approach when implementing a subtraction – if the two numbers have the same sign bit and the
circuit as it uses the same circuit as addition sum/difference has a different sign bit, then overflow
Examples:
borrow 2 from the previous
11010100 column 11010100 11010100
Below we see examples of four signed additions
- 00110011 - 00110011 + 11001101
10100001 110100001
Notice the overflow in this case too, but it differs from the
last example because we are using two’s complement
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Binary Subtraction
Binary subtraction is implemented by adding
the Two’s complement of the number to be
subtracted.
Two’s
Example complement
of 1001
1101 1101
-1001 +0111
10100
If there is a carry then it is ignored. Thus,
the answer is 0100.
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Binary Arithmatic Rules
Chap-1: Session-4 0 -1 = 1 (1 is
0+1 = 1 0*1 = 0 0÷1 = 0
borrowed)
05 April 2021
1+0 = 1 1- 0 = 1 1*0 = 0 1÷1 = 1
1+1 = 0 (1 is
1-1 = 0 1*1 = 1
carry forward)
Multiplication Example
First, load the multiplicand
• Multiplication is much like as you do it in decimal in M and the multiplier in Q
– Line up the numbers and multiply the multiplicand by one digit
of the multiplier, aligning it to the right column, and then A is an accumulator along
adding all products together with the left side of Q
• but in this case, all values are either going to be multiplied by 0 or 1
– So in fact, multiplication becomes a series of shifts and adds: As we shift C/A/Q, we
begin to write over part of Q
110011 (but it’s a part that we’ve
* 101001
already used in the
110011
000000
multiplication)
000000
110011 For each bit in Q, if 0 then
000000 merely shift C/A/Q,
110011 otherwise add M to C/A
Add these values Need 8 bit location to store result of
two 4 bit multiplications
Notice that A/Q stores the
We will use a tabular approach for simplicity (see next slides) resulting product, not just A
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NOTE: this algorithm works only if both
Multiplication numbers are positive. If we have negative
values in two’s complement, we will use a
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Booth’s Algorithm for Binary Multiplication Example...... Booth’s Algorithm
Compare rightmost bit of
We will use Q (that is, Q0) with the
Booth’s algorithm previous rightmost bit
if either or both from Q (which is stored
numbers are in a single bit Q-1)
negative
Initialize A to 0
Initialize Q to 0011
Initialize M to 0111
Initialize Q-1 to 0
1) Q/Q-1=10, AA–M,
Shift
2) Q/Q-1=11, Shift
3) Q/Q-1=01,AA+M,
Shift
4) Q/Q-1=00, Shift
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Codes and its classification?
A binary code is a group of n bits that assume up to 2n distinct
combinations of 1’s and 0’s with each combination representing one
element of the set that is being coded.
Binary Codes
Classification of binary codes
DLD: Chap-1 The codes are broadly categorized into following four categories.
• Weighted Codes
• Non-Weighted Codes (Excess-3 code and Gray code)
• Binary Coded Decimal Code (BCD or 8421 code)
• Alphanumeric Codes (ASCII, EBECDIC)
• Error Detecting and Correcting Codes (Parity codes)
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Rules for BCD addition BCD addition example
BCD subtraction
BCD Subtraction
Subtraction by addition 9= 1001
Negatige DECIMAL representation -5 = (+) 0100 (nine’s complement of 5)
• 9’s complement 1101 (invalid)
• 10’s complement
Example: add 0110
-5= in 9’s complement - 0100 10011
= in 10’s complement - 0101
1 Add end around carry (EAC)
0100 = +4
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BCD arithmetic counted…. BCD arithmetic of fraction
9.3 = 1001.0011
4= 0100 -5.1 = (+) 0100.1000 (nine’s complement of 5.1)
-8 = (+) 0001 (Nine’s complement of 8) 1101.1011 (invalid)
0101 (No carry, “-ve” number) add 0110 .0110
Nine’s complement of 0101 = 4 10011 .10001
The answer is -4 1. 1 Add end around carry (EAC)
0100. 0010 = +4.2
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Error Codes
Alphanumeric codes
Error-Detecting codes
The alphanumeric codes are the codes that represent numbers Whenever a message is transmitted, it may get scrambled by noise or
and alphabetic characters. It Represent other characters such as data may get corrupted. To avoid this, we use error-detecting codes
symbol and various instructions necessary for conveying information. which are additional data added to a given digital message to help us
An alphanumeric code should at least represent 10 digits and 26 detect if an error occurred during transmission of the message. A
letters of alphabet i.e. total 36 items. simple example of error-detecting code is parity check.
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How to Detect and Correct Errors?
To detect and correct the errors, additional bits are added to the
data bits at the time of transmission.
• The additional bits are called parity bits. They allow
detection or correction of the errors.
The data bits along with the parity bits form a code word.
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Boolean Algebra
• Developed by George Boole in the 1850s
Boolean Algebra • Mathematical theory of logic.
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Operators: AND Operators: NOT
• The result of an AND is a 1 only when both • NOT is a unary operator – it operates on
operands are 1s. only one operand.
• If either operand is a 0, the result is 0. • NOT negates it’s operand.
• If the operand is a 1, the result of the NOT
is a 0.
• AND is like our old nemesis multiplication, • If the operand is a 0, the result of the NOT
but operates on binary values. is a 17.678.
just kidding – it’s a 1 (wake up)!
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Quiz (already?)
Equations
What is the value of each X:
Boolean algebra uses equations to express
relationships. For example:
X 1 1 (0 1)
X2 A A
X A (B C)
X3 A A
This equation expressed a relationship X 4 X 4 1
between the value of X and the values of A,
B and C. Go to ZOOM’s CHAT option and TEXT me (HOST)
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your answer within 3 minutes 8
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Basic Postulates of Boolean
Laws of Boolean Algebra
Algebra
Just like in good old algebra, Boolean • Using just the basic postulates – everything
Algebra has postulates and identities. else can be derived.
–Commutative laws
We can often use these laws to reduce –Distributive laws
expressions or put expressions in to a –Identity
more desirable form. –Inverse
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A0 A A A 1
A 1 A
A A 0
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Commutative Laws Distributive Laws
A B B A A ( B C ) ( A B) ( A C )
A B B A A ( B C ) ( A B) ( A C )
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De Morgan’s Theorems
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Associative Laws DeMorgan’s Theorems
A ( B C ) ( A B) C A B A B
A ( B C ) ( A B) C
A B A B
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Other Operators
• Boolean Algebra is defined over the 3 operators
AND, OR and NOT.
– this is a functionally complete set. Boolean Functions
• There are other useful operators:
– NOR: is a 0 if either operand is a 1
– NAND: is a 0 only if both operands are 1
– XOR: is a 1 if the operands are different.
• NOTE: NOR is (by itself) a functionally complete
set!
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Question
• How many Boolean functions of 1 variable
• Boolean functions are functions that operate are there?
on a number of Boolean variables. • We can answer this by listing them all!
• The result of a Boolean function is itself f1 ( x) x
either a 0 or a 1.
f 2 ( x) x
• Example: f(a,b) = a+b f 3 ( x) 0
f 4 ( x) 1
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OR as a Boolean Function
for(a,b)=a+b Truth Tables
a b OR AND NOR NAND XOR
d a b for(a,b)
calle e” 0 0 0 0 1 1 0
s abl
is i t 0 0 0
Th ruth 0 1 1 0 0 1 1
t
a“ 0 1 1
1 0 1 0 0 1 1
1 0 1
1 1 1 1 0 0 0
1 1 1
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Logic Conventions
• Binary information is represented in digital
computers by physical quantities called signals.
• Two different electrical voltage levels such as 3
Logic Gates volts and 0.5 volts may be used to represent binary 1
and 0.
DLD: Chap-1, Session-9 • Binary logic deals with binary variables and with
operations that assume a logical meaning.
Positive logic convention: If the signal has for its high (1)
level a voltage more positive than for its low (0) level
Negative logic convention: If the signal has for its high (1)
level a voltage more negaitive than for its low (0) level 2
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A Gate Logic Gates
– AND
– OR
A Output – NOT (Inverter)
Inputs
B
??? f(A,B) – NAND (Not AND)
– NOR (Not OR)
– XOR (Exclusive-OR)
– Exclusive-NOR
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7 8
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Logic Gates Cont. Logic Gates Cont.
•NOT Logic Gate Truth •NAND Logic Gate Truth
Table Table
A x A
A x x AB x
0 1 B
1 0 0 0 1
0 1 1
x=A.B
x=A 1 0 1
1 1 0
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Logic Gates Cont. Gates compute something!
•Exclusive-NOR Logic Gate Truth
Table
A AB x
x
B
0 0 1
0 1 0
x=A+B 1 0 0
1 1 1
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Truth Table for our circuit Alternative Representations
a b a b a•b a•b
0 0 1 1 1 0
0 1 1 0 0 1
1 0 0 1 0 1
1 1 0 0 0 1
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One Implementation
Example: f A B A B
A B A B A B f f A B A B
0 0 0 0 0 A
0 1 0 1 1
1 0 1 0 1 f
1 1 0 0 0
B
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Homework:
Another Implementation
Proof it’s the same function
A
f A B A B A B A B
f
Hint: One solution may be the use of the
following laws on the LHS of the equation
B
DeMorgan's Law
Distributive
f A B A B A B A B Inverse, Identity
DeMorgan's Laws
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Proof it’s the same function
A B A B
A B A B DeMorgan's Law
A B A B DeMorgan's Laws
A A B A A B B B Distributive
B A A B Inverse, Identity
B A A B DeMorgan's Law
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Can you guess the Logic
functions?
light/load
DLD: Chap-1: Session-10 light/load
Electronic Logic gates
AND OR
Logic Gates: Diode Logic (DL): AND Logic Gates: Diode Logic: OR
The simples gates are AND and OR. They can be built from switches
or using the simplest form of electronic logic - diode logic.
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DL Gates: Limitations Logic Gates: NAND & NOR
• The simple diode logic allows AND and OR, but not inverters • Any gate can be built from
NAND or NOR gates. This
an incomplete form of logic.
enables a circuit to be built
from just one type of gate,
• Also, without some kind of amplification it is not possible to either NAND or NOR.
have such basic logic operations cascaded as required for more • To build NAND or NOR
complex logic functions. inverter is required
transistors needed.
Conclusion.
• To build a functionally complete logic systems transistors are
used.
NJIT ECE271 Dr.Serhiy Levkov Topic 7 - 5 • The most basic digital building block is the inverter.
On the left, diodes D1 and D2 are both off, whereas D3 and Q1 are
on. Node 1 is at 1.3 V:
V1 = VD3 + VBE = 0.6 V + 0.7 V = 1.3 V
The current I through resistor RB and diode D3 becomes the base
current IB of transistor Q1.
The value of IB is designed to cause Q1 to saturate so that vO =
VCESAT (for example, 0.05 to 0.1 V).
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Diode-Transistor Logic (DTL) Gate The Ideal Inverter
The ideal inverter has the following voltage transfer characteristic
(VTC) and is described by the following symbol
A similar situation holds for the circuit if both inputs are low.
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Inverter - circuit Inverter - circuit
An inverter operating with power supplies at V+ and 0 V An inverter operating with power supplies at V+ and 0 V
can be implemented using a switch with a resistive load. can be implemented using a switch with a resistive load.
MOSFET
Q-point
Q-point
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Feature of logic families
Logic Families The feature to be concerned of IC logic families:
– fan-out
• The no. of standard loads can be connected to the output of the
gate without degrading its normal operation
• Sometimes the term loading is used
– fan-in
DLD: Chap-1, Session-12 • The number of inputs that the gate can handle properly with out
disturbing the output level.
– Power dissipation
• The power needed by the gate (Expressed in mW)
– Propagation delay
• The average transition-delay time for the signal to propagate
from input to output when the binary signal changes in value
– Noise margin
• Noise margin is the maximum noise added to an input signal of a
digital circuit that does not cause an undesirable change in the
circuit output
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Resistance-Transistor Logic (RTL)
RTL....
In RTL (resistor transistor logic), all the
logic are implemented using resistors
• The basic circuit of the RTL logic family is the NOR.
and transistors. One basic thing about
• Each input is associated with one resistor and one transistor.
the transistor (NPN), is that HIGH at
• The collector of the transistor are tied together at the output
input causes output to be LOW (i.e. like
• The voltage levels for the circuit are 0.2v for the low level and from
a inverter).
1 to 3.6v for the high level
Transistor-Transistor Logic
Charracteristics (TTL)
• It has a fan-out of 5.
In Transistor Transistor logic or
• Propagation delay is 25 ns. just TTL, logic gates are built only
• Power dissipation is 12 mw. around transistors. Through the
• Noise margin for low signal input is 0.4 v. years basic TTL has been
• Low speed improved to meet performance
requirements. There are many
versions or families of TTL.
Standard TTL.
High Speed TTL
Low Power TTL.
Schhottky TTL.
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2
Totem-pole TTL
TTL TTL families have three configurations for outputs.
• It can perform many digital function and have achieved the most
Totem - Pole output.
popularity.
• TTL IC are given the numerical designation as 5400 and 7400 series Open Collector Output.
Tristate Output.
• The basic circuit of TTL with totem pole output stage is NAND
gate
• TTL uses a multi-miter transistor at the input and is fast saturation This extra output stage is known
logic circuit. as totem-pole stage because three
output components Q3 and Q4
and Diode are stacked on one
another.
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ECL operation
Emitter-coupled logic (ECL) • Emitter coupled logic (ECL) is a non saturated logic, which means
that transistors are prevented from going into deep saturation, thus
eliminating storage delays. Preventing the transistors from going into
saturation is accomplished by using logic levels whose values are so
close to each other that a transistor is not driven into saturation when
its input switches from low to high. In other words, the transistor is
switched on, but not completely on. This logic family is faster than
TTL.
• Voltage level for high is -0.9 Volts and for low is -1.7V; thus biggest
problem with ECL is a poor noise margin.
• When any input is HIGH (-0.9v), its connected transistor will conduct,
and hence will make Q3 off, which in turn will make Q4 output
HIGH.When both inputs are LOW (-1.7v), their connected transistors
will not conduct, making Q3 on, which in turn will make Q4 output
13 LOW. 14
4
Pseudo NMOS inverter Pseudo-nMOS NOR
• Normally it is difficult to fabricate resistors VDD
inside the chips, so resistor is replaced with
NMOS gate as shown below. This new
NMOS transistor acts as resistor
Output
17
Output
Input 2
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CMOS inverter
• CMOS or Complimentary Metal Oxide
Semiconductor logic is built using both NMOS and
PMOS. Below is the basic CMOS inverter circuit,
which follows following rules.
– NMOS conducts when its input is HIGH.
– PMOS conducts when its input is LOW.
• So when input is HIGH, NMOS conducts, and thus
output is LOW, when input is LOW PMOS conducts
and thus output is HIGH.
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