Computer Architecture (PTU) 3-37 Microprocessor 8085

The instruction SHLD 5648 H will copy the contents of register L (79 H) to
memory location 5648 H and the contents of register H (43 H) to memory location
5649 H.
10. LHLD Address [L+ (Address), H- (Address + 1)]
This instruction copies the contents of memory location specified in instruction to
the registers H and L.
The contents of the memory location specified in the instruction are copied into
the L register and the contents of the next memory location are copied to the H
register.
Example : LHLD 5648 H
Let H=43 H,L=79 H, the contents of memory locations 5648 H and 5649 Hare
10H and 50H.
The instruction LHLD 5648 Hwill copy the contents of memory location 5648 H
(10H) to the register L and the contents of memory location 5649 H(50 H) to the
register H.
11. STAX Rp (Rp )- AJ
This instruction copies the contents of .accumulator to memory location whose
address is pointed by the specified register pair.
The register R, can be a valid register pair like BC or DE only.
The contents of the accumulator remain unchanged.
Example: STAX D:
Let A=29 H, D=57 H, E= 48 H.
The instruction STAX D will copy the contents of accumulator (29 H) to the
memory location, whose address is given by DE register pair i.e. 5748 H.
12. LDAX R [A+ (R)]
This instruction copies the contents of memory location whose address is pointed
by the specified register pair to the accumulator.
The register R, can be any valid register pair like BC or DE only.
The contents of the memory location remain unchanged.
Example : LDAX D:
Let A = 29 H, D = 57 H, E = 48 H.
The instruction LDAX D will copy the contents of the memory location, whose
address is given by DE register pair i.e. 5748 H(10 H) to the accumulator.
13. XCHG [H + D, L + E]
Example:XCHG
Let H= 12 H, L= 11 H, D= 57 H, E= 23 H
 Computer Architecture (PTU) 3-38 Microprocessor 8085

The instruction XCHG exchanges the contents of register pair HL with the
contents of register pair DE.
3.17.3 Arithmetic Group Instructions :
This group of instructions pcrform arihmctic opcrations such as addition, subtraction,
increment and decrement :
Addition
Any 8-bit number, or the contents of a register or the contents of a
memory location can be added to the contents of the accumulator
and the sum is stored in the accumulator. No two other 8-bit
registers can be added directly (e.g., the contents of register B
cannot be added directlyto the contents of the register C).
Subtraction Any 8-bit number, or the contents of a register, or the contents of a
memory location can be subtracted fromn the contents of the
accumulator and the results stored in the accumulator. The
subtraction is performed in 2's complement, and the results if
negative, are expressed in 2's complement. No two other registers
can be subtracted directly.
Increment/Decrement The 8-bit contents of a register or a memory location can be
incremented or decrement by 1. Similarly, the 16-bit contents of a
register pair (such as BC) can be incremented or decrement by 1.
These increment and decrement operations differ from addition and
sublraction in an important way; i.e., they can be performed in any
one of the registersor in a memory location.
The arithmetic group of instructions include following instructions :
1. ADD R 2. ADD M 3. ADC R 4. ADC M
5. ADI data 6. ACI data 7. DAD R 8. SUB R
9. SUB 10, SBB R 11. SBB M 12. SUl data
13. SBI data 14. DAA 15, INRR 16. INR M
17. DCR R 18. DCR M 19. | INX Rp 20. DCX Rp
14. ADD R [A-A+R]
This instruction adds the contents of register R with the
contents of he
accumulator. The result of addition is stored in the accumulator.
The register R can be any general purpose registers such as A, B, C, D, E,
L.
H and

Example : ADD C
A+C- A.
Computer Architecture (PTU) 3-39 Microprocessor 8085
Let A=50 H, C= 20 H.
The instruction ADD Cwill add the contents of register C (20 H) with
the
contents of the accumulator i.e.50 H. The result of addition (70 H) will be stored
in the accumulator.
15. ADD M (A-A+ (HL))
This instruction adds the contents of memory location pointed by the HL register
pair with the contents to accumulator. The result is stored in accumulator.
Example:ADD M
A+ M ’ A.
Let A=50 H, H= 24 H, L=56 H, contents of memory location 2456 H= 40H.
The instruction ADD M will add the contents of memory location 2456 H
1.e. (40H) with the contents of the accumulator ie.50 H. The result of addition
(90 H) will be stored in the accumulator.
16. ADI Data [A+A +Data (8 bit)]
This instruction adds the 8 bit data specified along with the contents of the
accumulator. The result is stored in accumulator.
Example :ADI 40 H
This instruction adds the immediate data (40 H) to contents of the accumulator.
The result is in accumulator.
17. ADC R [A+A+R+ CY]
This instruction adds the contents of register R along with the carry to the contents
of the accumulator. The result of addition is stored in the accumulator.
The register R can be any general purpose registers such as A, B, C, D, E, H
and L.
Example: ADC C
A+C+ CY ’ A.
Let A=50H, C =20 H and CY = 1.

The instruction ADC Cwill add the contents of register C(20 H) and contents of
carry (01 H) with the contents of the accumulator i.e.50 H. The result of addition
(71 H) will be stored in the accumulator.
18. ADC M [A + A+ (HL) + CY]
This instruction adds the contents of nemory location pointed by the HL register
pair and the contents of carry with the contents to accunulator. The result is
stored in accumulator.
Computer Architecture (PTU) 3-40
MicroproCeSSor 8085
Example: ADC M
A+ M + CY ’ A.
Let A= 50 H, H= 24 H, L = 56 H, contents of memory location 2456 He An
and the Contents of carry = 1.
The instruction ADC M will add the contents of memory location 2456 u
i.e. (40H) and carry along with the contents of the accumulator i.e.50 H Tha
result of addition (91 H) will be stored in the accumulator.
19. ACI Data [A+A+ Data (8 bit) +CY]
This instruction adds the 8 bit data specified and contents of carry along with the
contents of the accumulator. The result is stored in accumulator.
Example: ACI 40H
This instruction adds the immediate data (40 H) and carry (01 H) to contents of
the accumulator. The result is stored in the accumulator.
20. DAD Rp [HL 4 HL + Rp]
This instruction adds the contents of specified register pair to HL pair and stores
the result in HL pair.
The register pair R, can be SP, BC, DE or HL.
Example : DAD B:BC + HL ’HL.
Let BC =5023 H, HL = 1234 H then the instruction DAD B will add the contents
of register pair BC (5023 H) with the contents of register pair HL (1234 H) and
the result of addition 6257 H is stored in the HL
register pair.
21. SUB R [A+A-R]
This instruction subtracts the contents of register R from the contents of us
accumulator. The result of subtraction is stored in the accumulator.
The register R can be any general purpose registers such as A, B, C, D, E, Ha
L.
Example : SUB C
A-C’ A.
Let A=50 H, C= 20 H.
The instruction SUB C will subtract the contents of register C (20 H) from the
contents of the accumulator i.e.50 H. The result of subtraction (30 H) willbe
stored in the accumulator.
22. SUB M
[A+A-(HL)]
This instruction subtracts the contents of memory location pointed by the HL
register pair from the contents to accumulator. The result is stored in accumulator.
 3-41 Microprocessor 8085
Computer Architecture (PTU)

Example: SUB M
AM’A.
Let A =50 H, H = 24 H, L= 56 H, contents of memory location 2456 H=40 H.
The instruction SUB M will subtract the contents of memory location 2456 H
i.e. (40 H) with the contents of the accumulator i.e.50 H. The result of subtraction
(10 H) willbe stored in the accumulator.
23. SUI Data [A= A-Data (8 bit)]
This instruction subtracts the 8 bit data specified from the contents of the
accumulator. The result is stored in accumulator.
Example: SUI 4OH
This instruction subtracts the immediate data (40 H) from the contents of the
accumulator. The result is in accumulator.
24. SBB R [A+A-R-CY]
This instruction subtracts the contents of register R along with the carry from the
contents of the accumulator. The result of subtraction is stored in the accumulator.
The register R can be any general purpose registers such as A, B, C, D, E. H and
L.
Example: SBB C
AC-CY ’A.
Let A = 50 H,C = 20 H and CY = 1.
The instruction SBB Cwill subtract the contents of register C (20 H) and contents
of carry (01 H) from the contents of the accumulator i.e.50 H. The result of
subtraction (2F H) will be stored in the accumulator.
25. SBB M (A+A-(HL) CY]
This instruction subtracts the contents of memory location pointed by the HL
register pair and the contents of carry from the contents to accumulator. The result
is stored in accumulator.
Example: SBB M
A- M -CY ’ A.

Let A = 50 H, H = 24 H, L = 56 H, contents of menory location 2456 H= 40 H

and the contents of carry = 1.
The instruction SBB M will subtract the contents of memory location 2456 H
i.e. (40 H) and carry from the contents of the accumulator i.e. 50 H. The result ot
subtraction (0F H) willbe stored in the accumulator.
 Computer Architecture (PTU) 3-42 MicroprOcessor 8085
26. SBI Data [A+A- Data (8 bit) CY]
This instruction subtracts the 8 bit data specified and contents of carry along with
the contents of the accumulator. The result is stored in accumulator.
Example: SBI 40 H
This instruction subtracts the immediate data (40 H) and carry (01 H) from the
contents of the accumulator. The result is stored in the accumulator.
27. DAA [A+ Sum in Aadjusted to packed BCD format]
Algorithm : If lower nibble of A>9 or AF = 1then,
Lower nibble of A = lower nibble of A + 06 H
If higher nibble of A>9FHor CF =1 then,
Higher nibble of A = higher nibble of A + 60 H
CF = 1
This instruction is used to make sure that the result of adding two packed BCD
numbers is adjusted to be a legal BCD number.
It operates only on A register.
If number in the lower nibble of A register after addition is greater than 9 or if the
auxiliary carry flag is set add 6.
If the lower nibble of A is greater than 9 or if the carry flag is set then add 60 H.
Example: ADD A, B
If A=59 H valid BCD, B = 34 H valid BCD
A=8D H invalid BCD after addition of Aand B
DAA ’ 1 0 0 0 1 1 0 1
+ 00 0 0 1 0
1 1 0 0 1 1

9 3
A = 93 H BCD

28. INR R [R +R+ 1]

This instruction increments the contents of the specified register R by
is stored in the same register.
1.The result
R can be any general purpOse registers such as A, B, C, D, E, H
and L.
Example: INR B
Let B = 50 H
Then the instruction INR B will increment the contents of
register B by 1.
Computer Architecture (PTU) 3-43 Microprocessor 8085

29. INR M [(HL)- (HL) +1]

This instruction increments the contents of memory location addressed by HL
register pair by 1.The result is stored back at same nmemory location.
The HL register pair is used as memory pointer.
Example: INR M
Let H = 57 H, L = 48 H, the contents of memory location 5748 H = 10 H. The
instruction INR Mwill increment the contents of memory location 5748 H.
30. INX Rp [Rp Rp+1)
This instruction increments the contents of register pair specified in the instruction
by 1.
The register pair R, can be any valid register pair likeBC, DE, HL and SP. Only
higher order register is specified for register pair in instruction.
Example: INX B
Let B = 50 H, C = 23 H The instruction INX B will increment the contents of
register pair BC by 1.
31. DCR R [R +R-1]
This instruction decrements the contents of the specified register R by 1.The result
is stored in the same register.
R can be any general purpose registers such as A, B, C, D, E, Hand L.
Example : DCRB
Let B = 50 H
Then the instruction DCR B will decrement the contents of register B by 1.
32. DCR M [(HL) (HL) - 1]
This instruction decrements the contents of memory location addressed by HL
register pair by 1. The result is stored back at same memory location.
The HL register pair is used as memory pointer.
Example: DCR M
Let H = 57 H, L = 48 H, the contents of memory location 5748 H = 10 H. The
instruction DCR M will decrement the contents of memory location 5748H.
 Computer Architecture (PTU) 3-44 Microprocessor 8085

33. DCX R, (R, - R, - 1]

This instruction decrements the contents of register pair specified in the
instruction by 1.
The register pair R, canbe any valid register pair like BC, DE, HL and SP. Only
higher order register is specified for register pair in instruction.
Example: DCX B
Let B = 50 H, C= 23 H. The instruction DCX B willdecrement the contents of
register pair BC by 1.
3.17.4 Branch Group:
Ma 2005
The microprocesSor executes machine codes in a sequential manner. It goes on
executing from one memory location to the next. Branch group of instructions instructs the
microprocessor to go to a different memory location. The microprocessor continues executing
machine codes from that new location, The address of the new memory location is either
specified in the instruction or supplied by the microprocessor or given by extra hardware. The
branch group instructions are classified in 3 categories :
(a) CALL instructions :
1. JMP address
2. Conditional CALL instructions
3. PCHL
(b) Calland return instructions :
1. CALL address
2. Conditional call instructions
3. RET
4. Conditional RET instructions.

(c) Restart instructions : 3

RST N

34. JMP Address [PC Address]

This instruction loads the PC with the address given within the instruction and
continues with the program execution from this location.
Example : JMP C200 H.
This instruction will load the PC with C200 H and the processor will
fetch the
instruction from this address.
Computer Architecture (PTU) 3-45 Microprocessor 8085

35. Conditional JUMP Instructions :

In conditional JUMP instructions, when the condition is true or satisfied then only
JUMP is made at the specified address.
If condition is false or not satisfied it will just check and proceed further to
execute the next instruction after it.

Instruction code Description Condition for JUMP

JZ JUMP if zero ZF =1
JNZ JUMP if not zero ZF =0
JP JUMP if positive SF=0

JPO JUMP if parity odd PF = 0

JPE JUMP if parity even PF = 1

JM JUMP on minus SF = 1

JC JUMP if carry CF = 1

JNC JUMP if no carry CF =0

Example: JZ C200
Let ZF =1.
This istruction will cause a JUMP to an address C200 H. ie. program counter
will load with C200 H as ZF =1,

36. PCHL [PC HL]

The contents of H and L registers are transferred to program counter.
The H contents to high order 8 bits and Lcontents to low order 8 bits of program
Counter.

This instruction is equivalent to a 1 byte unconditional JUMP instruction,

provided the address of JUMP is specified by the HL register pair. The program
sequence is transferred to address specified by the HL register pair.
37. CALL Address [(SP -1) +PCH, (SP -2) + PCL, SP SP -2, PCaddress]
This instruction is used to transfer the programn control to a subprogram or
subroutine.
i.e. whenever this instruction is executed the program control is transferred to the
address specified in the instruction.
The current contents of the PC are pushed onto the stack i.e. the address of the
next instruction is pushed onto thestack.
The Stack pointer is decremented by 2.
 Computer Architecture (PTU) 3-46
Microprocessor 8085
After the execution of the subroutine it is
back to the calling program. To do this the
essential to transter the program control
of the next instruction after the CALL processor has to remember the address
to the stack when the stack CALL instruction. Processor saves this address on
instruction is executed.
Example: CALL C200
When this instruction is executed, program counter contents CO09
on to the stack and will be stored
microprocessor will load the PC with C200 H and starts
executing instructions fromn C200 onwards.
Note : The Stack is a part of read/ write memory set
and addresses. aside for storing intermediate results
38.
Conditional CALL Instructions :
Inconditional CALL instruction, when the condition is true, then a
NEW address is made. CALL at
If the conditioa is not satisfied then the instruction that after the CALL
is satisfed. instruction
Before Call, the address of the instruction after the
the Stack and the Stack pointer is CALL instruction is stored on
decremented by 2.
Following table shows the possible condition for calls.
Instruction code Description Condition for CALL
CZ CALL on zero ZF = 1
CNZ CALL if not zero ZF = 0
CP CALL if positive SF = 0
CPO CALL if parity odd PF = 0
CPE CALL if parity even PF = 1
CM CALL on minus SF = 1
CC CALL if carry CF = 1
CNC CALL if no carry CF = 0
Example: CC C200
CALL if carry flag is set, the program written from
address
executed. If carry flag is reset microprocessor will execute C200
next
onwards will be
CC C200. instruction after
39. RET [PCL 4 (SP), PCH (SP + 1), SP + SP+2]
When this instruction is executed program
control is transferred from the
subroutine to the calling program.
Computer Architecture (PTU) 3-47
Microprocessor 8085
The return address is popped / taken from stack
(where the call instruction has
stored its PC contents i.e. return address) this address is
loaded in PC and the
program execution begins at address taken from stack.
Thus, the program control is transferred to the next
instruction after CALL in the
main program.
40. Conditional RET Instructions :
In conditional RET instruction, when the
condition is true, then the Control is
transferred to the main program.
Following table shows the possible condition for returns.
Instruction code Description Condition for RET
RZ RET On zero ZF = 1
RNZ RET if not zerO ZF = 0
RP RET if positive SF = 0
RPO RET if parity odd PF = 0
RPE RET if parity even PF = 1
RM RET on minus SF = 1
RC RET if carry CF = 1
RNC RET if no carry CF = 0
3.17.5 Logical Group Instructions :
These instructions perform various logical operations with the
contents of the accumulator.
AND, OR Any 8-bit number, or the contents of a register, or of a
Exclusive-OR can be logically ANDed, Ored, or memory location
Exclusive-ORed with the contents of
the accumulator. The results are stored in the
accumulator.
Rotate Each bit in the accumulator can be shifted either lett or
right to the next
position.
Compare Any 8-bit number, or the contents of a register, or a
memory location can
be compared for cquality, greater than, or less than, with the
contents of
the accumulator.
Complement The contents of the accunmulator can be complemented. All Os are
replaced by ls and all Is are replaced by Os. The logical group of
instructions include following instructions:
Computer Architecture (PTU) 3-48 Microprocessor 8085

1. ANA R 2. ANA M 3. ANI data 4. ORA R

5. ORA M 6. ORA data 7. XRA R 8. XRA M

9. XRI data 10. CMA 11. CMC 12. STC

13. CMP R 14.1 CMP M 15. CPI data 16. RLC
17. RRC 18. RAL 19. RAR
41. ANA R : [A ’A R]
Mnemonic A ’AR
The contents of the specified register are logically ANDed with the contents of
accumulator. The result is stored in accumulator.
The operation of ANDing is performed bit by bit i.e. D, bit of accumulator is
ANDed with bit D, of register and so on up to D, bit of accumulator ANDed with
D, bit of register.
R can be any general purpose registers such as A, B, C, D, E, H and L.
Example ANA B
Let the contents of register A = FO H and contents of register B = 20 H. The
contents of register B are ANDed with the contents of the accumulator. The result
is stored in the accumulator.
42. ANA M: [A-An(HL)]
The contents of the memory location pointed by the HL register pair are logically
ANDed with the contents of accumulator. The result is stored in accumulator.
The operation of ANDing is performed bit by bit i.e. Do bit of accumulator is
ANDed with bit Do of memory and so on up to D, bit of accumulator ANDed with
D, bit of memory.
Example ANA M
Let A = FOH, H =57 H, L= 48 H and contents of memory location 5748 H= 20
H. The contents of memory location 5748 H are ANDed with the contents of the
accumulator. The result is stored in the accumulator.
43. ANI Data : [A+A Data]
The contents of the 8 bit data specified in the instruction are logically ANDed
with the contents of accumulator. The result is stored in
accumulator.
The operation of ANDing is performcd bit by bit i.e. D, bit of
ANDed with bit Do of data and so on up to D, bit of accumulator
accumulator IS
bit of data. ANDed with Dn
Computer Architecture (PTU) 3-49 MicroprOcessor 8085

Example ANI20 H

Let the contents of register A = FO H. The immediate data contents (20 H) are
ANDed with the contents of the accumulator. The result is stored in the
accumulator.
44. XRA R: [A+A XOR R]
The contents of the specified register are logically EX-ORed with the contents of
accumulator. The result is stored in accumulator.
The operation of EX-ORing is performed bit by bit i.e. D, bit of accumulator is
EX-ORed with bit D, of register and so on up to D, bit of accumulator EX-ORed
with D, bit of register.
Rcan be any general purpose registers such as A, B, C, D, E, Hand L.
Example XRA B.
Let the contents of register A = FO H and contents of register B = 20 H.The
contents of register B are EX-ORed with the contents of the accumulator. The
result is stored in the accumulator.
45. XRA M : [A+-A XOR (HL)]
The contents of the memory location pointed by the HL register pair are logically
EX-ORed with the contents of accumulator. The result is stored in accumulator.
The operation of EX-ORing is performed bit by bit i.e. Do bit of accumulator is
EX-ORed with bit D,of memory and so on up to D, bit of accumulator EX-ORed
with D, bit of memory.
Example: XRA M.
Let A = FO H, H= 57 H, L = 48 H and contents of memory location 5748 H = 20
H. The contents of memory location 5748 H are EX-ORed with the contents of
the accumulator. The result is stored in the accumulator.
46. XRIData: [A +AXOR Data]
The contents of the 8bit data specified in the instruction are logicallyEX-0Red
with the contents of accumulator. The result is stored in accumulator.
The operation of EX-ORing is performed bit by bit i.e. D, bit of accumulator is
EX-ORed with bit Do of data and so on up to D, bit of accumulator EX-ORed with
D, bit of data.
Example XRI 20 H
Let the contents of register A = FO H .The inmediate data contents (20 H) are
EX-ORed with the contents of the accumulator. The result is stored in the
accumulator.
Computer Architecture (PTU) 3-50 Microprocessor 8085
47. ORA R: [A+A v R]
The contents of the specified register are logically ORed with the contents of
accumulator. The result is stored in accumulator.
The operation of ORing is performed bit by bit i.e. D, bit of accumulator is ORed
with bit Do of register and so on up to D, bit of accumulator ORed with D, bit of
register.
R can be any gencral purpose registers such as A, B, C, D, E, H and L.
Example ORA B
Let the contents of register A =FO H and contents of register B = 20 H The
ContentsS of register B are ORed with the contents of the accumulator. The result is
stored in the accumulator.
48. ORA M: [A -Av (HL)]
The contents of the memory location pointed by the HL register pair are logically
ORed with the contents of accumulator. The result is stored in accumulator.
The operation of ORing is performed bit by bit i.e. D, bit of accumulator is ORed
with bit Do of register and so on up to D, bit of accumulator ORed with D, bit of
register.
Example ANA M
Let A = FO H, H= 57 H, L=48 H and contents of memory location 5748 H = 20
H. The contents of memory location 5748 Hare ORed with the contents of the
accumulator. The result is stored in the accumulator.

49. ORI Data : [A +A v Data]

The contents of the 8 bit data specified in the instruction are logically ORed with
the contents of accumulator. The result is stored in accumulator.
The operation of ORing is performed bit by bit i.e. D, bit of accumulator is ORed
with bit Do of data and so on up to D, bit of accumulator ORed with D, bit of data.
Example ORI 20 H
Let the contents of register A =FO H. The immediate data contents (20 H) are
ORed with the contents of the accumulator. The result is stored in the
accumulator.

50. CMP R:

Operation:
This instruction connpares the contents of accumulator with the contents
register specified in the instruction. The conmparison is done by subtracting
of
contents of the register from the contents of the accumulator. The ressult
subtraction is discarded.
Computer Architecture (PTU) 3-51 Microprocessor 8085

The result is not storcd ir cither of the register or accumulator. The

accumulator
andregister remain unchanged. only flags areupdated.
If the contents of accumulator are equal to the contents of the register then the
zero tlag is set. If the contents of accunulator arc less than the contents of the
register then the carry flag is set. If the contents of accumulator are more than the
contentsof the register then the carry flag and the zero flag are reset.
The register Rmay be any general purpose register A, B. C. D. E. Hor L.
Note The compare instructions are often used with conditional Jump instructions.

Compare CF ZF
A>R 0
A<R 1
A=R 0 1

Example CMP B
Let A = 29 H, B = 43 H.
Then the instruction CMP B will result with carry flag set as the contents of the
accumulator are less than the contents of register B.
51. CMP M :

Operation :
This instruction compares the contents of accumulator with the contents of
memory location specified by the HL register pair. The comparison is done by
subtracting the contents of the memory location from the contents of the
accumulator. The result of subtraction is discarded.
The result is not stored in either of the memory location or accumulator. The
accumulator and register remain unchanged, only tlags are updated
If the contents of accumulator are cqual to the contents of the memory location
then the zero flag is set. If the contents of accumulator are less than the contents
of the memory location then the carry tlag is set. If the contents ot accumulalor
are more than the contents of the menory location then the carry tlag and the zero
flag are reset.
Note The compare instructions are often used with conditional Jump instructions.
Compare CF Z
A> M 0 0

A< M

A= M
 Microprocessor 808s
3-52
Computer Architecture (PTU)
CMP M memory location 5748 H=15 H.
Example of
H=57 H, L=48 H, contents contents of theaccumulator are more
Let A = 29 H, carry flag reset as
the
will result with ofregister B.
Then the instruction CMP M than the contents
52. CPI Data :
sets the conditinn
Operation immediate data with accumulator and
compares
This instruction
subtraction.
flags as a result of the
contents are not altered.
The accumulator Jump instructions
used with conditional
Note The compare instructions are often
CF ZF
Compare
A> M 0
A<M 1 0

A= M 1

Example CPIFO H
Let A = OFO H
flag reset as the contents of the
Then the instruction CPI FOH will result with zero
accumulator are equal to the contents of register B.
53. STC :
Operation This instruction sets the carry flag.
Before execution After execution

SF ZF U AF PF CF SF ZF AF PF U CF

Carry is set.
Fig.3.15
54. CMC :

Operation CY= CY
This instruction inverts the value of carry flag.
Before execution After execution
SF ZF U AF PF CF SF ZF U AF PF U CF
1

Carry is complemented
Fig. 3.16
Computer Architecture (PTU) 3-53 Microprocessor 8085

CMA:
55.
Operation : A= A

This instruction inverts the value of contents of the accumulator.

The complement is performing a NOT operation with each bit i.e. all 0's will be
replaced by l'sand all 1's with O's.
Example Suppose A= FE H, and CMA instruction is executed.
A =11111 110
A =00000001

56. RLC:

Operation CF +MSB LSB

to the left, by one bit

This instruction rotates all the bits in the accumulator
positions.
into the LSB. The data bit rotated
The data bit rotated out of MSB is circled back
bit BÍ as well as in carry.
out of MSB is also copied to CF. i.e. bit B, is placed in
Example RCL
Let A = 1111 1110, CY = 1
1bit to left.
This instruction rotates the contents of A register by
After execution
Before execution

Fig. 3.17

57. RRC :
CF MSB ’ LSB
Operation

This instruction rotates all the bits of the accumulator by 1bit position to the right.
The bit moved out of the LSB is rotated around into the MSB.
The data bit moved out of LSB is also copied into CF.
Bit Bo is placed in bit B, as well as in carry.
Example RRC
Let A = 1111 1110and CY= 1
 Computer Architecture (PTU) 3-54
MicroprOcessor 8085
Before execution After execution

Fig. 3.18
58. RAL :

Operation CF MSB -LSB

This instruction rotates all the bits in he

left along with the carry. accumulator by one bit position to the
Bit B, isplaced in Carry and Carry is
placed in bit Bo.
Example RAL
Let A = 1111 1110and CY = 1.
Before execution
After exxecution

59. rig. 3.19

RAR:
Operation CF ’ MSB ’ LSB

This instruction rOtates all

along with the carry. the bits of the
Bit Bois placed in
accumulator by one bit
position to rngnl
Carry and Carry is placed in bit
Example RAR B,.
Before execution
After execution

Fig. 3.20
Computer Architecture (PTU) 3-57 Mícroprocessor 8085

o477 Machine Control Instructions :

65. NOP :

Operation PC= PC+1

When this instruction is executed no operation is performed instead of that
instruction.
'66. HLT:
Operation
i.e. this instruction
When this instruction is executed, the microprocessor halts
interrupt or RESET signal.
stops the microprOcessor .It can be restarted by a valid
The registers and status flags remain unaffected.
67. El:
enable flip-flop is set so that all
When this instruction is executed the interrupt
maskable interrupts are enabled.
interrupt enable flip-flop is reset to
After an interrupt is acknowledged, the
reenable the interrupts.
68. DI :
enable flip-flop is reset so that all
When this instruction is executed the interrupt
maskable interrupts are disabled.
interrupts can be disabled.
Apart from TRAP all other maskable
69. RIM :
A= Status of interrupts
Operation
the interrupts is copied into the
When this instruction is executed the status of
accumulator.
pin.
It also reads serial data through the SID
Serial Pending Interrupt
interrupts mask
port Dg Dz D, Do
D, D6 Ds D4
SID I7.5I 6.5 I 5.5 IE M7.5 M6.5 M5.5
+Mask RST 5.5

Serial input data +Mask RST 6.5

Mask RST 7.5
RST 7.5
1 = Masked
0 = Unmasked
RST 6.5
+ InterTupt enable
RST 5.5
1= INTE flip-flop is set
1= Pending 0 = INTE flip-flop is reset
0 = Not active
Fig. 3.22
 Computer Architecture (PTU)

masked
I- interrupt is pending /
pending / masked
0- interrupt is not
logic Jer.l.
SID bit - specifies serial ip data. When RIM instruction is executed the
serial port.
Bit D, is status of
SID pin is copied at bitD,. interrupts. lf RST 7.5and RST5.5 innuto
of pending
Bits D, D, and D, are status RST 7.5. As the RST 5.5 is having Jecn
ISR of
occurs the 8085 will branch to interrupt. when RIM instruction is
RST 7.5 so it will be pending
priority then and RST 5.5 pending is copied at bits D6
executed the status of RST 7.5, RST 6.5
D, and D, respectively.
to D, are status of interrupt enable flip flop, mask 7.5, mask 6.5 and mask
Bits D,
5.5. When RIM instruction is executed the status of masking is
loaded at bits D., to
Do
Examples :
(a) RIM instruction is executed and accumulator bit pattern is 0010 0000. The bit
pattern indicates that RST 6.5 is pending interrupt.
(b) RIM instruction is executed and accumulator bit pattern is 0000 1010. The bit
pattern indicates interrupt enable flip flop is set, RST 6.5 is masked and RST 7.5
and RST 5.5 are unmasked.
70. SIM :

When this instruction is executed the

specified in the accumulator contents.
interrupts are masked or kept pending as
It also sends data on SOD pin.

Serial port
control
Dy
Interrupt control logic
D6 Ds D4 D3 De
SOD SDE X D Do
R7.5 MSE M7.5
M6.5 M5.5
Serialoutput data <
’Mask RST 5.5
Serial data enable
1= Enable serial port ’Mask RST 6.5
0= Disable serial port +Mask RST 7.5
Don't care 1 = Mask or disable
O= Unmask or enable
1=
0= Reset
R
No effect7.5
on flip-flop
Mask set enable
R7.5 1=Masking is enabled
O= Masking is disabled
Fig. 3.23
Computer Architecture (PTU) 3-59 MicroproOcessor 8085

1- interrupt is pending / masked

0-interrupt is not pending /masked
SODbit - specifies serial o/p data.
Bits D, and D,are serial port control. The SDE is enable bit used to enable/disable
serial output data.
Bit D, is R7.5 part of interrupt control logic. It is used to reset R 7.5 flip flop
regardless of RST 7.5 masking.
Bits D, to D, are part of interrupt control logic. These bits are used to mask RST
5.5, RST 6.5 and RST 7.5 interrupts. The MSE bit is master control over M 7.5,
M6.5 and M 5.5 bits. If MSE = 0, the M bits have no effect, but if MSE = 1, the
M bitsdecides mask or unmask respective interrupts.
To enable RST 6.5 and disable RST 7.5 and RST 5.5 the
Example
following SIM format is required.
SOD SDE X R7.5 MSE M7.5 M 6.5 M 5.5 = 0D H

1 0 1

MVI A, 0D H Load SIM format in accumulator

SIM Set interrupt mask
No. of bytes 1byte
Flags No flags are modified.
71. IN 8-bit address:
specified into
This instruction is used to copy data from input port address
accumulator.
specified is
When this instruction is executed the contents of port whose address is
copied into the accumulator.
IN 100 H
Example 100 H into the
address is
This instruction will copy the contents at port whose
accumulator

72. OUT 8-bit address :

This instruction is used to copy the contents of accumulator to the output port
whose address is specified into the instruction.
OUT 100 H
Example
This instruction will copy the contents of accumulator to the output port whose
address is 100 H.
 Computer Architecture (PTU) 3-60
MicroprOcessor 8085
RESTART
72. RST n:
[n is from 0 to 7]
Operation (SP - 1) = PCH
(SP - 2) = PCL
SP = SP 2
PC = (n x 8)in hex
This instruction transfers the program control to the specific memory addrese
shown in the table below.
It is used like a fixcd CALL instruction. These addresses are referred to as vector
addresses.
The microprocessor multiplics the RST by &to estimate these vector addresses.
Before transferring the program control to the instruction following the vector
address RST instruction saves the current programn counter contents on the stack
like CALL instruction.
These instructions can be used as software interrupts in aprogram to transfer
program execution to one of the 8 locations depending on which RST instruction
is executed.
Restart instructions and its locations are as followS :
Instructions Restart locations
RST 0 0 x 8=0000 H
RST 1 1x 8=0008 H
RST 2 2 x 8 = 0010H
RST 3 3 x 8 =0018H
RST 4 4 x 8= 0020H
RST 5 5x 8 = 00 28 H
RST 6 6x 8= 0030 H
RST 7 7x 8=0038 H
This instruction is equivalent to CALL 0010, the PC
contents are stored on to
stack and program sequence is transferred to address 0010 H.
Example 2: Write instruction (8085) to : Load OOH in the
accumulator : Display the result.
accumulator : Decrement the
(Dec. 2007)
Solution:
MVIA, OOH Load OOH in the accumulator
DCR A Decrement the accumulator
Separate two nibbles