SUBJECT CODE & NAME: CS3351 &DIGITAL PRINCIPLES &COMPUTER

ORGANIZATION

YEAR/SEMESTER: II/III BATCH: 2022-2026 ACADEMIC YEAR: 2023-2024 (ODD)

UNIT I

COMBINATIONAL LOGIC

PART A 10x2=20 Marks

1. Evaluate logic circuit of 2- bit magnitude comparator. (APR/MAY 2023)

Refer notes I page no:51

2. Construct the full adder using two half adder and OR gate. (APR/MAY 2019)

3. Construct half adder and full Adder. (APR/MAY 2023)

Refer notes I page no:32

4. What is meant by combinational circuits? Give examples. (NOV/DEC 2022)
When logic gates are connected together to produce a specified output for certain specified
combination of input variables, with no storage involved is called combinational circuits. Examples are
Adder, Comparator, Encoder, Decoder, Multiplexer, and DE multiplexer

5. Draw the truth table for half adder circuit. (APR/MAY 2019)

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6. What is meant by decoder circuit? (APR/MAY 2019)
A decoder is a multiple-input, multiple-output logic circuit that converts coded inputs into coded
outputs, where the input and output codes are different. The input code generally has fewer bits than
the output code, and there is one-to-one mapping from input code words into output code words.

7. Why NAND and NOR gates are called universal gates? (APR/MAY 2018)
A universal gate is a gate which can implement any Boolean function without need to use any
other gate type. The NAND and NOR gates are called as universal gates because they can perform all
these three essential functions of AND ,OR,NOT gates.
8. What do you mean by magnitude comparator?(NOV/DEC2019)
A magnitude digital Comparator is a combinational circuit that compares two digital or binary
numbers in order to find out whether one binary number is equal, less than, or greater than the other
binary number. We logically design a circuit for which we will have two inputs one for A and the
other for B and have three output terminals, one for A > B condition, one for A = B condition, and
one for A < B condition.
9. Distinguish between a decoder and encoder.
Encoder: It converts the applied information signal into a coded digital bit stream.
The number of inputs accepted by an encodes is 2 n.
The output lines for an encoder are n.
Decoder: It performs reverse operation and recovers the original information signal from the coded
bits.
The number of inputs accepted by decoder is only n inputs.
The output lines of an decoder is 2 n.
10. What is multiplexer?(NOV/DEC2022)
A mux is a combinational circuit that selects binary information fr4om one of many input lines And
direct it to a single output line. The selection particular input line is controlled by a set of selection
lines. Normally, there are 2n input lines and n selection lines whose bits combination determines
which input is selected.

PART B 5X13=65 Marks

1. Design a 4-bit binary adder/sub tractor circuit. (APR/MAY 2019) (APR/MAY 2023)

Refer notes I page no:37-49

2. Explain the logic diagram for priority encoder. (APR/MAY 2019) (APR/MAY 2023)

Refer notes I page no:64-66

3. Design a full adder using two half adder and verify the truth table. (APR/MAY 2023)

Refer notes I page no:33-36

3. Simply the function using multiplexer f=∑(0,1,3,4,8,9,15) (APR/MAY 2023)

Refer notes I page no:77

4. Write short notes on Demorgan’s theorem, absorption law, consensus law.(NOV/DEC2018)

Refer notes I page no:4-9

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5. Design and verify BCD to grey code conversion. (APR/MAY 2019)

Refer notes I page no:54-57

PART C 1x15=15 Marks

1.Simplify F=(A,B,C,D)=∑(0,1,2,5,8,9,10) in SOP and POS using K-map.(NOV/DEC2019)

Refer notes I page no:23

2. Outline the design of 3 to 8 line decoder circuit using NOT and AND gates and also present
Truth table for the same. (NOV/DEC2022)

Refer notes I page no:59-61

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SUBJECT CODE & NAME: CS3351 &DIGITAL PRINCIPLES &COMPUTER
ORGANIZATION

YEAR/SEMESTER: II/III BATCH: 2022-2026 ACADEMIC YEAR: 2023-2024 (ODD)

UNIT-2
SYNCHRONOUS SEQUENTIAL LOGIC

PART A 10x2=20 Marks

1. State the difference between latches and flip-flops.(APR/MAY 2019)

s.no Latch Flip-flop

1 A simple latch is the basis for flip-flop It is built by connection some additional
components around a latch.

2 It operates with signals levels and their It have their content change only either at the
content changes immediately when their rising edge or falling edge of the enable
inputs change. signal.

3 It is also called as level sensitive devices It is also called as edge sensitive device.

2. What is meant by edge triggered flip-flop.(APR/MAY 2019)

The output responds to the changes in the input only at the positive or negative edge of the clock pulse
at the clock Input.

3. Draw the logic diagram and write the function of D-latch. (APR/MAY 2019)

Refer notes I page no:92

4. Outline the difference between synchronous and asynchronous circuit.(NOV/DEC2022)

s.no Synchronous Asynchronous circuit

1 These are digital circuits governed by clock These are digital circuits that are not driven
signals by clock

2 They bare also called as clocked sequential They can be called as self timed circuits
Circuits

3 Output behavior on the input at discrete time Output depends on the sequence in which the
input changes

5. Distinguish sequential logic with combinational logic. (APR/MAY 2023)

s.no combinational logic sequential logic

1 Memory unit is not required Memory unit is need to store the past input
states.

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2 Faster than sequential circuit Slower than combinational circuit

3 Easy to design It is comparatively harder to design

6. Give the excitation table of JK flip flop. (APR/MAY 2023)

Refer notes I page no:101

7. Draw the logic diagram of SR flip-flop.

Refer notes I page no:88

8. What is called latch?

In the latches, their outputs are constantly affected by their inputs as long as the enable signal is
asserted.Simply,storing elements that operate with signal levels and their content changes immediately
when their input changes.

9. What is ring counter?

A ring counter is a circular shift register with only one flip-flop being set at any particular time and all
others are cleared .The single bit is shifted from one flip-flop to the next to produce the sequence of
timing signal.

10. Define state diagram. Write the uses of state diagram.

State diagram is a graphical representation of the information available in the state table .Here, a state
is represented by a circle and the transitions between states are indicated by directed lines connecting
the circles.

Each line originates at a present state and terminates at a next state , depending on the input applied
when the circuit is in the present state.

PART B 5X13=65 Marks

1. Describe the operations of SR flip-flop with neat sketch. (APR/MAY 2019)
(NOV/DEC2022)

Refer notes I page no:86-92

2. Realize D-flip-flop using SR flip-flop and construct 4-bit down counters using logic gates.
(APR/MAY 2023)

Refer notes I page no:96-98

3. Give the analysis and design of clocked sequential circuits. (APR/MAY 2023)

Refer notes I page no:105-110

4. Outline the Moore model and Mealey model of sequential circuits with neat diagram.
(NOV/DEC 2022)

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Refer notes I page no:111-113

5. What is shift-registers? Outline the design of 4-bit shift registers with neat diagram.
(NOV/DEC 2022)

Refer notes I page no:121-124

PART C 1x15=15 Marks

1. Outline the BCD ripple counter using JK flip-flop with state diagram and logic diagram.
(NOV/DEC 2022)

Refer notes I page no:131-133

2. Explain in detail about 4- bit Johnson counter. (NOV/DEC 2018)

Refer notes I page no:128-130

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SUBJECT CODE & NAME: CS3351 &DIGITAL PRINCIPLES &COMPUTER
ORGANIZATION

YEAR/SEMESTER: II/III BATCH: 2022-2026 ACADEMIC YEAR: 2023-2024 (ODD)

UNIT-III
COMPUTER FUNDAMENTALS

PART A 10x2=20 Marks

1. Draw the stock diagram of von-Neumann architecture. (APRIL/MAY 2023)

Refer notes II page no:2

2. List the types of addressing modes. (APRIL/MAY 2023)
 Register mode
 Absolute mode or direct mode
 Immediate mode
 Indirect mode
 Index mode
 Relative mode
 Auto increment mode
 Auto decrement mode
3. What is data transfer function? (NOV/DEC2022)
The operation involves the movement of data from one virtual machine storage to another virtual
machine storage.
4. Define immediate & absolute Addressing Mode.
The operand is given explicitly in the instruction. The address of the location of the operand is given
explicitly as a part of the instruction.
5. What is instruction set architecture?
One of the most important abstractions is the interface between the hardware and the lowest software.
Because of its importance, it is given a special name instruction set architecture of a computer.
6. State the need for indirect addressing modes. Give an example.
In indirect addressing mode, the instruction specifies the address where the address of the operand is
located. In case of register indirect addressing, the address of the operand is specified by the contents
of the register. These operating modes are needed when we need to access arrays.specially,in register
indire3c addressing, registers are used as pointers and they are very useful for dealing with arrays or
tables of simple data values.
7. What is stack addressing modes?
A stack addressing modes is a linear array of reserved memory locations. It is associated with a pointer
called stack pointer. Usually stack grows in the direction of descending addresses, starting from a high
address and progressing to lower one. In these stacks is decremented before any items are appended on
stack and SP is incremented after any items popped from the stack.
8. Define interpreter.
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It is high level language statement in a source program to a machine code and executes it immediately,
before translating the next source language statement. When an error is found, the execution of the
program is halted and an error message is displayed on the screen of the computer.
9. Compare machine level, assembly level and high level language.
s.no Machine language Assembly language High-level language
1 Programs require less Programs require less memory Programs require more
memory memory
2 Programs have less Programs have less execution Programs have more execution
execution time time time
3 Program development Simpler than machine language Program development is easy
is difficult
4 It is not user friendly It is less user friendly It is user friendly
10. What is the role of MAR and MDR?
The MAR is used to hold address of the location to or from which data are to be transferred the MDR
contains the data to be written into or read out of the addressed location.

PART B 5X13=65 Marks

1. Explain about functional unit in digital computer. (APRIL/MAY 2023)
Refer notes II page no:1-6

2. Discuss about instruction Sequencing. (APRIL/MAY 2023)

Refer notes II page no:13-23

3. Explain about encoding in assembly language and types of instructions (APRIL/MAY

2023)Refer notes II page no:28-29

4. Outline Von-Neumann architecture with neat diagram. (NOV/DEC2022)

Refer notes II page no:1-6,30-31

5. What are addressing modes? Outline the types of addressing modes with an example.
(NOV/DEC2022)
Refer notes II page no:24-27

PART C 1x15=15 Marks

1. Discuss the interaction between assembly language and high level language.
(APRIL/MAY 2023)

Refer notes II page no:30-31

2.Write a program to evaluate the arithmetic statement Y=(A+B)*(C+D) using three address,
two-address, one-address and zero-address instructions.
Refer Notes I Page no (134-135)

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SUBJECT CODE & NAME: CS3351 &DIGITAL PRINCIPLES &COMPUTER
ORGANIZATION

YEAR/SEMESTER: II/III BATCH: 2022-2026 ACADEMIC YEAR: 2023-2024 (ODD)

UNIT-IV
PROCESSOR

PART A 10x2=20 Marks

1. What do you mean by pipelining? List its types. (APRIL/MAY 2023), (NOV/DEC 2022)
The pipelining is a technique of decomposing a sequential process into stub operations with each stub
process being executed in a special dedicated segment that operated concurrently with all other
segments.
2. Differentiate data hazards and control hazards. (APRIL/MAY 2023)
Whether either the source or the destination operands of an instruction are not available at the time
expected in the pipeline and as a result pipeline is stalled, we say such a situation, is a data hazard.
The hazard due to pipelining branch and other instructions that change the contents of program counter
is called instruction or control hazard.
3. What is program counter? (NOV/DEC 2022)
PC is a specialized register and contains the memory address of the next instruction to be fetched and
executed. During the execution of an instruction, the contents of the PC are updated to correspond to
the address of the next instruction to be executed.
4. Define instruction fetch cycle.(APRILMAY 2018)
In this cycle, the instruction is fetched from the memory location whose address I sin the PC.This
instruction is placed in the IR in the processor.
5. Define data path.
Data path is a unit use to operate on or hold data within processor. Its elements include the instruction
and data memories, the register file, the ALU and adders.
6. What is meant by hazards in pipelining?
Any reason that causes the pipelining to stall is called a hazard.
7. Mention the various phases in executing an instruction.
Fetch, decode, execute, store.
8. Name the control signals required to perform arithmetic operation.
Control signal RegDst,Regwrite and ALUop1 are required to perform arithmetic operation
9. What are the types of data hazards?
RAW, WAW,WAR
10. Define pipeline bubble/pipeline stall.
It is a delay in execution of an instruction in an instruction pipeline in order to resolve a hazard.

PART B 5X13=65 Marks

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1. What are hazards? Give the hazard free realization for the following Boolean functions
F(A,B,C,D)=∑m(1,5,6,7) using AND –OR gate network. Discuss essential hazards.
(APRIL/MAY 2023)
Refer notes II page no:

2. Outline the control unit with neat diagram and state the functions performed by control unit.
(NOV/DEC 2022)
Refer notes II page no:45-47

3. Outline the difference between hardwired control and microprogrammed control.

(NOV/DEC 2022)
Refer notes II page no:48-52

4. What are pipeline hazards? List the types of pipeline hazards. (NOV/DEC 2022)

Refer notes II page no:53-59

5. Explain in detail about MIPS implementation.(APRIL/MAY 2019)

Refer notes II page no:39-44

PART C 1x15=15 Marks

1. Write short notes on data hazards.(NOV/DEC 2018)
Refer notes II page no:57-59

2. Write short notes on control hazards.(APRIL/MAY 2018)

Refer notes II page no:59-60

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SUBJECT CODE & NAME: CS3351 &DIGITAL PRINCIPLES &COMPUTER
ORGANIZATION

YEAR/SEMESTER: II/III BATCH: 2022-2026 ACADEMIC YEAR: 2023-2024 (ODD)

UNIT-V
MEMORY and I/O

PART A 10x2=20 Marks

1. Why do we need memory as hierarchy? (APRIL/MAY2023)
Ideally, computer memory should be fast, large and inexpensive.Unfortunately,it is impossible to meet
all the three of these requirements using one type of memory. Hence it is m=necessary to implement
memory as hierarchy.
2. What is hit time?(NOV/DEC 2022)
A successful access to data in cache memory is called hit time
3. What is direct mapping cache? (NOV/DEC 2022)
It is a cache structure in which each memory location is mapped to exactly one location in the cache.
4. Compare DRAM and SRAM.
s.no DRAM SRAM
1 Contains more cells as compared to SRAM Contains less cells
2 More access time Less access time
3 Cost is less Cost is more
4 Refreshing circuitry is required Refreshing circuitry is not required

5. How many total bits are required for direct mapped cache with 16 kb o data and 4-word
blocks, assuming a 32-bits address?
16kb =4K words=212 words
Block size of 4 words=210 blocks
Each block has 4x32=128 bits of data +tag+valid bit
Tag+valid bit=(32-10-2-2)+=19
Total cache size=210(128+19)=2 10x147
147kb are needed for the cache.
6. What is called a hub?
Each node of the tree has a device called a hub which acts as an intermediate control point between the
host and the I/O devices
7. What are the characteristics of semiconductor RAM memories?
 Cycle time range from 100ns to less than 10 ns
 Replaced the expensive magnetic core memories
 Used for implementing memories

8. What is tan interrupt?

An interrupt is an event causes the execution of one program to be suspended and another program to
be executed.
9. Define cache memory.
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In the memory system small of SRAM is added along with main memory, referred to as cache memory
10. What does isochronous data stream means?
The sampling process yields a continuous stream of digitized samples that arrived at regular intervals,
synchronized with the sampling clock. Such a data stream is called isochronous data stream, meaning
that successive events are separated by equal periods of time.

PART B 5X13=65 Marks

1. Explain detail about DMA operation. Discuss about modes of DMA. (APRIL/MAY2023)
Refer notes II page no:76-79

2. Discuss about parallel serial interface.

Refer notes II page no:86-89

3. Elucidate interconnection standards. (APRIL/MAY2023)

Refer notes II page no:93-97

4. Present an outline of virtual address, physical address, address translation, segmentation,

Page table, swap space, page Fault.(NOV/DEC 2022)
Refer notes II page no:72-75

5. Present an outline of interrupt driven I/O.(NOV/DEC 2022)

Refer notes II page no:59-60

PART C 1x15=15 Marks

1. Explain in detail about memory Hierarchy.( APRIL/MAY 2019)
Refer notes II page no:61-66

2. Outline about cache memories.(APRIL/MAY 2019)

Refer notes II page no:60-72

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