XXXXX: Important Instructions To Examiners
XXXXX: Important Instructions To Examiners
XXXXX: Important Instructions To Examiners
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WINTER – 2022 EXAMINATION
Subject Name: Microprocessor Model Answer Subject Code: 22415
Important Instructions to examiners: XXXXX
1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme.
2) The model answer and the answer written by candidate may vary but the examiner may try to assess the
understanding level of the candidate.
3) The language errors such as grammatical, spelling errors should not be given more Importance (Not applicable for
subject English and Communication Skills.
4) While assessing figures, examiner may give credit for principal components indicated in the figure. The figures
drawn by candidate and model answer may vary. The examiner may give credit for any equivalent figure drawn.
5) Credits may be given step wise for numerical problems. In some cases, the assumed constant values may vary and
there may be some difference in the candidate’s answers and model answer.
6) In case of some questions credit may be given by judgement on part of examiner of relevant answer based on
candidate’s understanding.
7) For programming language papers, credit may be given to any other program based on equivalent concept.
8) As per the policy decision of Maharashtra State Government, teaching in English/Marathi and Bilingual (English +
Marathi) medium is introduced at first year of AICTE diploma Programme from academic year 2021-2022. Hence if
the students in first year (first and second semesters) write answers in Marathi or bilingual language (English
+Marathi), the Examiner shall consider the same and assess the answer based on matching of concepts with
model answer.
(ii) DT/𝐑̅ (Pin number 27) – This pin is used to show whether the data is getting
transmitted or is received. A high signal at this pin provides the information regarding
the transmission of data. While a low indicates reception of data.
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ROL BX, CL
OR
MOV CL,04H
RCL BX, CL
c) List directives used for procedure. 2M
Ans The assembler directive that are used for defining a procedure in the 8086 Each 1 M
microprocessors are: PROC and ENDP
Ans 1) Load the count in CX and clear AX and BX. Any other
2) Store the starting address in SI. correct relevant
3) Move data stored at address pointed by SI in DX. algorithm 2 M
4) Add AX=AX+DX.
5) If carry exists, increment BX.
6) Increment SI twice. Decrement CX.
7) If CX is not zero, return to step 3.
8) Store the sum (AX) and carry (BX) in memory.
9) Terminate the program.
f) What is the use of REP in string related instruction? Explain. 2M
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Two more prefix.
REPE/REPZ: Repeat if Equal /Repeat if Zero.
It will cause string instructions to be repeated as long as the compared by words Are
equal and CX≠0.
REPNE/REPNZ: Repeat if not equal/Repeat if not zero.
It repeats the strings instructions as long as compared bytes or words are not equal
And CX≠0.
Example: REP MOVSB
Re-entrant Procedures:
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Description:
Data segment is used to hold data, Code segment for the executable program,
Extra segment also holds data specifically in strings and stack segment is used
to store stack data.
Each segment is 64Kbytes & addressed by one segment register. i.e CS,DS,ES
or SS
The 16 bit segment register holds the starting address of the segment.
The offset address to this segment address is specified as a 16-bit displacement
(offset) between 0000 to FFFFH. Hence maximum size of any segment is
216=64K
locations.
Since the memory size of 8086 is 1Mbytes, total 16 segments are possible with
each having 64Kbytes.
The offset address values are from 0000H to FFFFH so the physical address
range
from 00000H to FFFFFH.
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2) EQU: Equate to
The EQU directive is used to declare the micro symbols to which some constant value
is assigned.
Micro assembler will replace every occurrence of the symbol in a program by its value.
Syntax: Symbol name EQU expression
Example: CORRECTION_FACTOR EQU 100
3) SEGMENT:
The SEGMENT directive is used to indicate the start of a logical segment. Preceding
the SEGMENT directive is the name you want to give the segment.
For example, the statement CODE SEGMENT indicates to the assembler the start of a
logical segment called CODE. The SEGMENT and ENDS directive are used to
“bracket” a logical segment containing code of data
4) ASSUME: Assume directive is used to tell Assembler the name of the logical
segment it should use for the specified segment.
Example: Assume CS: MAP_CODE, DS: MAP_DATA
d) What are the functions of CALL and RET instructions? Describe in brief. 4M
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Ans CALL Instruction: It is used to transfer program control to the sub-program or 2M-For Each
subroutine. The CALL can be NEAR, where the procedure is in the same segment Instruction
whereas in FAR CALL, procedure is in a different segment.
Syntax: CALL procedure name (direct/indirect)
Operation: Steps executed during CALL
Example:
1) For Near CALL
SP ←SP - 2
Save IP on stack
IP address of procedure
2) For Far call
SP ← SP-2
Save CS on stack
CS New segment base containing procedure
SP←SP-2
Save IP on stack
IP Starting address of called procedure
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4. DX – Data register can be used as a port number in I/O operations and implicit
operand or destination in case of few instructions. In integer 32-bit multiply and divide
instruction the DX register contains high-order word of the initial or resulting number.
5. CS – Code Segment – holds base address for all executable instructions in a program
Segment registers:
To complete 1Mbyte memory is divided into 16 logical segments. The complete
1Mbyte memory segmentation is as shown in above figure. Each segment contains
64Kbyte of memory. There are four segment registers.
1.Code segment (CS) is a 16-bit register containing address of 64 KB segment with
Processor instructions. The processor uses CS segment for all accesses to instructions
Referenced by instruction pointer (IP) register.
2.Stack segment (SS) is a 16-bit register containing address of 64KB segment with
Program stack. By default, the processor assumes that all data referenced by the stack
Pointer (SP) and base pointer (BP) registers is located in the stack segment.
3.Data segment (DS) is a 16-bit register containing address of 64KB segment with
Program data. By default, the processor assumes that all data referenced by general
Registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment.
4.Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually
with program data.
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Pointers and index registers.
The pointers contain within the particular segments. The pointers IP, BP, SP
usually contain offsets within the code, data and stack segments respectively.
Stack Pointer (SP) is a 16-bit register pointing to program stack in stack segment.
Base Pointer (BP) is a 16-bit register pointing to data in stack segment.
Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and
register
Indirect addressing, as well as a source data addresses in string manipulation
instructions.
Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and
register indirect addressing, as well as a destination data address in string manipulation
Instructions.
UP:
MOV AL , [SI] ; Read byte from memory
ADD SUM_LSB , AL ; Add with sum
DAA
JNC NEXT
INC SUM_MSB
NEXT:
INC SI ; Increment memory pointer
LOOP UP ; Decrement byte counter
; If byte counter==0 then exit
; else read next number
MOV DL , SUM_MSB
MOV AH , 2
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INT 21H
MOV DL , SUM_LSB
MOV AH , 2
INT 21H
MOV AH , 4CH
INT 21H
END
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START:MOV AX,DATA
MOV DS,AX
CALL FACTORIAL
MOV AH,4CH
INT 21H
FACTORIAL PROC
MOV AX,A
MOV BX,AX
DEC BX
UP: MUL BX ; MULTIPLY AX * BX
MOV FACT_LSB,AX ;ANS DX:AX PAIR
MOV FACT_MSB,DX
DEC BX
CMP BX,0
JNZ UP
RET
FACTORIAL ENDP
CODE ENDS
END START
d) Write an assembly language program for conversion of BCD to Hexe 4M
number.
Ans 4M- For Correct
Program
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CODE ENDS
END START
1.
c) Write an assembly language program to Count No. of 1's in a 16-bit 4M
number.
Ans Assume the number to be stored in BX register. Store the result in CX register. 4M- For Correct
MODEL SMALL Program
.DATA
NUM DW 0008H
ONES DB 00H
.CODE
START:
MOV AX,@DATA
MOV DS,AX
MOV CX, 10H ; initialize rotation counter by 16
MOV BX, NUM ; load number in BX
UP: ROR BX, 1 ; rotate number by 1 bit right
JNC DN ; if bit not equal to 1 then go to DN
INC ONES ; else increment ones by one
DN: LOOP UP ; decrement rotation counter by 1 and if not zero
then go to up
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X = (A +B) * (C +D)
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a) Define logical and effective address, Describe physical address generation process 6M
in S086 microprocessor. Calculate physical address by taking suitable DS, CS and
IP.
Ans Logical Address: It is generated by CPU in perspective of program. A logical address Definition-2 M
may be different from the physical address due to the operation of an address translator
or mapping function. Description-2 M
Effective Address or Offset Address: The offset for a memory operand is called the
Calculation
operand's effective address or EA. It is an unassigned 16 bit number that expresses the Example-2 M
operand's distance in bytes from the beginning of the segment in which it resides. In
8086 we have base registers and index registers.
Generation of 20 bit physical address in 8086:-
1. Segment registers carry 16 bit data, which is also known as base address.
2. BIU appends four 0 bits to LSB of the base address. This address becomes 20-bit
address.
3. Any base/pointer or index register carries 16 bit offset.
4. Offset address is added into 20-bit base address which finally forms 20 bit physical
address of memory location
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Example: MOV AX, [BX+SI]
7. Register relative addressing mode: An instruction in which the address
of the operand is obtained by adding the displacement (8-bit or 16 bit) with the contents
of base registers or index registers (BX, BP, SI, DI). The default segment register is DS
or ES.
Example: MOV AX, [BX+50H]
8. Relative Based Indexed addressing mode
An instruction in which the address of the operand is obtained by adding the
displacement (8 bit or 16 bit) with the base registers (BX or BP) and index Registers
(SI or DI) to the default segment.
Example: MOV AX, [BX+SI+50H]
Ans Branch instruction transfers the flow of execution of the program to a new address Any 3 branch
specified in the instruction directly or indirectly. When this type of instruction is instructions: 2
executed, the CS and IP registers get loaded with new values of CS and IP M each
corresponding to the location to be transferred
Unconditional Branch Instructions:
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Syntax: IRET
Conditional Branch Instructions When this instruction is executed, execution control is
transferred to the address specified relatively in the instruction
1. JZ/JE Label :
8. JP Label
Transfer execution control to address ‘Label’, if PF=1.
9. JB Label
Transfer execution control to address ‘Label’, if CF=1.
10. JNB Label
Transfer execution control to address ‘Label’, if CF=0.
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All flags are updated; OF becomes Undefined after this instruction.
For AL register ONLY
If D3 – D0 ˃ 9 OR Auxiliary Carry Flag is Set, ADD 06H to AL.
If D7 – D4 ˃ 9 OR Carry Flag is Set, ADD 60 H to AL.
Assume : AL = 14H,
CL = 28H
Then ADD AL,CL gives
AL = 3CH
Now DAA gives
AL = 42(06 is added to AL as C> 9)
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Ans
Start
AL = [SI]
Copy Character in AL to DI
[DI]= AL
]
Increment SI and Decrement DI
Decrement CX
N
Is CX= 0
Stop
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