Hardware Solutions for Fuzzy Control

ALESSANDRA COSTA, ALESSANDRO DE GLORIA, PAOLO FARABOSCHI,

ANDREA PAGNI, AND GIANGUIDO RIZZOTTO

A large fraction of sofhoare designs using microcontrollers is play an important role [9], [IO], [24], [26]. The areas where
today adopting fuzzy logic algorithms and this fraction is likely fuzzy logic has been successfully applied encompass a
to increase in the future. Hardware implementation of fuzzy logic wide variety of applications, characterized by extremely
ranges from standard microprocessors to dedicated ASIC’s and
each different approach is targeted to a different application different complexity and time performance ranges. For
domain or market area. instance, we can find fuzzy control algorithms in washing
In this paper, we present an overview of the computational com- machine control, automatic focusing control, servo motor
plexity of the fuzzy inference process and the various techniques force control, and many other devices [1]-[3], [8], [12],
adopted for fuzzy control tasks, highlighting the tradeoffs that
can guide a system designer toward correct choices according to
[161, [461, [471.
application features and imt/petjormance issues. Finally, we observe that the use of FL is not limited to
In addition, we detail three case studies of architectures that control fields, but it also applies to other decision making
address three different market segments in the fuzzy hardware tasks based on experience such as medical diagnosis [ 5 ] ,
scenario: dedicated fuzzy coprocessors, RlSC processors with [32], business forecasting, image processing and computer
specialized fuzzy support and application specific fuzzy ASIC’s. vision [18], [211, [231, [291, and many more [ l l ] , [31].
I. INTRODUCTION 11. COMPUTATIONAL COMPLEXITY OF FUZZY INFERENCES
Fuzzy logic (FL) is a computational paradigm originally The term f u u y inference indicates the process that com-
developed in the early 1960’s [48], [50] that provides a putes an output value from an input value by means of the
mathematical tool to deal with the uncertainty and the application of linguistic rules.
imprecision typical of the human reasoning. The main char- From now on, we use the term rule base to represent the
acteristic of FL is its capability to express the knowledge whole set of rules involved in an application. Fuzzy rules
in a linguistic way, allowing a system to be described by have an j. f - then structure and involve linguistic values
simple. human friendly rules. This alternative linguistic ap- for the input and the output variables.
proach leads to a meaningful reduction of the computational We can distinguish two parts in a fuzzy rule:
burden and to an improvement of the description capability
overcoming the conflicting logic sometimes generated by 1) The antecedent part, i.e., the terms between I F and
the traditional rigid binary logic [49]. However, we must THEN concerning the inputs (premises), and
stress the fact that FL solutions are usually not aimed at 2) the consequent part, i.e., the terms after ‘THENcon-
achieving the computational precision of traditional tech- cerning the outputs (conclusions).
niques, but aims at finding acceptable solutions in shorter
time. We observe that the general format of a rule includes
It is important to underline that FL and traditional control both AND and OR functions to combine the premises.
techniques should not to be considered as antagonist but However, in some case (Max-Min inference method), we
as complementary approaches. FL is not a panacea for all can restructure the rule base so that only AND rules are
applications, but a useful tool to solve still pending issues used, by using the distributive property of the und operator.
that can not be easily tackled with traditional methods. For instance a rule of the form
The natural applications of FL to control systems are if ( A or B ) and C thenX
those systems whose mathematical model is unknown, very
complex or time-varying, and where human experience can can be equivalently translated in the pair of rules
Manuscript received April 19, 1994; revised November 29, 1994. if AandCthenX
A. Costa, A. De Gloria, and P. Faraboschi are with the Department if BandCthenX
of Biophysics and Electrical Engineering (DIBE), University of Genoa,
16145 Genova, Italy. The output values are computed from the evaluation of
A. Pagni and G. Rizzotto are with SGS-Thomson Microelectronics,
20041 Agrate Brianza (MI), Italy. the whole rule base, taking into account the contribution of
IEEE Log Number 9408302. the single rule, through three main steps:

0018-9219/95$04.00 0 1995 IEEE

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 Fuuijkation: is the operation that translates a crisp data 111. IMPLEMENTATION
ALTERNATIVES
value in a linguistic variable to a membership degree (called
alpha value). The membership degree depends on the shape A. Classification and Problem Space
of the membership function used [38]. There are two basic A fuzzy rule base is characterized by a set of parameters
strategies for the evaluation of membership degrees: that identify its computational complexity:
1) Memory Oriented Approaches: The membership de-
Number of crisp and fuzzy inputs;
grees for each input and output are evaluated off-line and Number of crisp and fuzzy outputs;
stored in memory as discretized values. In this case the Number and shape of membership functions per in-
shape of the membership function does not influence the
put/output;
computational load of the algorithm. Despite this advantage, Number of rules;
if we decide to have a high discretization resolution, the
Number of antecedentskonsequents per rule;
memory occupied will be very large. In details, if we have Precision (number of bits for discretizing the span and
Nmf membership functions, use b;, bits for the input value the alpha values of MF); and
and b, bits for alpha value, we need Mmf bytes for storing Algorithm variants (membership computation method,
the membership functions, where:
rule inferencing method, defuzzification method).
In addition to complexity parameters, we need to define
speed parameters to establish a consistent basis for com-
parison. We measure performance in terms of the system
response time, i.e., the latency required by the fuzzy system
For example, 50 MF with 8 b resolution on input and alpha to generate a crisp output after presented with a crisp input.
value require 409.600 bytes. However only one address There are two main reasons for our choice:
computation and one memory access is required to compute
a single alpha value. Specialized measurement units proposed in literature,
2 ) Computation Oriented Approaches: The evaluation of such as the fuzzy logic inferences per second (FLIPS),
the alpha values is made on-line, and we have to store only rely on the concept of fuzzy inference that is not
the parameters needed to calculate the membership degrees. uniquely defined and may be ambiguous depending on
the assumptions on number and type of inputs/outputs,
In this case the shape of the membership functions is a very
important aspect since the drawbacks on the computational precision, rule format, and so on.
Processor throughput time (outputs per second) may
load can be significant. In case of triangular membership
functions, the necessary parameters are the gradient and the be misleading since, in control applications, the out-
puts of a fuzzy controller influence its future inputs.
intercept of the two straight lines composing the triangle.
For this reason, pipelined fuzzy hardware that begins
Execution time depends on the shape of the membership
functions. For triangular (trapezoidal) functions, we need processing inputs before outputs are generated may be
4 (5) comparisons, 1 addition and 1 multiplication to useless.
compute the alpha value. For example, we need only 100 Fig. 1 shows a qualitative classification of typical control
bytes to store 50 triangular membership functions (e.g., problems depending on the complexity (number of rules)
10 inputs with five sets each), but two memory accesses, and the system response time.
three comparisons, one addition and one multiplication to
compute a single alpha value. B. Hardware and Software: Where to Draw the Line?
3 ) Fuzzy Inference is the operation that uses the rule base As in other application domains, fuzzy logic imple-
and the alpha values to deduce the fuzzy output. This step mentations suffer from the never ending debate between
can be accomplished in many different ways. The most supporters of general purpose systems and of dedicated
classical inference methods are the ma-min method and systems, and many solutions have been proposed for either
the m a - d o t method [51]. If each rule involves all input alternative.
variables (worst case) and we have R rules, we must The structure and relative simplicity of fuzzy processing
execute R( N i , - 1) cascaded minimum operations. algorithms, naturally leads to straightforward implementa-
4 ) Defuzz$ication is the step that translates the fuzzy tions in dedicated hardware structures. The problem is to
output to a precise answer (also called crisp output). In decide how much flexibility (in terms of programmability,
case of control applications,.the crisp output is usually the membership functions, inferencing method, defuzzification
value of the control action. Many defuzzification methods method, rule format, precision, to name a few) we should
have been proposed in literature. The most commonly used support in a dedicated fuzzy device.
are the center of gravity method, the centroid method and Obviously, an optimal solution for the full application
the mean of maxima method [19], [38].For example if we range of fuzzy logic does not exist, but different approaches
decide to use the centroid or the center of gravity methods, have to be used according to the rule base complex-
we need to execute a number of multiply-and-accumulate ity and application features. Speed, complexity, real-time
steps that is proportional to the number of rules. In this case constraints, and interaction requirements with nonfuzzy
the complexity is logarithmic with respect to the number algorithms are the factors that influence the choice of a
of rules: O(Iog,(R)). fuzzy controller design.

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 I I I I I I
t

10 100 loo0
Complexity (tuzzy rules)

Fig. 1. Control applications: complexity and performance.

$
C. General-Purpose Solutions
Software implementation of fuzzy algorithms on standard
microcontrollers (MC68HC11, i8 051, ST9, etc.) are today
the most widely used techniques. While this approach well
suites nontime-critical applications it becomes inadequate
whenever processes requiring high or medium throughput
appear.
The following table shows advantages and disadvantages
of the approach.
Pros:
I I ,
10 1W IOW complete flexibility,
Complexity (tuzzy rules)
support of nonfuzzy computations by itself,
Fig. 2. Hardware alternatives versus problem complexity and availability of development systems, and
speed. availability of system support tools.
As a general taxonomy, we can identify four classes Cons:
among the different implementation alternatives: slow speed.
An interesting example in this area is represented by
Software and hardware solutions with general purpose the cooperation between Motorola and Aptronix, whose
components. intent is to provide a fuzzy development system for existing
General purpose processors with instructions for spe- microcontrollers. The development system, called Fuzzy
cialized computations. Inference Development Language (FIDE) [ 5 ] , [25] has been
Dedicated fuzzy coprocessors. developed by Aptronix and allows the user to define U 0
Fuzzy ASIC’s capable of stand-alone operations. variables, membership functions, rules and source code for
Fig. 2 shows a qualitative allocation of the different specific applications. The system then can generate real-
classes in the problem space. time code for existing Motorola microcontrollers, such as
The stages of development, prototyping, low and high the 6805, 68HC05, and 68HC11.
volume production may obviously require different solu- The same approach is followed by Inform [13] which
tions to meet performance and cost criteria. For instance, developed fuzzyTECH. Different so-called Edition of
if an application is fixed and we are focused on volume fuzzyTECH are available to best complement the needs of
production, we can easily trade some flexibility for a cost various hardware platforms. For example the fuuyTECH
reduction, and prefer a completely fixed ASIC solution MCU-XX Editions can generate the assembly code for the
against the choice of a programmable (but expensive) ST-6, 8051, 8096, 80C196, TMS320 as well as for other
microcontroller. On the other side, during the development microcontrollers.
phase, we demand flexibility but may disregard cost. Fig. 3 Moreover, fuzzyTECH Precompiler Edition generates a
shows the likely choices according to the design phase and complete fuzzy logic system as highly optimized, royalty-
the application nature. free C source code for solution that have to be integrated

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 programmability
.

. *
a
I* Applicrlon

Fig. 3. Hardware alternatives versus design phases.

as portable C code with other software on different target simple extension of existing cores, and
hardware platforms. automatic support of nonfuzzy computations.
TIL Shell by Togai InfraLogic [41] is a Windows-based Cons:
tool for the development of fuzzy applications. It supports higher cost compared to standard, microcontrollers
real time on line debugging and tuning of fuzzy rules and (due to smaller production volume), and
MF's and allows the user to choose the inference method as limited performance for high-end applications.
well as the defuzzification technique. It also supports the Among the different solutions, we can distinguish two al-
C code generation. ternative techniques that correspond to the different design
Togai InfraLogic also developed MicroFPL a tool for the philosophies of the microcontroller core:
assembly code generation for a large set of microcontrollers For complex instruction set microcontrollers (CISC
such as the Intel 8051 family, the Motorola 68 11 family, architecture), it is possible to add dedicated firmware
the Oki 65000 series, and others. support for fuzzy logic, by properly modifying the
An interesting feature of this approach is the ability to controller microprogram. The Fuzzy-1 66 Firmware
use fully tested and reliable development tools, such as [14] microcontroller from Inform 1131 is an example
compiler, assembler, linker, debugger, and simulator. For in which special firmware is added to a standard
instance, we observe that a complex application requires Siemens/ST general purpose microcontrollers. Process-
just about 1.5-2.0 KBytes of code space. ing time for a benchmark rule base with 4 inputs, 3
Obviously, a fuzzy algorithm in a general purpose mi- outputs and 51 rules is 268 11s.
crocontroller can only be used to control systems that have For reduced instruction set processors (RISC archi-
a relatively slow dynamics (i.e., frequency response in the tecture), an interesting possibility is to add a few
range of 0.1-1 kHz). dedicated instructions to a general-purpose instruction
An alternative approach, still requiring only standard set that allow a compiler to optimize fuzzy applica-
components, is represented by Look-up table implementa- tions. Such products have not yet appeared on the
tions [20], 1301. In this approach output values are pre- market, but several studies are currently under way
computed for every input value and stored in a RAM. In [ 6 ] , 1441, and prototypes are expected soon.
this case the inference speed is very high but there is an These systems can be used to support frequency ranges
exponential growth of the required memory if the number of 1-10 kHz (CISC) or 1-50 kHz (RISC) for the response
of input and output variables or the resolution increases. of the plant. Further details are given in Section IV-A.
Usually the use of look-up tables is limited to applications
with 2-3 input variables and 1-2 output variables and a E. Special-Purpose Coprocessors
low resolution (4-8 b) [20]. Most of the dedicated fuzzy processors fall in this class.
These are special-purpose processors dedicated to fuzzy
D. General-Purpose Processors with Fuzzy Support computations that cannot implement the entire control sys-
An alternative approach that still maintains general pur- tem by themselves due to lack of general-purpose com-
pose computation capabilities employs the use of general- putation capability, but still provide some flexibility and
purpose processors with the addition of a few specialized configurability features.
instructions to accelerate fuzzy tasks. The following table shows the advantages and disadvan-
The following table shows advantages and disadvantages tages of the approach.
of this approach. Pros:
Pros: high speed (for high-end applications),
complete flexibility, modularity, and
higher speed compared to standard microcontrollers, some flexibility (not committed to a single application).

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 Cons: provides an easy way of incorporating fuzzy capabilities
limited flexibility (limited rule and MF range), into the construction of application specific chips.
high cost, and Since FCA is a technology rather than a fixed core library,
need of a general purpose processor to support non- TIL can tailor a core to fit a particular customer application.
fuzzy parts. It supports up to 1024 inputs and outputs and up to 5 11
These special purpose coprocessors usually adopt trian- rules per output but these parameters might be affected
gular membership functions, flexible rule format (number of by the rule base memory size. The resolution is 10 b, the
inference speed is 69 ps in case of 20 MHz clock, 8 inputs,
antecedents and consequents), max-min inference method,
4 outputs, 5 antecedents per rule, 2 consequents per rule,
8-b precision and centroid defuzzification method. All
20 rules.
these products act as coprocessors to be coupled with
[Toshiba [42] T/FC150] It is a processor capable of
general purpose microprocessors for the nonfuzzy part of
handling a maximum of eight inputs and one output. The
the control algorithm. Among the many developed solutions
resolution of input/output values is 10 b and the resolution
[33], [43], we note the following commercial products:
of membership functions is 8 b. Its maximum processing
[Fujitsu F’RU-81 Single chip fuzzy controller that com-
speed is 4 400 000 rules per second, with two inputs, one
bines a fuzzy engine, an existing CPU core (4/8 b) memory
output and four rules.
and peripherals on chip. The device has no limits on number
In terms of performance, specialized fuzzy coprocessors
on inputs and outputs, and can support trapezoidal func-
can be used for moderately complex applications in the
tions. Inference processing time is qualitatively in the range range 10-100 kHz for the plant frequency response.
100 ps-10 ms and its natural application is for low-end
systems. [Siemens 81C99] Single chip fuzzy coprocessor to
be coupled with a standard host microcontroller. It supports
F. Dedicated ASIC’s
up to 256 inputs, 64 outputs, 64 modules with 256 rules and
any kind of membership functions [37]. It is in general fast The ultimate solution for achieving performance in fuzzy
and flexible, but its high cost makes it targeted to high-end application is to develop a dedicated architecture committed
applications. Processing time for 8 inputs, 1 output, and 256 to a single application. Due to the particular nature of the
rules are about 78 p s . [Omron [27] FPlOOO FP3000 FP5000 fuzzy inference process, it is possible to directly implement
FZOOl] FP3000 [36] is a fuzzy processor designed to work a fuzzy algorithm with dedicated hardware structures in a
way that maximizes speed and minimizes silicon area, by
together with a general purpose microcontroller. It supports
up to 8 inputs, 4 outputs, and 128 rules. The rule format using high-level synthesis techniques.
The resultant solution is obviously tailored to a single
is fixed (8 antecedents, 2 consequents) but the resolution
application, and the configurable parameters are reduced
is 12 b. It is not too fast for a dedicated processor, and is
to a minimal set, that does not compromise speed and
generally targeted to medium-range applications The best
area. The synthesis procedure from a fuzzy algorithm
inference processing time obtained using 24 MHz clock (per
directly to hardware structures is detailed in Section IV-C.
20 rules with 5 antecedents and 2 consequents) is 650 ps.
Several ASIC’s (or ASIC blocks) tailored to a single fuzzy
The FPlOOO is a fuzzy processor best fit for mass
application (or application domains) have been studied and
produced products. Its inference methods are made to be
developed For an example, see [45].
a sub set of FP3000. Like the FP3000 it supports up to 8
The following table shows the advantages and disadvan-
antecedents, 4 outputs but it can have 96 rules with this
tages of the approach.
format.
Pros:
The FF5000 is an extension of the FP3000. It supports a
maximum of 128 antecedents and a max number of single very fast processing, tuned to the application
rules of 32 639 (single rule means 1 antecedent and 1 very quick design tumaround time (automated synthe-
consequent). It has a very fast inference speed: 10 000 000 sis)
single rules per second and its maximum clock frequency is low cost in terms of Si area (5-10 K gates)
20 MHz. Its application areas range from image processing available as a block in a single-chip control system
to expert systems [35]. implementable as field programmable gate array
The FZOOl is a fuzzy coprocessor used for industrial (FPGA) for prototyping
control on programmable logic controllers (PLC). It allows cost-effective for high-production volumes.
to integrate fuzzy inference capability with Omron’s lines Cons:
of PLC’s. It supports 5 antecedents and 2 consequents with no flexibility (the application is fixed)
128 rules. The maximum inference time is 125 ps per rule. limited complexity
[ST WARP] It is a dedicated coprocessor [28], [34] from only for ASIC-based (or PGA-based) systems
SGS-THOMSON (ST). It allows up to 16 inputs, 16 outputs need of a microprocessor to support nonfuzzy parts.
and 256 rules. It is rather fast and configurable. Target The natural application area of dedicated ASIC’s is
application areas are medium and high-end systems. Details high-end systems with strict timing constraints, a fixed
on the WARP processor are given in Section IV-B. [Togai application and medium-high production volumes. If we
Infra Logic [41] FCA] It is a core cell technology that want to keep chip complexity (15-20 K gates) within a

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 e !

r H 0 is Positive and
If e is Positive and
If 8 IS Negative and
e
e is
6
is Negative then F is Negative
Zero
is Positwe
then F is Negative
then F is Positive
’
If e IS Zero and e is Negatlve then F is Pwilwe
If e IS Zero and 8 Positwe
IS then F is Negative
If e is Zero and e Zero
IS then F IS Zero

Fig. 4. The sample problem.

Table 1 Problem Template. NI Is the Number of Inputs, NO Is

the Number of Outputs, NR Is the Number of Rules, NMF Is the
different machines in a consistent way. For this purpose,
Number of MFS, and NB Is the Number of Bits and following the idea suggested in [401, we have defined
three different problem templates corresponding to three
different application classes of increasing complexity (see
Table 1). We use the memory-oriented approach for the
fuzzification, the Max-Min technique for the inference
Medium
and the Centroid algorithm for the defuzzification. The
3 80 5 following sections present an overview of the different
approaches and, for each technique, describe an application
example to give a better feel for the involved problems.
cost-effective range, the achievable inference speed of an The example shown for the three approaches is the same
ASIC solution is in the range 100 kHz-1 MHz. and represents a simplified version of the control rules for
the inverted pendulum problem. The problem is to control
the motion of a moving pendulum to obtain an equilibrium
IV. CASE STUDIES state. Fig. 4 shows the system diagram, and both a linguistic
As a joint project between SGS-THOMSON (ST) and and tabular representation of the rule base for the control
University of Genoa, Italy (DIBE), different hardware im- algorithm.
plementations of fuzzy control are currently under devel-
opment. The aim of the project is to develop different
alternative solutions along three main implementation di-
A. FLORA: Fuzzy Logic on RISC Architectures
rec tion s:
Processors with Fuzzy Support: DIBE and ST have 1 ) Principles and Design Methodolo,qy. The FLORA pro-
designed a processor core (FLORA: Fuzzy Logic On RISC ject aims at developing a RISC core with a minimum set
Architectures) to be implemented by ST, that combines a of specialized instructions that can speed up the execution
basic RISC instruction set with a few specialized instruction of fuzzy control algorithms. In this way the processor
for fuzzy tasks. maintains general-purpose computation capabilities and at
Dedicated F u u y Coprocessors: ST has designed and the same time can provide fast qpced in the fuzzy task. The
implemented the WARP processor, that represents a good design of FLORA offers several advantages:
compromise between performance and flexibility. 1) Flexibility: The FLORA processor efficiently sup-
Application Specific Fuzzy ASIC’s: DIBE has developed ports general purpose tasks, as well as fuzzy logic
a fuzzy-very High speed integrated circuit description lan- applications.
guage (VHDL) compiler that can synthesize a standard cell 2) Specialization: It is possible to exploit the peculiar-
ASIC directly from a set of high-level fuzzy specifications. ities of each problem, eliminating redundancies in
We will describe these solutions in detail to illustrate computation by means of a proper source code and
the different approaches. In order to classify and evaluate advanced compiler optimizations.
the different solutions, we have defined a set of bench- 3 ) Simplicity: We can achieve good performance with a
marks with which we can measure the performance of relatively simple hardware structure.

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 trapezoidal membership functions,
minimum functions to implement “and” operators in
antecedents,
Cross Compiler minimum-product correlation inferences to combine
rules, and
Cross Assembler
I
I centroid calculation for defuzzification.
Other choices regarding rule and defuzzification opera-
I
Cross Linker 1 tors may suggest the use of different instructions, while
other types of membership functions may be used without
1 affecting our results. The application of analysis tools to the
Profiler
1 benchmarks problems has highlighted the importance of a
1 few additional instructions that may not be usually present
Analyzer
I
1 in general purpose processors:
The minimum (MIN ) instruction, to efficiently imple-
I
4
C-
Suggestions > ment rule antecedent combination, without interrupting
the execution pipeline with control instructions.
The multiply-and-accumulate (MACC) instruction,

& Target Machine

+
that performs a = a b . c, to efficiently implement
output defuzzification.
The simulation with different benchmarks problems
Fig. 5. The design flow in the FLORA project.
shows that having these two specialized instructions allows
a speed-up ranging from 1.61 to 2.24 times (average
1.91) [6]. This solution produces optimized code both for
4) Reliability: We can take advantage of well devel- memory oriented and computational oriented approach, as
oped system support tools such as real-time operating the improvements mainly affect the rule inference phase,
systems, optimizing compilers, run-time libraries, de- that consists of a somewhat long sequence of minimum
buggers, etc. operations, and the defuzzification phase, that is consists
All specialized features introduced in FLORA are derived of many multiply-and-add steps.
from analysis of experimental results and noting is assumed 3) Archirecture Support: The core of the FLORA proces-
a priori. Fig. 5 shows the design flow within the adopted sor is a 32-b RISC with a 4-stage pipeline, conceived to
design methodology and the software tools developed in implement only truly useful structures. The processor core
the FLORA project. includes an ALU, a parallel multiplier, a barrel shifter, a
In details: register file. The machine cycle frequency is in the range
The compiler is a retargeted version of the GNU GCC. of 40-50 MHz. Table 2 contains the complete instruction
GCC is the well known and widely adopted public set of FLORA. All instructions have a three-cycle latency
(no register bypass). Table 3 shows the simulated perfor-
domain C, ANSI C, and C++ compiler, developed by
mance results of the FLORA architecture on the benchmark
the Free SofnYare Foundation. and it has been chosen
problems, assuming 50 MHz clock cycle.
due to the ease of porting and the rich set of libraries
4 ) Application Example: Fig. 6 shows the code necessary
available with it.
for the FLORA processor to implement the simplified
The Simulator is based on an Instruction Set Archi- pendulum control algorithm. We can observe the absence
tecture (ISA) execution-driven event-based simulation of branch instructions within the main loop that contributes
engine that was developed in-house for this project. to optimize performance by keeping the execution pipeline
It models the semantic of the instruction set and always fully operative. This is made possible by the intro-
mimics the program run, by iterating fetch, decode duction of the min instruction. The number of cycles for
and execution phases. The simulator is mainly used the example is 95, leading to an estimated inference speed
as a code projiler to extract execution statistics from of 2.0 p s , assuming a 20 ns cycle.
benchmarks.
The analyzer is used to find sequences of instructions B. WARP: Weight Associative Rule Processor
that have a significant frequency in the considered
I ) Principles and Design Methodology: WARP [28], [34]
benchmarks and that can represent good candidates to
is a dedicated coprocessor designed by ST to efficiently
be combined in an optimized hardware structure.
perform Fuzzy Logic computing.
2 ) lnstruction Set Analysis: The FLORA architecture WARP uses different data structures in the various phases
may support any membership function, any connective of fuzzy computation and stores the necessary information
operator in antecedent combinations, any rule inferencing in two main memories, one for the membership functions
and fuzzificatioddefuzzification method. However, for the of the antecedents and one for those of the consequents.
analysis phase, we have made the following assumptions: The resolution is 6 or 7 b for the input values and 4 b

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 Fig. 6. A C-like code and the FLORA assembled code (without nops) for the sample problem.

Table 2 The Instruction Set of the FLORA Core

Transfer Instructions: Flow Control Instructions:

LD, LDH, load word, J jump

LDB halfword, byte

LDI load register J.xx conditional jump

with immediate

ST, STH, store word, JL jump-and-link

STB halfword, byte

MV move register TRAP trap (system call)

to register 4 M.F.l M.F2 M.F.9

ALU Instructions: Specialized Instructions:

ADD, SUB classical ALU MIN signed minimum

operations

MUL, DIV, multiplier/ MACC multiply and

MOD divider accumulate

UMUL,,
UDIV,
UMOD

AND, OR, Fig. 7. The memory organization of the WARP processor

XOR

ASHR, SHL, for the alpha values. The adopted memory organization for
SHR the antecedent part allows retrieval of all the alpha values
using the crisp input value to calculate the address in the
proper fuzzy memory bank. Fig. 7 shows the organization
of the antecedent memory. To compute the output values,
Table 3 Performance Results of the FLORA Architecture
the consequent memory contains the area underlined by a
Problem I FLORA membership function and its barycenter. This organization
Simple I 2.0 ps (95 cycles)
of the information storage supports only the Mar-Dot [51]
inferencing method.
Medium 3.7 p s (185 cycles) 2 ) Architecture Support: The WARP architecture (Fig. 8)
Complex
exploits the memory organization described above. To
18.2 ,us (910 cycles)
increase the computation speed, the Antecedents Memory

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 I
I
WARP
....................................................................................................
I I
I F=w-
I
,

I
I
I
I
I
I
I
I
I
I
=s2xJ.EF
....................................................................................................
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I I

I
:L
...................... -:. ........................................................... i
I
I
I
F-d.
....................................................................................................

I
I
I
......... '4
-
Fig. 8. The block structure of the WARP architecture. 6 is the truth level for modifying a variable
of -the consequent part.

Table 4 Performance Results of the WARP Architecture

~~~
C. Automated Synthesis of Fuzzy ASIC's
Problem WARP I ) Principles and design methodology: Dedicated hard-
Simple 0.6 /is
ware provides an improvement in computing power
through the introduction of special purpose units and the
Medium 1.0 11s exploitation of parallelism. Moreover, this solution can be
Complex 4.5 p s
cost effective as it only implements the hardware resources
needed by the application and the availability of logic
synthesizers also allows non-VLSI specialists to design an
has been split into four blocks, each one containing the ASIC.
values of one or more fuzzy MF's. Such a structure allows Unfortunately, current synthesis tools do not support
the parallel retrieval of the alpha values. These values are high-level descriptions and the generation of an appropri-
then stored in a register set and processed by a fuzzy ate architecture from an algorithm specification. This still
inference engine to evaluate the weights on the consequent remains a major research challenge.
part. These weight values are used for the computation of To reach an optimal price/performance ratio requires
the addresses in the consequent memory. exploring tradeoffs both in the algorithm and in the physical
The assembling phase of all the consequent membership design space. Although a solution to the general problem
functions and the defuzzification process are carried out in is not reachable in the near term, we can develop specific
the Defuzzifier block. Table 4 shows the performance re- tools dedicated to specific applications.
sults of the WARP architecture on the benchmark problems We present an automatic synthesis approach 171 that
assuming 40 MHz clock. derives a complete circuit definition from a high level
3) Application Example: Fig. 9 shows the data memory description of the fuzzy rules and the Fystem requirements.
for the sample problem. We can observe that WARP needs The proposed synthesis system implements a particular
0.5 ps for the example and performs better than FLORA but type of fuzzy controller, with fixed methods for inference
does not have the flexibility of a general purpose processor and defuzzification. The reference fuzzy controller operates
core. on the following assumptions:

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 ..................
Memory Organization

,? N Z P

”,
125 84
ee;
Block 1: 0 Points 1 - 32

..--
.___
.___.- ---- , .
* .

-.--._ ....................... _.--

Fig. 10. The synthesis flow for a fuzzy ASIC

~ 1 1 I 1 E&) E$Es I
::::::::: :.:::: :::: :::1
::I
:::
In order to reach an aredtime eflicient solution, the
Block 2 : 0 Points 33 - 64 VHDL generator assumes a finite set of resources to which
Block 3 : 6 Points 1 - 32 it maps the control steps necessary to execute the fuzzy
Block 4 : 6 Points 33 - 64 algorithm under synthesis.
The underlying architecture assumes a microarchitec-
Fig. 9. The WARP data memory for the sample problem. ture composed of functional units that can execute micro-
operations in parallel, and of a set of general-purpose
registers that are used to store intermediate results. The
“IF x1 IS a1 AND --.x,IS a, THEN y IS b” rule functional units are:
format. This choice requires software preprocessing of ALU units,
the expert rules, in order to translate them into the Minimum units,
required format. Parallel multiplier units, and
Max-Min inference to produce fuzzy output. Memory interface units.
Defuzzification performed using centroid computation. The control steps of the algorithm are generated by a
Memory oriented approach in membership function hardwired sequencer unit, that assigns the selection sig-
evaluation. nals necessary to route data between functional units and
registers. Fig. 10 shows the flow of the synthesis process.
We adopt a WARP-like memory organization, i.e., the
The design process operates as follows:
membership value addresses are computed using the crisp
3) Rule Assembler: The rule hase of the target application
input values, and a synchronous design methodology based
is processed and converted to a straight-line sequence of
on a single task clocking scheme. Preliminary simulations
pseudo-instructions that we call intermediate code. Inter-
show that this methodology allows to reach a clock fre-
mediate code instruction represent elementary functions of
quency of 50 MHz for most problems and without any
the basic machine units (e.g., ADD, MUL, MIN, LOAD,
hand modification of the resulting circuit. More advanced
etc.) and are in direct correspondence with the control steps.
clocking strategies that allow to process data in a pipelined
4 ) Scheduler: Intermediate code instruction do not spec-
fashion and further reduce the cycle time are currently under
ify timing relationships among operations, but only data
development.
dependencies. Consequently, to obtain the sequence of
2 ) The Synthesis Procedure: The proposed synthesis pro-
control steps, we perform a scheduling pass that allocates
cedure is structured in three main steps:
the micro-operations to the different machine units and
Rule definition, cycles. The algorithm tries to maximize microarchitectural
Generation of a synthesizable VHDL description, and parallelism and to minimize data movements and regis-
Netlist synthesis. ters, and operates according to a modified list-scheduling
technique [22].
The major phase in the process is VHDL generation, as 5 ) VHDL Generator: The set of conlrol steps generated
most standard logic-level synthesizers can efficiently obtain by the scheduler and the used machine resources are
an optimized register transfer level netlist from VHDL to converted to a synthesizable format by the VHDL generafor.
feed to place and route tools. The use of VHDL is motivated by its wide usage and

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 I mulo Woo( BEGINPRCCESS
! 8EDlN

Fig. 11. The (simplified) VHDL code for the pendulum problem.

Table 5 Synthesis Results lor the Different Problem Templates

Problem Complexity Area Cycles (time) Hardware Configuaration

Constraints gates Ah Min Mu1 Mem Regs

Simple (< 10K gates) 9392 15 (0.3 p s ) 4 1 2 4 15

Medium (< 20K gates) I 18276 I 31 (0.6 /IS) 4 4 4 22

Complex 50K
(i gates) I 49621 I 894 (17.8 ps) I 3 1 1

by the fact that it can be used in all design phases, from DefiuiJication: The final steps performs the computa-
documentation to simulation and synthesis. tion of the crisp outputs from their fuzzy values. This task
6) Low-Level Synthesis: Once the VHDL description is is performed according to the centroid calculation. This
obtained, commercial tools can be applied to synthesize a operation is the most area expensive and time consuming
netlist of standard cells, gate arrays or FPGA primitives. as it requires several multiply-accumulate steps.
The netlist can then be processed by standard place and
route tools to obtained the device. The realization of the units is strictly based on the appli-
The data flow of the architecture defined by the VHDL cation requirements. The system can use different types of
generation tool reflects the three main tasks to be accom- adder (carry select, carry look ahead, etc.) and multipliers
plished by a fuzzy controller: (parallel, sequential) according to perfomlance and area
constraints. For instance, the use of a parallel multiplier
FuzziJication: The inputs received by the fuzzy rule base leads to a considerable performance improvement, but there
are used to address the external membership memory. are classes of applications without strict time constraint
The addresses of the membership values are computed where it would be more area-and-cost efficient to use a
by adding the crisp input to the base addresses of each sequential (add-and-shift) structure.
membership function. The number of cycles required to Table 5 shows the synthesis results for the benchmark
read the fuzzy values depends on the characteristics of the problems. The table shows the best obtained configura-
external memory and on the number of available adders. tion (number and type of units) constrained by the spec-
In case of multiple memory banks (one per input), the ified number of gates. For the different applications, we
parallel computation of the proper addresses may allow have chosen three different complexity limits (100 000
concurrent acquisition of multiple membership values. gates for Simple, 20 000 gates for Medium, 60 000 gates
Inference: The second step is rule application. From an for Complex). Time results (computed assuming a 20 ns
hardware point of view, this corresponds to the execution cycle time) show that the ASIC approach is substan-
of a set of minimum operations for each rule. tially faster than more general techniques for 5imple and

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 [321 E. Sanchez and L. A. Zadeh, Approximate Reasoning in Intel- Alessandra Costa received the M.S. degree in electronic engineering at
ligent Systems, in Decision and Control. Oxford, UK Perga- the University of Genoa, Italy, in 1992. She is now studying for the
mon. Ph.D. in biophysical and electronic engineering at the same university.
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[36] K. Shimizu, M. Osumi, and F. Imae (Omron Corp.), “The digital University of Genoa in 1980 and 1982, respectively.
fuzzy processor FP-5000,” in Proc. 2nd Int. Con$ on FUZJ In 1983 he joined the VLSI Design Center of the University of Genoa
Logic and Neural Networks, Izuka, Japan, 1992, pp. 539-542. as a Research Scientist. His research interests include VLSI design and
[37] Manuscript no. ZC-014 parallel architectures. He has authored more than 40 papers in those
[38] Siemens GmbH., Siemyns Data Sheets, May 1993. research fields. He has been a chairman of VLSI conferences and is
[39] M. H. Smith, “Evaluation of performance and robustness of a General Chairman of the 22nd International Symposium on Computer
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[42] Togai InfraLogic Inc., Imine, CA 92718 He is presently a visiting research scientist at Hewlett-Packard Labo-
[43] Toshiba Corp. ratories. His major research interests are VLSI design, instruction-level
[44]J. Wang, “A 12-bit fuzzy computational acceleration (FCA) parallelism, parallelizing compilers, and VLIW architectures.
core,” in Proc. Fuzzy Logic ’93, Burlingame, CA, 1993, p.
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and Cybern., vol. SME-3, pp. 28-45. Jan. 1993. He has worked as a software specialist for TELE’ITRA (Italy) and
[51] -, “The concept of a linguistic variable and its application GTE (USA). He began working on semiconductors at Texas Instruments
to approximate reasoning,” Inform. Sci., vol. 8, pp. 199-249, adn later for the Naitonal Semiconductor Corporation as director of
1975. European Telecom industrial marketing. He has been with SGS-Thomson
[52] H. Zimmerman, Fuzzy Set Theory and its Applications, 2nd Ed. Microelectronics since 1982, where he is director of the Corporate
Boston, MA: Kluwer, 1990. Advanced System Architectures Group. He has published several technical
papers and has seven patents.

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