Scribd
Upload
29 views9 pages

Structural Modeling 10-07-2023

The document describes 4 experiments using structural modeling: 1. A 4-to-1 multiplexer (mux) is implemented using two 2-to-1 mux modules. 2. A 16-to-1 multiplexer is implemented using four 4-to-1 mux modules. 3. A 4-bit adder is implemented using four 1-bit full adder modules in a ripple carry configuration. 4. A 3-to-8 decoder is implemented using two 2-to-4 decoder modules.

Uploaded by

najmuus786
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
29 views9 pages

Structural Modeling 10-07-2023

The document describes 4 experiments using structural modeling: 1. A 4-to-1 multiplexer (mux) is implemented using two 2-to-1 mux modules. 2. A 16-to-1 multiplexer is implemented using four 4-to-1 mux modules. 3. A 4-bit adder is implemented using four 1-bit full adder modules in a ripple carry configuration. 4. A 3-to-8 decoder is implemented using two 2-to-4 decoder modules.

Uploaded by

najmuus786
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 9

List of experiments using structural modeling

1. Mux 4x1 using Mux 2x1


2. Mux 16x1 using Mux 4x1
3. 4-bit adder using 1-bit full-adder(Ripple carry adder)
4. 3-to-8 decoder using 2-to-4 decoder

1. Mux 4x1 using Mux 2x1

module mux4x1(
input [3:0] in,
input [1:0] sel,
output reg out);

wire mux_out1, mux_out2;

// level-1 2:1 multiplexers

mux2x1 mux1(in[0], in[1], sel[0],mux_out1);


mux2x1 mux2(in[2], in[3], sel[0],mux_out2);

// level-2 2:1 multiplexer

mux2x1 mux3(mux_out1, mux_out2, sel[1],out);

endmodule

module mux2x1 (
input wire a,
input wire b,
input wire sel,
output reg out
);
always @* begin
case (sel)
1'b0: out = a;
1'b1: out = b;
endcase
end
endmodule
//testbench

module mux4x1_tb;

// Inputs
reg [3:0]
in;
reg [1:0] sel;

// Outputs
wire out;

// Instantiate the module under test


mux4x1 dut (
.in(in),
.sel(sel),
.out(out)
);

// Test
stimulus initial
begin
$monitor("in=%b, sel=%b, out=%b", in, sel, out);
// Initialize inputs
in = 4'b1010;
sel = 2'b00;
#10; // Wait for some time

sel = 2'b01;
#10; // Wait for some time

sel = 2'b10;
#10; // Wait for some time

sel = 2'b11;
#10; // Wait for some time

$finish;
end
endmodule
Output Waveforms:

Rtl Schematic :

2. Mux 16x1 using Mux 4x1

//Mux 16x1

module mux16x1( input [15:0] i,


input [3:0] select,
output y);

// level 1
mux4x1 dut1(i[3:0],select[1:0],y1);
mux4x1 dut2(i[7:4],select[1:0],y2);
mux4x1 dut3(i[11:8],select[1:0],y3);
mux4x1 dut4(i[15:12],select[1:0],y4);

//level 2

mux4x1 dut5({y4,y3,y2,y1},select[3:2],y);
endmodule

//Mux 4x1
module mux4x1(input [3:0]i,
input [1:0]select,
output reg y);

always@*
case(select)

2'b00: y=i[0];
2'b01: y=i[1];
2'b10: y=i[2];
2'b11: y=i[3];

endcase
endmodule
//Testbench
module test_mux16x1;

// Inputs
reg [15:0] data_in;
reg [3:0] select;

// Outputs
wire out;

// Instantiate the DUT


mux16x1 dut (
.i(data_in),
.select(select),
.y(out)
);
// Initialize inputs
initial begin
$monitor($time, "data_in=%b select=%0d out = %b", data_in,select,out);
data_in = 16'b1010_1010_1010_1010;
select = 4'b0000;
end
// Stimulus
always #5 select = select + 1'b1;
initial
#50 $finish;

endmodule
Output Waveform:

3. 4-bit adder using 1-bit full-adder(Ripple carry adder)

module full_adder(a,b,cin,sum,co);

input a,b,cin;
output sum,co;

assign sum=a^b^cin;
assign co=(a&b)|(a&cin)|(cin&b);

endmodule

//Design of 4 Bit Adder using 4 Full adder (Structural Modeling Style)

module adder_4bit (a,b,cin,sum,cout);

output [3:0]sum;
output cout;

input [3:0]a;
input [3:0]b;
input cin;

wire [2:0]c;

full_adder u0 (a[0],b[0],cin,sum[0],c[0]);
full_adder u1 (a[1],b[1],c[0],sum[1],c[1]);
full_adder u2 (a[2],b[2],c[1],sum[2],c[2]);
full_adder u3 (a[3],b[3],c[2],sum[3],cout);

endmodule

//Testbench Code- Ripple carry adder

`timescale 1ns / 1ps

module TestModule;
// Inputs
reg [3:0] a;
reg [3:0] b;
reg cin;

// Outputs
wire [3:0] sum;
wire cout;

// Instantiate the Unit Under Test


(UUT) adder_4bit
dut(a,b,cin,sum,cout);

// Initialize Inputs

initial begin
$monitor("a=%0d b=%0d cin=%b sum=%0d cout=%b",a,b,cin,sum,cout);
a = 0;
b = 0;
cin = 0;
// Wait 100 ns for global reset to
finish #100;
a = 5;
b = 6;
cin = 1;
// Wait 100 ns for global reset to
finish #100;
end
endmodule

Output Waveform:

RTL Schematic:
4. 3-to-8 decoder using 2-to-4 decoder

module decoder2x4_enable(input [1:0] sel, input enable, output reg [3:0]

out); always @(sel, enable) begin


if (enable) begin
case(sel)
2'b00: out = 4'b0001;
2'b01: out = 4'b0010;
2'b10: out = 4'b0100;
2'b11: out = 4'b1000;
endcase
end else begin
out = 4'b0000;
end
end

endmodule

//3 to 8 decoder
module decoder3x8(input [2:0]sel, output [7:0]out);

decoder2x4_enable uut1(sel[1:0],~sel[2], out[3:0]);


decoder2x4_enable uut2(sel[1:0],sel[2], out[7:4]);

endmodule

//Testbench

module testbench();

// Declare the inputs and outputs for the


testbench reg [2:0] sel;
wire [7:0] out;

// Instantiate the DUT (device under test)


decoder3x8 dut(.sel(sel), .out(out));

// Initialize the inputs


initial begin
$monitor("sel = %d, out = %b", sel, out);

sel = 0;
#10;
sel = 1;
#10;
sel = 2;
#10;
sel = 3;
#10;
sel = 4;
#10;
sel = 5;
#10;
sel = 6;
#10;
sel = 7;
#10;
$finish;
end

endmodule

Output Waveform:

You might also like