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CS429 Lab4

The document describes a Verilog code for a 4-bit ALU and its testbench. It contains the behavioral and RTL models of the ALU along with the code and output waveforms are shown. A 4-bit ripple carry adder and BCD adder are also implemented along with their testbenches.

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YASH KUMAR SINGH
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20 views19 pages

CS429 Lab4

The document describes a Verilog code for a 4-bit ALU and its testbench. It contains the behavioral and RTL models of the ALU along with the code and output waveforms are shown. A 4-bit ripple carry adder and BCD adder are also implemented along with their testbenches.

Uploaded by

YASH KUMAR SINGH
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Lab Assignment 4

CS429: Embedded Systems

NAME : YASH KUMAR SINGH


ROLL NO. : 202151181

VERILOG CODE :

primitive mux_udp(out,sel0,sel1,a,b,c,d);

input sel0,sel1,a,b,c,d;

output out;

table

//s0 s1 a b c d : out

0 0 0 ? ? ? : 0;

0 0 1 ? ? ? : 1;

0 1 ? 0 ? ? : 0;
0 1 ? 1 ? ? : 1;

1 0 ? ? 0 ? : 0;

1 0 ? ? 1 ? : 1;

1 1 ? ? ? 0 : 0;

1 1 ? ? ? 1 : 1;

? x ? ? ? ? : x;

x ? ? ? ? ? : x;

endtable

endprimitive

module lab4_q1_udp(out,sel0,sel1,a,b,c,d);

input sel0,sel1,a,b,c,d;

output out;

mux_udp obj(out,sel0,sel1,a,b,c,d);

endmodule
TESTBENCH :

`include "lab4_q1.v"

module mux_udp_tb();

reg sel0,sel1,a,b,c,d;

wire out;

lab4_q1_udp

obj(.out(out),.sel0(sel0),.sel1(sel1),.a(a),.b(b),.c(c),.d(d));

initial begin

$dumpfile("lab4_q1.vcd");

$dumpvars(0,mux_udp_tb);

end

initial

begin

#0 sel0=0; sel1=0; a=0; b=0; c=1; d=1;

#10 sel0=0; sel1=0; a=1; b=0; c=1; d=1;


#10 sel0=0; sel1=1; a=0; b=0; c=1; d=1;

#10 sel0=0; sel1=1; a=0; b=1; c=1; d=1;

#10 sel0=1; sel1=0; a=0; b=0; c=0; d=1;

#10 sel0=1; sel1=0; a=0; b=0; c=1; d=1;

#10 sel0=1; sel1=1; a=0; b=0; c=1; d=0;

#10 sel0=1; sel1=1; a=0; b=0; c=1; d=1;

#10 $finish;

end

endmodule

GTKWAVE :
USING BEHAVIORAL MODEL :

VERILOG CODE :
module ALU_Beh_dataflow (

input [3:0] A,

input [3:0] B,

input [2:0] ALU_OP,

output reg [3:0] out

);

always @(*) begin

case (ALU_OP)

3'b000: out = A + B;

3'b001: out = A - B;

3'b010: out = ~(A & B);

3'b011: out = ~(A | B);

3'b100: out =(A < B) ? 4'b1 : 4'b0; 3'b101: out = (A == B) ? 4'b1 : 4'b0;

3'b110: out = A << B[1:0];

3'b111: out = A >> B[1:0];


default: out = 4'bxxxx;

endcase

end

endmodule

TESTBENCH CODE :
module ALU_behavioral_tb();

reg[3:0]A,B;

reg[2:0]ALU_OP;

wire[3:0]out;

ALU_Beh_dataflow a1(A,B,ALU_OP,out);

initial

begin

$dumpfile("ALU_dataflow_beh.vcd");

$dumpvars(0,ALU_behavioral_tb);

ALU_OP=3'b000;A=4'b1010;B=4'b0101;

#10;

ALU_OP=3'b001;A=4'b1010;B=4'b0101;

#10;

ALU_OP=3'b010;A=4'b1010;B=4'b0101;

#10;
ALU_OP=3'b011;A=4'b1010;B=4'b0101;

#10;

ALU_OP=3'b100;A=4'b1010;B=4'b0101;

#10;

ALU_OP=3'b101;A=4'b1010;B=4'b0101;

#10;

ALU_OP=3'b110;A=4'b1010;B=4'b0101;

#10;

ALU_OP=3'b111;A=4'b1010;B=4'b0101;

#10;

end

initial begin

$monitor("ALU_OP = %b, A = %b, B = %b, out = %b",ALU_OP,A,B,out); end

endmodule
OUTPUT :

GTKWAVE :
USING RTL MODEL :

VERILOG CODE :
module ALU_4bit_dataflow (

input [3:0] A,

input [3:0] B,

input [2:0] ALU_OP,

output [3:0] out

);

assign out = (ALU_OP == 3'b000) ? A + B :

(ALU_OP == 3'b001) ? A - B :

(ALU_OP == 3'b010) ? ~(A & B) :

(ALU_OP == 3'b011) ? ~(A | B) :

(ALU_OP == 3'b100) ? (A < B) ? 4'b1 : 4'b0:

(ALU_OP == 3'b101) ? (A == B) ? 4'b1 : 4'b0:

(ALU_OP == 3'b110) ? (B[1:0] == 2'b00) ? A : (B[1:0] == 2'b01)

? (A << 1) : (B[1:0] == 2'b10) ? (A << 2) : (A << 3) :

(ALU_OP == 3'b111) ? (B[1:0] == 2'b00) ? A : (B[1:0] == 2'b01)

? (A >> 1) : (B[1:0] == 2'b10) ? (A >> 2) : (A >> 3) : 4'bxxxx; //

Default operation

endmodule
TESTBENCH :
module lab4_q2a_tb();

reg[3:0]A,B;

reg[2:0]ALU_OP;

wire[3:0]out;

ALU_4bit_dataflow a1(A,B,ALU_OP,out);

initial

begin

$dumpfile("ALU_RTL_dataflow.vcd");

$dumpvars(0,lab4_q2a_tb);

ALU_OP=3'b000;A=4'b1100;B=4'b0011;

#10;

ALU_OP=3'b001;A=4'b1100;B=4'b0011;

#10;

ALU_OP=3'b010;A=4'b1100;B=4'b0011;

#10;

ALU_OP=3'b011;A=4'b1100;B=4'b0010;

#10;

ALU_OP=3'b100;A=4'b0110;B=4'b0011;

#10;
ALU_OP=3'b101;A=4'b1010;B=4'b1010;

#10;

ALU_OP=3'b110;A=4'b1010;B=4'b0010;

#10;

ALU_OP=3'b111;A=4'b1010;B=4'b0010;

#10;

end

initial begin

$monitor("ALU_OP = %b, A = %b, B = %b, out = %b",ALU_OP,A,B,out); end

endmodule

OUTPUT :
GTKWAVE :
VERILOG CODE :
module FullAdder(

input a,

input b,

input c,

output sum,

output carry

);

assign sum = a ^ b ^ c;

assign carry = (a & b) | (b & c) | (a & c);

endmodule

module RippleCarryAdder(

input [3:0] a,

input [3:0] b,

output [3:0] sum,

output carry

);

wire c1, c2, c3;

FullAdder FA0 (.a(a[0]), .b(b[0]), .c(1'b0), .sum(sum[0]), .carry(c1));

FullAdder FA1 (.a(a[1]), .b(b[1]), .c(c1), .sum(sum[1]), .carry(c2)); FullAdder

FA2 (.a(a[2]), .b(b[2]), .c(c2), .sum(sum[2]), .carry(c3)); FullAdder FA3

(.a(a[3]), .b(b[3]), .c(c3), .sum(sum[3]), .carry(carry));

endmodule
TESTBENCH CODE :
module RippleCarryAdder_tb;

reg [3:0] a, b;

wire [3:0] sum;

wire carry;

RippleCarryAdder UWU (a,b,sum,carry);

initial

begin

$dumpfile("RippleCarryAdder_q3.vcd");

$dumpvars(0, RippleCarryAdder_tb);

#0 a = 4'b0001; b = 4'b0010;

#10 a = 4'b1100; b = 4'b0011;

#10 a = 4'b1111; b = 4'b0000;

#10 a = 4'b0110; b = 4'b0110;

#10 a = 4'b1001; b = 4'b0111;

#10 $finish;

end

initial

begin

$monitor("a = %b, b = %b, sum = %b, cout = %b", a, b, sum, carry);

end

endmodule
OUTPUT :

GTKWAVE :
VERILOG CODE :

module FullAdder(input a,input b,input c,output sum,output carry);

assign sum = a ^ b ^ c;

assign carry = (a & b) | (b & c) | (a & c);

endmodule

module RippleCarryAdder(input [3:0] a,input [3:0] b,output [3:0]

sum,output carry);

wire c1, c2, c3;

FullAdder FA0 (.a(a[0]), .b(b[0]), .c(1'b0), .sum(sum[0]),

.carry(c1));

FullAdder FA1 (.a(a[1]), .b(b[1]), .c(c1), .sum(sum[1]), .carry(c2));

FullAdder FA2 (.a(a[2]), .b(b[2]), .c(c2), .sum(sum[2]), .carry(c3));


FullAdder FA3 (.a(a[3]), .b(b[3]), .c(c3), .sum(sum[3]),

.carry(carry));

endmodule

module BCDAdder(input [3:0] a,input [3:0] b,output [4:0] sum);

wire [3:0] rca_sum;

wire rca_carry;

RippleCarryAdder RCA(

.a(a),

.b(b),

.sum(rca_sum),

.carry(rca_carry)

);

assign sum = (rca_sum > 4'd9) ? rca_sum + 4'd6 : rca_sum;

endmodule
TESTBENCH :
module BCDAdder_tb;

reg [3:0] a, b;

wire [4:0] sum;

BCDAdder UUT (a,b,sum);

initial

begin

$dumpfile("BCDAdder.vcd");

$dumpvars(0,BCDAdder_tb);

#0 a = 4'b0001; b = 4'b0010;

#10 a = 4'b1100; b = 4'b0011;

#10 a = 4'b1111; b = 4'b0100;

#10 a = 4'b0110; b = 4'b0110;

#10 $finish;

end

initial

begin

$monitor("a = %b, b = %b, sum = %b", a, b, sum);

end

endmodule
OUTPUT :

GTKWAVE :

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