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COA Unit 1

This document discusses computer system architecture and classification. It describes the Von Neumann model and its components. It also discusses parallel processing, Flynn's classification of computer architectures into SISD, SIMD, MISD, and MIMD categories.

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0% found this document useful (0 votes)
30 views21 pages

COA Unit 1

This document discusses computer system architecture and classification. It describes the Von Neumann model and its components. It also discusses parallel processing, Flynn's classification of computer architectures into SISD, SIMD, MISD, and MIMD categories.

Uploaded by

nishita22164063
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Computr Uorgonisatiom lhehiehe

’T i vsed to dosgn comnhehr sysieros. to be those atibu


(ombeter Arcitectuop isvisiconsiolered
ble to the User l Ke addhesing
Hal are for data a
Sjstem sets and bits vSPd
techmiqve, jmstTVC Hon togic txecuion f a boegm
diod impact he nanner.
have a abstact
1m an
the ysiemclos the system
’ Tt dlyAines wih what sgstrrn
’ T deals he uay in whieh a
mfutrr orgonzahon is Units anel tte intom
’ (o and it is
operaional
hos to strvcture
between them. abstract model
rphlzahom of te
’ I t i's Hhe imhlemnt he systrn.
IH dals with ow to

Vs Co

cA
comce med with he
T! is
combont on structure and beha viows f a
way harduare o mpute system
Connected togethor to fom
user
compeute sstem.
acet as h interface betueen ’ H deas with the componns
’ tn aa systom.
hordwore and softiore a con nPcHom
the
>It helb s fo. vmelershond system ar
lunctiomalities of a system Onl.intorco nnectecl.
basis f ne
I is doe om the
oTchi'tpcture is onsiderl
’I} dlals j h ow-level
lecle wih igh -leve) cles ign issue.
’ I
T n voives
piyscatConyfonnt
’ in velves logi
neneral yste mhrhitrcture
DStore Paoggom (ontrel Concft.
’ TE rfes to he storage aof instrcho ns na Computr
memoqy to enab le it do perform a vari ety f
tos hs in seqvence o jmter mHrntly
>Tis idea wos intodvced n He late o os b4 JTohn
Vom

’ ENIAC Cleztaonie Nomtrical Integrator amel (omb)


was tee inst based on stored Progrom (oncept
>Von-NPUmOn modll

Sbrd Po oqvam (oncept


Poralel Procesig)

Von- Neuma mmocel


1445.
’ I t was brobosPd im neHc and logica
Con tro) bmit, Arith
’Cons Lsted a e aput/outputs.
memog vnit, Rrgis tezs and
program data
data are storel
data &
’ n this ims trvction
Single procrssog
both stutio
’ Uses one memoy for
anel olata
bnecuts þrgeans fola
-drcode -Precut

cycle.
(omponenls Vom- Neemamn Moolel

past o a computea thal performs te bulk af datee


’ CPU =
processinq operations.
rrs.
Comsisk a ALV, CU and ariey of rgit
hgh shead sorae ars in he CPU.
kysters refrs.to cpu ore fokhed foon he rgser
by the
The data þrocesstd ejsters that plag Cveial role. loc.
Following are the holes the mmorg lbc
pddres Reqishe)>
)mAR Cmemory meeds to bo cccessed
Hat thad
of te data Regiaher)> T} holds He lal
ory Datatrnsforrd to or fsom momy
2 mDRL mem
3 being intermrliate ALW rewls.
hccumulalor)> It hold addrss of ho nost
3) Ac C
’ (onlajms he
CProgtam(entr) mstvchion to be executed
9) PC crrrpt
Registe) ’ (onlains e
Instruchion þrocessing
s) cIRC(urrent jnstovchon during
wweh information j's shoed
> These ae the
means by
’ Buses
ines, one
(onsist af a set t (om mon
Abus sfrvcture th rogh 'ch bina ctomine
ach bit of yistea, (ondrol sgynals
fortranfored one afa hime. duing rch Joaheulay
is seleched by Hhe bus
which rgiatet js
(om þalsrd af th reemafo
Nvermonn trchitecture
’ Von-
bus Syste m addess of dala ba proso
(arris Ae
) Address Rus> ond He memo
þrocess, memory t
’ Carris dta b/bfas pro(eis,
2) Data Bus lwites.
ond inbul foutput /com mands fromhe
lorries
3) (ondrol Bus >CPU.
)eneoral Purbose System
’ J is a modilied ver
Versiom the Von - pU man n rchitrature
hat it s a modn lay architcral
7ehresen toon of tomputer sysien
omtrol Shatus

Address
Process o Systero Bus
Data

Titeface Totrfac
Device 2
Device 1 Device a

) Porallel Pro tessimg


’It cwn be les cribed as class of techniques whtch
date -
Pnables the syste m to achive simul tamesus
tasks to n c raase he com þutetional shr of
þrocessimg
a computt ystem
’prima z penpose af Parallel Processimg s to nhance he
capability
(o mbater þrocessing.omot
thgougtbut, ie te f brocessin that can
accompi'shed dering a giver in terual off time.
he
lAdeder subtra clo

To mory Processo [ogic unit


>S entk
Tneremtese
Floahing pointk
S

) Flyn's Classiliraion of (o onpaters


’mIMI Flynm booposrd a classfhcabon for he orgodzahon
competer system by ha nembor Tostchon and
a
lata items tat monibulated si elhonsssly-
mulhble
Single Single
strtom
Tmstruchon SImD
SISD
Uniprocessor Vechor Pro cessor
|Parallel Process/ng

MISD
MIMD
mulh-combates
May be þjbelined mvlh-pT0(eSS OTS
computer
pota Streum

divides computer into fous mejo


Flynn's lassificahon
groups hat are:
Stoeam, Single Data strRom
instruchom
) Single
It rebrsend he orgazaon af a single tomfteo and a memo4
comtrel ni, a brocess oT Unt
(omtainlng CU= ontelwiH
Cu PE= froressinq
PE

Single Instrvcion and muh ple Date Sotan


)
orgenigaton thet includes man
ndey he spyision f a common
bro cessing vns
Com trol ut.
Dota Bus
ContralVit Tnsfavion stseam

Processog mits
P
Alignment ntwogk
Jm) mmong modules

Meltiple Tnstavchon and Singe Data stnan


itrst
Ris strvchurr is only for thlaelcal
Simce mo bractical has been (onstsv cted vsin
practical gsem
(
>
stomPeta

Tnstavchion Strtam
L
i'smomozy eIto
prrohon.bifornatien wite cald
stoged to Qutsil
min. envgo
n
memoy infornation
from Tronsfr
af
to
gead ishateberetion (onsist
ef
ite
Stoond
in
Micro logle 3)
s bit heraton
dala
tronsfr Anithmutie
stord
inPrform mef->
eg.of. onth.
Yrnshr
n iafa binazy
clea Joad,
Pion Gheae mico Called
at exeutet e
shogd
in on oheratonserahion Micos
Newosk connechom Tntor
PEJ
PE PE
he at dta Veis
Hne. dilfeornt
Seme dieend eitvte (on
prrato strvehoms
and m
puteg lel pora (eSSOTs poo all this tn
eam ste Data
9Adross
Can be slatpel ae

Read

3us ehi tecture


A
H com mumleation þath way (on neehng 2or
morp devices
> A bus hat (omnect magor omponnts
boocess od , memag, Il) is called Sys trm
bs
yirally (ontains abod lt
> ystem bus
to hundmds
assigns Some fnetion
epeutnd odo ? fentonal
Sy stem tus vsualy> data bus

nemary
c)
lata bus

(omtoa by
Data b us Corrics lala

> ! (omsists ob 8, 32, 61, )28,


lims rrfed
(olleHom wins vsel lo
-
Address bus basicular location in

detesmme
yste ms.

(ootrol bus ’Ih always contrel timmi'g

Variovs levlces
memo
memo Bus Brchtrcheop
Tradi'tiomal
|Ceche CPU
Pro crssor
Condrolleg

main Menal

Syshrm hus
lexponstod

Exbenslo n
Bos abitation
cess
brocesS o 90sol wimq onllict hat rico
lhon hmeeltble dulees atemAt to a
at he Some Hme

do data
>Bus Arbitatom Scheme vsvally ta to balsmee
Rus praoty

arbitshon metak,
tpes hes
bus
’Tor art seve val

) De contali'eed
Pistributed
Knoen as Hu bes (otrles
tali2Pd Hsingle Dwice, managi ng access to he
is esbong ble Bor
has jts
dewico
Drcendgalzrd ’ pach
access to he
fas
Device (ombete
Ddstsiheted
signal
grent
Jo He
’Bus Prbitraton frs

us af
2ccess to a
mas to.
()
Abblicaton Bes ybitafom
) sharrd mrmey elti þle Devices nead lo access
f's
so hat
he momoT4
Pach otor.

)Molt- Procosor system


daka and Koordinte
each ote to shoe processers to Shore
wih meltHble with ach oha
ollow
þrocess ng. Tt com
nlato
the hus to
access to moy.
Shard me
H
ond
input/opet deuices to
meeltiple mvncote the
wth
T alloew. doo com
co
de
d beg
acc ess to
brocessoo and memoT

Real- Aime Syste ms helb to esUre hat Aata nsfeg


con
Occvs wihin
access do e bu.

Em bedded Systems muliplo dvias o sharg


allou mumate
Com with e
he s to
Qccess to
proCessoo and men
keo apbvoac hes to hue arbitoion
)ontoalized Bus a, bi dastom
Con cls 4 hroe meth als
y
D Daisy chaining math ad
D Polling or RodetHng Pojoy mathad
) ixed þrion oT Tndepndd Requet Mothod.
Method
chaimim4 methd wherp al
is a slm ple and Ch Popeg
vses He same lime for makn
He bus master
bus reqvests
BaT DeviceL 6r
Bus BRQ
Prbiter SACK
BRR Bus Reqvest Quee

Rlondage
’ Sinpieitg and salabili'y
chain, ub jo a (etan ma eelee.

Disadundag
Te vale of baioriy ac<gnd}o a devta
depenks posihon
Propagotion lelay ojss 'a heés ansthof.
clwice
ill stop wor hiog.
Polling or Rolatinq Prior'h Mr thod
he (ontrollrr is vsed to gmorate the
n thi's
master, he nunmbo
addsoss Ros the teas comm ttey
Ho mumber of mas
20qviztd debrnds on

Puie 2/
Bus Polli
|Pobitey Bus Requ
Bus Bus
stebs ' bus not busy, make bus oqusd
þlacing dulee TDon polliy ir
Mastos Polls by make bus bues4.
I detp ges
Alvontag
abo quite simpla

Disaduentaqe masters is diMical


> hdding
bes
mumbor Systey
Hhan He Prtr
will mat
9

Tixed Poiooiy or Tn depndgt Rrgest meth ad


ot
sepoatr jair
to has a
Im this, ach mas 2m2t 'ms and tach pa'
eguest ahed bus
tus to t .
has a borioity css
Device 2 u'ce m
Bus
Arbito Bus 1Busy

a fast Repenst
’ is method grate
Disoakiantag lage

Rrgster Orgonizabiom
forms gstes.
spad sfo age ay
Vnique gh-
's a
T he CPU.
'n
aluays defintd in a
ino
Krgis tor jnblemk to jnhor knt
supfort a a tmponany sloragc pcation for
dabe
>It cn i'ntlenni'ng
ontimning prgms
gs he
Ti's sutbokost dinily
acess He lata i 7guird.
to
to have os l e pU and data
Can sawe He status
Tt

Clock

Ra

Ry

Re

Rz
EL B|
mux
mux
B BUs
ABUs

Decooler frihmete lop'c wnit


oþR CALU)
SeLD Contoot ond

outpu)
olecion
sCLA1 seB
IBimazy focle
Jnbut
R, R,
R2.
R:
R" R1
Rg R< Rs
Re Re
R,

(moding ALV ohea tio n


OPR selet oheation
oO00O TSFA
INCA
Add At B ADD
Sultralt A-B SUB
DecA
oollo AND
ADD Aand B
O}0oO OR
OR Aand B
Olo lo XOR
XOR Aand B
romb l e t A
SHRA
loo o0
ALU mirro - opeahon Comtae wod
sELA sel B sELD OPR oolo)
o|0 ol) oo)
R, ojolo
Re |oo lol |o0
OR
Rs oo) ||oocoolo
PPD
1lo

pddvessinq Modes
dddress of destinatiom of esud is
data d or he mocle.
ms truchon is called pddresstng
way in whith he eperond of he
Irfers to the
mstrvchon is sfecified. he ads
for mateporp nq mafyin
addiss ing omale.
instvchon is called
fied f on
('3085 micro pro cesser)
Tgtes af hddresing mocle
) DirAt hddressing mocle
Am
3) Register Tadi'met
ter Am
) Rgi's
s) Tanmmpdiate
A m

Im lez

19 Bose Rrgister A m
timoton. cles Ae is
B
(move) ration ope the s mo
A,mov
rpase otprand
is he his In
Moele pddorss
ing Regktey 3)
R
(onten avaablt adelrss
s Liooo
wherelocahon memoy
he
efberatron he L0Ds
[ioo LORD
R, o]
dolss efeive he wheh addsrss
at the qives
rvctom feld adolses
a ef he this Ya
moddepddressin. Tnclirect )
olsimaton. Accumelato
e i's
sovre addsrss
ef e ssooH
e) toofeTajon
a(load he isLDA
where
26ooH LDA
elf. ts iHion nstruc the 1m
n opra
is nd et
Headdrss the this In
modeAddrrssing Dirrct )
)Register Todirtct Adclarssing, pioale
Tn dhs he ado ss o eborand is stpciki
a
rgater beu r.
b

mov s ho pprafom
's he memorg (ocatlon
oles ti'natio n.
s phe

Tmm polatp Addo resing macle


) rangis sbecilied withi he
Tn this he ope
jnstweho7 sef
LDP # looo
where LPA s the eteratioy
immkko lota sove)
Jooo (o ms te
LOAD ##looo, RI

meolbeto olta
Lm
t'm
looo Comstant
clstinatiog odr
cdtrss,
RI I's hee

Adldrns ing mode


DYan plicit GovTls ot dat os wol as
Jn Hhts
ef lustinatiom of result ' nsrbo.
addrss ohond alrg
Arumletor)
(Conplennt
wuhre: CMA is Me operaation ALO
Arcvmlaton s he sovP ( )
clstenatson
Aecumylator i's he
Relaive Addrssing mocle
Cakaulatet by adlig the (ontet e cPU rg'ste

by anng
The Cllatup adlars 's ala lates in
mm mediate value givn the instretton)
disblace men
ond te ngis teo kalee.
EA- CPD mgistos + Displacement
LDA $ADRS
where
LDA
$ADRS s he addoss to fna ne
eddsss with addihon o vale f pC.
Accumlator s the destnatog

Trdereel Addons img mode


e adarss ot of he jnstruetion
Ts adoled to adols.
tain the chßreivp
to ot
EA = dddorss ba he metrvcthom +
toteat f IR
LDA pDRS (R)
wherp
LDÐ Is he ofoation
ADRS he addss to fia e ltin
dsh'naton
ACC mADRS RI7
RI ts ossumd as Tnoea Rrgistro
Angster peroshe ode
9 Bose- bose rgatrr is
to
allnss ord ef ho jnstrvchon

LDA ADRSLRI)
.

wih adoli hom

Auto-Deotmant Aldansing mode


Cvfmtnt/ allrrssing
) Pto-in he ngisto
Jrdinc
o
T} i's s/miler Valee 's s d o

deerpetd

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