2023 3rd International Conference on Electrical Engineering and Mechatronics Technology (ICEEMT)

FPGA-based Train Onboard PCIe Board Design and

2023 3rd International Conference on Electrical Engineering and Mechatronics Technology (ICEEMT) | 979-8-3503-0369-8/23/$31.00 ©2023 IEEE | DOI: 10.1109/ICEEMT59522.2023.10262887

Implementation
Xiao Qi Chen1,a LI Yan Zhang 2,b
School of Automation and Electrical Engineering, Dalian School of Computer and Communication Engineering, Dalian
Jiaotong University Jiaotong University
Dalain, China Dalian, China
e-mail: [email protected] e-mail: [email protected]

Chang Xian Li 3,c*

National and local joint Engineering Research Center for rail
transit equipment, Dalian Jiaotong University
Dalain, China
*Corresponding author: e-mail: [email protected]

Abstract—Since its introduction in 1992, PCI (Peripheral

Component Interconnect) interface has been widely applied in II. OVERALL PROGRAMME DESIGNE
various fields. In 2001, Intel launched the PCIe (Peripheral
Component Interconnect Express) interface, which aimed to A. Selecting a Template
replace the old PCI, PCI-X (Peripheral Component Interconnect Based on the PCIe interface implementation of the data I/O
eXtended) and AGP (Accelerated Graphics Port) bus standards. board, the physical layer interface for the PCIe X4 interface,
PCI-Express interface features high speed and high bandwidth, the hardware part of the programming is implemented by the
which overcomes the bottlenecks of traditional PCI bus in system
FPGA, and the interaction with the board on the Host side of
bandwidth and speed and demonstrates a promising application
the device for the X86 architecture, the Host to run based on
potential. By using FPGA (Field Programmable Gate Array) to
design data transmission based on PCIe bus, the hardware design the Linux 14.0 design of the PCIe simple test program or run
cost can be reduced, the integration can be improved, and the on the Windows 10 system WinDriver program on the Host.
flexibility and adaptability of the design can be enhanced by Verify the accuracy of data transmission. The key to the circuit
using the programmable features of FPGA. In this paper, a design is the power supply circuit of the FPGA, crystal circuit,
transmission scheme of PCIe Hard IP Core and DMA (Direct PCIe interface circuits and others of the hardware. The key to
Memory Access) IP Core based on Altera FPGA is implemented, the system design of the FPGA is the PCIe interface control
and the design implementation and data transmission test are module and the DMA module.
conducted.
FPGA selected Altera's Cyclone IV series
Keywords- FPGA，PCIe，DMA，Qsys，Data I/O chip,EP4CGX75CF23C8, according to Altera's datasheet, the
performance of the chip fully meets the operational
requirements of Altera's PCIe IP core, with detailed
I. INTRODUCTION engineering manuals, as well as has a very good scalability, to
With the rapid development of modern railway, the digital facilitate the future design and development.
communication method is also improving. The commonly used Its power supply circuit is realized by the LMR14020
TCN (Train Control Network) network bus in China has a voltage regulator chip to realize the power supply circuit,
transmission rate of 1Mbps for the train-level bus WTB (Wire realize the output 2.5V, 3.3V supply voltage.
Train Bus) and 1.5Mbps for the vehicle-level bus MVB
(Multifunction Vehicle Bus),[1] which can no longer satisfy the According to the PCIe electrical standard, a PCIe male
large data transmission in the train network. In the future, the connector is designed on the data I/O card to meet the physical
in-vehicle communication network will be comprehensively connection with the female slot of the host motherboard, thus
upgraded, which will significantly increase the communication realising the data communication between the data I/O card and
speed and the amount of data sent and received by the in- the host.
vehicle data interaction board. Early data I/O board through the The overall design block diagram is shown in Figure 1.
PC104 interface connected to the host for data exchange can
not meet the requirements. Therefore, the PCIe interface is
adopted as the interaction interface of the new generation of in-
vehicle data I/O boards.

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 B. FPGA circuit design
Host(X86)
In the FPGA circuit design, the main connection circuits are
Driver
the circuits of the PCIe interface, the crystal circuit, and the
connection of the power supply module. According to the chip
PCIe female datasheet, the crystal device used is NB6N11S. The NB6N11S
connector is a differential 1:2 Clock and will accept Any Level input
signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS. These
signals will be translated to LVDS and two identical copies of
Data I/O PCIe male Clock or Data will be distributed, operating up to 2.0 GHz or
Board(FPGA) connector 2.5 Gb/s, respectively. The NB6N11S has a wide input
common mode range from GND + 50 mV to VCC − 50 mV.
Qsys
PCIe control Combined with the 50 Ω internal termination resistors at the
inputs, the NB6N11S is ideally suited for converting a wide
variety of differential or single-ended clock or data signals to a
DMA typical 350 mV LVDS output level. LVDS output level. The
specific circuit design is shown in Figure 3.

On Chip Memory

Figure 1. Block diagram of the overall

system

III. HARDWARE CIRCUIT DESIGN

A. power supply circuit design

The design of the power supply circuit is based on the chip
requirements of the FPGA.The power supply circuit uses the
voltage regulator chip LMR14020 chip.
The LMR14020 device is a 40V, 2A buck regulator with an
integrated high-side MOSFET. The device has a wide input
voltage range of 4V to 40V, and the device also has a variety of
built-in protection features: cycle-by-cycle current limit
protection, thermal sensing and thermal shutdown protection
against excessive power consumption, and output overvoltage
protection. The LMR14020 is used in the power supply circuit Figure 3. FPGA crystal circuit design
design to realize 2.5V, 3.3V and 1.2V voltage outputs. In order
to meet the FPGA chip power supply, PCIe circuit design, as C. PCIe Interface Circuit Design
well as for the board to expand the functions of the required
power supply voltage. The specific circuit design diagram is PCle devices are powered by two power signals, Vcc and
shown in Figure 2. Vaux, which are rated at 3.3 V. Vcc is the main power supply,
and the main logic modules used in PCIe devices are powered
by VCC, while some logic related to power management is
powered by Vaux. In PCle devices, some special registers
usually use Vaux power supply, such as Sticky Register, at this
time to make the PCle device Vcc is removed, these logic
related to power management and the content of these special
registers will not change.
The main reason for using Vaux in the PCle bus is to
reduce power consumption and shorten system recovery time.
Because Vaux is not removed in a multi-teach situation, when
the Vcc of a PCIe device is restored, the device does not have
to revert to using Vaux-powered logic, and thus the device can
quickly return to normal operation.[2]
The maximum width of PCIe link is x32, but in practical
applications, x32 link width is rarely used. In this board design,
the main use of X4 PCIe interface, need to use PETp0~3,
Figure 2. Board power supply design

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PETn0~3 and PERp0~3, PERn0~3 a total of 16 signals, A. PCIe bus standard
composed of 8 pairs of differential signals, of which 4 pairs of In the PCI bus data transmission, data are from the
PET signals are used to send links, 4 pairs of PER signals are transmitting end to the receiving end to complete the overall
used to receive links. The specific circuit design is data sending and receiving. The PCIe structure system, data
shown in Figure. 4. initially generated by the transmitter device core layer, through
the transaction layer, data link layer and physical layer, and
ultimately sent out, while the receiving end by the physical
layer to receive the data uploaded to the core layer of the
device.[3] PCIe bus hierarchy composed of structural diagrams
as shown in Figure 6.

Device A Device B

Device Core Device Core

Transaction Layer Transaction Layer

Data Link Layer Data Link Layer

Physical Layer Physical Layer

Figure 4. PCIe interface circuit design Logical Sub_block Logical Sub_block

IV. FPGA SOFTWARE PROGRAMME DESIGN AND Electrical Sub_block Electrical Sub_block

IMPLEMENTATION
According to the content of the overall system design block RX TX RX TX
diagram, the FPGA system program design, the core Link
component of the FPGA program is the PCIe Hard IP Core,
mainly responsible for PCIe protocol analysis, the transport
layer interface to provide users with the use of the system
design, to determine the relevant interfaces and then carry out
the data transmission, and then the system needs to use the
DMA module, the PCIe data has a key role in data transmission.
Data transmission has a key role, can reduce the PCIe Figure 6. PCIe bus hierarchy
transmission data on the core chip resource occupation, and has
a certain impact on the speed of PCIe digital transmission. 1) Transaction Layer
FPGA system block diagram shown in Figure 5. Transaction Layer is the external interface layer of PCIE
protocol, the user frames and parses the data in this layer, the
packets generated in this layer are called TLP (Transaction
Layer Packets).[4] In addition, Transaction Layer also has the
Data
DMA
function of flow control based on credit, which supports
TX different forms of data transmission for different types of
Data transactions.
Data
PCIe Hard IP 2) data link layer
The data link layer acts as an intermediate stage between
RX On Chip Memory the transaction layer and the physical layer and its main
responsibilities include link management and data integrity
including error detection and correction.[5] The data link layer
receives the TLP packets from the transaction layer on the
transmission link adding the sequence number and checksum to
the physical layer, and the link layer is very dutiful and caches
Figure 5. Block diagram of FPGA system
the packets delivered by the transaction layer and retransmits
them if a transmission error is detected until they are received
correctly or until it is determined that the link communication
has failed. Link layer also has link management functions, and
there is a corresponding packet, called " DLLP (Data Link

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Layer Packet)" [6] The packet is to achieve the data exchange Within Qsys, each module needs to satisfy Avalon's address
between the two components, and there is no routing function, allocation between them. The specific allocation method can be
in other words, if a packet of data to reach the receiving end selected from the system's automatic allocation, or the address
across mountains and rivers, the middle of the countless allocation can be customized according to the needs of the
stations, the DLLP packet The DLLP packet exchanges data actual system design, but it must satisfy the requirements of
only between two stations, and mainly implements the Qsys. The specific address allocation is shown in Table 1
functions of flow control, power management, answering
mechanism and virtual channel.[7] TABLE I. AVALON ADDRESS ALLOCATION TABLE
3) physical layer
DMA interface
The physical layer is divided into two parts, one logical
sublayer and one electrical sublayer. The logical sublayer Dma read Dma write
module is responsible for the data exchange with the data link 0x0000 0000- 0x0000 0000-
layer, will receive the link layer transactions again encapsulated, PCIe_ip_txs
0x001f ffff 0x001f ffff
to receive the electrical sublayer transactions for parsing, and 0x0020 000- 0x0020 000-
OnChipMemory_s1
will carry out 8B/10B encoding or 128B/130B encoding[8], to 0x0020 0fff 0x0020 0fff
carry out the transfer between the conversion and polarity
reversal, etc., and the electrical sublayer is more responsible for After Generate within Qsys, the Schematic and Memory-
the clock data recovery, equalisation and other electrical Mapped Interconnect tools check that the data flow and
operations.[9][10] The specific TLP packet transmission and interface connections are as expected, as shown inthe following
reception process is shown in Figure 7. figure 8.

Transmit Receive

Transaction Layer Packet(TLP) Transaction Layer Packet(TLP)

Header Data Payload ECRC Header Data Payload ECRC

Link Packet Link Packet

Sequence TLP LCRC Sequence TLP LCRC

Physical Packet Physical Packet

Figure 8. Schematic connection content
Start Link Packet END Start Link Packet END

Finally, the top file is realized in Quartus, and the PCIe

Hard IP Core of Qsys and the required IP of the clock are
Figure 7. TLP packet transmission and acceptance process
exemplified into the top file, and Analysis and Synthesis are
carried out. Due to the large core of the PCIe IP, Testbench is
B. Qsys programming not easy to realize, and the BFM tool can be used to verify the
The system design uses Quartus II integrated Qsys system project through simulation. Finally, according to the data
to design and realize the system, PCIe Hard IP Core support manual in the Pin Planner pin constraints and timing
chip design PCIe Gen1 X4 interface. Qsys can call a variety of constraints, to complete the system design content.
IP cores, through the Avalon bus to realize the communication
between the IP and the advantage is to facilitate the V. TEST PROGRAMME AND VALIDATION OF RESULTS TESTING
construction of the project, and at the same time, Qsys can be PROGRAMME
packaged within the functional modules designed to meet the
needs of different system design. A. Test program
The system design needs to use the IP core including PCIe In the process of setting up the overall test environment,
Hard IP Core, DMA IP core, On Chip Memory IP core, the due to the monitoring of the PCIe physical signals require
three IP cores will be automatically added by the Qsys system higher sampling frequency equipment, in order to test the
interconnection module and does not affect the data transfer. In convenience and low-cost, so it is necessary to use an
Qsys, the PCIe interface will send the address of the bar to the additional computer equipment, the board for the burning of the
DMA through the Avalon-MM Master interface. After the program as well as the use of the Quartus II comes with the
address translation inside Qsys, the target address of the DMA Signal Tap tool on the PC device to monitor the internal
will be clearly defined, and then the DMA will read and write resources of the FPGA, combined with the simple driver on the
the data from the txs interface of the PCIe Hard IP Core to the Host side to verify the feasibility of the PCIe interface. The
On Chip Memory IP Core. simple driver on the host side is used to verify the feasibility of
the PCIe interface. The specific topology is shown in Figure 9.

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 Monitoring
software

Host
I/O
Board
Figure 11. Data captured within the FPGA at the Signal Tap side
Figure 9. Topology of the test environment

VI. CONCLUSIONS
B. Test results This system design, the PCIe interface in the continuous
A simple driver was designed by using the devmem read and write loopback test, in line with the design of the
character device, which will access the physical memory space expected transmission speed as well as the interface of the data
of the PCIe device according to the PCIe device number, map transmission accuracy also meets the design requirements. The
the physical memory space to the user space, and then read and transmission capability of the train's on-board data board has
write to it, thus realizing the test in the linux environment. The been improved, laying the foundation for the future
results of 1000 consecutive reads and writes to the development of data I/O boards, and in the follow-up, the
corresponding memory within the simple driver and the results remaining on-chip resources and pins of the FPGA chip can be
displayed within Linux are shown in Figure 10. utilized for the construction of the acquisition interface to
realize data transmission; as well as the realization of a
heterogeneous platform with ARM and other chips to carry out
more development in the area of data transmission.

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