Chapter 2 Logic

Simulation
Logic Simulation

l Purposes
l Verification
l Debugging
l Studying design alternative (cost/speed)
l Computing expected behavior for tests
l Simulation-based design verification
l To check correct operations:
l e.g. delays of critical paths
l free of critical races & oscillation
l Problem is that tests are hand crafted; Very hard to prove
that a test is complete.
l Formal and assertion-based verification required

2
Modeling for Circuit Simulation

l Circuit models
l Modeling levels
l Behavioral, logic, switch, timing, circuit
l Modeling description (languages)
l Signal models
l Logic value models
l Timing value models
l Choices of models determine the complexity
and accuracy of simulation

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Level of Circuit Modeling (1/2)

l Electronic system level

l Software+hardware
l Transaction/cycle-accurate functions
l C/C++, SystemC, SystemVerilog, etc.
l Register-Transfer-Level (RTL)
l Define bit and timing (almost) accurate architecture for
sign-off
l VHDL and Verilog
l Logic/cell/gate level
l Interconnected Boolean gates
l AND, OR, NOR, NAND, NOT, XOR, Flip-flops,
Transmission gates, buses, etc.
l Suitable for logic design, verification and test
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Level of Circuit Modeling (2/2)
l Switch level
l Interconnects of ideal transistor switch
l Need transistor size, node R and C to determine logic value
l Zero delay in timing
l Suitable for full-custom high-performance ASIC
l Timing level
l Use transistors with detailed device models
l Calculate charge/discharge current with transistor’s voltage-
current model and obtain node voltage as a function of time
l Mainly for post-PR timing verification, e.g., TimemillÔ
l Circuit level
l Lowest level, ultimate in simulation accuracy
l Obtain timing by solving the equations relating branch/loop
current and node voltage
l Critical timing analysis for digital circuits
l Mixed-signal circuit simulation
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Logic States for Simulation
l Two states (0, 1) for combinational and
sequential circuits with known initial
states.
l Three states (0, 1, X) for sequential
circuits with unknown initial states
l X (unknown state) for cases when the logic
value cannot be determined
l X can be either 0 or 1.
l Sources: uninitialized FF, bus, memory, multi-
cycle paths, etc.

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Logic Operations with X

AND 0 1 x OR 0 1 x
0 0 0 0 0 0 1 x
1 0 1 x 1 1 1 1
x 0 x x x x 1 x

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Problems with 3-Valued Logic

l May cause information loss

l Fail determining the logic value even though that
value can be easily determined
l Example:
The output is evaluated as x even though it
should be 1 regardless of the actual value of x
1 x
x
x
x
x
1
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Symbolic Simulation of “x”

l Treat “x” as a signal

1 x
l NOT x = x’
l x + x’ = 1 x

x’
x’
1
l Problem
l There can be multiple sources of X, e.g., Flip-flops
l One “x” for each unknown value (x1, x2, …)
l Impractical for large circuits, e.g., x1 + x2 = ?

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High-Impedence State Z
l Floating state: a node w/o a path conducting to
either Vdd or Gnd
l Logic state of Z is interpreted dynamically
l Single floating node
l Same as its driven value before becoming floating
l A set of floating nodes get connected
l Depends on charge sharing, may become uncertain
l A floating node connected to Vdd/Gnd becomes 1/0
l When multiple source drive a floating node, the value
depends on the strength of the driving logics.
l Most MOS circuits containing dynamic logic
require four states (0,1, x, z) for simulation
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An Example of High-Z Bus

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Delay (Timing) Models
l Delay of a logic element
l Time between an input change (cause) and the output
change (effect), e.g. C->E or D->E
l Called gate delay, pin-pin delay, or switching delay
l Interconnect delay
l Time between the generation of a signal transition at a
gate output and its arrival at the input of a fanout gate,
e.g. A->C, or B-> D
l Or called switching delay
l Consider R, C (L) effects A
C E

A C D
B

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Terms for Cell Delay Models

l Zero and unit delay

l Rise (fall) delay
l Gate delays of different final output states
l Inertia delay
l Minimum pulse width to cause a transition
l Used for filtering input/output pulse
l Input inertia delay: minimum pulse width for input
l Output inertia delay: minimum pulse width for output
l Min/Max Delay
l The minimum or maximum bound of a gate delay
l Transition time
l Time for a signal to transit from 0 to 1 or 1 to 0.
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Delay Models Examples
A C
A 3
B=1
transport delay = 2
C 2 3
(transition-independent)
3
1 rise delay = 1
C fall delay = 3
1
1 min-max delay
C (transition independent)
3 3 1£d£3
C input inertia delay = 4

2 input inertia delay = 2

C 3 & transport delay = 2

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Common Cell Delay Models

l Table-based
l A pin-pin min/max rise/fall delay of a cell = f(CL, Tr)
l CL=output load
l Tr=input transition time
l Current-source based
l A voltage-controlled current source I(Vi, Vo)
l I: Vdd to Gnd current
l Vi: input voltage
l Vo: output voltage
l More accurate in terms of noise, but more CPU intensive
l Interconnect delays
l Elmore delay

15
Modeling Levels and Signals

level Circuit Signal Timing Application

Description Resolution
ESL SystemC 0,1 transaction system
Behavior HDL 0,1 cycle architecture
Logic gate-level HDL 0, 1, X, Z zero, unit, logic design
(with multiple cell and test
signal delays
strength)
Switch transistor, RC 0, 1, X zero, possible full-custom
interconnects (with gross-grain logic
signal timing verification
strength)
Timing same as above Analog fine-grain time timing
(SPICE) verification
Circuit same as above Analog continuous timing/analog
(SPICE) time verification
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Types of Logic Simulators

l Compiled-driven simulators
l The compiled code is generated from an RTL or gate-
level description of the circuit
l Simulation is simply execution of the compiled code
l Event-driven Simulators
l Simulate only those signals with value changes
l Only propagate necessary events (value changes)

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Compiled Simulation
l A circuit is simulated by executing a
compiled code of the circuit.
l Levelization
l to ensure that a signal is evaluated after all its
sources are evaluated
a
e
Levelization b g
•Assign all PI’s level 0 f
c
• The level of gate G is h
d
Lg = 1 + max(L1,L2,…)
• level 0: a, b, c, d
where Li’s are G’s input
• level 1: e, f
gates
• level 2: g, h
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Flow of Levelization

19
Example of Levelization

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Compiled Simulation – cont’d

l Code generation & execution

while (1) {
a read_in(a,b,c,d);
e
e = AND(a,b);
b g
f = NOR(b,c);
f
c g = OR(e,f);
h h = NAND(d,f);
d
print_out(g,h);
}

l Very effective for 2-state (0,1) simulation

l Can be compiled directly into machine codes
l Mainly for functional verification, where timing is
irrelevant
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Compiled Simulation –
Example in C
l Code generation in C
#include <stdlib.h>
a int main(){
e unsigned int a=0xF; //1111
b g unsigned int b=0xA; //1010
f unsigned int c=0x8; //1000
c
h unsigned int d=0x7; //0111
d unsigned int e, f, g, h;
e = a&b;
f = ~(b|c);
g = e|f;
h = ~(d&f);
printf("g,h=%X,%X", g, h);
}

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Problems with Compiled
Simulation
l Zero-delay model
l Timing problems, e.g., glitches and races, cannot
be modeled
l Simulation time could be long
l Proportional to W(input vectors´number of gates)
l Entire circuit is evaluated even though typically
only 1-10% of signals change at any time
l Note RTL compiled simulation is different and fast,
since branching can be used.
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Event-Driven Simulation

l An event is a change in value of a signal line

l An event-driven simulator evaluates a gate
(element) only if one or more events occur at
its inputs
l Only does the necessary amount of work
l Follows the path of signal flow
0 1
1
0
0
1
0
0 => 0
1 => 1
0 => 1
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Zero-Delay Event-Driven
Simulation
Read in initial state
information

More input No
Stop
vector?
Yes
Yes
Read in new i/p vector,
and put the fanout gates
Is Q empty?
of the PIs with events in
No event queue Q.

Evaluate next g in Q.
If g changes state,
put its fanout gates
in event queue Q.

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Gate Evaluation – Table
Lookup
l The most straightforward and easy way to implement
l For binary logic, 2n entries for n-input logic element
l May use the input value as table index
l Table size increases exponentially with the number of inputs
l Could be inefficient for multi-valued logic
l A k-symbol logic system requires a table of 2mn entries for an
n-input logic element
l m = log2k
l Table indexed by mn-bit words

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Gate Evaluation – Input
Scanning
l Assume that only dealing w/ AND, OR, NAND, and
NOR primitive gates
l These gates can be characterized by controlling
value c and inversion i
l The value of an input is said to be controlling if it determines the
gate output value regardless of the values of other inputs

c i
AND 0 0
OR 1 0
NAND 0 1
NOR 1 1
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Input Scanning – cont’d
I/P of a 3-input primitive gate O/P
c x x cÅi
x c x cÅi
x x c cÅi
c’ c’ c’ c’Åi

Evaluate(G,c,i){
u_values = false;
for every input value v of G{
if (v == c) return cÅi;
if (v == x) u_values = true;
}
if (u_values) return x;
return c’Åi;
}

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Gate Evaluation – Input
Counting
l To evaluate the output, it’s sufficient to know
l Whether any input equals c
l If not, whether any input equals x
l Simply maintain c_count & x_count
l Example: AND gate
l 0 => 1 at one input: c_count--
l 0 => x at one input: c_count--, x_count++
l Evaluate(G,c,i){
if (c_count > 0) return cÅi;
if (x_count > 0) return x;
return c’Åi;
}
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Event-Driven Simulation with
Delays
l While ( event list is not empty ){
t = next time in list;
process entries for time t;
}
l The key is to construct a queue entry for
every time point

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Time wheel
Event Lists
t=max
t=0
Current time ptr t=1
t=2
t=3
t=4
t=5

l Max units is the largest delay experienced by any

event
l All gates + interconnects
l A total of max+1 slots

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 Flow of Simulation with Delays
Algorithm 1 (two-pass)

evaluates the activated

gates and schedules
Pass 1 their computed values.
retrieves the entries from event list & Pass 2
determine the activated gates.
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Simulation with Delays
Algorithm 1
Activated = f
For every event (g, vg+) at list of time t { //from LE
if (vg+ ¹ vg ) // vg is the original value at signal g {

vg = vg+;
for every j on fanout list of g {
update input value of j;

add j to LA if j is not a member of LA;

} /* for */
} /* if */
} /* for */

For every g Î LA{

vg+ = evaluate (g);
schedule (g, vg + ) for time t+delay(g);
}
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Two-Pass Algorithm
0 0
1

1
1 0
1
Gate delay
G1: 8ns
G2: 8ns
G3: 4ns
G4: 6ns

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Example (Cont.)

35
 Example of Algorithm 1 to
schedule a Null Event a z
8
b
a
0 4

z
l Time 0 : event (a, 1) 8 10
evaluate z=1 Þ (z,1) scheduled for time 8
l Time 2 : event (b, 0)
evaluate z=0 Þ (z, 0) scheduled for time 10
l Time 4 : event (a, 0)
evaluate z=0 Þ (z, 0) scheduled for time 12
The last scheduled event (at t=12) is not a real event!!

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An Improved Algorithm
Change Pass 2 to:

For every j Î Activated {

vj¢ = evaluate (j);
if (vj¢ ¹ lsv(j)) (lsv: last saved value)
{
schedule (j, vj¢) for time t+d(j);
lsv(j) = vj¢;

}
}
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Two Pass V.S. One Pass
Algorithm
l Two-pass strategy performs the evaluations only
after all the concurrent events have been retrieved
l to avoid repeated evaluations of gates having multiple
input changes.
l Experience shows, however, that most gates are
evaluated as a result of only one input change.
l One-pass strategy:
l Evaluates a gate as soon as it is activated
l Avoids the overhead of building the Activated set

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 One Pass Algorithm

For every event (g, vg+) pending at current time t {

vg = vg+ ;
for every j on the fanout list of g {
update input values of j;
vj+ = evaluate (j);
if (vj+ ¹ vj) {
schedule (j, vj+) for time t+d(j);
vj = vj+;
}
}
}

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An Example of Hazards

40
Type of Hazards

l Static or dynamic
l A static hazard refers to the transient pulse on a
signal line whose static value does not change
l A dynamic hazard refers to the transient pulse
during a 0-to-1 or 1-to-0 transition
l 1 or 0

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Static Hazard Detection
l Extra encoding can be used to detect hazards during
logic simulation.
l Note that hazards only occur during signal transition
l Two consecutive vectors are considered simultaneously
l The following is the 6-valued encoding for a pair of
vectors.
l For example, 0->1 transition (R) is encoded as 0X1.
Value Sequence(s) Meaning
0 000 Static 0
1 111 Static 1
0/1, R {001,011} = 0x1 Rise (0 to 1) transition
1/0, F {110,100} = 1x0 Fall (1 to 0) transition
0* {000,010} = 0x0 Static 0-hazard
1* {111,101} = 1x1 Static 1-hazard
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6-Valued Logic for Static Hazard
Analysis

AND 0 1 R F 0* 1*
0 0 0 0 0 0 0
1 0 1 R F 0* 1*
R 0 R R 0* 0* R
F 0 F 0* F 0* F
0* 0 0* 0* 0* 0* 0*
1* 0 1* R F 0* 1*

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Oscillation

l Oscillating circuits will result in repeated scheduling

& processing of the same sequence of events

S = 1=>0=>1 S 4
3 y
3
y 3

3 y’ y’ 3
R=1 3

l Oscillation control takes appropriate action upon

detection of oscillation

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Local Oscillation Control

l identify conditions that causes oscillations in

specific sub-circuits, e.g., latches, flip-flops
l For an oscillating latch, the appropriate corrective
action is to set y = y’ = x (unknown)
l Oscillation control via modeling
l Example: when y=y’=0 (oscillation condition, also
implying S=R=1), G = x causes y = y’ = x and stops
oscillation
S
S y
y
G
x

y’
y’ R
R

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Global Oscillation Control

l Detection of global oscillation is

computationally infeasible
l Requires detecting cyclic sequences of values for
any signal in the circuit
l A typical procedure is to count the number of
events occurring after any primary input
change
l Oscillation is “assumed” if the number exceeds
the specified limit

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Simulation Engines

l Motivation
l Logic simulation is time consuming.
l Simulation engines are special-purpose
hardware for speeding up logic simulation.
l Usually attached to a general-purpose host computer
through, for example, VME/PCI bus.
l FPGA-based logic emulation
l Use parallel and/or distributed processing
architectures.

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