Lecture 04 Interconnects 28092023
Lecture 04 Interconnects 28092023
Introduction to VLSI
VLSI Interconnects
20 SEP 2023
transmitters receivers
schematics physical
q Interconnect parasitics
§ reduce reliability
§ affect performance and power consumption
q Classes of parasitics
§ Capacitive
§ Resistive
§ Inductive
M2
Cdb2 Cg4 M4
Cgd12
Vin Vout Vout2
Cdb1 Cw Cg3
M1 M3
Interconnect
Fanout
Vin Vout
Simplified
Model CL
W Electrical-field lines
tdi Dielectric
Substrate
e di S 1
cint = WL SCwire = =
t di S × SL SL
(a)
H W - H/2
(b)
(from [Bakoglu89])
ECE413 Introduction to VLSI Jirjees Matti Interconnect
12 Fall 2023
EE141
Interwire Capacitance
Current flow
W Electrical-field lines
tdi Dielectric
Substrate
fringing parallel
(from [Bakoglu89])
R=r L
HW
L Sheet Resistance
H Ro
R1 R2
W
q SelectiveTechnology Scaling
q Use Better Interconnect Materials
§ reduce average wire-length
§ e.g. copper, silicides
q More Interconnect Layers
§ reduce average wire-length
q New technology
§ Low-resistive interconnect materials
§ Increasing of switching frequencies (super-GHz)
q Inductance is more important today!
§ Ringing
§ Overshoot effects
§ Reflections of signals due to impedance mismatch
§ Inductive coupling between lines
§ Switching noise
Definition of inductance
cwi re
Driver
R d r iv e r
Vout
V in
C lu m p e d
x= L/10
2
x = L/4
1.5
v o lta g e ( V )
x = L/2
1
x= L
0.5
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
time (nsec)
V in