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Lecture 04 Interconnects 28092023

The document discusses VLSI interconnects and their modeling. It covers interconnect parasitics such as capacitance, resistance, and inductance. It also discusses modeling techniques such as lumped and distributed RC models and their usage for analyzing delay.

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Zeeshan Haider
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0% found this document useful (0 votes)
72 views37 pages

Lecture 04 Interconnects 28092023

The document discusses VLSI interconnects and their modeling. It covers interconnect parasitics such as capacitance, resistance, and inductance. It also discusses modeling techniques such as lumped and distributed RC models and their usage for analyzing delay.

Uploaded by

Zeeshan Haider
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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ECE413/ECE514

Introduction to VLSI

VLSI Interconnects
20 SEP 2023

ECE413 Introduction to VLSI Jirjees Matti Interconnect Fall 2023


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Before We Begin…

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The Wire

transmitters receivers

schematics physical

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Wire Models

All-inclusive model Capacitance-only

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Impact of Interconnect Parasitics

q Interconnect parasitics
§ reduce reliability
§ affect performance and power consumption
q Classes of parasitics
§ Capacitive
§ Resistive
§ Inductive

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INTERCONNECT
CAPACITANCE

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Capacitance of Wire Interconnect
VDD VDD

M2
Cdb2 Cg4 M4
Cgd12
Vin Vout Vout2

Cdb1 Cw Cg3
M1 M3
Interconnect

Fanout
Vin Vout
Simplified
Model CL

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Interconnect Layout

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Capacitance: The Parallel Plate Model
Current flow

W Electrical-field lines

tdi Dielectric

Substrate

e di S 1
cint = WL SCwire = =
t di S × SL SL

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Permittivity

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Fringing Capacitance

(a)

H W - H/2

(b)

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Fringing versus Parallel Plate

(from [Bakoglu89])
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Interwire Capacitance
Current flow

W Electrical-field lines

tdi Dielectric

Substrate

fringing parallel

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Impact of Interwire Capacitance

(from [Bakoglu89])

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Wiring Capacitances (0.25 µm CMOS)

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INTERCONNECT
RESISTANCE

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Wire Resistance

R=r L
HW

L Sheet Resistance
H Ro

R1 R2
W

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Interconnect Resistance

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Dealing with Resistance

q SelectiveTechnology Scaling
q Use Better Interconnect Materials
§ reduce average wire-length
§ e.g. copper, silicides
q More Interconnect Layers
§ reduce average wire-length

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Interconnect Resistance Data

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Skin Effect

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Skin Effect

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INTERCONNECT
INDUCTANCE

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INTERCONNECT INDUCTANCE

q New technology
§ Low-resistive interconnect materials
§ Increasing of switching frequencies (super-GHz)
q Inductance is more important today!
§ Ringing
§ Overshoot effects
§ Reflections of signals due to impedance mismatch
§ Inductive coupling between lines
§ Switching noise

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INTERCONNECT INDUCTANCE

Definition of inductance

Inductance physical relationship

Inductance physical relationship

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INTERCONNECT INDUCTANCE

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Interconnect
Modeling

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The Lumped Model
Vout

cwi re
Driver

R d r iv e r
Vout

V in
C lu m p e d

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The Lumped RC-Model
The Elmore Delay

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The Ellmore Delay
RC Chain

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The Ellmore Delay
RC Chain (Example)

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Wire Model

Assume: Wire modeled by N equal-length segments

For large values of N:

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The Distributed RC-line

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Step-response of RC wire as a
function of time and space
2.5

x= L/10
2

x = L/4
1.5
v o lta g e ( V )

x = L/2
1
x= L

0.5

0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
time (nsec)

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RC-Models

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Design Rules of Thumb

q rc delays should only be considered when


tpRC >> tpgate of the driving gate
Lcrit >> Ö tpgate/0.38rc
q rc delays should only be considered when the
rise (fall) time at the line input is smaller than
RC, the rise (fall) time of the line
trise < RC
§ when not met, the change in the signal is slower
than the propagation delay of the wire

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Driving an RC-line
(r w,cw,L)
R s V o ut

V in

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