1.

P-N DIODE CHARACTERISTICS

1.1 Objective
To study the Volt-Ampere Characteristics of Silicon P-N Junction Diode and to find
its cut-in voltage, static and dynamic resistances.
1.2 Hardware Required
S. No Apparatus Type Range Quantity
01 PN Junction Diode 1N4001 1
1k ohm, 10% tolerance,
02 Resistance 1
1/2 watt rating
03 Regulated power supply (0 – 30V), 2A Rating 1
04 Ammeter MC (0-30)mA, (0-500)μA 1
05 Voltmeter MC (0 – 1)V, (0 – 30)V 1
Bread board 1
06
Connecting wires Few

1.3 Introduction
Donor impurities (pentavalent) are introduced into one-side and acceptor impurities
into the other side of a single crystal of an intrinsic semiconductor to form a p-n diode with a
junction called depletion region . This region gives rise to a barrier potential V γ called Cut-
in Voltage. This is the voltage across the diode at which it starts conducting. The P-N
junction can conduct beyond this Potential.
The P-N junction supports uni-directional current flow. If (+) ve terminal of the input
supply is connected to anode (P-side) and (–)ve terminal of the input supply is connected to
cathode (N- side), then diode is said to be forward biased. In this condition the height of the
potential barrier at the junction is lowered by an amount equal to given forward biasing
voltage.
Both the holes from p-side and electrons from n-side cross the junction
simultaneously and constitute a forward current ( injected minority current – due to holes
crossing the junction and entering N-side of the diode and current due to electrons crossing
the junction and entering P-side of the diode). Assuming current flowing through the diode to
be very large, the diode can be approximated as short-circuited switch. If (–) ve terminal of the
input supply is connected to anode (p-side) and (+)ve terminal of the input supply is
connected to cathode (n-side) then the diode is said to be reverse biased. In this condition an
amount equal to reverse biasing voltage increases the height of the potential barrier at the
junction.
Both the holes on p-side and electrons on n-side tend to move away from the junction
thereby increasing the depleted region. However the process cannot continue indefinitely,
thus a small current called reverse saturation current continues to flow in the diode. This
small current is due to thermally generated carriers. Assuming current flowing through the
diode to be negligible, the diode can be approximated as an open circuited switch.
1.4 Circuit diagram:

1.4.1 Forward Bias

Fig 1.1 Circuit diagram for Forward bias

1.4.2 Reverse Bias
 Fig 1.2 Circuit diagram for Reverse bias
1.5 Precautions
1. While doing the experiment do not exceed the ratings of the diode. This may lead to
damage of the diode.
2. Connect voltmeter and Ammeter in correct polarities as shown in the circuit diagram.
3. Do not switch ON the power supply unless you have checked the circuit connections as
per the circuit diagram.

1.6 Characteristics of PN junction diode

1. Breakdown voltage can be traded with switching speed. A reduction in recombination
lifetime through addition of suitable impurities will increase leakage current. This can
be countered by decreasing diode area which however will lead to reduced forward
current rating unless doping is increased. This will lead to a reduced breakdown
voltage.
2. The breakdown voltage and reverse recovery are also related together in more direct
manner. Regions which have higher doping also have a lower recombination lifetime so
that a lower breakdown voltage diode is likely to have lower lifetime and better
switching speeds. So a single diode cannot meet the diverse applications.

1.7 Procedure
1.7.1 Forward Biased Condition
1. Connect the PN Junction diode in forward bias (i.e )anode is connected to positive of
the power supply and cathode is connected to negative of the power supply .
2. Use a Regulated power supply of range (0-30) V and a series resistance of 1kΏ.
3. For various values of forward voltage (Vf) note down the corresponding values of

forward current (If).

1.7.2 Reverse Biased condition

4. Connect the PN Junction diode in Reverse bias i.e; anode is connected to negative of
the power supply and cathode is connected to positive of the power supply.
5. For various values of (Vr) note down the corresponding values of reverse current ( Ir ).

1.8 Tabular column

1.8.1 Forward Bias

S. No Vf (volts) If (mA)

1.8.2 Reverse Bias

S. No Vr (volts) Ir (μA)
1.9 Model Graph

Fig 1.3 Model graph

Forward Bias

Fig 1.4 PSPICE Simulation output for Forward Bias

Reverse Bias
 Fig 1.5 PSPICE Simulation output for Reverse Bias

1.10 Result
Thus the VI characteristic of PN junction diode was verified.
i. Cut in voltage = V

ii. Static forward Resistance rdc(Vf/If) = Ω

iii. Dynamic forward Resistance rac (∆Vf/∆If)= Ω

iv. Static Reverse Resistance rdc(Vr/Ir) = Ω

v. Dynamic Reverse Resistance rac(∆Vr/∆Ir)= Ω

1.11 Pre lab Questions

1. What is the need for doping?
2. How depletion region is formed in the PN junction?
3. What is break down voltage?
4. What is cut-in or knee voltage? Specify its value in case of Ge or Si?
5. What are the differences between Ge and Si diode?
6. What is the relationship between depletion width and the concentration of impurities?
1.12 Post lab Questions
1. How does PN-junction diode acts as a switch?
2. Comment on diode operation under zero biasing condition.
3. For a uniformly doped silicon PN junction diode with an N-type doping of and a P-
type doping of 2 x , what fraction of the built-in voltage is dropped in the N-region?
Where will most of the built-in voltage be dropped if the P type doping is much larger than the
N-type doping?
4. The depletion capacitance/Area measured for a symmetrical Silicon PN junction at different
bias voltages is given below:
 (a) Determine the doping of N and P-regions, (b) Determine the built-in voltage
(c) Determine the depletion width at zero bias

5. Draw the circuits used to get the following outputs.

 2. ZENER DIODE CHARACTERISTICS

2.1 Objective
To study the Volt-Ampere characteristics of Zener diode and to measure the Zener break
down voltage.

2.2 Hardware Required

S.
Apparatus Type Range Quantity
No
01 Zener Diode IZ 6.2 1
1k ohm, 10% tolerance, 1/2 watt
02 Resistance 1
rating
03 Regulated power supply (0 – 30V), 2A rating 1
04 Ammeter mC (0-30)mA 1
05 Voltmeter mC (0 – 1)V, (0 – 10)V 1
Bread board 1
06
Connecting wires Few

2.3 Introduction
An ideal P-N Junction diode does not conduct in reverse biased condition. A Zener diode
conducts excellently even in reverse biased condition. These diodes operate at a precise value of
voltage called break down voltage. A Zener diode when forward biased behaves like an ordinary P-
N junction diode. A Zener diode when reverse biased can either undergo avalanche breakdown or
Zener breakdown.
Avalanche breakdown:-If both p-side and n-side of the diode are lightly doped, depletion
region at the junction widens. Application of a very large electric field at the junction may rupture
covalent bonding between electrons. Such rupture leads to the generation of a large number of
charge carriers resulting in avalanche multiplication.
Zener breakdown:-If both p-side and n-side of the diode are heavily doped, depletion region
at the junction reduces. Application of even a small voltage at the junction ruptures covalent bonding
and generates large number of charge carriers. Such sudden increase in the number of charge carriers
results in Zener mechanism.
2.4 Circuit diagram
2.4.1 Forward Bias

Fig 2.1 Circuit diagram for Forward bias

2.4.2 Reverse Bias

Fig 2.2 Circuit diagram for Reverse bias

2.4.3 Zener Diode Symbol

2.5 Precautions
1. While doing the experiment do not exceed the ratings of the diode. This may lead to damage of
the diode.
2. Connect voltmeter and Ammeter in correct polarities as shown in the circuit diagram.
3. Do not switch ON the power supply unless you have checked the circuit connections as per the
circuit diagram.

2.6 Characteristics of Zener Diode

For IZ6.2 Zener diode,
Forward Bias
At a given (constant) diode current, V exhibits an approximately linear shift in the VI -characteristic
due to the combined effect of the temperature dependences of both IS and VT
Typically, the VI -characteristic shifts approximately -2 mV/°C.
Reverse Bias
The temperature dependence of the reverse current is that of IS alone, which changes exponentially
as a function of temperature. Typically, I S approx. doubles for every 10 °C increase in Temperature.
These variations may lead to significant changes in the operation of a circuit over a large
temperature range and, in many applications, requires compensation strategies to be implemented in
the design of some circuits.

2.7 Procedure
2.7.1 Forward Biased Condition
1. Connect the Zener diode in forward bias i.e; anode is connected to positive of the power supply
and cathode is connected to negative of the power supply as in circuit
2. Use a Regulated power supply of range (0-30) V and a series resistance of 1kΏ.

3. For various values of forward voltage (Vf) note down the corresponding values

of forward Current (If).

2.7.2 Reverse biased condition
1. Connect the Zener diode in Reverse bias i.e; anode is connected to negative of the power
supply and cathode is connected to positive of the power supply as in circuit.
2. For various values of reverse voltage (Vr ) note down the corresponding values of reverse
current ( Ir ).

2.8 Tabular column

2.8.1 Forward Bias
S. No Vf (volts) If (mA)

2.8.2 Reverse Bias

S. No Vr (volts) Ir (mA)
2.9 Model Graph

Fig 2.3 Model graph

Forward Bias

Reverse Bias

Fig 2.4 PSPICE Simulation output for Forward Bias

Fig 2.5 PSPICE Simulation output for Reverse Bias

2.10 Result
The Zener diode characteristics have been verified and the following parameters were
calculated
i) Cut in voltage = ……… V
ii) Break down voltage =…..........V

2.11 Pre lab Questions

1. Explain the concept of Zener breakdown?
2. How depletion region gets thin by increasing doping level in Zener diode?
3. State the reason why an ordinary diode suffers avalanche breakdown rather than Zener
breakdown?
4. Give the reasons why Zener diode acts as a reference element in the voltage regulator circuits.
5. What type of biasing must be used when a Zener diode is used as a regulator?

2.12 Post lab Questions

1. Design a DC power supply network using Zener diode.
2. What happens when the Zener diodes are connected in series?

3. Justify the use of zener diode in a stabilization circuit?

4. How will you differentiate the diodes whether it is Zener or avalanche when you are given two
diodes of rating 6.2 v and 24V?
5. How does a zener diode protect meters from excess voltage that is applied accidentally?
 3. a .APPLICATION OF PN DIODE-RECTIFIER
3.1 Objective
To design and construct the application of PN diode using rectifier circuit and analyze the
following parameters
a. To plot Output waveform of the rectifier
b. To find ripple factor using formulae
c. To find the efficiency

3.2 Hardware Required

S. No Apparatus Type Range Quantity
(6-0-6 )V, 500mA, 1A
01 Step down Transformer 1
Rating
470 ohm, 10% tolerance,
02 Resistance 1
1/2 watt rating
03 Capacitor 470µF 1
04 Diode IN4001 1
Bread board 1
05
connecting wires Few

3.3 Half wave rectifier

A device is capable of converting a sinusoidal input waveform into a unidirectional
waveform with non-zero average component is called a rectifier. A practical half wave rectifier with
a resistive load is shown in the circuit diagram. In positive half cycle, Diode D is forward biased and
conducts. Thus the output voltage is same as the input voltage. In the negative half cycle, Diode D is
reverse biased, and therefore output voltage is zero. A smoothing filter is induced between the
rectifier and load in order to attenuate the ripple component. The filter is simply a capacitor
connected from the rectifier output to ground. The capacitor quickly charges at the beginning of a

cycle and slowly discharges through RL after the positive peak of the input voltage. The variation in
the capacitor voltage due to charging and discharging is called ripple voltage. Generally, ripple is
undesirable, thus the smaller the ripple, the better the filtering action.
Ripple factor is a measure of effectiveness of a rectifier circuit and defined as a ratio of RMS
value of ac component to the dc component in the rectifier output.
Theoretical calculations for Ripple Factor:
Without Filter:
Vrms = Vm / 2

Ripple factor (Theoretical)

Ripple Factor (practical) where

With Filter:

Ripple Factor (Theoretical)

Where f = 50Hz, R = 1K , C = 1000 F

Ripple Factor (practical)

Percentage Regulation %
VNL = DC voltage at the load without connecting the load (Minimum current).
VFL = DC voltage at the load with load connected.

Efficiency
PAC = V2rms / RL
PDC = Vdc / RL

The ripple factor can be lowered by increasing the value of the filter capacitor or increasing the load
capacitance.
3.4 Circuit Diagram of Half Wave Rectifier

Fig 3.1 Circuit diagram and model graph of half wave rectifier
3.5 Observations
Output
Ripple Voltage
Waveform
Parameter Input Waveform
(with filter)
(without filter)
Amplitude(volts)

Time Period(s)
Frequency(Hz)
3.6 Full wave rectifier
A device is capable of converting a sinusoidal input waveform into a unidirectional
waveform with non zero average component is called a rectifier.
A practical half wave rectifier with a resistive load is shown in the circuit diagram. It consists of
two half wave rectifiers connected to a common load. One rectifies during positive half cycle of
the input and the other rectifying the negative half cycle. The transformer supplies the two
diodes (D1 and D2) with sinusoidal input voltages that are equal in magnitude but opposite in
phase. During input positive half cycle, diode D1 is ON and diode D2 is OFF. During negative
half cycle D1 is OFF and diode D2 is ON. Peak Inverse Voltage (PIV) is the maximum voltage
that has to be withstand by a diode when it is reverse biased. Peak inverse voltage for Full Wave

Rectifier is 2Vm because the entire secondary voltage appears across the non-conducting diode .
The output of the Full Wave Rectifier contains both ac and dc components. A majority of
the applications, which cannot tolerate a high value ripple, necessitates further processing of the
rectified output. The undesirable ac components i.e. the ripple, can be minimized using filters.
Ripple Factor:
Ripple factor is defined as the ratio of the effective value of AC components to the
average DC value. It is denoted by the symbol ' '.

Efficiency:
The ratio of output DC power to input AC power is defined as efficiency.

= 81% (if R >>Rf, then Rf can be neglected).

The maximum efficiency of a Full Wave Rectifier is 81.2%.

3.7 Theoretical Calculations:

Without filter:
Ripple factor (Theoretical) =

Ripple Factor (Practical)

With filter:

Ripple factor (Theoretical)

Percentage Regulation = %
VNL = DC voltage at the load without connecting the load (Minimum current).
VFL = DC voltage at the load with load connected.

Efficiency

PAC = V2rms / RL
PDC = Vdc / RL

3.8 Circuit Diagram

Where f = 50Hz, R =1K , C = 1000 F.

 Fig.3.6 Circuit diagram of full wave rectifier (Center tapped) Ripple Factor

3.9 Observations
Output Ripple Voltage
Parameters Input Waveform
Waveform
(with filter)
(without filter)

Amplitude(volts)
Time Period(s)

Frequency(Hz)

Efficiency, η is the ratio of dc output power to ac input power

The maximum efficiency of a Full Wave Rectifier is 81.2%

3.10 Model Graph

Fig 3.13Model graph of Full wave bridge rectifier

3.11 Result

Thus the Rectifier Circuits are constructed and ripple factor, efficiency, Vp(rect), and Vdcvalues
for circuits has been analyzed.

3.12 Pre lab Questions:

1. What is the PIV of rectifier circuits?
2. A bridge rectifier is preferable to a full-wave rectifier using center-tap transformer as
(a) It uses four diodes
(b) Its transformer does not require center-tap
(c) It requires much smaller transformer for the same output
(c) All of these
3. In a full-wave bridge rectifier, the current in each diode flows for
(a) Complete cycle of the input signal
(b) Half-cycle of the input signal
(c) Less than half-cycle of the input signal
(d) More than half-cycle of the input signal
4. What is the purpose of a filter in dc power supply?
5. What is TUF? Give the TUF of half wave, full wave-center tapped and bridge rectifier.
3.13 Post lab Questions:
1. When a 50Hz ac signal is fed to a rectifier, the ripple frequency of
the outputvoltagewaveformfor full bridge rectifier is
(a) 25 Hz (b) 50 Hz (c) 100 Hz (c)150 Hz

2. Trace the current through this rectifier circuit at a moment in time when the AC source’s
polarity is positive on right and negative on left as shown. Be sure to designate the convention
you use for current direction (conventional or electron flow):
Also, mark the polarity of the voltage drop across Rload.
3. For the figure shown below. Determine (a) the DC output voltage, (b) DC load current, (c) the
RMS value of the load current, (d) the DC power, (e)the AC power, (f) efficiency of rectifier,
(g) peak inverse voltage of each diode, and (h) output frequency. Assume all diodes are ideal.
 3.b APPLICATION OF ZENER DIODE-SHUNT REGULATOR

3.1 b Objective
1. To design the application of zener diode using a shunt voltage regulator
2. To find load regulation
3. To find line regulation
3.2 Hardware Required
S. No Apparatus Type Range Quantity
1 Power transistor 2N3055 1
2 Transistor BC147 1
1Z6.2,
3 Zener diode 1
1Z5.1
1KΩ, 947Ω, 2.48KΩ, 2.2kΩ,
4 Resistors 2.75KΩ, 49.6Ω, 10% 1
tolerance, ½ watt
5 Voltmeter MC (0 – 30)V 1

6 Bread board & wires

7. Decade Resistance Box 50Ω 1

3.3 Introduction
The term regulation is the ability of the power supply source to maintain a constant
output voltage in spite of line voltage fluctuations and changes in load current
The factors of poor regulation are
1. The line voltage changes which causes a dc output change and the ripple content of the dc
input due to inadequate filtering.
2. The load current changes which causes a variable internal drop due to the internal
resistance of the regulator and the consequent change in the output voltage and
3. The temperature coefficient of the device parameters which results in a change of the
output voltage.
Voltage regulators can be classified by the method of achieving regulation as linear regulators
and switching regulators. They are also classified by the way they are connected to the load as
series regulators and shunt regulators. Standard regulator contains three basic elements namely a
precision voltage reference, an error amplifier and a power control element.

In series voltage regulator the transistor Q 2functions both as a voltage comparator and dc

amplifier. Any increase in the output voltage V o either due to the input-voltage variation or

change of load results in increase of V BE of the transistor Q2. Hence the collector current IC 2

increase. Due to this the total current following through R 3 increases. Hence the collector voltage

of Q2 decreases.

Since the base of Q1 is tied to the collector of T2, the base voltage of Q1.with respect to

ground decreases thereby decreasing the forward bias of the emitter junction of Q 2. Hence the

collector emitter voltage of Q1 has to increase in order to maintain the same emitter current. If

the change in VCE, of Q1 can be made equal to Vi then the output voltage will remain constant.

Since VCBI =VCEI. We can assume that if Vi dropped across R3, then the output voltage will
remain constant.
The function of a voltage regulator is to provide a stable dc voltage to electronic circuits
and capable of providing substantial output current. Since the element or component used for
voltage regulation is connected across the load, it is called as shunt voltage regulator. There are
two types of shunt voltage regulator
1. Zener diode shunt voltage regulator
2. Transistor shunt voltage regulator

A zener diode is connected in parallel with the load; a resistance (R 2) is connected in series with

the zener to limit the current in the circuit. Hence the resistance is called as series current

limiting resistor. The output voltage (V o) is taken across the load resistance (R 1). Since the

reverse bias characteristics of sener diode are used in voltage regulation, the input voltage is

always maintained greater than zener voltage (Vz).

3.3.1 Line Regulation
Line regulation is a measure of the ability of the power supply to maintain its output voltage
given changes in the input line voltage. Line regulation is expressed as percent of change in the
output voltage relative to the change in the input line voltage.
Line regulation = (output voltage at High line input voltage - output voltage at low line input voltage)
x100 (High line input voltage - low line input voltage)

3.3.2 Load Regulation

Load regulation is a measure of the ability of an output channel to remain constant given
changes in the load. Depending on the control mode enabled on the output channel, the load
regulation specification can be expressed in one of two ways In constant voltage mode,
variations in the load result in changes in the output current. This variation is expressed as a
percentage of range per amp of output load and is synonymous with a series resistance. In
constant voltage mode, the load regulation specification defines how close the series resistance
of the output is to 0 ohms - the series resistance of an ideal voltage source.
In constant current mode, variations in the load result in changes to the current through
the load. This variation is expressed as a percentage of range change in current per volt of
change in the output voltage and is synonymous with a resistance in parallel with the output
channel terminals. In constant current mode, the load regulation specification defines how close
the output shunt resistance
is to infinity—the parallel resistance of an ideal current. In fact, when load regulation is
specified in constant current mode, parallel resistance is expressed as 1/load regulation.
Load Regulation can be defined as a percentage by the equation:

Where
• FullLoad (EfL) is the load that draws the greatest current (is the lowest specified load
resistance - never short circuit)
• MinimumLoad (EnL) is the load that draws the least current (is the highest specified load
resistance - possibly open circuit for some types of linear supplies, usually limited by pass
transistor minimum bias levels) NominalLoad (EfL) is the typical specified operating load
3.4 Model Graph

VL VL

Vin = Constant RL= Constant

RL Vin

Fig 3.1 LOAD REGULATION Fig 3.2 LINE REGULATION

3.5 Circuit Diagram - Shunt Voltage Regulator

3.6 Characteristics
Series Voltage Regulator
This series voltage regulator is suitable only for low output voltages because of the
following reasons
1. With the increase in room temperature, the values of Vbe and Vzener tend to decrease.
 Thus the output voltage cannot be maintained a constant. This will further
increase the transistor base emitter voltage and thus the load.
2. There is no option to change the output voltage in the circuit.
3. Due to small amplification process provided by only one transistor(BC147),
the circuit cannot provide good regulation at high currents.
4. The power dissipation of a pass transistor is large because it is equal to
VccIc and almost all variation appears at Vce and the load current is
approximately equal to collector current. Thus for heavy load currents pass
transistor has to dissipate a lot of power and, therefore, circuit becomes hot. So
some heat sink is required.
Shunt Voltage Regulator
The series resistor causes a huge amount of power loss.The circuit may have
problems regarding over voltage mishaps.
3.7 Procedure
Connect the circuit as per the circuit diagram.
1.
For load regulation characteristics, keep the input voltage constant, find VL

for different values of RL. Plot the graph by taking RL in the axis and VL in the

Y axis.
2.
For line regulation characteristics, keep RL constant and for different values of
input Vin

find VL. Plot the graph by taking Vin in x axis and VL in the y axis
3.8 Tabulation
Shunt Regulator
3.8.a Line regulation RL =-------------------------------------(Ω)
S. No Vi Vo (V)
(V)
1.

2.

3.
 4.

5.

6.

7.

8.

9.

10.
10
11
12

Vi =-------------(V)
3.8.b .Load regulation

S.No RL(Ω) Vo(V)

1.

2.

3.

4.

5.

6.

3.9 Result
 The shunt voltage regulator were designed and constructed and the
characteristics were plotted.
1. The regulated output voltage was found to be--------------V
.2. Line regulation was found to be ---------------------
3. Load regulation was found to be ----------------------
7.12 Prelab Question
1. What are the three basic elements inside a standard voltage regulator?
2. What device is used as a control element? Why?
3. What are the performance measures of the regulator?
4. What is line regulation and Load regulation What is the efficiency of series voltage
regulator
5. List the difference between Series and Shunt Voltage Regulator
7.13 Post Lab Question
1. With reference to the above circuit (fig 7.4), What will be the output voltage if
reference voltage was short circuited?
2. The 7812 regulator IC provides .
a) 5V
b) -5V
c) 12V
d) -12V
3. what will happen if potential divider was open circuited
4. The transistor shunt regulator shown in figure has a regulated output voltage of
10 volts, when input varies from 20 volts to 30 volts. The relevant parameters
for the zener diode and the transistor are: VZ = 9.5 volts, VBE = 0.3 votls, β = 99.
Neglect the current throught RB. Then the maximum power dissipated in the

zener diode (PZ) and the transistor (PT) are

 4.Design & Analysis of CE-BJT amplifier

4.1 OBJECTIVE
1. To design a single stage CE amplifier Circuit for the given specifications.
2. To perform the transient analysis and determine the phase difference between input
and output signals.
3. To measure the voltage gain of the amplifier over a range of frequencies and plot the
frequency response curve.
4. To determine the values of lower and upper 3-dB frequencies and 3-dB bandwidth.

4.2 HARDWARE REQUIRED

S. No Apparatus Type Range Quantity

1 Transistor BC147 1
68KΩ, 47K, 22KΩ, 2.2kΩ,
2 Resistors 4.7KΩ, 10% 1
tolerance, ½ watt

3 Capacitor 6µF,0.33µF,100µF 1

4 Bread board & wires 1

4.3. THEORY
Amplifier is an electronic circuit that is used to raise the strength of a weak signal. The
process of raising the strength of a weak signal is known as amplification. One importance
requirement during amplification is that only the magnitude of the signal should increase
and there should be no change in signal shape. The transistor is used for amplification.
When a transistor is used as an amplifier, the first step is to choose a proper configuration in
which device is to be used. Then the transistor is biased to get the desired Q-point. The
signal is applied to the amplifier input and gain is achieved.
4.3.1 CE amplifier operation
Consider a CE amplifier circuit as shown in fig. 4.1

Rc
R1
CC

Vout
Vcc Rs Cc
Q1

Rf

V in
R2

Re
Ce

Fig 4.1 CE Amplifier

When the capacitors are regarded as ac short circuits, it is seen that the circuit input
terminals are the transistor base and emitter, and the output terminals are the collector and
the emitter. So, the emitter terminal is common to both input and output, and the circuit
configuration is termed Common Emitter (CE).
4.3.2 Transient Analysis
Transient analysis is nothing but taking voltages and current at different instants. It is
seen that there is a 180o phase shift between the input and output waveforms. This can be
understood by considering the effect of a positive going input signal. When V S increases in
a positive direction, it increases the transistor VBE. The increase in VBE raises the level of
IC, thereby increasing the drop across Rc, and thus reducing the level of the V C. The
changing level of VC is capacitor-coupled to the circuit output to produce the ac output
voltage, VO. As VS increases in a positive direction, VO goes in a negative direction.
Similarly, When VS changes in a negative direction, the resultant decrease in V BE reduces
the IC level, thereby reducing VRC, and producing a positive going output.
4.3.3 CE amplifier circuit elements and their functions
(i) Biasing circuit: The resistances R1, R2 and RE form the biasing and stabilization
circuit. The biasing circuit must establish a proper operating point, otherwise a part
 of the negative half-cycle of the signal may be cut-off in the output.
(ii) Input capacitor, C1: An electrolyte capacitor C1 is used to couple the signal to the
base of the transistor. If it is not used, the signal source resistance, R s will come
across R2 and thus change the bias. C1 allows only ac signal to flow but isolates the
signal source from R2.
(iii) Emitter bypass capacitor, Ce: An Emitter bypass capacitor, Ce is used parallel with
RE to provide low reactance path to the amplified ac signal. If it is not used, then
amplified ac signal flowing through RE will cause a voltage drop across it, thereby
reducing the output voltage.
(iv) Coupling capacitor, Cc: The coupling capacitor, Cc couples one stage of
amplification to the next stage. If it is not used, the bias conditions of the next stage
will be drastically changed due to the shunting effect of R C. This is because RC will
come in parallel with the upper resistance R 1 of the biasing network of the next
stage, thereby altering the biasing conditions of the latter. In short, the coupling
capacitor C2 isolates the dc of one stage from the next stage, but allows the passage
of ac signal.
4.3.4 CE amplifier circuit currents
(i) Base current
iB = IB +ib
Where IB = dc base current when no signal is applied
ib = ac base when as signal is applied
and iB = total base current
(ii) Collector current
iC = IC+ic
Where IC = zero signal collector current
ic = ac collector current when ac signal is applied
and iC = total collector current

(iii) Emitter Current

iE = IE + ie
 Where IE = Zero signal emitter current
Ie = ac emitter current when ac signal is applied
and iE = total emitter current
It is useful to keep in mind that
IE = IB + IC
and ie = ib +ic
Also, IE  IC and ie ic
4.3.5 CE amplifier frequency response
The voltage gain of an amplifier varies with signal frequency. It is because
reactance’s of the capacitors in the circuit changes with signal frequency and hence affects
the output voltage. The curve between voltage gain and signal frequency of an amplifier is
known a frequency response.
It is clear that the voltage gain drops off at low (< f L) and high (> fH) frequencies
whereas it is uniform over mid-frequency range (fL to fH).
(i) At low frequencies (< fL), the reactance of coupling capacitor is quite high and hence
very small part of signal will pass from amplifier stage to the load. Moreover, C E cannot
shunt the RE effectively because of its large reactance at low frequencies. These two
factors cause a falling of voltage gain at low frequencies.
(ii) At high frequencies (> fH), the reactance of Cc is very small and it behaves as a short
circuit. This increases the loading effect of amplifier stage and serves to reduce the voltage
gain. Moreover, at high frequency, capacitive reactance of base-emitters junction is low
which increases the base current. These reduce the current amplification factor. Due to
these two reasons, the voltage gain drops off at high frequency.
(iii) At mid frequencies (fL to fH), the voltage gain of the amplifier is constant. The effect
of coupling capacitor Cc in this frequency range is such as to maintain a uniform voltage
gain. Thus, as the frequency increases in this range, reactance of C C decreases which tend
to increase the gain.
4.3.6 CE amplifier analysis
The first step in AC analysis of CE amplifier circuit is to draw ac equivalent circuit
by reducing all dc sources to zero and shorting all the capacitors. Fig 2.2 shows the ac
equivalent circuit.

Rs R
Q1 Q1

Rc R
R1 R2 R R
Vs Vs

Fig 4.2 Equivalent Circuit

The next step in the ac analysis is to draw h-parameter circuit by replacing the
transistor in the ac equivalent circuit with its h-parameter model. Fig. 4.3 shows the h-
parameter equivalent circuit for CE circuit.

Fig 4.3. h- Parameter Equivalent Circuit

The typical CE circuit performance is summarized below:
Device input impedance, Zb = hie
Circuit input impedance, Zi = R1|| R2|| Zb
1
ZC 
Device output impedance, hoe

Z O  RC Z C  RC
Circuit output impedance,
 h fe
AV   ( RC R L )
Circuit voltage gain, hie

h fe RC R B
Ai 
Circuit current gain, ( RC  R L )( RC  hie )

Circuit power gain, AP = AV x Ai

1.4 MODEL GRAPH

1.4.1 Transient Analysis

Fig 4.4(a) Input Voltage Waveform

Fig 4.4(b) Output Voltage Waveform

4.4.2 Frequency Response
 Fig 4.5 Frequency Response
4.5 CE AMPLIFIER CIRCUIT DESIGN

Design of CE circuit normally commences with a specification of supply voltage,

minimum voltage gain, frequency response, signal source impedance load impedance,
stability factor and the Q-point.
Selection of IC, RC and RE
h fe
AV   ( RC R L )
hie

 For satisfactory transistor operation, Ic should not be less than 500µA. A good
minimum Ic to aim for is 1mA.
 The VCE should typically be around 3v to ensure that the transistor operates linearly
and to allow a collector voltage swing of ±1v which is usually adequate for small-signal
amplifier
o Note: RC should normally be very much larger than R L, so that RL has little effect
on voltage gain.
 Select VE = 5v for good bias stability in most circumstances.
o Note: When VE>>VBE, VE will be only slightly affected by any variation in V BE (due
to temperature change or other effects)
 Once VE, VCE and Ic are selected, VRC is determined as VRC = VCC – VCE – VE
V RC V
RC  RE  E
Then, RC and RE are calculated as I C and IC

Selection of bias resistors

 As discussed in lab-1, experiment-1.1, section-1.1, selection of voltage divider
current (I2) as IC/10 gives good bias stability and reasonably high input resistance. The bias
resistors are calculated as
VB V  VB
R2  R1  CC
I 2 and I2

Selecting R2 = 10RE gives I2 = IC/10 the precise level of I2 can be calculated as I2 = VB/R2
and this can be used in the equation for R1.
Selection of bypass capacitor, CE
Basically the capacitor values are calculated at the lowest signal frequency that the
circuit is required to amplify. This frequency is the lower cut-off frequency, fL.
hie
X CE 
1  h fe
Choose at fL for CE calculation to give the smallest value for the bypass
capacitor.
Selection of coupling capacitors, C1 and C2
The coupling capacitors C1 and C2 should have a negligible effect on the frequency
response of the circuit. To minimize the effects of C 1 and C2, the reactance of each
coupling capacitor is selected to be approximately equal to one-tenth of the impedance in
series with it at the lowest operating frequency of the circuit (fL).
Z i  rs
X C1 
10
Z O  RL
X C3 
10
Usually, RL>> ZO and often Zi>> rS, so that ZO and rS can be omitted in the above
equations.
4.6 DESIGN PROBLEM

(i) Design a single stage CE transistor amplifier using BC107 transistor with Vcc =
15V, VCEQ = 5V, VE = 3V, RL = 47K and fL = 100Hz.
(ii) Determine Zi, ZO, AV, Ai and AP for the CE circuit designed in problem (i).
Procedure
Given VCC = 15V, VCE = 5V, VE = 3V, RL = 47k and fL = 100Hz.
The data sheet of BC107 transistor shows:
hie = 3k and hFE=190
Selection of RC
RC<< RL so that RL will have little effect on the circuit voltage gain.
R L 47 K
RC    4 .7 K 
Select 10 10 (Standard value)
Selection of RE
VE VE
RE  
IE IC

VRC VCC  VCE  VE (15  5  3)V

IC     1.4mA
Where RC RC 4.7K

3V
RE   2.14KΩ
 1.4mA (use a standard 2.2 k)
Selection of R1 and R2
Selection of voltage divider current I 2 as IC/10 gives good bias stability and reasonably
high input resistance
Selecting R2 = 10 RE gives I2 = IC/10

i.e., R2  10  2 K  22 K (standard value)

I C 1.4mA
I2    140μ4
and 10 10
VCC  VB 15  (VBE  VE ) 15  (0.7  5)
R1     66.43KΩ
 I2 140μ4 140μ4 (use standard 68k)
Selection of C1 and C2
The coupling capacitors C1 and C2 should have negligible effect on the frequency response
of the circuit. So, the reactance of each coupling capacitor is selected to be approximately
equal to 1/10th of the impedance in series with it at the lowest operating frequency for the
circuit.
 Z i R 1 R 2 h ie 68K 22K 3K
X C1     254
10 10 10 
1 1
C1    6μF
2ππL X C1 2  π  100  254
(Standard value 10µF)

R L 47K 1 1
X C2    4.7KΩ C2    0.34μF
10 10  2ππL X C2 2  π  100  4.7K

(use a standard 0.47μf)

C1 = CCin Input Side
C2 = CC in Output Side
Selection of CE
h ie 3KΩ
X CE    15.71
1  h fe 1  190

1 1
CE    101.36μ0
 2ππL X CE 2  π  100  15.71 (use a standard 100μf)
Neglect source resistance RS and feedback resistor Rf

Calculation of Zi, ZO, AV, Ai and AP

Input impedance, Zi = R1||R2|| hie = 68k||22k||3K
= 2.54KΩ
Output impedance, ZO = RC = 4.7k
h fe 190
AV   (R C R L )   (4.7K 47K )  270.61
Voltage gain, h ie 3K

h fe R C R B 190  4.7K  (68K 22K )

Ai    37.23
Current gain, (R C  R L )(R C  h ie ) (4.7K  47K)(4.7K  3K)

Power gain, AP = AV x Ai = 270.61 X 37.23 = 10K

4.6.1 Design Constraints
If IC> VCC/2(RE+RC) and VCE< VCC/2 is not satisfied, then thermal runaway will
occur.
 15V

4.7KΩ
68KΩ

0.33µF
6µF

47KΩ
22KΩ
100mV,
1KHz 100µF
2.2KΩ

Fig 4.6 CE -amplifier designed Circuit

4.7 PROCEDURE
Transient and Frequency response curve measurements
a. Feed 100mV (peak-to-peak) sinusoidal signal at 1KHz frequency as the input signal (Vs)
to the CE circuit.Observe the input and output voltages simultaneously on a CRO. Note
down the amplitude, frequency and phase difference between the two voltages in the table.
b. In the above assembled circuit, keep the magnitude of the source same, ie., 100mv and
vary the frequency from 50 Hz to 10 MHz and measure the voltage gain of the amplifier
at each frequency across RL. Take atleast 10 readings and tabulate the reading in Table. Plot
on a semi log graph sheet the frequency response (voltage gain Vs frequency) curve using
the
above measurements.
c.From the plot, determine the values of (a) Mid band voltage gain, Av(mid), (b) Lower
Cut-off frequency, (c) upper cut-off frequency and (d) Bandwidth.
4.8 TABULATION
A.Transient Analysis
Amplitude(volts
parameters
) Frequency(Hz) Phase difference
Input signal

Output signal

B.Frequency Response Vi = 100mV

Gain in db
Frequency Output Voltage Gain (Vo/Vi) Av = 20
(Vo) log(Vo/Vi)
4.9 PRELAB QUESTIONS
1. Define Biasing.
2. What are the different h-parameters of CE amplifier?
3. What are the main applications of CE amplifier?
4.10 POSTLAB QUESTIONS
1. How do coupling capacitors C1 and C2 affect the frequency response? Why?
2. What is the effect on the amplifier performance of omitting RE?
3. What is the effect on input impedance of removing bypass capacitor CE?
4.11 RESULT
a. The phase difference between the input and output voltage waveform is ________
b. The Mid-band voltage gain =
c. The Lower cutoff frequency =
d. The Upper cutoff frequency =
e. Bandwidth =
 6.Design and analysis of CS-MOSFET amplifier

6.1 Objective
To simulate drain and transfer characteristics of Metal Oxide Semiconductor FET
(MOSFET) using and to find its drain resistance and transconductance.

6.2. Theory
In a MOSFET, current flows from the drain terminal to the source terminal through
a semiconductor channel. The resistance of the channel, and therefore its ability to conduct
current, is controlled by a voltage applied to a third terminal denoted as the gate.MOSFETs
can be either an n-channel type or a p-channel type. In a n-channel MOSFET a positive
voltage is applied to the drain terminal for operation while in a p-channel MOSFET a
negative voltage is applied to the drain terminal for operation. An n-channel and p-channel
type MOSFET may be one of two modes; enhancement mode or depletion mode. The
enhancement mode MOSFET is normally “off” (in cutoff and conducting no current) when
no voltage is applied to the gate and is “on” (in saturation and conducting current) when a
voltage greater than the gate-to-source threshold is applied to the gate. The depletion mode
MOSFET is normally “on” (in saturation and conducting current) when no voltage is
applied to the gate and is “off” (in cutoff and not conducting current) when a voltage more
negative than the gate-to-source threshold is applied to the gate.
 Fig 6.1 Symbol of MOSFET

6.2.1 Transfer Characteristics

In most MOSFET applications, an input signal is the gate voltage V G and the output

is the drain current ID. The ability of MOSFET to amplify the signal is given by the

output/input ratio: the transconductance, gm = dID/dVGS with VDS constant

6.2.2 Drain Characteristics

MOSFET operates in three operation mode, Cut-off when V GS<Vt, Linear mode when

VGS>Vth and VDS< ( VGS– Vth ) and Saturation when VGS>Vth and VDS≥( VGS– Vth). Pinch off

occurs when VDS= VSat= VGS– Vt. The drain resistance, Rd= dVDS/dID with VGS constant

6.3 Circuit Diagram

M1
Vds
20Vdc
IR F 150
Vgs
10Vdc

Fig 6.2 MOSFET Characteristics Circuit diagram.

6.4 Model Graph
6.4.1 Transfer Characteristics: 6.4.2 Drain Characteristics:
 Fig 6.3 Characteristics of MOSFET

6.5 PSPICE Simulation for MOSFET Characteristics

Fig 6.4 PSPICE Simulation

Fig 6.5. MOSFET – Transfer characteristics

 Fig 6.6 MOSFET – Drain characteristics

6.6 Handling Precautions

1. When handling power MOSFETs, the man should be ground. And Power MOS FETs,
should be handled by the package, not by the leads.
2. When handling or installing Power MOSFETs into circuits, use metal plates that it
grounded on Work Stations.
3. When testing Power MOSFETs, Test Circuit (Curve tracer, etc.) should be grounded.
4. When using soldering irons, soldering irons should be grounded. (It’s better to use
battery operated soldering irons.)
5. When shipping in circuit boards, they should be placed in antistatic bags, unless the
gate and the source are connected by resistors or inductors.
6.7 Procedure
6.7.1 Transfer characteristics
1. Connect the MOSFET as per the circuit diagram
2. Keep the VGS =10 V, VDS =20 V
3. Set in the DC sweep primary and secondary values.
4. Place the voltage probe at source of MOSFET and simulate the circuit.
6.7.2 Drain characteristics
1. Connect the MOSFET as per the circuit diagram
2. Keep the VGS =10 V, VDS =20 V
3. Set in the DC sweep primary and secondary values.
4. Place the voltage probe at source of MOSFET and simulate the circuit
6.8 Result
The drain Characteristics and Transfer Characteristics of MOSFET was simulated using
PSPICE, the transconductance = _________ and drain resistance = -------------- was found.
6.9 Pre-Lab Questions
1. With the E-MOSFET, when gate input voltage is zero, what is the drain current?
2. Compare the input impedance of MOSFET with that of BJT and FET.
3. In MOSFET devices the N-channel type is better the P-channel type. How?
6.10 Post lab Questions
1. In a MOSFET, the polarity of the inversion layer is the same as that of
_____________
2. What is the difference between depletion MOSFET and JFET?
3. What are the three regions of operation in MOSFET?
 7.NEGATIVE FEEDBACK OP-AMP CIRCUITS
7.1 OBJECTIVE
1. To design the negative feedback op-amp circuits and explain the operation of each:
a. Inverting amplifier
b. Voltage follower

7.2 HARDWARE REQUIRED

S.No Equipment/Component name Specifications/Value Quantity

1 IC 741 Refer data sheet in 1

appendix

2 Cathode Ray Oscilloscope (0 – 20MHz) 1 1

3 Resistors 1.5K Ω, 15 K Ω 2

4 Dual Regulated power supply (0 -30V), 1A 1

5 Function Generator (0-2) MHz 1

7.3 THEORY
An op-amp is a high gain, direct coupled differential linear amplifier choose response characteristics
are externally controlled by negative feedback from the output to input, op-amp has very high input
impedance, typically a few mega ohms and low output impedance, less than 100Ω.
Op-amps can perform mathematical operations like summation integration,
differentiation, logarithm, anti-logarithm, etc., and hence the name operational amplifier op-amps are also
used as video and audio amplifiers, oscillators and so on, in communication electronics, in instrumentation
and control, in medical electronics, etc.

7.3.1 Circuit symbol and op-amp terminals

The circuit schematic of an op-amp is a triangle as shown below in Fig. 1-1 op-amp has two input
terminals. The minus input, marked (-) is the inverting input. A signal applied to the minus terminal will be
shifted in phase 180o at the output. The plus input, marked (+) is the non-inverting input. A signal applied to
the plus terminal will appear in the same phase at the output as at the input. +VCC denotes the positive and
negative power supplies. Most op-amps operate with a wide range of supply voltages. A dual power supply
of +15V is quite common in practical op-amp circuits. The use of the positive and negative supply voltages
allows the output of the op-amp to swing in both positive and negative directions.

Fig.7.1 op-amp circuit symbol and pin diagram

7.3.2 Op amp internal block diagram
Commercial integrated circuit OP-amps usually consists of your cascaded blocks as shown in Fig 1-2.

Fig.7.2 Op-amp Internal Block Diagram

The first two stages are cascaded difference amplifier used to provide high gain. The third stage is a buffer
and the last stage is the output driver. The buffer is usually an emitter follower, whose input impedance is
very high, so that it prevents loading of the high gain stage. The output stage is designed to provide low
output impedance. The buffer stage along with the output stage also acts as a level shifter so that output
voltage is zero for zero inputs.

In this laboratory experiment, Students will learn several basic ways in which an op-amp can be
connected using negative feedback to stabilize the gain and improve the frequency response. The extremely
high open-loop gain of an op-amp creates an unstable situation because a small noise voltage on the input
can be amplified to a point where the amplifier in driven out of its linear region. Also unwanted oscillations
can occur. In addition, the open-loop gain parameter of an op-amp can vary greatly from one device to the
next. Negative feedback takes a portion of output and applies it back out of phase with the input, creating an
effective reduction in gain. This closed-loop gain is usually much less than the open-loop gain and
independent of it.
7.3.3 Closed – loop voltage gain, ACL
The closed-loop voltage gain is the voltage gain of an op-amp with external feedback. The amplifier
configuration consists of the op-amp and an external negative feedback circuit that connects the output to the
inverting input. The closed loop voltage gain is determined by the external component values and can be
precisely controlled by them.
7.3.4 Non-inverting amplifier
An op-amp connected in a closed-loop configuration as a non-inverting amplifier with a controlled amount
of voltage gain is shown in Fig 1-3.

Fig.7.3 Non-inverting amplifier configuration of op-amp

The input signal is applied to the noninverting (+) input. The output is applied back to the inverting (-) input
through the feedback circuit (closed loop) formed by the input resistor R 1 and the feedback resistor Rf. This
creates negative feedback loop. Resistors R 1 and Rf form a voltage-divider circuit, which reduces V O and
connects the reduced voltage Vf to the inverting input. The feedback is expressed as:

Vf=
( R1
)
V
R 1+ R f 0
The difference of the input voltage Vin and the feedback voltage Vf is the differential input of the op-amp.
This differential voltage is amplified by the gain of the op-amp and produces an output voltage expressed as

Rf
V 0=(1+ )V ¿
R1
The closed-loop gain of the non-inverting amplifier is, thus
Rf
ACL (NI) =(1+ )
R1
An expression for the input impedance of a non-inverting amplifier can be written as

Z ¿ ( ¿ ) =(1+ A OL β )Z ¿
Where AOL = open-loop voltage gain of op-amp
Zin = internal input impedance of op-amp (without feedback)

= attenuation of the feedback circuit =

Vf
=
R1
(
V 0 R1 + Rf )
Above equation shows that the input impedance of the non-inverting amplifier configuration with negative
feedback is much greater than the internal output impedance of the op-amp itself.
The output impedance of a non-inverting amplifier can be written as

Z ZO
O (¿)=¿ ¿
1+ A OL β
This equation shows that the output impedance of non-inverting amplifier is much less than the internal
output impedance, Zo of the op-amp.
7.3.5 Voltage follower
The voltage follower configuration is a special case of the non-inverting amplifier, where all the
output voltage is feedback to the inverting input by straight connection, as shown in Fig.7.4

Fig.7.4 Voltage follower configuration of op-amp

The straight feedback connection has a voltage gain of unity (which means there is no gain).
ACL (VF) = 1

The most important features of the voltage follower configuration are very high input impedance and very
low output impedance. These features make it a nearly ideal buffer amplifier for interfacing high-impedance
sources and low-impedance loads.

Z ¿(VF )=(1+ A OL )Z ¿
Z Z O
O (VF )=¿ ¿
1+ AOL
The voltage follower input impedance is greater for a given A OL and Zin than for the non-inverting amplifier.
Also, its output impedance is much smaller.
7.3.6. Inverting amplifier
An op-amp connected as an inverting amplifier with a controlled amount of voltage gain is shown in
Fig. 7.5

Fig.7.5 Inverting amplifier

The input signal is applied through a series input resistor R 1 to the inverting input. Also, the output is fed
back through Rf to the same input. The non-inverting input is grounded. An expression for the output voltage
of the inverting amplifier is written as R f
−Rf
VO = V¿
R1
The –ve sign indicates inversion. The closed-loop gain of the inverting amplifier is, thus R f
Rf
ACL(I) =
R1
The input & output impedances of an inverting amplifier are
Zin(I) = R1

ZO
ZO (I )=
1+ A OL β
The output impedance of both the non-inverting and inverting amplifier configurations is very low; in fact, it
is almost zero in practical cases. Because of this near zero output impedance, any load impedance connected
to the op-amp output can vary greatly and not change the output voltage at all.
7.4 PRE LAB QUESTIONS

1. A non-inverting amplifier has R1 of 2KΩ & Rf of 200KΩ. Determine Vf and β

(Feedback voltage and feedback fraction), if VO = 5V.

2. An inverting amplifier with gain of 1 has different input voltages: 1.2 V, 3.2 V and 4.2 V. Find
the output voltage?
3. Give an expression for output voltage of non-inverting summing amplifier with five input
 voltage.
7.5 EXPERIMENT
(1) Inverting amplifier
1.1 Design an inverting amplifier for the gain of 10. Let R1=1.5k Ω. Assemble the circuit.
1.2 Feed sinusoidal input of amplitude 1V and frequency 1KHz.
1.3 Observe the input and output voltages on a CRO. Tabulate the readings.

(2) Voltage follower

2.1 Assemble a voltage follower circuit.
2.2 Feed sinusoidal input of amplitude 1V and frequency 1KHz.
2.3 Observe the input and output voltages on a CRO. Tabulate the readings.

Observation:
op-amp Input signal Output signal Voltage gain Phase
shift
configuration /
circuit Amplitude Frequency Amplitude Frequency Designed Observed
value value

Voltage follower

Inverting
amplifier

7.6. POST LAB QUESTIONS

1. What is the relationship, if any, between the polarity of the output and input voltages
in your experimental op-amp?
2. Find the value of Rf that will produce closed-loop gain of 300 in the given amplifier.

3. Determine the output voltage for the open loop inverting amplifier if the
input voltage is 20mV DC.
Result:
 8.OP-AMP CIRCUITS-I
(BASIC COMPARATOR)

8.1 OBJECTIVE:
Design the comparator for a frequency of 1 KHz sine wave with 5 Vpp at the non-inverting input
terminal and apply 1V dc voltage as reference voltage at the inverting terminal of IC741.
8.2 HARDWARE REQUIRED
S.No Equipment/Component name Specifications/Value Quantity
1 IC 741 Refer data sheet 1
2 Cathode Ray Oscilloscope (0 – 20MHz) 1
3 Resistors 10 kΩ 2
56 K Ω 1
4 Dual Regulated power supply (0 -30V), 1A 1
5 Function Generator (0-2) MHz 1

8.3 THEORY

8.3.1 Comparator
A Comparator is a non-linear signal processor. It is an open loop mode application of op-amp
operated in saturation mode. Comparator compares a signal voltage at one input with a reference voltage at
the other input. Here the op-amp is operated in open loop mode and hence the output is ±V sat. It is basically
classified as inverting and non-inverting comparator. In a non-inverting comparator V in is given to +ve
terminal and Vref to –ve terminal. When Vin < Vref, the output is –Vsat and when Vin > Vref, the output is +Vsat. In
an inverting comparator input is given to the inverting terminal and reference voltage is given to the non-
inverting terminal. The output of the inverting comparator is the inverse of the output of non-inverting
comparator. The comparator can be used as a zero-crossing detector, window detector, time marker generator
and phase meter.
 .
Fig. 8.1 Comparator

Fig. 8.2 Comparator Input & Output Waveforms

8.4 PRE LAB QUESTION

1. Draw the transfer characteristics of open loop op-amp.
2. How many basic input parameters are required for a comparator?
3. Why this circuit is called a non-inverting comparator?
8.5 EXPERIMENT
8.5.1 Comparator
1. Connect the components as shown in the circuit diagram.
2. Switch ON the power supply.
3. Apply 1 KHz sine wave with 5 Vpp at the non-inverting input terminal of IC741 using a function
generator.
4. Apply 1V dc voltage as reference voltage at the inverting terminal of IC741.
5. Connect the channel-1 of CRO at the input terminals and channel-2 of CRO at the output terminals.
6. Observe the input sinusoidal signal at channel-1 and the corresponding output square wave at channel-
2 of CRO. Note down their amplitude and time period.
7. Overlap both the input and output waves and note down voltages at positions on sine wave where the
output changes its state. These voltages denote the Reference voltage.
8. Plot the output square wave corresponding to the sine input with Vref = 1V.
Observation:
Theoretical Reference voltage (From the circuit)
Practical Reference voltage (From output waveform)

8.6 POST LAB QUESTION

1. Draw the circuit diagram of a non-inverting and inverting comparator.
2. What is the role of resistors R1 and R2 in the comparator circuit?
3. List the applications of comparator.

Result:
 9.OP-AMP CIRCUITS-II
(INTEGRATOR AND DIFFERENTIATOR)

9.1 OBJECTIVE
1. Design an integrator for a frequency of 500 Hz, given R=1KΩ, C=0.1 µF and Rf = 1MΩ. Conduct the
experiment and plot integrated output waveforms for various input waveforms and analyse.
2. Design a differentiator for a frequency of 500 Hz, given R=1KΩ, and C=0.1µf and R 1 = 470Ω.
Conduct the experiment and plot differentiated output waveforms for various input waveforms and
analyse.

9.2 HARDWARE REQUIRED

S.No Equipment/Component name Specifications/Value Quantity

1 IC 741 Refer data sheet in 1
appendix
2 Cathode Ray Oscilloscope (0 – 20MHz) 1
3 Resistors 1K Ω 1

1M Ω 1

10 K Ω 1

470 Ω 1
4 Capacitors 0.1µf 2

5 Dual Regulated power supply (0 -30V), 1A 1

6 Function Generator (0-2) MHz 1

9.3 THEORY
In this laboratory experiment, several basic ways are learned in which an op-amp can be connected
using negative feedback to stabilize the gain and increase the frequency response. The extremely high open-
loop gain of an op-amp creates an unstable situation because a small noise voltage on the input can be
amplified to a point where the amplifier in driven out of its linear region. Also unwanted oscillations can
occur. In addition, the open-loop gain parameter of an op-amp can vary greatly from one device to the next.
Negative feedback takes a portion of output and applies it back out of phase with the input, creating an
effective reduction in gain. This closed-loop gain is usually much less than the open-loop gain and
independent of it.

9.3.1 Integrator

An op-amp integrator simulates mathematical integration which is basically a summing process that
determines the total area under the curve of a function ie., the integrator does integration of the input voltage
waveform. Here the input element is resistor and the feedback element is capacitor as shown in Fig.9.1.

Fig.9.1 Basic op-amp integrator

The output voltage is given by
t
−1
V 0= ∫ ❑V s dt +V c (t=0)
RC 0
Where VC (t=0) is the initial voltage of the capacitor. For proper integration, R C has to be much greater than
the time period of the input signal.

It can be seen that the gain of the integrator decreases with the increasing frequency so, the integrator
circuit does not have any high frequency problem unlike a differentiator circuit. However, at low frequencies
such as at dc, the gain becomes infinite. Hence the op-amp saturates (ie., the capacitor is fully charged and it
behaves like an open circuit). A practical integrator circuit is shown in Fig. 2.2.

Fig. 9.2 Practical op-amp integrator

9.3.2 Differentiator
An op-amp differentiator simulates mathematical differentiation, which is a process of determining
the instantaneous rate of change of a function. Differentiator performs the reverse of integration function.
The output waveform is derivative of the input waveform. Here, the input element is a capacitor and the
feedback element is a resistor. An ideal differentiation is shown in Fig. 9.3.

Fig.9.3 Basic op-amp differentiator

The output voltage is given by
dV s
VO = RC
dt
For proper differentiation, RC has to be much smaller than the time period of the input signal. It can be seen
that at high frequencies a differentiator may become unstable and break into oscillation. Also, the input
impedance of the differentiator decreases with increase in frequency, thereby making the circuit sensitive to
high frequency noise. So, in order to limit the gain of the differentiator at high frequencies, the input
capacitor is connected in series with a resistance R 1 and hence avoiding high frequency noise and stability
problems. A practical differentiator circuit is shown in Fig.9.4.

Fig9.4 Practical op-amp differentiator

9.4 PRE LAB QUESTIONS

1. Op-amp is used mostly as an integrator than a differentiator. Why?
2. Why open-loop op-amp configurations are not used in linear applications?

9.5 EXPERIMENT
(1) Integrator
1.1 Assemble an integrator circuit with R=1K and C=0.1µf. Connect Rf of value 1M across the capacitor.
1.2 Feed +1V, 500Hz square wave input.
1.3 Observe the input and output voltages on a CRO.
1.4 Determine the gain of the circuit and tabulate the readings in table. Model waveform is shown.
1.5 Plot the input and output voltages on the same scale on a linear graph sheet.

(2) Differentiator
2.1 Assemble a differentiator circuit with R=1K and C=0.1µf. Connect a resistor R1 of value 470 between
the source and the capacitor.
2.2 Feed +1V, 500Hz square wave input.
2.3 Observe the input and output voltages on a CRO.
2.4 Determine the gain of the circuit and tabulate the readings. Model waveform is shown below.
2.5 Plot the input and output voltages on the same scale on a linear graph sheet.

Observation:
op-amp Input signal Output signal
configuration / Amplitude Frequency Amplitude Frequency
circuit

Integrator
Differentiator
9.6. POST LAB QUESTIONS
1. What are the limitations of an ordinary op-amp differentiator & How that will be eliminated in
practical differentiator?
2. What are the limitations of an ordinary op-amp integrator & How that will be eliminated in practical
differentiator?
3. List out the applications of integrator and differentiator op-amp?
Result:
 10.ANALYSIS & DESIGN OF RC OSCILLATORS

10.1 OBJECTIVE
Design a RC phase shift oscillator using operational amplifier .

10.2 HARDWARE REQUIRED

S. Equipment/Component Specifications/ Quanti

No name Value ty
Refer data sheet in
1 IC 741 1
appendix
2 Cathode Ray Oscilloscope (0 – 20MHz) 1

1.5K Ω 4
15K Ω 2
1M Ω 1
4.7K Ω 1
3 Resistors
18K Ω 1
10K Ω 1

0.1µf 3
4 Capacitors
0.01µf 2
5 Regulated power supply 15 V 1

10.3. THEORY
RC phase shift oscillator
The feedback network consists of three identical RC sections. Each section produces a
phase shift of 60o . Therefore, the net phase shift of the feedback is 180 o the amplifier stage
introduces a phase shift of 180 o. Hence, the total phase shift between the input and output is
o
360 or 0 o. When the circuit is energized, by switching on the supply, the circuit starts
oscillating. The oscillations will be maintained if the loop gain is at least equal to unity.

Feedback fraction of the RC phase shift network is β=1/29.

 The frequency of oscillation is f0=1/2 πRC√6.
Circuit diagram

C=0.1µF, R=1.5KΩ, R1=15KΩ, RF=1MΩ pot

Design:

f0=1/2 πRC√6

Rf 29R 1

R1 ≥ 10R
Choose C =0.1µF

f0 = 500 Hz

1
R=
2 π f 0 C √6

1
R= =1.3 KΩ
2 ×3.14 × 500 ×0.1 ×10 × √ 6
−6

Choose R = 1.5KΩ
R1≥ 15KΩ (to prevent loading)
R1 = 10R = 15KΩ

Rf = 29R1=29x15KΩ=435KΩ (Use 1MΩ pot)

 Design Constraints
 The loading effect of the amplifier on the feedback network has an effect on the

frequency of oscillations and can cause the oscillator frequency to be up to 25% higher than
calculated. Then the feedback network should be driven from a high impedance output
source and fed into a low impedance load such as a common emitter transistor amplifier but
better still is to use an Operational Amplifier as it satisfies these conditions perfectly.

 The voltage gain of the Wien bridge oscillator circuit must be equal to or greater than
three “Gain = 3″ for oscillations to start.

 Due to the open-loop gain limitations of operational amplifiers, frequencies above

1MHz are unachievable without the use of special high frequency op-amps.

10.4 PRE LAB QUESTIONS

1. State Barkhausen criterion for oscillation

2. Write the formula to calculate frequency of oscillation for RC &Wien bridge oscillator

3. What are the applications of oscillators?

4. In RC phase shift oscillator using, the value of capacitor is 0.01µF and the frequency of
oscillation is 35 KHz the voltage gain of the amplifier should be 30. Calculate the value of
R of RC feedback Network.

6.3 EXPERIMENT

1. Connect all the components as shown in the circuit diagram.

2. Observe the output sinusoidal signal in CRO and note down the amplitude and
time period of output waveform.
3. Plot the output wave form.
Observation :

Oscillator Amplitude(V) Time period (ms) Frequency (Hz) Frequency (Hz)

(Design) (Observed)
RC Phase Shift
10.5 POST LAB QUESTIONS

1. What are the merits and demerits of RC phase shift oscillator?

2. Why do we need three RC networks for a phase shift oscillator?
3. Explain the main difference between an amplifier and an oscillator.
4. In as RC phase shift oscillator, if R1 = R2 = R3 = 200kΩ and C1 = C2 = C3 = 100pF.
Find the frequency of oscillation.

Result:
 DESIGN OF ASTABLE MULTIVIBRATOR USING IC555 TIMER
11.1 OBJECTIVE
Design an Astable multivibrator for a frequency of 1KHz with 60% duty cycle using 555
timer.

11.2 HARDWARE REQUIRED

S.No Equipment/Component name Specifications/Value Quantity

Refer data sheet in
1 IC 555 Timer 1
appendix
2 Cathode Ray Oscilloscope (0 – 20MHz) 1
330 Ω 1
15K Ω 1
3 Resistors 10 M Ω 1
6.8 K Ω 1
1K Ω 1
0.1µf 1
4 Capacitors
1µf 1
5 Regulated power supply (1 -5V), 1A 1

11.3 THEORY
The 555 Timer is a monolithic timing circuit that can produce accurate and highly stable
time delays or oscillations. The timer basically operates in one of the two modes-monostable
(one-shot) multivibrator or as an astable (free-running) multivibrator. In the monostable mode, it
can produce accurate time delays from microseconds to hours. In the astable mode, it can produce
rectangular waves with a variable duty cycle. Frequently, the 555 is used in astable mode to
generate a continuous series of pulses, it can also be used as a one-shot or monostable circuit.
 Fig. 11.1
Functional block diagram of IC 555
In astable or free running mode, the 555 can operate as an oscillator. The uses include
LED and lamp flashers, logic clocks, security alarms, pulse generation, tone generation, pulse
position modulation, etc. In the bistable mode, the 555 can operate as a flip-flop and is used to
make bounce-free latched switches, etc.

Fig 11.2 Pin diagram of IC555

11.3.1 ASTABLE MULTIVIBRATOR
An astable multivibrator is a wave-generating circuit in which neither of the output levels
is stable. The output keeps on switching between the two unstable states and is a periodic,
rectangular waveform. The circuit is therefore known as an ‘astable multivibrator’. Also, no
external trigger is required to change the state of the output, hence it is also called ‘free-running
multivibrator’. The time for which the output remains in one particular state is determined by the
two resistors and a capacitor externally connected to the 555 timer.

If the output is high initially, capacitor C starts charging towards V cc through RA and RB.
As soon as the voltage across the capacitor becomes equal to 2/3 V cc, the upper comparator
triggers the flip-flop, and the output becomes low. The capacitor now starts discharging through
RB and transistor Q1. When the voltage across the capacitor becomes 1/3 V cc, the output of the
lower comparator triggers the flip-flop, and the output becomes high. The cycle then repeats. The
output voltage and capacitor voltage waveforms are shown in Fig. 8.6.

Fig. 11.3 Astable Multivibrator using IC 555

 Fig 11.4 Input and Output waveform of Astable Multivibrator
Design
In output voltage waveform the time during which the capacitor charges from 1/3 V cc to 2/3 Vcc is
equal to the time the output is high and is given by
ton =0.69(RA + RB)C
the time during which the capacitor discharges from 2/3 Vcc to 1/3 Vcc is equal to the time the
output is low and is given by
toff =0.69RBC
the total period of the output wave form is
T=ton+toff=0.69(RA+2RB)C
Thus the frequency of oscillation is
fo=1/T=(1.45/(RA+2RB)C)
Design Constraints

● The 555 Timer is a very versatile low cost timing IC that can produce a very accurate

timing periods with good stability of around 1%

● Duty cycle should be greater than 50% to 80%

● Single RC network connected to a single positive supply of between 4.5 and 16 volts.
● Load resistance minimum value is 1KΩ.

11.4 PRE LAB QUESTIONS

Choose the correct answer
1.A quasi-stable state is such that the output
a) does not change at all
b) Changes unpredictably
c) Changes after a predetermined period of time
d) Changes just after a very short duration of time.
2. A monostable multivibrator is also called a ‘one-shot multivibrator’ because
a) Each time a trigger pulse is applied, the circuit produces a single pulse.
b) The circuit has to be triggered only once
c) The output pulse duration is very small
d) None of the above.
3. For a 5 V circuit, if pin 4 is connected to 1 V, does the chip reset?
a) Yes
b) No
c) Cannot be determined

11.5 EXPERIMENT

1. Connect the circuit as shown in the figure with the designed values.
2. Switch on the power supply and observe the waveform.
3. Note down the amplitude and time period.
4. Plot the waveforms on a graph sheet.

Theoretical Output Practical Output

TOTAL TIME TOTAL TIME

TON TON

TOFF TOFF
Amplitude of Close to VCC Amplitude of
Square waveform. Square waveform.
Charge & discharging 2/3 VCC – 1/3 VCC Charge & discharging
of capacitor by of capacitor by
measuring Amplitude 3.3 – 1.6 = 1.7 v measuring Amplitude

Design Constraints

● The 555 Timer is a very versatile low cost timing IC that can produce a very accurate

timing periods with good stability of around 1%

● Duty cycle should be greater than 50% to 80%

● Single RC network connected to a single positive supply of between 4.5 and 16 volts.

● Load resistance minimum value is 1KΩ.

11.6 PRE LAB QUESTIONS

Choose the correct answer
1.A quasi-stable state is such that the output
a) does not change at all
b) Changes unpredictably
c) Changes after a predetermined period of time
d) Changes just after a very short duration of time.
2. A monostable multivibrator is also called a ‘one-shot multivibrator’ because
a) Each time a trigger pulse is applied, the circuit produces a single pulse.
b) The circuit has to be triggered only once
c) The output pulse duration is very small
d) None of the above.
3. For a 5 V circuit, if pin 4 is connected to 1 V, does the chip reset?
d) Yes
e) No
f) Cannot be determined

11.7 EXPERIMENT
 5. Connect the circuit as shown in the figure with the designed values.
6. Switch on the power supply and observe the waveform.
7. Note down the amplitude and time period.
8. Plot the waveforms on a graph sheet.

Observation :

Theoretical Output Practical Output

TOTAL TIME TOTAL TIME

TON TON

TOFF TOFF

Amplitude of Close to VCC Amplitude of

Square waveform. Square waveform.
Charge & discharging 2/3 VCC – 1/3 VCC Charge & discharging
of capacitor by of capacitor by
measuring Amplitude 3.3 – 1.6 = 1.7 v measuring Amplitude

11.8 POST LAB QUESTIONS

1.Why the control voltage pin (pin 5) of 555 timers is connected to ground through a 0.01µf
capacitor?
2.Calculate the ON time, OFF time, Total time period, Duty cycle and Frequency of the output
generated by an astable multivibrator using resistors RA = 5KΩ, RB =5KΩ and capacitor C =
10µf.
3.Why the Reset pin of IC555 is normally connected to Vcc?

Result: