BSc CSIT 2nd Semester

Microprocessor
Unit 3: Instruction Cycle
Syllabus:

8085 Instruction Cycle

The time required for the completion or execution of one instruction is known as the Instruction
Cycle in Microprocessor. The instruction cycle of the 8085 microprocessor consists of four basic
steps, which are:
1. Fetch: In this step, the microprocessor fetches the instruction from the memory location
pointed to by the program counter (PC). The PC is incremented by one after the fetch
operation.
2. Decode: Once the instruction is fetched, the microprocessor decodes it to determine the
operation to be performed and the operands involved.
3. Execute: In this step, the microprocessor performs the operation specified by the instruction
on the operands.
4. Store: Finally, the result of the execution is stored in the appropriate memory location or
register.

Once the execution of an instruction is complete, the microprocessor returns to the fetch step to
fetch the next instruction to be executed. This cycle repeats until the program is complete or
interrupted.

Machine Cycles in Microprocessor

The time needed for completing one operation of accessing memory, I/O or acknowledging an
external request is termed as Machine cycle. It is comprised of T-states. One subdivision of the
operation completed in one clock period is termed as T-state. The following are the various machine
cycles of 8085 microprocessor.

1. Opcode Fetch (OF)

2. Memory Read (MR)
3. Memory Write (MW)
4. I/O Read (IOR)
5. I/O Write (IOW)
6. Interrupt Acknowledge (IA)
7. Bus Idle (BI)

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Microprocessor

T states in Microprocessor
 A portion of an operation carried out in one system clock period is called as T-state.
 It is one subdivision of the operation performed in one clock period.
 It is part of the machine cycle.
 One clock period is equal to one t state.

Timing Diagram in Microprocessor

The timing diagram in Microprocessor is a graphical representation. It is used for the
representation of the execution time taken by each instruction in a graphical format. The t states
represent the timing diagrams.

Control signals meaning in 8085 timing diagram

Signals Significance
IO/M = 1 (read/write operation to an IO device)
̅
IO/ 𝑀 IO/M = 0 (read/write operation to the memory))
S1 and S1 and S0 = 00 (Halt)
S0 S1 and S0 = 01 (A write operation)
S1 and S0 = 10 (A read operation)
S1 and S0 = 11 (Either opcode fetch or interrupt acknowledge)

ALE ALE = 0 (AD0-AD7 is available for data transfer)

ALE = 1 (AD0-AD7 is carrying the lower eight bits of the address)
̅̅̅̅
𝑅𝐷 This is an active low signal and simply tells us whether it is a read operation when
it is low.
̅̅̅̅̅
𝑊𝑅 This is an active low signal and simply tells us whether it is a write operation when
it is low.

Machine Cycle of 8085 Microprocessor:

1. Opcode Fetch (OF)
2. Memory Read (MR)
3. Memory Write (MW)
4. I/O Read (IOR)

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Microprocessor
5. I/O Write (IOW)
6. Interrupt Acknowledge (IA)
7. Bus Idle (BI)
Control signals of different machine cycle ….

Sr. Machine cycle ̅

IO/𝑴 S1S0 Other control
No. signals
1 Opcode fetch machine cycle 0 11 ̅̅̅̅ = 0
𝑅𝐷
Memory read machine cycle / Operand ̅̅̅̅
2 0 10 𝑅𝐷 = 0
Fetch machine cycle
3 Memory write machine cycle 0 01 ̅̅̅̅̅
𝑊𝑅 = 0
4 IO read machine cycle 1 10 ̅̅̅̅
𝑅𝐷 = 0
5 IO write machine cycle 1 01 ̅̅̅̅̅
𝑊𝑅 = 0
6 Interrupt acknowledge machine cycle 1 11 ̅̅̅̅̅̅̅ = 0
𝐼𝑁𝑇𝐴
̅̅̅̅̅̅̅
𝐼𝑁𝑇𝐴 = ̅̅̅̅
𝑅𝐷 =
7 Bus Idle machine cycle 0 00 ̅̅̅̅̅
𝑊𝑅 = 1

op-code fetch

The opcode fetch machine cycle involves the fetching of the opcode of the instruction to be
executed and the decoding process of that opcode. Usually, it consists of four T states.

1st T state
 During the first T state, the address of the location where the opcode is stored is loaded on the
address bus. In 8085, this address is stored in a 16-bit register called the program counter.
Higher eight bits of the address are loaded on A8-A15, and the lower eight bits of the address
are loaded into AD0-AD7 for de-multiplexing.

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Microprocessor
 Also, the ALE signal becomes active in the first T state to indicate that the data on AD0-AD7
pins are the lower address bits.
 IO/𝑀̅ signal becomes low at the beginning of the first T state to indicate that the opcode will
be fetched from memory (reading from memory).
 At the beginning of the first T state, signals S1 and S0 take the value 1 and 1 respectively to
indicate that it is an opcode fetch machine cycle.

2nd T state
 By the beginning of the 2nd T state or the end of 1st T state, the ALE signal goes low. By this
time, 8085 expects that the lower address bits are latched, and AD0-AD7 is free to be used as
a data bus.
 At the beginning of the second T state, ̅̅̅̅
𝑅𝐷 goes low, indicating that the read process has
started. Meanwhile, higher address bits are present in A8-A15, and lower address bits are
expected to be latched.
 As 𝑅𝐷 ̅̅̅̅ goes low, the opcode (eight bits) is loaded into the data bus AD0-AD7 . In above case
41H is loaded into the data bus AD0-AD7.

3rd T state

 The opcode loaded on the data bus is present there until the middle of the third T state.
 ̅̅̅̅ goes up, indicating that the read operation is completed and ‘the
During the third T state, 𝑅𝐷
opcode is fetched’ and placed in the instruction register.
 The data on the data bus and the higher address bits on A8-A15 exist until the middle of this T
state.

4th T state
 During the fourth T state, the fetched opcode is decoded. There is nothing much to observe in
the timing diagram during this process.
 During the fourth T state, after decoding the opcode, the microprocessor decides if it needs
fifth and sixth T states, or should proceed to the next machine cycle.
 PC is incremented by 1 here or in the sixth T state if the OFMC is extended upto sixth T state.

5th and 6th T state

 In case of one-byte instructions that operate on 16-bit data and some other instructions,
OFMC may extend up to six T states. During the fifth and sixth T states, execution of these
instructions takes place. Since these instructions are simple, they get executed in the OFMC
itself. Examples of such instructions are DCX, INX, PCHL, SPHL, CALL, RSTN and
conditional RET.

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Microprocessor

Memory read
Contents from a memory location are read during the memory read machine cycle (MRMC). This
cycle is also known as the operand fetch machine cycle. But there are cases when MRMC is not used
for operand fetch but for reading data at given memory location. This machine cycle spans over three
T states.

There are certain machine cycles where Program Counter is incremented and some, where it is
not incremented.

 If the address is loaded into the address bus from the program counter, then PC in incremented
at the end of that machine cycle otherwise PC is not incremented.
 For reading the operands, memory read machine cycles are executed. In such machine cycles,
PC is incremented as the address is loaded from the PC.
 But during the execution of instruction MOV A, M the last machine cycle is the memory read
machine cycle in which the address is loaded on the address bus from the HL register. Hence,
the PC is not incremented in this case

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1st T state
 Higher address bits loaded into A8-A15.
 Lower address bits loaded into AD0-AD7.
 ALE signal goes high in the beginning to indicate that AD0-AD7 contains lower address bits.
 IO/𝑀̅ goes low since it is a memory operation.
 S1 and S0 become 1 and 0 respectively, indicating Memory Read Machine Cycle.
 ALE goes low by the end of the first T state. Lower address bits are expected to be latched by
this time.

2nd and 3rd T states

 ̅̅̅̅
𝑅𝐷 goes low, indicating the initiation of the read operation.
 Data is read from the memory location and is loaded into the data bus AD0-AD7. The data is
loaded into the data bus at the beginning of the 2nd T state and exists until the end of the third
T state.
 ̅̅̅̅ goes high, indicating the end of the read operation.
By the end of the third T state, 𝑅𝐷

Memory write
Contents are written to a memory location/stack during a memory write machine cycle
(MWMC). This machine cycle spans over three T states. Each of these T states are explained here
along with the timing diagram. PC is not incremented in this machine cycle. This is very similar to
MRMC, except a few differences.

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Microprocessor

1st T state
 Higher address bits loaded into A8-A15.
 Lower address bits loaded into AD0-AD7.
 ALE signal goes high in the beginning to indicate that AD0-AD7 contains lower address bits.
 IO/𝑀 ̅̅̅goes low since it is a memory operation.
 S1 and S0 become 0 and 1 respectively, indicating MWMC.
 ALE goes low by the end of the first T state. Lower address bits are expected to be latched by
this time.

2nd and 3rd T states

 𝑊𝑅
̅̅̅̅̅ goes low, indicating the initiation of the write operation.
 Data to be written is loaded on the data bus at the beginning of the second T state and exists
until the end of the third T state when the data is transferred from the data bus to the memory
location.
 By the end of the third T state, ̅̅̅̅̅
𝑊𝑅 goes high, indicating the end of the write operation. Thus,
MWMC comes to an end.

IO read machine cycle

Contents from an IO device are read during IO read machine cycle (IORMC). This machine
cycle spans three T states and is similar to MRMC except for the IO/𝑀 ̅ signal. The destination of this
read operation is the accumulator. The Program Counter is not incremented here. IO/𝑀 ̅ goes high
instead of going low, indicating that the microprocessor is talking to an IO device.

There is an important point to be noted here. In 8085, IO devices have an 8-bit address. But we
have AD0-AD7 and A8-A15 for addresses. So, whenever the microprocessor is exchanging data with
and IO device (during IORMC and IOWMC), the same 8 bits are loaded into both the upper address

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Microprocessor
bus and the lower address bus. During interfacing of an IO device, we can use any one of the upper
and lower address buses according to our convenience.

1st T state
 8-bit address is loaded into A8-A15.
 The same 8-bit address is loaded into AD0-AD7.
 ALE signal goes high in the beginning to indicate that AD0-AD7 contains address bits and not
data bits.
 IO/𝑀 ̅ goes high since the microprocessor is dealing with an IO device.
 S1 and S0 become 1 and 0 respectively, indicating a ‘read’ machine cycle.
 ALE goes low by the end of the first T state. Address bits in AD0-AD7 are expected to be
latched by this time.

2nd and 3rd T states

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 ̅̅̅̅ goes low, indicating the initiation of the read operation.
𝑅𝐷
 Data is read and is loaded on the data bus (AD0-D7) at the beginning of the second T state and
exists until the end of the third T state.
 In the third T state, the data is transferred from the data bus to the accumulator.
 By the end of the third T state, ̅̅̅̅
𝑅𝐷 goes high, indicating the end of the read operation.

IO write machine cycle

Contents are written to an IO device during IO write machine cycle (IOWMC). This machine
cycle spans three T states and is similar to MWMC except for the IO/𝑀 ̅̅̅signal. IO/𝑀
̅̅̅goes high
instead of going low, indicating that the microprocessor is talking to an IO device. The contents of the
accumulator are transferred to the data bus and written to an output device in this cycle.

1st T state
 8-bit address is loaded into A8-A15.
 The same 8-bit address is loaded into AD0-AD7.
 ALE signal goes high in the beginning to indicate that AD0-AD7 contains address bits.
 IO/𝑀 ̅̅̅ goes high since the microprocessor is dealing with an IO device.

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 S1 and S0 become 0 and 1 respectively, indicating a write machine cycle.
 ALE goes low by the end of the first T state. Address bits in AD0-AD7 are expected to be
latched by this time.

2nd and 3rd T states

 ̅̅̅̅̅
𝑊𝑅 goes low, indicating the initiation of the write operation.
 Data to be written is loaded on the data bus at the beginning of the second T state and exists
until the end of the third T state.
 In the third T state, the data is transferred from the data bus to the IO device.
 By the end of the third T state, 𝑊𝑅̅̅̅̅̅ goes high, indicating the end of the write operation.

Interrupt acknowledge machine cycle

An external IO device issues an interrupt signal (INTR), to tell the microprocessor that it wants
a certain task done. When a microprocessor receives such a signal, it responds by making
the ̅̅̅̅̅̅̅̅
𝐼𝑁𝑇𝐴 signal (interrupt acknowledgement signal) low for some time to tell the device that it has
received the request and will take the necessary actions. Responding to an external device
with ̅̅̅̅̅̅̅̅
𝐼𝑁𝑇𝐴 signal after receiving an interrupt request – this whole process is carried out in a machine
cycle called “Interrupt acknowledge machine cycle.”

To interrupt the 8085 microprocessor, we usually execute one of the two instructions – RST
or CALL.

The RST instruction has only one interrupt acknowledge cycle of 6 T-states. Whereas the
CALL instruction has three interrupt acknowledge cycles. RST is a one-byte instruction and CALL is
a three-byte instruction that’s why they are one and three T states respectively..

The addresses for the Interrupt Subroutine (ISR) will be provided by the instructions themselves.
Hence, the PC won’t be incremented.

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Microprocessor

1st T state
 The first T state of all the machine cycles involving data transfer is for the de-multiplexing of
AD0-AD7. The same is the case here. A8-A15 contains higher address bits. ALE signal goes
high. AD0-AD7 contains address for that interval of time.
 The difference here is that the 𝐼𝑁𝑇𝐴
̅̅̅̅̅̅̅̅signal is high. RD and WR both are low. IO/M = 1 and
S1S0 = 1

2nd and 3rd T state

 These are also similar to the 2nd and 3rd T state of OFMC.
 ALE goes low. AD0-AD7 is ready for data transfer and now contains the data until the middle
of the third T state.

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Microprocessor
4th, 5th, and 6th T state
 During the last three T states, instruction is decoded, and according to the decoded
instructions, further machine cycles are executed to complete that instruction.
 The decoded instruction is either CALL instruction or RST instruction. The execution of
decoded instruction is completed in the subsequent machine cycles.

Timing diagram of RST instruction

 Notice that the instruction cycle of RST instruction consists of three machine cycles.
 The first one is the Interrupt Acknowledge Machine Cycle explained above. At the end of the
IAMC, the instruction is decoded.
 Since it is RST instruction, two more machine cycles, both of them being MWMC, are
executed.
 In the second and third machine cycles, the contents of the program counter are written on the
stack and after the execution of RST instruction, program execution jumps to the interrupt
service routine.

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Microprocessor
Timing diagram of CALL instruction

 The instruction cycle of CALL instruction consists of five machine cycles.

 The first three T states are the Interrupt Acknowledge Machine Cycle . At the end of the
IAMC, the instruction is decoded.
 In the second and third machine cycles, the device which caused the interruption gives the
address of the location where the program location is supposed to jump after getting the
interrupt signal.
 The fourth and fifth machine cycles are MWMC. During these machine cycles, the
microprocessor saves the contents of the program counter into stack since it will be executing
the interrupt service routine and will have to return to that location again.

Bus idle machine cycle

There are some situations when no data transfer takes place. But it does not mean that the
microprocessor is idle during that time as there might be some operations going on in the CPU. It is
the data/address bus that is idle. Such a machine cycle is named a Bus Idle machine cycle (BIMC).

One such example where this situation occurs is the DAD instruction. So, let us have a look at the
timing diagram of DAD instruction and understand more about BIMC.

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Example :
DAD Rp
Here, DAD is a mnemonic, which stands for Double ADd and also rp stands for any one of the
register pairs BC, DE, or HL

In this instruction HL register pair works as Accumulator. Because the 16-bit content of rp will
be added with HL register pair content and sum thus produced will be stored back on to HL again.

Timing diagram of DAD instruction

The DAD instruction adds the 16-bit contents of a specified register pair with the 16-bit
contents of the HL pair and stores the result in the HL pair. So, the first thing is to read the opcode for
the DAD instruction, which is achieved in the OFMC. Since the operands (values to be added) are
stored in the register pairs and microprocessor does not need to read any values from memory using
the buses. It just needs to add the values and store the result. For this task, the microprocessor takes
another six T states, which are a part of Bus Idle MC.

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1st Machine cycle – Opcode Fetch MC

 The first machine cycle is the opcode fetch machine cycle. It takes 4 T states to get executed.

2nd Machine cycle – Bus Idle MC

 The second machine cycle of DAD instruction is BIMC.
 Notice that ̅̅̅̅ 𝑊𝑅 , and ̅̅̅̅̅̅̅
𝑅𝐷, ̅̅̅̅̅ 𝐼𝑁𝑇𝐴 are inactive during BIMC.
 IO/𝑀 = S1 = S0 = 0 signifying that it is a Bus Idle Machine Cycle.
̅
 Since no data transfer takes place, data present in the address bus and data bus is unspecified.
 ALE signal is low for the entire six T states.
 The addition operation is carried out in the CPU and is not represented here on the timing
diagram.

Timing Diagram of MOV, MVI, IN, OUT, LDA, STA

MOV instruction

MOV B, C

Given instruction copy the contents of the source register into the destination register and the contents
of the source register are not altered. Here, B is the destination register and C is the source register
whose contents need to be transferred to the destination register.

Opcode: MOV

Operand: B and C

2000: MOV B, C

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In Opcode fetch ( t1-t4 T states):

 00 – lower bit of address where the opcode is stored, i.e., 00.

 20 – higher bit of address where the opcode is stored, i.e., 20.
 ALE – provides signal for multiplexed address and data bus. Only in t1 is it used as an address
bus to fetch a lower bit of address otherwise it will be used as the data bus.
 RD (low active) – signal is 1 in t1 & t4 as no data is read by the microprocessor. Signal is 0 in
t2 & t3 because here the data is read by a microprocessor.
 WR (low active) – signal is 1 throughout, no data is written by a microprocessor.
 IO/M (low active) – signal is 1 throughout because the operation is performing on memory.
 S0 and S1 – both are 1 in case of opcode fetching.

MOV B, C

Suppose B register content is DBH, H register content is 40H, and L register content is 50H. Let
us say location 4050H has the data value 24H. When the 8085 executes this instruction, the contents
of B register will change to 24H, as shown below.

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Microprocessor

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 BSc CSIT 2nd Semester
Microprocessor
MVI Instruction

MVI instruction stores the immediately provided 8-bit data into the specified location, which
can be either a register or a memory location. Suppose we have instruction

MVI A, 45H

This is a 2-byte instruction. One byte for the opcode, second byte for the operand.

So, the first machine cycle will be OFMC, during which the microprocessor will read the opcode.
During the second machine cycle, the microprocessor will read the operand, which is the 8-bit
number 45H. So, the second machine cycle will be MRMC. You can refer to the timing diagram of
the MVI instruction above.

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IN instruction

The I/O read cycle is executed by the processor to read a data byte from I/O port or from
peripheral, which is I/O mapped in the system. The 8-bit port address is placed both in the lower and
higher order address bus. The processor takes three T-states to execute this machine cycle.

Example:

IN 05H

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OUT Instruction
The I/O write cycle is executed by the processor to write a data byte to I/O port or to a peripheral,
which is I/O mapped in the system. The processor takes three T-states to execute this machine cycle.

Example:

OUT 05H

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LDA Instruction

LDA is a mnemonic that stands for LoaD. It load Accumulator with the contents from memory. In
this instruction Accumulator will get initialized with 8-bit content from the 16-bit memory address as
indicated in the instruction as a 16. Example:

LDA 4050H

Address Mnemonic Opcode

2008 LDA 4050H 3A

2009 50

200A 40

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The initial content of memory address 4050H is ABH. Initially Accumulator content is CDH.

As after execution A will be initialized with value ABH. Memory location 4050H will still remain
with the content ABH. The results of execution of this instruction is as below –

Before After

(4050) ABH ABH

A CDH ABH

STA instruction

Example :
STA 526AH
 STA means Store Accumulator -The contents of the accumulator is stored in the specified
address (526A).
 The opcode of the STA instruction is said to be 32H. It is fetched from the memory 41FFH
(see fig). - OF machine cycle
 Then the lower order memory address is read (6A). - Memory Read Machine Cycle
 Read the higher order memory address (52).- Memory Read Machine Cycle
 The combination of both the addresses are considered and the content from accumulator is
written in 526A. - Memory Write Machine Cycle
 Assume the memory address for the instruction and let the content of accumulator is C7H. So,
C7H from accumulator is now stored in 526A.

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Microprocessor

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Microprocessor

Interfacing:
A microprocessor has to be interfaced with various peripherals to perform various functions. Let's
discuss about the Interfacing techniques in detail.
 We know that a microprocessor is the CPU of a computer.
 A microprocessor can perform some operation on a data and give the output. But to perform the
operation we need an input to enter the data and an output to display the results of the operation.

Interfacing Types
There are two types of interfacing in context of the 8085 processor.
(a) Memory Interfacing.
(b) I/O Interfacing.

Memory Interfacing:
While executing an instruction, there is a necessity for the microprocessor to access memory
frequently for reading various instruction codes and data stored in the memory. The interfacing circuit
aids in accessing the memory.

Memory requires some signals to read from and write to registers. Similarly the microprocessor
transmits some signals for reading or writing a data.

The interfacing process involves matching the memory requirements with the microprocessor
signals. The interfacing circuit therefore should be designed in such a way that it matches the memory
signal requirements with the signals of the microprocessor.

Basic concepts of Memory Interfacing:

The programs and data that are executed by the microprocessor have to be stored in
ROM/EPROM and RAM, which are basically semiconductor memory chips.

Microprocessor need to access memory quite frequently to read instructions and data stored in
memory; the interface circuit enables that access.

Fig: 8085 interfacing with memory Chips

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Microprocessor

The interface process involves designing a circuit that will match the memory requirements with
the microprocessor signal. Memory has certain signal requirements to read from and write into
memory. Similarly Microprocessor initiates the set of signals when it wants to read from and write
into memory.

 8085 has 16 address lines (A0 - A15), hence a maximum of 64 KB (= 216 bytes) of memory
locations can be interfaced with it.
 The memory address space of the 8085 takes values from 0000H to FFFFH.
 The 8085 initiates set of signals such as IO/M, RD’ and WR’ when it wants to read from and
write into memory.
 Similarly, each memory chip has signals such as CE or CS (chip enable or chip select), OE or
RD’ (output enable or read) and WE or WR’ (write enable or write) associated with it.

Generation of Control Signals for Memory:

When the 8085 wants to read from and write into memory, it activates IO/M, RD and WR
signals as shown. Status of IO/M, RD’ and WR’ signals during memory read and write operations

IO/M’ RD’ WR’ Operation

0 0 1 8085 reads data from

0 1 0 8085 writes data into
memory
Using IO/M , RD and WR signals, two control signals MEMR (memory read) and MEMW (memory
write) are generated. Fig. below shows the circuit used to generate these signals.

 8085 places 16-bit address on address bus and with this address only one register should be
selected (only 11 low order address lines are required).

 Remaining 8085 address lines (A15-A11) should be decoded to generate chip select.

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 8085 provides two signal-IO/M’ and RD’– to indicate that is memory read operation MEMR’.
(Similarly signal-IO/M’ and WR’– indicates memory write operation MEMW’).

Primary Function of memory interfacing is that the microprocessor should be able to read from and
write into a given register of a memory chip:

 Select the Chip

 Identify the register
 Enable the appropriate buffer. .

I/O Interfacing:
We know that keyboard and Displays are used as communication channel with outside world. So
it is necessary that we interface keyboard and displays with the microprocessor. This is called I/O
interfacing. In this type of interfacing we use latches and buffers for interfacing the keyboards and
displays with the microprocessor.

----------------------------------------------End Of Unit-3-------------------------------------------

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Microprocessor
Assignment:

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