BSc CSIT 2nd Semester

Microprocessor
Unit 2: Basic Architecture
Syllabus:

8085 Microprocessor:
8085 is an 8-bit microprocessor as it operates on 8 bits at a time and is created with N-
MOS technology. This microprocessor exhibits some unique characteristics and this is the reason
it still holds popularity among the microprocessors.

Architecture and its Operations:

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Microprocessor
The architecture of 8085 microprocessor provides the idea about what are the operations to
be executed and how these are performed.

It can perform operations that are given below:

 Operates on and stores 8-bit data.
 It executes arithmetic and logic operations.
 8085 also sequences the instructions to be executed.
 Stores data temporarily.

However, in order to perform all such operations, the processor needs a control unit,
arithmetic logic unit, registers, buses etc.

8085 Microprocessor Architecture consists of various functional blocks as listed below :

 Registers
 Arithmetic and Logic Unit
 Instruction decoder and machine cycle encoder
 Address buffer
 Address/Data buffer
 Incrementer / Decrementer Address Latch
 Interrupt control
 Serial I/O control
 Timing and control circuitry.

Registers:
It has eight addressable 8-bit registers : A, B, C, D, E, H, L, F, and two 16-bit registers PC and
SP. These registers can be classified as:
1. General Purpose Registers
2. Temporary Registers :
a. Temporary data register
b. W and Z registers
3. Special Purpose Registers :
a) Accumulator
b) Flag registers
c) Instruction register
4. Sixteen bit Registers :
a) Program Counter (PC)
b) Stack Pointer (SP)

1.General Purpose Registers:

B, C, D, E, H, and L are 8-bit general purpose registers can be used as a separate 8-bit
registers or as 16-bit register pairs, BC, DE, and HL. When used in register pair mode, the high
order byte resides in the first register (i.e. in B when BC is used as a register pair) and the low
order byte in the second (i.e. in C when BC is used as a register pair).

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Microprocessor
HL pair also functions as a data pointer or memory pointer. H & L can be used as a data
pointer which holds memory address. To store and read data from these registers bus access is
not required, it is an internal operation. Thus it provides an efficient way to store intermediate
results and use them when required.

2.Temporary Registers:
(a) Temporary Data Register :
It is an 8-bit register that holds the operand and provides it to the ALU for program
execution. AS ALU has two inputs. One input is supplied by the accumulator and other
from temporary data register. Also, the immediate results are stored by the ALU in this
register.
The programmer cannot access this temporary data register. However, it is
internally used for execution of most of the arithmetic and logical instructions.

(b) W and Z registers :

W and Z registers are temporary registers. These registers are used to hold 8-bit data
during execution of some instructions. These registers are not available for programmer,
since 8085 Microprocessor Architecture uses them internally. 8085A places the data into
it for a brief period.

Use of W and Z registers:

XCHG instruction exchanges the contents of H with D and L with E, At the time of
exchange W and Z registers are used for temporary storage of data.

3.Special Purpose Registers:

(a) Register A (Accumulator) :
It is a tri-state eight bit register. It is extensively used in arithmetic, logic, load, and
store operations, as well as in, input/output (I/O) Most of the times the result of
arithmetic and logical operations is stored in the register A. Hence it is also identified
as accumulator.

(b) Flag Register :

It is an 3-bit register, in which five of the bits carry significant information in the
form of flags : S (Sign flag), Z (Zero flag), AC (Auxiliary carry flag), P (Parity flag), and
CY (carry flag); as shown in Fig. 1.2.

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Microprocessor
S-Sign flag : After the execution of arithmetic or logical operations, if bit D7 of the result
is 1, the sign flag is set. In a given byte if D7 is 1, the number will be viewed as negative
number. If D7 is 0, the number will be considered as positive number.

Z-Zero flag : The zero flag sets if the result of operation in ALU is zero and flag resets if
result is non zero. The zero flag is also set if a certain register content becomes zero
following an increment or decrement operation of that register.

AC-Auxiliary Carry flag : This flag is set if there is an overflow out of bit 3 i.e. carry
from lower nibble to higher nibble (D3 bit to D4 bit). This flag is used for BCD operations
and it is not available for the programmer.

P-Parity flag : Parity is defined by the number of ones present in the accumulator. After
an arithmetic or logical operation if the result has an even number of ones, i.e. even
parity, the flag is set. If the parity is odd, flag is reset.

CY-Carry flag : Carry is generated when performing n bit operations and the result is
more than n bits, then this flag becomes set i.e. 1, otherwise, it becomes reset i.e. 0. This
flag is set if there is an overflow out of bit 7.

c) Instruction Register :
In a typical processor operation, the processor first fetches the opcode of instruction from
memory (i.e. it places an address on the address bus and memory responds by placing the data
stored at the specified address on the data bus). The CPU stores this opcode in a register called
the instruction register. This opcode is further sent to the instruction decoder to select one of the
256 alternatives.

4.Sixteen Bit Registers:

a) Program counter (PC) :
Program is a sequence of instructions. As mentioned earlier, microprocessor fetches
these instructions from the memory and executes them. The program counter is a special
purpose register which, at a given time, stores the address of the next instruction to be
fetched. Program Counter acts as a pointer to the next instruction. How processor
increments program counter depends on the nature of the instruction; for one byte
instruction it increments program counter by one, for two byte instruction it increments

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Microprocessor
program counter by two and for three byte .instruction it increments program counter by
three such that program counter always points to the address of the next instruction.

In case of JUMP and CALL instructions, address followed by JUMP and CALL
instructions is placed in the program counter. The processor then fetches the next
instruction from the new address specified by JUMP or CALL instruction.

In conditional JUMP and conditional CALL instructions, if the condition is not satisfied,
the processor increments program counter by three so that it points the instruction
followed by conditional JUMP or CALL instruction; otherwise processor fetches the next
instruction from the new address specified by JUMP or CALL instruction.

b) Stack Pointer (SP) :

The stack pointer is 16-bit register. It used to point into memory. The memory, this
register points to a special area called the stack. The stack is an area of memory used to
hold data that will be retrieved soon. The stack is usually accessed in a Last In First Out
(LIFO) fashion.

Arithmetic Logic Unit (ALU):

The 8085’s ALU performs arithmetic and logical functions on eight bit variables. The
arithmetic unit performs bitwise fundamental arithmetic operations such as addition and
subtraction. The logic unit performs logical operations such as complement, AND, OR and EX-
OR, as well as rotate and clear. The ALU also looks after the branching decisions.

Instruction decoder and machine cycle encoder

In the 8085 microprocessor, the instruction decoder is responsible for decoding the
machine language instructions fetched from memory and generating the appropriate control
signals to execute the instructions. The instruction decoder decodes the opcode (operation code)
of each instruction to determine the specific operation to be performed.

The machine cycle encoder, on the other hand, is responsible for generating the timing and
control signals required to carry out the instruction execution. It takes the decoded instruction
from the instruction decoder and generates a series of control signals that control the internal
operation of the microprocessor.

The 8085 microprocessor follows a basic machine cycle of fetching an instruction, decoding the
instruction, executing the instruction, and optionally performing memory read/write operations.
The machine cycle encoder determines the type of machine cycle based on the decoded.

The basic steps involved in the execution of an instruction in the 8085 microprocessor are as
follows:

 Instruction Fetch: The microprocessor fetches the opcode of the instruction from
memory. This is done in the first machine cycle, called the opcode fetch cycle.

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Microprocessor
 Instruction Decode: The instruction decoder decodes the fetched opcode to determine
the specific operation to be performed. It generates the necessary control signals based on
the decoded instruction.
 Operand Fetch: If the instruction requires data from memory or registers, the operands
are fetched in this cycle. This is typically done in the second machine cycle.
 Execution: The instruction is executed during this cycle. The ALU (Arithmetic Logic
Unit) performs the necessary arithmetic or logical operations based on the decoded
instruction.
 Memory Write: If the instruction writes data back to memory, the result is stored in the
specified memory location during this cycle. The data is written back in the third machine
cycle.
 Interrupt Acknowledge: If an interrupt occurs during the execution of an instruction, the
interrupt is acknowledged and appropriate actions are taken. This may involve saving the
current state of the processor and transferring control to the interrupt service routine.

The machine cycle encoder generates the control signals to coordinate these steps and
ensure the proper execution of instructions. It generates signals such as Memory Read,
Memory Write, I/O Read, I/O Write, and control signals for the ALU operations.

Incrementer/Decrementer Address Latch:

Incrementer/decrementer address latch is 16-bit register which is responsible for
modifying the memory address during certain operations. This component is utilized to
increment or decrement the address stored in the program counter (PC) register or other address
registers.

In the 8085 microprocessor, the incrementer/decrementer address latch is commonly associated

with the program counter (PC). The PC register holds the address of the next instruction to be
fetched from memory during program execution. The incrementer/decrementer latch assists in
modifying the PC value to move to the next instruction in the program or to branch to a different
address.

When an instruction is fetched, the program counter is automatically incremented by the

microprocessor. However, there are instructions that require the PC value to be modified
explicitly, such as branching instructions (e.g., JMP, CALL) or conditional jumps (e.g., JZ, JC).
In such cases, the incrementer/decrementer address latch comes into play.

Address Buffer:
In the 8085 microprocessor, an address buffer is a component that acts as an interface
between the microprocessor and the external memory or input/output (I/O) devices. Its main
function is to amplify and buffer the address signals generated by the microprocessor before they
are sent to the external devices.

The Address bus is used to transfer the memory address of the data that needs to be read or
written. The address buffer typically consists of a set of tri-state buffers or line drivers. These

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Microprocessor
buffers receive the address signals from the microprocessor and amplify them to drive the
external devices. The tri-state feature allows the microprocessor to control the direction of the
address bus, enabling it to share the bus with multiple devices.

By using an address buffer, the 8085 microprocessor can effectively interface with external
memory and I/O devices, ensuring reliable and accurate communication between the
microprocessor and the external components.
The address buffer in the 8085 microprocessor serves the following purposes:
Signal Amplification: The address buffer amplifies the weak address signals generated by the
microprocessor so that they can drive the larger capacitive loads of the external memory or I/O
devices. This ensures that the address signals reach the external devices with sufficient strength
and integrity.
Signal Isolation: The address buffer isolates the microprocessor from the external devices,
preventing any backflow of signals that could interfere with the internal operation of the
microprocessor. It ensures that the microprocessor's internal circuitry is not affected by the
loading and noise from the external devices.
Multiple Device Support: The address buffer provides the capability to drive multiple devices
connected to the microprocessor's address bus.
Fan-Out Expansion: The address buffer enables the microprocessor to drive a larger number of
memory or I/O devices than it would be capable of directly. It increases the fan-out capability of
the microprocessor, allowing it to connect to multiple devices without degrading the signal
quality.

Address/Data Buffer:
Address/data buffer is used to facilitate communication between the microprocessor and
external memory devices. The buffer acts as an intermediate storage location for data and
addresses during memory operations.
The address bus is responsible for transmitting the memory address from the microprocessor
to the external memory devices, while the data bus is used for bidirectional transfer of data
between the microprocessor and memory.
The address/data buffer in the 8085 microprocessor allows the CPU to perform separate read
and write operations by providing a temporary storage location for addresses and data. When the
CPU needs to read data from or write data to a memory location, it places the address of the
desired location on the address bus and stores it in the address buffer.
Once the address is stored in the buffer, the microprocessor activates the appropriate control
signals to initiate the memory read or write operation. During a read operation, the data from the
memory is fetched and stored in the buffer. Similarly, during a write operation, the data to be
written is stored in the buffer.

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Microprocessor
The buffer acts as a temporary storage for the data until it is either transferred to the CPU or
written to the memory. The bidirectional nature of the data bus allows the buffer to handle both
read and write operations.

Interrupt Control:
Whenever a microprocessor is executing the main program and if suddenly an interrupt
occurs, the microprocessor shifts the control from the main program to process the incoming
request. After the request is completed, the control goes back to the main program. The interrupt
control block has five interrupt inputs RST 5.5, RST 6.5, RST 7.5, TRAP and INTR and one
acknowledge signal INTA as follows:

Interrupt Request (INTR) Pin: The INTR pin is an active-high input pin of the 8085
microprocessor. When an external device wants to interrupt the processor, it raises the INTR pin
to a logic high level. The INTR pin can be enabled or disabled using the interrupt enable/disable
flip-flop (IFF) in the 8085.
INTA (Interrupt Acknowledge): INTA (Interrupt Acknowledge) is a control signal used to
acknowledge an interrupt request from an external device. When an interrupt is requested, the
8085 microprocessor responds by asserting the INTA signal to indicate that it has recognized the
interrupt and is ready to process it.

Restart (RST) Instructions: The 8085 microprocessor provides three software interrupt
instructions: RST 7.5, RST 6.5, and RST 5.5.
The RST 7.5 interrupt is the highest priority, followed by RST 6.5, and then RST 5.5. When
one of these interrupts is enabled, the microprocessor checks for the corresponding interrupt
request during the execution of each instruction. If an interrupt is detected, the microprocessor
completes the current instruction, saves the Program Counter (PC) value on the stack, and jumps
to the corresponding location of the ISR. These instructions are used to generate non-maskable
interrupts and are commonly used for handling specific events. Each RST instruction has a
predefined interrupt vector associated with it.

TRAP:
It is a non-maskable interrupt (NMI) and has the highest priority among all interrupts. The
TRAP interrupt is not associated with any specific instruction. When enabled, it can be used for
critical events that require immediate attention. Similar to other interrupts, the microprocessor
saves the PC value on the stack and jumps to the location 0024H to execute the TRAP ISR.

Serial I/O Control:

The Serial I/O Control refers to the control signals and operations related to serial data
communication. The 8085 microprocessor supports serial input and output operations, allowing
it to send and receive data in a serial fashion. The Serial I/O Control involves the following
signals and operations:

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Microprocessor
1. Serial Data Input (SID) and Serial Data Output (SOD):
 SID: The Serial Data Input pin is used to receive serial data into the microprocessor.
This pin is connected to an external device or a communication interface that
provides the serial data stream.
 SOD: The Serial Data Output pin is used to send serial data from the microprocessor.
This pin is connected to an external device or a communication interface that receives
the serial data stream.
2. Serial Data Transmission:
 The microprocessor uses the SID pin for receiving incoming serial data.
 To transmit serial data, the microprocessor writes the data byte to the Serial Data
Output Register (SODR), which holds the data to be transmitted.
 The microprocessor then initiates the transmission by asserting the Serial Output
Enable (SOE) signal.
3. Serial Data Reception:
 To receive serial data, the microprocessor waits for incoming data to be available.
 The Serial Input Enable (SIE) signal is used to enable the reception of serial data.
 Once data is available, the microprocessor reads the received data from the Serial
Input Data Register (SIDR), which holds the received data byte.
4. Control Signals:
 Serial Output Enable (SOE): This control signal is asserted by the microprocessor to
enable the transmission of serial data through the SOD pin.
 Serial Input Enable (SIE): This control signal is asserted by the microprocessor to
enable the reception of serial data through the SID pin.
5. Timing and Synchronization:
 Serial data communication requires proper timing and synchronization between the
transmitting and receiving devices.
 The baud rate, which determines the data transmission speed, is typically set using
external components, such as a clock generator or a programmable timer, connected
to the microprocessor.

Timing and Control Circuitry:

The timing and control unit comes under the CPU section, and it controls the flow of data
from the CPU to other devices. It is also used to control the operations performed by the
microprocessor and the devices connected to it.

Timing refers to the precise sequencing of events and the generation of appropriate control
signals to ensure proper operation. Control circuitry is responsible for generating and managing
these timing and control signals.

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Microprocessor

Here's an overview of timing and control in the 8085 microprocessor architecture:

Clock Signals
 X1, X2 (Input): X1 and X2 are terminals to be connected to an external crystal oscillator
which drives an internal circuitry of the microprocessor. It is used to produce a suitable
clock for the operation of microprocessor.
 CLK (Output): CLK is a clock output for user, which can be used for other digital ICs.
Its frequency is same at which processor operates.

Clock Generator: The clock generator produces a regular oscillating signal with a specific
frequency, known as the system clock. The clock signal synchronizes the internal operations of
the microprocessor, ensuring that instructions and data are processed at the correct rate.
Timing and Control Signals: The timing and control circuitry generates various signals that
control the microprocessor's operation. These signals include:

 READY : This pin is used to specify whether the peripheral is able to transfer
information or not. When this pin is high, it transfers data and if this is low, the
microprocessor device needs to wait until the pin goes to a high state.
 Read (RD) and Write (WR): These signals are generated to control memory and I/O
operations. The RD signal indicates a memory or I/O read operation, while the WR signal
indicates a memory or I/O write operation.
 Address Enable (ALE): The ALE signal is generated by the microprocessor to indicate
the availability of a valid address on the address bus. It latches the lower 8 bits of the
address during a memory or I/O operation.

Status Signals:
These signals indicate the status of the microprocessor, such as the state of the interrupt
system, carry/borrow flags, zero flag, sign flag, and other condition flags.

 IO/M Signal: The IO/M signal differentiates between memory and I/O operations. When
IO/M is high, it indicates an I/O operation, and when it is low, it indicates a memory
operation.
 S0 and S1 pins : These pins are the status signals which defines the below operations and
those are:

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Microprocessor

S0 S1 Functionality
0 0 Halt
1 0 Write
0 1 Read
1 1 Fetch

DMA Signals:

 HOLD – It indicates that another device is requesting the use of the address and data bus.
Having received HOLD request the microprocessor relinquishes the use of the buses as
soon as the current machine cycle is completed. Internal processing may continue. After
the removal of the HOLD signal the processor regains the bus.

 HLDA – It is a signal which indicates that the hold request has been received after the
removal of a HOLD request, the HLDA goes low.

Reset Signals
The reset circuit provides a mechanism to initialize the microprocessor to a known state
during system power-up or after a reset signal is received. It ensures that the microprocessor
starts executing from a predefined memory location, typically the reset vector address.

 RESET IN – This pin signifies resetting the program counter to zero. Also, this pin resets
the HLDA flip-flops and IE pins. The control processing unit will be in a reset state till
RESET is not triggered.
 RESET OUT – This pin signifies that the CPU is in reset condition

The flow of an Instruction Cycle in 8085 Architecture :

1. Execution starts with Program Counter. It starts program execution with the next address
field. it fetches an instruction from the memory location pointed by Program Counter.
2. For address fetching from the memory, multiplexed address/data bus acts as an address
bus and after fetching instruction this address bus will now acts as a data bus and extract
data from the specified memory location and send this data on an 8-bit internal bus. For
multiplexed address/data bus Address Latch Enable(ALE) Pin is used. If ALE = 1
(Multiplexed bus is Address Bus otherwise it acts as Data Bus).

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Microprocessor
3. After data fetching data will go into the Instruction Register it will store data fetched
from memory and now data is ready for decoding so for this Instruction decoder register
is used.
4. After that timing and control signal circuit comes into the picture. It sends control signals
all over the microprocessor to tell the microprocessor whether the given instruction is for
READ/WRITE and whether it is for MEMORY/I-O Device activity.
5. Hence according to timing and control signal pins, logical and arithmetic operations are
performed and according to that data fetching from the different registers is done by a
microprocessor, and mathematical operation is carried out by ALU. And according to
operations Flag register changes dynamically.
6. With the help of Serial I/O data pin(SID or SOD Pins) we can send or receive
input/output to external devices .in this way execution cycle is carried out.
7. While execution is going on if there is any interrupt detected then it will stop execution
of the current process and Invoke Interrupt Service Routine (ISR) Function. Which will
stop the current execution and do execution of the current occurred interrupt after that
normal execution will be performed.

• In memory, programs are stored with their locations. For example, Facebook Messenger
is stored in phone, when it is clicked, its address will come to Program Counter. For
example, 1000 is the address of it. That address is stored in PC.
• That 1000 address will be sent from Microprocessor to Memory via address bus. The
control bus will send Read Signal (RD), because we need to get the information of
Instruction in that address.
• The instruction(data) stored in 1000 address is 1st instruction, which will be received by
up via Data Bus and that instruction is stored in Instruction Register (IR). Till now the
Fetching operation is complete. Fetching means fetching or getting data from memory to
processor.
• After fetching, the instruction will go to Decoding. Till now one instruction is finished.
As soon as one Instruction is fetched, then PC will automatically increases to fetch next
instruction. Now the address of PC becomes 1001. This is done by INR/DCR register.

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Microprocessor
• After PC, the address will go to memory. PC is 16 bit, half will go to two 8 bit
information. From this data bus will carry data. Same bus acts as address bus and data
bus.
• After fetching, Instruction Decoder will decode and give it to Timing and Control unit. It
will use Read signal (Control bus). This block, releases all the control signals. Execution
will take place in full architecture.
• Accumulator (A) is the most important register. First information is stored in A. Second
operand from General purpose register. And the result also stores in A.

Microprocessor - 8085 Pin Configuration

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Microprocessor

The pins of a 8085 microprocessor can be classified into seven groups −

1. Address bus
Address bus contains the address of the desired memory location from where the data or
instruction is to be fetched . It bus has 16 lines . However, out of 16, 8 are multiplexed with the
data bus and the leftover 8 are separately shown by pin number 21 to 28 in the pin configuration.

These are used to carry the address of data and instruction from the processor to the
memory location and is unidirectional in nature. These are denoted by A8 to A15 that represents
the 8 MSB of the memory location or input-output address.

2.Data bus
Data bus contains the data or instruction that is needed to be fetched from the memory.
AD7-AD0, it carries the least significant 8-bit address and data bus.

3.Control and status signals

These signals are used to identify the nature of operation. There are 3 control signal and 3 status
signals.
Three control signals are RD, WR & ALE.
• RD − This signal indicates that the selected IO or memory device is to be read and is
ready for accepting data available on the data bus.
• WR − This signal indicates that the data on the data bus is to be written into a selected
memory or IO location.
• ALE − ALE is an acronym for address latch enable and is pin number 30 in the
configuration. It is a positive going pulse generated when a new operation is started by
the microprocessor. When the pulse goes high, it indicates address. When the pulse goes
down it indicates data.

Three status signals are IO/M, S0 & S1.

 IO/M
This signal is used to differentiate between IO and Memory operations, i.e. when it is
high indicates IO operation and when it is low then it indicates memory operation.

 S1 & S0
The pins S0 and S1 represent the status signal at pin number 29 and 33 respectively.
These signals are used to identify the type of current operation. The table below
represents the status of the data bus under different conditions:

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Microprocessor

IO/M S1 S0 Data Bus Status

0 1 1 Opcode fetch

0 1 0 Memory read

0 0 1 Memory write

1 1 0 I/O read

1 0 1 I/O write

1 1 1 Interrupt acknowledge

0 0 0 Halt

4.Power supply
There are 2 power supply signals − VCC & VSS. VCC indicates +5v power supply and
VSS indicates ground signal.

5.Clock signals
There are 3 clock signals, i.e. X1, X2, CLK OUT.
 X1, X2 − X1 and X2 are terminals to be connected to an external crystal oscillator which
drives an internal circuitry of the microprocessor. It is used to produce a suitable clock for
the operation of microprocessor.
• CLK OUT − This signal is used as the system clock for devices connected with the
microprocessor.

6.Interrupts & externally initiated signals

Interrupts are the signals generated by external devices to request the microprocessor to
perform a task. There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR.
• INTA − It is an interrupt acknowledgment signal.
• RESET IN − This signal is used to reset the microprocessor by setting the program
counter to zero.
• RESET OUT − This signal is used to reset all the connected devices when the
microprocessor is reset.
• READY − This signal indicates that the device is ready to send or receive data. If
READY is low, then the CPU has to wait for READY to go high.
• HOLD − This signal indicates that some other device is waiting / requesting to use
address and data busses.

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Microprocessor
• HLDA (HOLD Acknowledge) − HOLD Acknowledge. This signal indicates that the
CPU has received the request made by hold and it will relinquish it in next clock cycle.

7. Serial I/O signals

There are 2 serial signals, i.e. SID and SOD and these signals are used for serial communication.
 SID (Serial I/P Data) : This input signal is used to accept serial data bit by bit from the
external device.
 SOD (Serial O/P Data) : This is an output signal which enables the transmission of serial
data bit by bit to the external device.

Addressing Modes
Every instruction of a program has to operate on a data. The method of specifying the data
to be operated by the instruction is called Addressing. and its addressing modes are the ways in
which it accesses memory or registers to retrieve or store data during processing.

The 8085 has the following 5 different types of addressing.

1. Immediate Addressing
2. Direct Addressing
3. Register Addressing
4. Register Indirect Addressing
5. Implicit Addressing

1.Immediate Addressing Mode:

 In immediate addressing mode, the data (8 / 16 bit) is specified in the instruction itself.
 The immediate addressing instructions are either 2 bytes or 3 bytes long.
 In 2 byte instruction, the first byte is OPCODE, and the second byte is the 8-bit data.
 In 3 byte instruction, the first byte is OPCODE, second and third bytes are 16-bit data.
 The instruction containing the letter “I” indicate immediate addressing mode.

Examples:
1. MVI A, A0 H : This instruction transfers immediate data (A0 H ) to A register.
2. LXI H, C200 H : This instruction transfer 16-bit immediate data C200 to HL register pair.
Lower order data(00H) to L register and high order data (C2 H) to H register.

2.Direct Addressing Mode:

 In direct addressing mode, the 16-bit address of the operand is given within the
instruction itself.
 The instruction in the direct addressing mode is 3-byte instructions. The first byte is
OPCODE, the second slower order address mode and the third is the higher-order address
mode.
 For I/O instruction that uses direct addressing mode are 2-byte as the address if I/O is one
byte.

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Microprocessor
Examples:
1. LDA C200 H : Load accumulator directly from the memory location. In this instruction,
the contents of C200 memory location are transferred to the accumulator.
2. STA C200 H : Store accumulator directly to memory location. In this instruction, the
content of the accumulator are store at memory location C200 H.

3.Register Addressing Mode:

 In register addressing mode the source and destination operands are general-purpose
registers.
 The register addressing instructions are generally of 1 byte i.e OPCODE only.
 The OPCODE specifies the operation and registers to be used to perform the operation.

Examples:
1. MOV D, B : This instruction copies the contents of register B to the D register. The
source and destination operands are both registers.
2. ADD B : This instruction adds the content of B register and A register, The data is present
in both B and A registers. The result is stored in the accumulator.
3. PCHL : This instruction will transfer the content of register pair HL to the PC ( Program
Counter)

4.Indirect Addressing Mode:

 In indirect addressing mode the instruction reference the memory through a register pair.
i.e. the memory address where the operand is located is specified by the content of a
register pair.

Examples:
1. MOV A, M : In this case, M is a memory pointer specifying the HL register pair where
the address is stored. The contents of the HL pair are used as addresses and the content of
that memory location is transferred to the accumulator.
2. LDAX B : In this case, the BC register pair is used as an address and the content of the
memory location specified by the BC register pair is copied to the accumulator.

5.Implied Addressing or Implicit Addressing Mode:

 The implied mode of addressing does not require any operand.
 The data is specified within OPCODE itself.
 Generally, the implied addressing mode instruction is a 1-byte instruction.
 The data is supposed to be present generally in the accumulator.

Examples:
1. RAL : Rotate accumulator left, it operates on the data in accumulator only. So whenever
RAL is used it is implied that the data to be operated on is available in the accumulator
only.
2. CMC : Complement carry flag.

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Microprocessor

Multiplexing and De-multiplexing of address/data bus

The Main Concern In Digital Electronics is to Reduce the space required for building the
electronic Chip. Reduction Of space means reduction of cost and building a efficient electronic
circuits.

The main reason of multiplexing address and data bus is to reduce the number of pins for address
and data and dedicate those pins for other several functions of microprocessor.

Multiplexed Address bus

The signal lines AD0 to AD7 in 8085 microprocessor used for dual purpose. They carry
address bits as well as data bits. This is called multiplexed address/data bus. This bus is used as
low order address bus and data bus. The address bus and data bus are multiplexed to reduce
number of pins in the IC package.

De-multiplexing
To avoid mixing up of address and data bits this must be de-multiplexed. de-multiplexing in
the 8085 microprocessor is the process of separating the address and data signals for efficient
transfer of information between the processor and its peripheral devices.

This can be done with the help of a latch (74LS373) i.e. Address Latch Enable (ALE).
 When ALE goes high, the latch is transparent and it enables lower order address bits (A0
to A7).
 When ALE goes low, the latch enables lower order data bits (D0 to D7)

The following diagram illustrates the process of address de-multiplexing in the 8085
microprocessor:

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Microprocessor

OR

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Microprocessor

8086 Microprocessor
 The 8086 is a 16-bit microprocessor. The term “16-bit” means that its arithmetic logic
unit, internal registers and most of its instructions are designed to work with 16-bit binary
words.
 The 8086 has a 16-bit data bus, so it can read data from or write data to memory and
ports either 16 bits or 8 bits at a time.
 The 8086 has a 20-bit address bus, so it can directly access 220 or 10,48,576 (1Mb)
memory locations. Each of the 10, 48, 576 memory locations is byte Therefore, a sixteen-
bit words are stored in two consecutive memory locations.
 The Features of 8086 Microprocessor can generate 16-bit I/O address, hence it can access
216 = 65536 I/O ports.
 The 8086 provides fourteen 16-bit registers.
 The 8086 has multiplexed address and data bus which reduces the number of pins
needed, but does slow down the transfer of data (drawback).
 The Features of 8086 Microprocessor is possible to perform bit, byte, word and block
operations in 8086. It performs the arithmetic and logical operations on bit, byte, word
and decimal numbers including multiply and divide.
 The Intel 8086 is designed to operate in two modes, namely the minimum mode and the
maximum mode. When only one 8086 CPU is to be used in a microcomputer system, the
8086 is used in the minimum mode of operation. In this mode the CPU issues the control
signals required by memory and I/O In multiprocessor (more than one processor in the
system) system 8086 operates in maximum mode. In maximum mode, control signals are
generated with the help of external bus controller (8288).
 The Intel 8086 supports multiprogramming. In multiprogramming, the code for two or
more processes is in memory at the same time and is executed in a time-multiplexed
fashion.
 An interesting feature of the 8086 is that it fetches up to six instruction bytes from
memory and queue stores them in order to speed up instruction execution.
 The 8086 Microprocessor provides powerful instruction set with the following addressing
modes : Register, immediate, direct, indirect through an index or base, indirect through
the sum of a base and an index register, relative and implied.

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Microprocessor

Architecture of 8086 Microprocessor

8086 Microprocessor is divided into two functional units, i.e., EU (Execution Unit)
and BIU (Bus Interface Unit).

EU (Execution Unit)
Execution unit gives instructions to BIU stating from where to fetch the data and
then decode and execute those instructions. Its function is to control operations on data
using the instruction decoder & ALU. EU has no direct connection with system buses as
shown in the above figure, it performs operations over data through BIU.

Let us now discuss the functional parts of 8086 microprocessors.

ALU
It handles all arithmetic and logical operations, like +, −, ×, /, OR, AND, NOT operations.

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Flag Register
It is a 16-bit register that behaves like a flip-flop, i.e. it changes its status according to the
result stored in the accumulator. It has 9 flags and they are divided into 2 groups −
Conditional Flags and Control Flags.

It is a 16-bit register. 9-bit are used as different flags, remaining bits unused

OF DF IF TF SF ZF AF PF CF

Fig: 16-bit flag register

Out of 9-flags, 6 are conditional (status) flags and three are control flags

Conditional Flags
It represents the result of the last arithmetic or logical instruction executed. Following is
the list of conditional flags −

 Carry flag − This flag indicates an overflow condition for arithmetic operations.
 Auxiliary flag − When an operation is performed at ALU, it results in a
carry/barrow from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), then
this flag is set, i.e. carry given by D3 bit to D4 is AF flag. The processor uses this
flag to perform binary to BCD conversion.
 Parity flag − This flag is used to indicate the parity of the result, i.e. when the
lower order 8-bits of the result contains even number of 1’s, then the Parity Flag is
set. For odd number of 1’s, the Parity Flag is reset.
 Zero flag − This flag is set to 1 when the result of arithmetic or logical operation is
zero else it is set to 0.
 Sign flag − This flag holds the sign of the result, i.e. when the result of the
operation is negative, then the sign flag is set to 1 else set to 0.
 Overflow flag − This flag represents the result when the system capacity is
exceeded.

Control Flags
Control flags controls the operations of the execution unit. Following is the list of control
flags −

 Trap flag − It is used for single step control and allows the user to execute one
instruction at a time for debugging. If it is set, then the program can be run in a
single step mode.
 Interrupt flag − It is an interrupt enable/disable flag, i.e. used to allow/prohibit the
interruption of a program. It is set to 1 for interrupt enabled condition and set to 0
for interrupt disabled condition.
 Direction flag − It is used in string operation. As the name suggests when it is set
then string bytes are accessed from the higher memory address to the lower
memory address and vice-a-versa.

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General purpose register

There are 8 general purpose registers, i.e., AH, AL, BH, BL, CH, CL, DH, and DL. These
registers can be used individually to store 8-bit data and can be used in pairs to store 16bit
data. The valid register pairs are AH and AL, BH and BL, CH and CL, and DH and DL. It
is referred to the AX, BX, CX, and DX respectively.

 AX register − It is also known as accumulator register. It is used to store operands

for arithmetic operations.
 BX register − It is used as a base register. It is used to store the starting base
address of the memory area within the data segment.
 CX register − It is referred to as counter. It is used in loop instruction to store the
loop counter.
 DX register − This register is used to hold I/O port address for I/O instruction.

Pointer and Index registers:

SP (Stack Pointer), BP (Base pointer), SI (Source Index), DI (Destination index)

 Pointer Registers:
The two pointer registers, SP and BP are used to access data in the stack segment.
The SP is used as offset from current Stack Segment during execution of instruction that
involve stack. SP is automatically updated. BP contains offset address and is utilized in
based addressing mode. Overall, these are used to hold the offset address of the stack
address.
 Index Registers:
EU also contains a 16-bit source index (SI) register and 16-bit destination index
(DI) register. These registers can be used for temporary storage of data similarly as the
general purpose registers. However they are specially to hold the 16-bit offset of the data
word. SI and DI are used to hold the offset address of the data segment and extra segment
memory respectively.

BIU (Bus Interface Unit)

BIU takes care of all data and addresses transfers on the buses for the EU like sending
addresses, fetching instructions from the memory, reading data from the ports and the
memory as well as writing data to the ports and the memory. EU has no direction
connection with System Buses so this is possible with the BIU. EU and BIU are connected
with the Internal Bus.

It has the following functional parts −

 Instruction queue − BIU contains the instruction queue. BIU gets upto 6 bytes of
next instructions and stores them in the instruction queue. When EU executes
instructions and is ready for its next instruction, then it simply reads the instruction
from this instruction queue resulting in increased execution speed.

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Fetching the next instruction while the current instruction executes is
called pipelining.

 Segment register − BIU has 4 segment buses, i.e. CS, DS, SS& ES. It holds the
addresses of instructions and data in memory, which are used by the processor to
access memory locations. It also contains 1 pointer register IP, which holds the
address of the next instruction to executed by the EU.
o CS − It stands for Code Segment. It is used for addressing a memory
location in the code segment of the memory, where the executable program
is stored. holds the upper 16-bits of the starting addresses of the segment from
which BIU is currently fetching instruction code bytes.
o DS − It stands for Data Segment. It consists of data used by the program
and is accessed in the data segment by an offset address or the content of
other register that holds the offset address.
o SS − It stands for Stack Segment. It handles memory to store data and
addresses during execution.
o ES − It stands for Extra Segment. ES is additional data segment, which is
used by the string to hold the extra destination data.
 Instruction pointer − It is a 16-bit register used to hold the address of the next
instruction to be executed.

Pin Diagram

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Power supply and frequency signals
It uses 5V DC supply at VCC pin 40, and uses ground at VSS pin 1 and 20 for its
operation.

Clock signal
Clock signal is provided through Pin-19. It provides timing to the processor for
operations. Its frequency is different for different versions, i.e. 5MHz, 8MHz and 10MHz.

Address/data bus
AD0-AD15. These are 16 address/data bus. AD0-AD7 carries low order byte data and
AD8AD15 carries higher order byte data. During the first clock cycle, it carries 16 -bit
address and after that it carries 16-bit data.

Address/status bus
A16-A19/S3-S6. These are the 4 address/status buses. During the first clock cycle, it
carries 4-bit address and later it carries status signals.

S7/BHE
BHE stands for Bus High Enable. It is available at pin 34 and used to indicate the transfer
of data using data bus D8-D15. This signal is low during the first clock cycle, thereafter it
is active.

Read
It is available at pin 32 and is used to read signal for Read operation.

Ready
It is available at pin 32. It is an acknowledgement signal from I/O devices that data is
transferred. It is an active high signal. When it is high, it indicates that the device is ready
to transfer data. When it is low, it indicates wait state.

RESET
It is available at pin 21 and is used to restart the execution. It causes the processor to
immediately terminate its present activity. This signal is active high for the first 4 clock
cycles to RESET the microprocessor.

INTR
It is available at pin 18. It is an interrupt request signal, which is sampled during the last
clock cycle of each instruction to determine if the processor considered this as an interrupt
or not.

NMI
It stands for non-maskable interrupt and is available at pin 17. It is an edge triggered
input, which causes an interrupt request to the microprocessor.

TEST
This signal is like wait state and is available at pin 23. When this signal is high, then the

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processor has to wait for IDLE state, else the execution continues.

MN/MAX
It stands for Minimum/Maximum and is available at pin 33. It indicates what mode the
processor is to operate in; when it is high, it works in the minimum mode and vice-a-
versa.

INTA
It is an interrupt acknowledgement signal and id available at pin 24. When the
microprocessor receives this signal, it acknowledges the interrupt.

ALE
It stands for address enable latch and is available at pin 25. A positive pulse is generated
each time the processor begins any operation. This signal indicates the availability of a
valid address on the address/data lines.

DEN
It stands for Data Enable and is available at pin 26. It is used to enable Transreceiver
8286. The transreceiver is a device used to separate data from the address/data bus.

DT/R
It stands for Data Transmit/Receive signal and is available at pin 27. It d ecides the
direction of data flow through the transreceiver. When it is high, data is transmitted out
and vice-a-versa.

M/IO
This signal is used to distinguish between memory and I/O operations. When it is
high, it indicates I/O operation and when it is low indicates the memory operation. It is
available at pin 28.

WR
It stands for write signal and is available at pin 29. It is used to write the data into the
memory or the output device depending on the status of M/IO signal.

HLDA
It stands for Hold Acknowledgement signal and is available at pin 30. This signal
acknowledges the HOLD signal.

HOLD
This signal indicates to the processor that external devices are requesting to access the
address/data buses. It is available at pin 31.

QS1 and QS0

These are queue status signals and are available at pin 24 and 25. These signals provide
the status of instruction queue.

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S0, S1, S2
These are the status signals that provide the status of operation, which is used by the Bus
Controller 8288 to generate memory & I/O control signals. These are available at pin 26,
27, and 28. '

LOCK
When this signal is active, it indicates to the other processors not to ask the CPU to leave
the system bus. It is activated using the LOCK prefix on any instruction and is availabl e at
pin 29.

RQ/GT1 and RQ/GT0

These are the Request/Grant signals used by the other processors requesting the CPU to
release the system bus. When the signal is received by CPU, then it sends
acknowledgment. RQ/GT0 has a higher priority than RQ/GT1.

INTERRUPTS IN 8086
Interrupts are signals generated by external devices or internal conditions that require the
immediate attention of the microprocessor. When an interrupt occurs, the microprocessor
temporarily suspends its current execution and transfers control to a specific interrupt handler
routine.
The interrupt handler routine, also known as the Interrupt Service Routine (ISR), handles the
interrupt and performs the required task. After completing the interrupt handling, the
microprocessor resumes the execution of the interrupted program.
When a microprocessor receives an interrupt signal it stops executing current normal
program, save the status (or content) of various registers (IP, CS and flag registers in case of
8086) in stack and then the processor executes a subroutine/procedure in order to perform the
specific task/work requested by the interrupt.

The subroutine/procedure that is executed in response to an interrupt is also called Interrupt

Service Subroutine (ISR). At the end of ISR, the stored status of registers in stack is restored to
respective registers, and the processor resumes the normal program execution from the point
(instruction) where it was interrupted.

There are two types of interrupts:

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Hardware Interrupts
Hardware interrupts are the types of interrupts which are caused by any peripheral
device and sends signals through a specified pin to the processor. Hardware interrupt is used to
handle external hardware peripherals , such as key boards, mouse, hard disks , floopy disks,
DVD drivers and printers.

 The 8086 has two hardware interrupt pins, i.e. NMI and INTR.
 NMI is a non-maskable interrupt and INTR is a maskable interrupt having lower priority.
 One more interrupt pin associated is INTA called interrupt acknowledge.

Non-Maskable Interrupt(NMI)
This interrupt has high priority than maskable interrupt. This cannot be replaced by any
software and it is also used by the processor to handle in case of any emergency.
Non-Maskable interrupts
 Used during power failure
 Used during critical response time
 Used during non-recoverable hardware errors
 Used watchdog interrupt
 Used during memory parity errors

Maskable Interrupt
The 8086 microprocessor has a dedicated hardware interrupt input pin called INTR (Interrupt
Request). When a hardware interrupt occurs, the INTR pin is activated, and the microprocessor
acknowledges the interrupt by executing the interrupt acknowledge cycle. The programmer can
choose to mask specific interrupts and re-enable them later.
When a maskable interrupt occurs… These actions are taken by the microprocessor –
 First completes the current instruction.
 Activates INTA output and receives the interrupt type, say X.
 Flag register value, CS value of the return address and IP value of the return address are
pushed on to the stack.
 IP value is loaded from the contents of word location X × 4
 CS is loaded from the contents of the next word location.
 Interrupt flag and trap flag is reset to 0

Software Interrupts
The software interrupts are program instruction. These instructions are inserted at desired
location in a program. While running a program , if software interrupt instruction is
encountered then the processor initiates an interrupt.

It can be interrupted by internal abnormal conditions and a programmer can also interrupt at
the required point while debugging a program. The 8086 processor has 256 types of software

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interrupts. The software interrupt instruction is INT n , where n is the type number in the range 0
to 255.

These 256 interrupts of 8086 are divided into 3 groups

1. Type 0 to type 4 interrupts-
These are used for fixed operations and hence are called dedicated interrupts

2. Type 5 to type 31 interrupts

Not used by 8086, reserved for higher processors like 80286, 80386 etc.

3. Type 32 to type 255 interrupts

Available for user, called user defined interrupts . these can be hardware interrupts and
Activated through Interline or can be software interrupts.
Examples of Software Interrupts are as below
 Type 0 (division by zero)
 Type 1 (Single step interrupt:- used for executing the program in single step mode by
setting Trap flag)
 Type 2 (Non Maskable interrupt:-failure of power condition) it represents NMI
 Type 3 (break point interrupt):- When this interrupt occurs a program would execute up
to its break point.
 Type 4 (overflow interrupt:- used to handle any overflow error)

8086 ADDRESSING MODES

The different ways in which a source operand is denoted in an instruction is known
as addressing modes. There are 8 different addressing modes in 8086 programming –

1.Immediate addressing mode

The addressing mode in which the data operand is a part of the instruction itself is known as
immediate addressing mode.

Here, Immediate data means constant data, whereas data transferred from a register or
memory location are variable data.

2.Register addressing mode

It means that the register is the source of an operand for an instruction.

Example - MOV CX, AX ;

It copies the contents of the 16-bit AX register into the 16-bit CX register.

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Here, All the registers, except IP, may be used in this mode.

3.Direct addressing mode

The addressing mode in which the effective address of the memory location is written directly in
the instruction.

4.Register indirect addressing mode

This addressing mode allows data to be addressed at any memory location through an offset
address held in any of the following registers: BP, BX, DI & SI.

Example - MOV AL, [BX] ;

Suppose the register BX contains 1102H, then the contents in 1102H are moved to AL

MOV AL,[BX]
Assume DS=5000H
Assume BX=1102H

Now Physical address will be

DS* 10H+1102H

PA=50000+1102H
=51102H

OR

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Microprocessor

Example - MOV AL, [SI] ;

Suppose the register SI contains 1102H, then the contents in 1102H are moved to AL

MOV AL,[SI]
Assume DS=5000H
Assume SI=1102H

Now Physical address will be

DS* 10H+1102H

PA=50000+1102H
=51102H

5.Based addressing mode

In this addressing mode, the offset address of the operand is given by the sum of contents of
the BX/BP registers and 8-bit/16-bit displacement.

 Based Addressing specifies a signed 8-bit or an unsigned 16-bit displacement and stores
the base value for the effective address in BX or BP.

 When there is an 8-bit displacement, the sign is 16-bit extended before being added to the
base value.

 When BX contains the base value of EA, DS, and BX are combined to form a 20-bit
physical address.
 BP and SS are used when BP holds the base value of EA.
 Examples of Based Addressing Modes are given below

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Example:
MOV DL,[BX]
Assume DS=5000H
Assume BX=0005H

Now Physical address will be

DS* 10H+0005H

PA=50000+0005H
=500005H

MOV DL,[BX]
Assume DS=5000H
Assume BX=0005H

Now Physical address will be

DS* 10H+0005H

PA=50000+0005H
=500005H

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6.Indexed addressing mode

In this addressing mode, the operands offset address is found by adding the contents of SI or DI
register and 8-bit/16-bit displacements.

Example –

MOV DL, [SI]

Assume DS=5000H
Assume SI=1002H
PA=DS*10H+[SI]
=5000H*10H+1002H
=50000H+1002H
=51002H

7.Based-index addressing mode

In this addressing mode, the offset address of the operand is computed by summing the base
register to the contents of an Index register.

MOV CH, [BX+SI]

This instruction moves bytes from address pointed by BX+SI in data segment to CH

Assume DS=5000H
Assume SI=4321H
Assume DX=1000H
PA=DS*10H+[SI]
=5000H*10H+4321H+1000H
=50000H+5321H

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=55321H

8.Based indexed with displacement mode

In this addressing mode, the operands offset is computed by adding the base register contents, an
Index registers contents and 8 or 16-bit displacement.
Example –
MOV CH, [BX+SI+04]
This instruction n moves a byte from the address pointed by BX+SI+04 H in data segment to
CL

Assume DS=5000H
Assume BX=4321H
Assume SI=1001H
Displacement=04H
PA=DS*10H+[SI]
=5000H*10H+4321H+1001H+04H
=50000H+5322H+04H
=55326H

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Microprocessor

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Microprocessor

----------------------------------------------End Of Unit-2-------------------------------------------

8085 Microprocessor Architecture and Operations

 Address, Data And Control Buses

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 Internal Data Operation and Registers

 Externally Initiated Operations
 Addressing Modes
 Memory and Memory Operations
 Flag and Flag Register
 8085 Pin Diagram and Functions
 Multiplexing and De-multiplexing of address/data bus
 Generation Of Control Signals

8086 Microprocessor
Logical Block Diagram
Segment Registers,
Memory Segmentation
Bus Interface Unit and Execution Unit
Pipelining

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