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-
-
 I
Junction capacitance is the capacitance
action apart
te Function capacitance which forms in a PN junction diode under
zero bias.
at reverse bias. In a normal capacitor, the
two parallel conducting plates are
abrupt ↑ electrodes which allow the conduction.

-
junction ↳

~
m 0.5
=

abruptregion

v/b.)"
3
=

I
m 0.33 linear
=

region
Cj
linear junction
-- was

is
7.0 ~

vasti--
&
0.3 -

0.0 -
Vp (v)
(Bias)
i
Level 3 model
/
-
can be varied
I
MnCox ([as-vin) ves
=

(Vas-V H)1 vas) Drain

Is:
MnCox
+
+

current

Vps] Vas-VTH of a MOSFET

mobility

3
Un->
Cox Oxide
->
Capacitance Process

Mn=f(Vos, was, temp---) w- width

2
Length
-
of gate
of gate
Dependant

f ( doping, UBS -....)

vix -> threshold voltage
ViH =

condition
Vos, Vis ->
operating
 He -
is e

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SPICE
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+

Switch
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-

Cala.
this
Parameter Units

ames symbol I
Vas, VT
Recomputing the value of iss

- in iterations each
- -
-

A in
-D
Ron iteration, it converges.
S

↓ Unitfor example

G
SPICE
does these iterations for you.
-
Sub Threshold
-
-
-

S
Rs

When G=0, Rs is
very high, the
urantflowing is
called

reverse saturation current. (SubTrshold)

when thoushold crosses, is becomes less,currentflaws.
 MOSFET To them on,
apply potential gate. at

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to
doest
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Channel ↓

Depletion
exists To turn
off... 4,

Source
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Insulator
-
W
x
-
oxide

#-
Drain
Enhancement
Mode Mode above thrusch old,
NMOSFET
when
I
applied is

ni
nightly doped
p-type, -T the
goes
into substrate - we come up
P A
substrate N
population inversion place
takes of

formed & capable of

E

chamel's is

Population inversion
transferring changes. But still bothSID
at
are same
potential yet.

VTh is
voltage reg. to oppose the
the

oppo change pastthem away of

to

exate a channel.

ene ↑
at
gate then resistance offered becomes

safe
lese 8 lesser.

R
Vas 4 RS
As
in, Gras is
fixed, is is
fixed.

Vass) Vas2) VasI If potential Drain

at inc, (VDs)
7
also increases.
Vass-VVGSz-VT VDS -> then charge flow
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↑
the sides of transistor has a thick
layer of oxide isolate
to

transistors.

~Breakdan
transistor
IB the
from other

Saturation The connected (thinner). Itisa

gate using gateoxide
is

!
Linda
thin
layer of oxide.

vs->

Mosfetresistance: (ContactResistance + Mire Resistance

+
Rdiffusion Rawal)
+ x 2

The contacts are

heavily doped to contact resistances is due to
difference in work
function
have a
gradual resistance of terminal (metal) 8 source/drain.

changes.
Box Rohannel
usually her
is -

factors of usually dependent

on urrent
 D

- .
*

a -

, a

Ts
a -
G- 1 -

11
-
T
S
B

NMOS with

NMOS Enhancement NMOS Panos Enhancement

Depletion Bulk contact

vt vTx
=

w(X-26,Ys -v2d=)
+
+

bulk
Vsis->Source to
-

bus-24-
-- visit
-

a
Resistina
e
Vas
↑

VI,..................... ID
Vis Vors-VT

:
-

caust"

- 2.S I

-2 -Is
I

⑧
I
S
-

Processed Transconductance
Parameter
Almost
is
linsan
channel
VDS
chanel-Is -> MnCox
E (Cras-v-> Vas-V
Kn=MnCox Mn 'Gox =

S
Cox per unit area
For small vis
ignore is
for Vis (Vas-V+]
In saturation.

Is:
* (Vas -vy(2(1 4(s) +
VDS Vas-VT
=

Voverdrine
=

Is aoruadin
Chanel
lengthmodulation
 -
823
a -
In linear region, Ups Vas-VT Is
k'n=MnCox
M
Sox.Processtransconductase
are
=

Amfferentform typical
unit:

transconductance

Is vs Vos
n
-

ID ID
R x

~
LL~ ->

vas
quadratic linear

long channel ShortChannel!

Mode
Saturation Vis >, Yas-Vi

E
(ras-ri) (1+ 4VasS
Is:
Iw
Ideally, L 0,
=
4with
decrease in

L- channel lengthmodulation index dimension of channel length.

 DSM
the era:-
->

IRelation
in
decity Suration
Deep submicron ra

4
Dimension of framistor
gets scaled
by
YV2 as
per
Moore'sLaw

VSat 1OS
=

:O
~
180 nm-BOnn-90nm-65nm confantvelocity

-- Constantmobility (Slope:-M)

In analog, channel
the
length of tramistor does remain I

>

its
3c 1S
the same for different technology.
=

field
T
b(A) both
was, was due to
-

Early saturation
a
old saturation
SV ->1000nm

↳
18V ->100um

Linear Relationship

>
VDS (V)

Vornardin
fou,
aut
current
VT have thin oxide.
Butwentreduces, due to
old DSm reduces as one

IV im A 0.SmA :Saturation occurs than

earlier normal case. scattering of charge density.
a

2V <mA Im A
it Beyond certain VDs, Mixes is Thisi sthe
doping field
Res, so, is
expected to
For same
of salt
3 w
9mA 1 SmA
reason for early saturation
see 4 in event.
IP
VDS VDDin=

Long-channel device

-Parisstart-canesame
digital

Input
-
charatis In(A)

a I
linear
quadratic
FA
few 100 of

....
! quadratic
>
v
... -

a
O
Vas CVS ~

subthreshold exponential
(v)

chanel
Long Short channel. CO2 all dimensions and all operating
of
- -

ratio
voltages being the same, the

Ratio of /events turn out to be

in NMOS
current to that
of PMOS
for the
same dimension
same as ratio
the of
of the MOSFETs and same
operating paint (i.e Vas, Vis
being same)
the around
is 25
2 to mobilities
to
of
holes.
electrons
 per unitarea

h
~ process
a

(CVas-vin) as
M

Ii MnCox E vas -

I
=
VGS=VD$

a
voverdrine
Ipsat
W

Y
-un()
n
design parameters
a t
process
personnets Vas, Ves -> runtime

"Vas 0
=

MOSFET -

Voltage controlled resistor

UDS VDD
=

R =

I
L

a
estimated
-
sno
Is
-
-
. . . . . .
operatic

* VDS
S
coin

>

when it is
in saturation, we can creater current
source.
 Resistor
Linear
region-VC

channel MOSFETis
Short not used

in
analog.
 parallel
putMOSFETs in

proval
Este in
 overlap Co:overlap
Gate Source
- capacitance
Gate drain overlap

R
M
as
Capacitance
a

W+LE
(g2 Cya

-
FLA

function of

Y
W
Vas

-
Lot

(s 0) CyCS 2AWALox
(with
WALAloX -
=

-
3
CyCb (g,d
Cgas= I

WACOR (qcd

-
Yas
↳ -
VDS/r-overdrine
Capacitance
as a

function degree of saturation

of the
 blate (_side-wall
C-diffusion: C-bottom +

(jsw Perimeter
2jxbottom-plate-area
*
=
+

(j*L-Source
AW +
Cjsw*(2*L-source W)
+

Cys (gcs+Cgso
=

Cyd=(qcd +Cgdo (yb (gcb

=

CSb Cdiffusion-sauce Cdb=

(diffusion-drain
=

Dynamic Power
Omw

ne
-

- 100nw
Leakage
-

channel DynamicPama: 0. Inw

=100nw

isman order
 Source N++
silicon
praintt
P substrate -
Ground

N)-substrate -

Vois

I Fi
N-well

↑we contact

⑮up
t
a re

お前はもう死んでいる
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The contacts wells take

up leakage charges
the A

hindered.
here the
original function is not
= FAN IN

controlling le
tphe neusarily
not

equal tpen
to

itthat
But
we want
way.
tp Propagation delay
=

tp 0.5*
= (tpn +tpen)

!Ias
I S
-
VsS
/A
A
~(s=VDDt 0
=

~ : s
a

~
-
-as=--
Vt

Vo
xDs ~VDD - 7

VIS
 UnCox
[(V-V) vo-22] o
-

R
= 0.5K
VDD

I
REIK a

varies

[II
I
R 1K =

I
-
- But
Voraia Vor_*Ye
7
Vo VDs
=
R 2K
=

(*) *
YD.

RPN
FDy

A
R rese

=As) VGS:va
()*
-

if (const
E4
E A) =

Vases =>
WN Rana
I Re * VocN

↳ Ronk I4
We cont

IRL Vor A
 Reistune
us
Fat Line
-

-
re
2 I
VOLI
u

VOLR- - -
w w,

W
=

w2
=

ras----
-

W Ws
=

Fidal
AspectRatio
WK r
L*

RPDN RPUE
+
 me overshootA undershoot
the
get
because
capacitor'svoltage cannot

-**
"
be
changed instantaneously.
So, we
getthe spikes in oven under.

/ Compensated Potential Dividen

"as , S
uni
Millman
E
=
& Tark

DC VTC Characteristics

utive
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NMOs with load.
passive
inverter as
resistance a