Unit-5 Syllabus:

Content Page no.

1. Memory Interfacing to 8086 (Static RAM and EPROM) 2
2. 8255 PPI various modes of operation 4
3. Interrupt structure of 8086 8
4. Interrupt Vector table (IVT) 9
5. Interrupt service routine (ISR) 9
6. 8259 PIC architecture and interfacing cascading of interrupt controller 11
and its importance
Prepared by Dr. Ajit Kumar (Asst. Professor, Dept. of ECE, Presidency University, Bengaluru)

1. Memory Interfacing to 8086 (Static RAM and EPROM)

The memory can be RAM or ROM – the difference is that ROM can only be read from, so the MEMWR
signal from the processor does not have any relevance for ROM. A typical RAM has the pin lines as
shown in Fig 1. As shown, it has data lines D o to DM−1. If it is a byte organized memory, the data lines are
D0 to D7. The number of address lines (A0 to AN−1) depends on the number of locations it contains.

Fig.1 RAM with control pins

For example in a 256 × 8 RAM chip, it has 8 data lines and a storage capacity of 256 locations – thus it
needs 8 address lines as 256 = 2 8. Thus, it is the capacity of the chip which decides the number of
address lines. The active low signals WE is to be connected to the MEMWR signal from the processor
side. Only if this pin is activated, can the write operation be done in the addressed location. For reading,
the pin MEMRD (from the processor side) is to be connected to the OE (output enable) pin of the
memory chip for reading. When this pin is low, the output lines are activated. The pin CS (chip select) is
the pin which enables the memory chip. No activity is possible if this pin is inactivated, as the chip
remains turned off.

A ROM chip is similar except that it does not have the WE pin, as it can only be read from. The
ROMs that are used are usually EPROM, which have a pin to enable the chip to be programmed (PGM).

Memory Address Decoding: Refer to the slides

Address Decoding Using Block Decoders: Refer to slides

Memory Banks

8086 has a 16-bit memory bus – which means that data transfer can occur at a maximum rate of
16 bits (one word) per bus cycle. However, sometimes only a byte needs to be accessed. This
means that the processor must have both options – i.e., both byte and word transfer must be
possible. We know that for a word transfer, two byte locations must be accessed i.e., two

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addresses are actually needed. A 16-bit data can be obtained by accessing two memory chips in
parallel, each having 8 bits each of the word as shown in Fig 2.

Fig.2. 16-bit memory realized using two 8-bit memory chips

This is the way memory is organized in 8086. A 16-bit word is obtained as the concatenation of two
bytes in two ‘memory banks’ i.e., memory is organized as two banks – one, the upper bank or high bank
with the data corresponding to the upper byte D8–D15, and the other, the lower bank or low bank
which has the data lines D0–D7. The upper bank is also called the odd memory bank, because it has the
odd addresses mapped to it – in the same way, the lower bank is called the even bank (Fig 3).
Remember that a 16-bit word has one byte with an odd address and one byte with an even address. If a
byte alone is to be accessed, it may be in the odd bank or even bank. Thus for reading / writing a byte,
only one of the banks is to be accessed, but to access a word, both memory banks have to be
accessed.

Fig.3. Memory banks of 8086

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The two banks differentiated by A0. An even address implies that the LSB of its address i.e., A 0 is low.
Thus A0 is be used to enable the even bank. To enable the high (odd) bank, 8086 generates a signal BHE
(Bus High Enable) which goes low whenever the addressed byte is in the high (odd) bank.

Fig.4. Memory banks with the respective bank enable signals, along with the decoder

2. 8255 PPI (Programmable Peripheral Interface) various modes of operation

This chip is also called a parallel port chip and it eases out the problems and issues related to parallel
data transfer to/from memory or I/O devices. When I/O devices are more versatile and have more
features, a PPI is be very useful, especially when more than one I/O device is to be interfaced to the
processor. This chip ensures that no other extra hardware is required to interface peripheral devices
that perform parallel data transfer. As shown in Fig.5, the 8086 microprocessor is connected to 8255
using data bus. When data transfer takes place between microprocessor and 8255 then these data are
need storage (registers) in 8255. Therefore 8255 has registers called ‘ports’ – there are three ports here
– A, B and C, and these ports have pins connecting it to external devices. Thus, port A has 8 pins PA0 to
PA7 – so also ports B and C, as well. To these port pins, external devices like keyboards, displays, printers
can be connected.

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Fig.5. The connection between 8086, 8255 and three peripherals

8255 pin configuration and Internal block diagram

Fig.6 (a) shows the pin configuration of the DIP (dual-in-line) version of the chip. It has 40 pins, which
consist of three 8-bit ports named Port A (PA), Port B (PB) and Port C (PC), each of which can be
programmed as input or output ports. Fig.2 (b) shows the internal block diagram of the chip with various
functional blocks as explained below

Data Bus Buffer There is a three state bi-directional 8-bit buffer which is used to interface the chip to
the data bus of the system. Upon execution of the processor’s input or output instructions, data and
control/status words are received or transmitted by the buffer.

Read/Write Control Logic It manages all data transfer between the chip and the processor, on accepting
control signals from the control and address buses of the system.

Group A and B Controls Functionally this chip has been divided as Group A and B and they have their
corresponding controls. The way the chip is to act is decided by a register called the control/status
register which can be written to and read from.

Programming the PPI

Programming the chip involves only the writing of a particular word to the control register.

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Fig.6 (a) Pin diagram of 8255 (b) Internal block diagram of 8255

The control register is an 8-bit register which can be written into. The bits of this word (called the
control word) will decide the way the ports of the chip are to be configured. The Fig.7 shows the control
word format.

Fig.7. Control word format of 8255

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The ports A, B and C are grouped into two – Groups A and B. Group A consists of Port A and upper 4 bits
(PC4–PC7) of Port C. Group B includes Port B and Port C lower (PC0–PC3). Thus Group A ports has three
operational modes (0, 1 and 2), but Group B ports have only two modes of operation.

Modes of Operation

The 8255 can be made to work in three modes as decided by the system designer. They are:

 Mode 0: Basic input/output

 Mode 1: Strobed input/output
 Mode 2: Bi-directional bus

Mode 0: This is the simplest and most widely used mode. In this mode, the two 8-bit ports A and B, and
the 4-bit ports Port C upper and Port C lower, may be used independently. Here data is simply taken in
from an input port or given to an output port.

The specifications of this mode are:

(1) Two 8-bit ports and two 4-bit ports.

(2) Any port can be input or output.
(3) Outputs are latched.
(4) Inputs are not latched.
(5) 16 different input/output combinations possible.

Mode 1: This is the ‘handshaking’ mode. Handshake implies data transfer in which the communicating
devices exchange request and acknowledge control signals with each other. For an 8255 operating in
this mode, Ports A and B pins are used for data transfer, while 4 bits of each of Port C are used for
generating the handshaking signals for each of the 8-bit ports.

The specifications of this mode are:

(1) Each group contains one 8-bit port and one 4-bit port. The 4-bit port is used for ‘handshaking’.
(2) The 8-bit port can be either an input or an output.
(3) Input and output are latched.
(4) The 4-bit port is used for control and status of the 8-bit data port.
(5) Interrupt logic is supported.

Mode 2: This is the bidirectional mode. Only Group A can use this mode. Here Port A is used for
transmitting as well as receiving data. Handshaking signals generated by the upper 4 bits of Port C
maintain bus discipline for proper flow of data in the required direction. Now, let us use the different
modes.

The specifications of this mode are:

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(1) Used in Group A only.

(2) One 8-bit, bi-directional bus port (Port A) and a 5-bit control port (Port C).
(3) Both inputs and outputs are latched.
(4) The 5-bit control port (Port C) is used for control and status for the 8-bit, bi-directional bus port
(Port A).

3. Interrupt structure of 8086

8086 has hardware interrupts, software interrupts and error generated interrupts. For the three cases
mentioned here, the interrupting mechanism is different, but the way the processor responds is similar.
After every instruction cycle, the processor checks if any interrupt is awaiting service. If, it finds an
interrupt request and decides to acknowledge and service it, the response is the following sequence of
steps:

(1) The flag register is pushed on to the stack.

(2) The interrupt flag is disabled (IF = 0).
(3) The trap flag is disabled (TF = 0).
(4) The CS register is pushed on to the stack.
(5) The IP register is pushed on to the stack.
(6) Control is transferred to the location in which the corresponding ‘Interrupt Service Routine’ (ISR)
is stored. This in effect, would be a far jump.
(7) The program corresponding to the ISR is executed. The last instruction in the ISR will be IRET.
(8) Then IP is popped off the stack.
(9) CS is popped off the stack.
(10)The Flag register is popped off the stack.
(11)Control returns to the point at which it had left off .

Fig.8. Steps in processing an interrupt request

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Prepared by Dr. Ajit Kumar (Asst. Professor, Dept. of ECE, Presidency University, Bengaluru)

4. Interrupt Service Routine

When an interrupt occurs, the processor suspends the execution of its current task and takes on
another task as required by the interrupting source. This program, or routine as it may be called,
is designated as an ‘interrupt service routine’. This routine corresponds to the request of a
particular source of interrupt and it is also called its ‘interrupt handler’. This means that for any
interrupt that occurs, there is a particular interrupt service routine (ISR).

5. Interrupt Vector table (IVT)

ISR is available in memory and must be accessed on occurrence of the specific interrupt. For that, the
address of the ISR must be obtained. The address of an ISR is called its ‘interrupt vector’. For an
8086 based system, any address of code is in the following form, CS: IP. Thus, the interrupt vector
for any interrupt has 4 bytes – two for the CS value and two for the IP value. Thus, if the interrupt
vector for a particular interrupt is obtained, control can be transferred to the new location by using the
new values of CS and IP specified as the ‘interrupt vector’. The 8086 has 256 interrupt vectors and
since each vector is specified by 4 bytes, it implies that 256 × 4 = 1024 bytes (1K) of memory are
allocated to store the interrupt vectors. These 256 vectors are stored in a table called the ‘Interrupt
Vector Table’ (IVT) in system RAM from locations 00000 to 003FFH.

Fig. 9 Interrupt vector table of 8086

How is an Interrupt Different from a ‘Call’?

An interrupt seems to perform actions similar to a far CALL instruction. It differs in a few points,
however. An interrupt causes the flag register to be pushed on the stack in addition to CS and IP
values. It clears the trap and interrupt flags. The action of clearing the flags is not associated with a
CALL, but is part of the automatic response due to an interrupt. Also, note that the ISR ends with

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Prepared by Dr. Ajit Kumar (Asst. Professor, Dept. of ECE, Presidency University, Bengaluru)

IRET rather than a RET instruction. The IRET instruction ensures that the flag register is also popped
off the stack, rather than just the CS and IP.

Dedicated Interrupt Types

Intel has dedicated certain interrupt types for specific applications directly related to CPU operations.
These are listed below.

INT 0 (Divide by Zero Error)

The interrupt with type number 0 is dedicated to the ‘divide by zero’ error. This interrupt is an ‘error
generated’ interrupt (also called an ‘exception’). On division, if the quotient register is not large enough
to contain the quotient, this interrupt is generated automatically. Dedicating Type 0 for this case means
that the corresponding interrupt vector in the interrupt vector table is available at 0000:0000.

INT 1 (Single Stepping)

This type number is dedicated for ‘single stepping’ or ‘trace’. Single stepping is an important idea in
debugging. During logical debugging of our programs, we would like to stop after the execution of each
instruction and check the contents of registers, memory and so on. We usually perform the action of
‘trace’ this way. Intel has provided the ‘Trap’ flag for this, and this flag has to be set to let this happen.

D1 D1 D1 D1 D1 D1 D D D D D D D D D D

5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0

U U U U OF DF IF TF SF ZF U AF U P U CF

INT 2 (Non Maskable Interrupt)

This interrupt corresponds to the vector (pointer) of the hardware interrupt NMI. When an interrupt is
received on the pin NMI (Non Maskable Interrupt) of the processor, a type 2 interrupt occurs – this means
that the ISR for NMI must be written in the address pointed by the corresponding IVT content.

INT 3 (Breakpoint Interrupt)

This is the breakpoint interrupt, which is useful for de-bugging. We need to set breakpoints (stop after
executing a group of instructions) and check the content of registers and memory after executing
instructions up to the breakpoint.

INT 4 (Overflow Interrupt)

This interrupt corresponds to the overflow flag. If the overflow flag is set, this interrupt occurs, but not
automatically. An instruction INTO (interrupt on overflow) must be written after the program segment
which is likely to cause the overflow flag (OF) to be set.

Software Interrupts

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When an interrupt is initiated by an instruction, it is called a software interrupt. The format of this
instruction is:

INT type number.

The type numbers can vary from 0 to 255. This is a very important and interesting way of using
procedures whose vectors are inserted into the IVT. Thus, the user can write any procedure as an ISR,
store it in some address in memory and call it by using the instruction INT n.

Hardware Interrupts

There are two pins on which interrupt requests can be received – they are the INTR pin and the NMI pin.

NMI

This is a positive edge triggered interrupt. This is a non maskable interrupt, in that it does not depend on
the setting of the interrupt flag (IF). It cannot be masked or prevented from being activated. It is a Type 2
interrupt, meaning that its vector is obtained from the corresponding location in the interrupt vector table.
NMI caters to applications of the highest priority, like power failure.

INTR

This is the non-vectored interrupt pin of the 8086, which means that when an interrupt request is received
on this pin, it does not get automatically directed towards any particular entry in the interrupt vector table.
Another feature of this interrupt is that the interrupt flag (IF) is required to be set for an interrupt request
on the INTR line to be honored. It is to be ensured that the IF is set by the instruction STI if interrupts on
the INTR lines are to be acknowledged. INTR is a high level triggered interrupt.

Priority of Interrupts

When many interrupts occur at the same time, which source gets its request honored first? The processor
decides the priority. The order of priority is set in the following manner:

1) Internal interrupts and Software interrupts – get the highest priority,

2) NMI,
3) INTR – gets the lowest priority

6. 8259 Programmable Interrupt Controller (PIC) architecture and interfacing cascading of

interrupt controller and its importance

There are only two hardware interrupt lines for the 8086. An external device can place its interrupt
request on either of these pins. One pin called NMI is a ‘vectored’ interrupt, in the sense that its interrupt
handler is pointed to, by a particular type number and that is ‘2’. Thus, NMI is a Type 2 interrupt, and
since it is non-maskable it is used for important and high priority services. As such, this interrupt pin is
not available for general interrupt requests from various peripherals. That leaves just one pin for
accepting hardware interrupt requests, and if many peripherals want to use this pin, obviously a number
of issues have to be resolved. It is in this context that a dedicated interrupt controller like 8259 is
necessary.

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The PIC has eight interrupt request lines IR0 to IR7, on which peripherals can place their
interrupt requests. If one interrupt request alone is received on the chip, that request is channeled to the
INTR line of the processor. As is the usual sequence, the processor sends back an acknowledge request in
the form of the INTA signal. Then the PIC (on behalf of the peripheral which has made the request) sends
to the 8086 the interrupt type number corresponding to that specific interrupt.

Another activity of the chip is to resolve priorities. Suppose interrupt requests arrive at more than
one interrupt input of the chip. Which one of these requests should be channeled to the processor? This
decision is made by the PIC.

Block Diagram of 8259

Fig. 10 Block diagram of PIC 8259

The function of various blocks is explained below:

Int (Interrupt) This output goes directly to processor interrupt input and causes the processor to send
back the INTA as an acknowledgement, to the 8259.

Interrupt Request Register (IRR) and In-Service Register (ISR): The interrupts at the IR input lines are
handled by two registers in cascade, the Interrupt Request Register (IRR) and the In-Service Register

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(ISR). The IRR is used to store all the interrupt levels which are requesting service; and the ISR is used to
store the interrupt levels which are being serviced.

Priority Resolver This logic block determines the priorities of the bits set in the IRR. The highest priority
is selected and strobed into the corresponding bit of the ISR (in service register) during the INTA pulse.

Interrupt Mask Register (IMR) The IMR stores the bits which mask the interrupt lines to be masked. The
IMR operates on the IRR. Masking of a higher priority input will not affect the interrupt request lines of
lower priority.

CAS0–CAS2: These three bi-directional lines can be used to cascade several such chips to expand the
number of interrupts up to 64, in a master or slave mode. The associated three I/O pins (CAS0-2) are
outputs when the 8259 is used as a master and are inputs when the 8259 is used as a slave.

SP / EN: This stands for Slave Program/Enable Buffer. This is also a bidirectional pin. In the buffered
mode, it can be used to control buffer transceivers (EN ). In other modes, it indicates whether the 8259
is a master (SP = 1), or whether it is a slave (SP = 0).

R / W LOGIC: Just as in the case of any other peripheral chip, the decoding logic on the CS and A0
determine the addresses of the registers within the chip, and in conjunction with the RD and WR signals,
the registers can be written into and read from (to get status information).

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