SMART CHARGING AND VEHICLE-TO-GRID (V2G)

SUPPORT ON S32G2 PROCESSORS

S32G2 Safe and Secure Vehicle Network Processors
SYSTEM BLOCK DIAGRAM
OVERVIEW • A hash engine supporting standard SHA1 and SHA2 SYSTEM BLOCK DIAGRAM
hash primitives up to 512-bit digest Communication
Smart charging enables a bidirectional charging Can be wired or controller of
infrastructure consisting of electric vehicles, charging • A public key cryptographic (PKC) engine which wireless connection the EV

stations and charging operators. Data communications accelerates RSA and ECC operations
Charging
between the interfaces are on a secure channel. ISO 15118, • Supported symmetric and asymmetric cryptography
Power Grid
Stations
the standard for communication between electric vehicles
(EVs) and charging stations, allows for a user-friendly “plug ENABLEMENT TOOLS Hardware Security Engine (HSE)
and charge” mechanism for authentication, authorization, in S32G274A used for secure
• S32 Design Studio for S32 platform processors with communications and verifying
billing and flexible load control based on information cryptographic mechanisms to
configuration tools
exchanged between an EV and the charging infrastructure. guarantee the confidentiality,
• S32 debugger probe enables debugging and trace for integrity, and authenticity of all
Some characteristics of smart charging include: exchanged data
S32G2
• No credit card or payment method requirement for
• Real Time Drivers combining functionalities of SDK and
charging a vehicle; the EV identifies itself to the charging
MCAL as single software product for single S32 families
statement and gets the authorized access to the energy
for charging its battery • Linux BSP the reference software for Arm Cortex-A53 ISO 15118
ISO 15118 AND RELATION
AND RELATION TO OSI LAYERS
TO OSI LAYERS
cores
• Energy transfers from the EV to the charging station and Application ISO 15118-2 Application layer messages (V2G message),
vice versa; this helps prevent overloading of the electric • HSE firmware enables hardware security module OSI Layer 7 SDP (SECC Discovery Protocol
Network and
grid integrated with S32G2 Application application EXI
OSI Layer 6 protocol (Efficient XML Interchange) ISO 15118-4
ISO 15118-1 requirements
• Wireless or wired software updates can occur during • FreeRTOS the real-time OS for Arm Cortex-M7 cores and Network and
Application General ISO 15118-20 V2GTP
application
charging OSI Layer 5 information
and use case 2nd
(Vehicle-to-grid Transfer Protocol)
protocol
conformance
S32G274ABLOCK
S32G2 BLOCK DIAGRAM
DIAGRAM (S32G274A) Application definition generation UPD (User Datagram Protocol),
tests
network and TCP (Transmission Control Protocol),
OSI Layer 4
S32G2 HARDWARE SECURITY ENGINE FEATURES Memory Network Acceleration
(merged with
contents of
application TLS (Transport Layer Security)
Processors protocol
System SRAM Automotive Networks Application ISO 15118-6 requirements IP (Internet Protocol), SLAAC, DHCP
• The hardware security engine (HSE) is a security Standby SRAM Arm Cortex-M7 Arm Cortex-A53 Arm Cortex-A53
Low Latency
Communications Engine
OSI Layer 3 for second
Arm Cortex-M7 Transport Layer Offload edition)
subsystem that runs relevant security functions for DDR3L/LPDDR4 I/F

NOR Flash Memory I/F

I-cache Arm
I-cache Arm
Cortex-M7
D-cache
Cortex-M7
D-cache
Arm ®
Cortex®-M7
Arm Cortex-A53
L1 L1
I-cache D-cache
Arm Cortex-A53
L1 L1
I-cache D-cache 16 x CAN FD FlexRay Application ISO 15118-3 ISO 15118-5 ISO 15118-8 ISO 15118-9
TCM I-cache D-cache
FPU Arm L1 L1 L1 L1 OSI Layer 2
confidentiality, data integrity and authenticity Cortex®-M7 Neon D-cache Neon D-cache
®
FPU D-cache
TCM I-cache I-cache I-cache
Flexible Buffers Physical and Physical and Physical and data link Physical and data link
NAND Flash Memory I/Fs
FPU D-cache
TCM I-cache
FPU D-cache
TCM I-cache Shared Neon TM
L2 Cache Neon
Shared L2 Cache data link layer data link layer layer requirements for layer conformance test
System TCM FPU 4 x LIN 4 x SPI Application requirements conform. tests wireless communication for wireless comm.
• HSE security engine firmware operates on a dedicated TCM Shared L2 Cache Shared L2 Cache
FPU
Security Offload
OSI Layer 1
FCCU and MBIST/LBIST

Arm® Cortex®-M7 core running at 400 MHz and utilizing PLLs

2 x Safe DMA
3x Dual-core Lockstep Cluster Lockstep Option Global Timestamping

Fabric
its own secure RAM and ROM Debug and Trace Unit
Safe Interconnect
Ethernet Networks
Packet Forwarding
Engine
Security
The HSE subsystem features the following cryptographic Hardware Security Engine Serial Communication Timers and ADCs
Stateful Inspection
Firewall

accelerators: Asymmetric Hardware

Accelerators
6 x SPI

Networking
5 x I2C
7 x Watchdog Timer Classification

Symmetric Hardware 8 x System Timer Header Manipulation

• A TDES engine
Accelerators 4 x CAN FD 3 x LIN/UART
Secure Memory 12 x FlexTimer IEEE 1588v2 + AVB
FlexRay® 1-GbE w/ TSN
Random Number 2.5-GbE 1-GbE 1-GbE

• An AES engine supporting all standard key sizes (128, Generators USB 2.0 OTG 2 x PCIe 3.0 2 x SAR ADCs (12-ch) MAC MAC MAC

192, 256 bits) and various complex ciphering modes

(CBC, CTR, GCM, etc.)

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Document Number: S32G2ZONECONFS REV 0