Digital Systems II Chapter 3

Shift Registers
Introduction
Shift registers are a form of sequential logic circuit used
predominantly for the storage of digital data, and they typically
lack a distinctive internal sequence of states. There are, however,
exceptions, which are covered in Section 8–4 (book). This chapter
examines the fundamental kinds of shift registers and presents
several applications. In addition, a troubleshooting procedure is
presented.

Shift registers operations

In digital systems, shift registers are crucial for storing and
transferring data using flip-flop layouts. There is no specific
sequence of states in a register, save in particular applications. A
register is generally used to store and shift data from external
sources, with no internal state sequence.

A register is a digital circuit that stores and moves data. Register

storage makes it an essential memory device. The figure below
shows how to store a 1 or 0 in a D flip-flop. The data input is set
to 1 and a clock pulse is used to store the 1 by setting the flip-flop.

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When the input 1 is withdrawn, the flip-flop stays in the SET
state, storing the 1. A similar process is used to store a 0 by
resetting the flip-flop, as seen in the Figure below.

The flip-flop is a storage element.

The storage capacity of a register is the number of bits (1s and 0s)
it can hold of digital data. The number of stages in a shift register
defines its storage capacity, as each flip-flop represents one bit of
storage capacity. The shift capability of a register allows data to
be moved between stages or out of the register using clock pulses.
Figure above.

Basic data movement in shift registers. (Four bits are used for illustration. The bits move in the
direction of the arrows.)

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 Types of Shift Register Data I/Os
This section discusses four shift register types depending on data
input/output: serial in/serial out, serial in/parallel out, parallel
in/serial out, and parallel in/parallel out.

Serial In/Serial Out Shift Registers

The serial in/serial out shift register receives data serially, or one
bit at a time on a single line. It also serializes the stored
information on its output. Let's start with the serial input of data
into a standard shift register. The diagram below depicts a 4-bit
gadget constructed with D flip-flops. This register has four stages
and can store up to four bits of data.

Serial in/serial out shift register.

The table below displays the four bits 1010 entered into the
register in Figure above, starting with the least significant bit. The
register begins clear. The data input line is set to 0 for FF0,

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resulting in D = 0. On the initial clock pulse, FF0 is reset, storing
0.

Shifting a 4-bit code into the shift register in Figure above Data bits are indicated by a beige
screen.

- The second bit, a 1, is applied to the data input, resulting in D =

1 for FF0 and D = 0 for FF1 as the D input is linked to the Q0
output. During the second clock pulse, the data input 1 is shifted
into FF0, setting it, and the 0 is moved into FF1.

-The data-input line receives the third bit, a 0, and a clock pulse.
The 0 is inserted into FF0, the 1 in FF0 is shifted to FF1, and the
0 in FF1 is shifted to FF2.

-Last bit, a 1, is applied to data input, and a clock pulse is applied.

This time, the 1 is inserted into FF0, the 0 in FF0 is relocated to
FF1, the 1 in FF1 to FF2, and the 0 in FF2 to FF3. The four bits
are serially entered into the shift register and can be stored for any
duration as long as the flip-flops have DC power.

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To remove data from the register, shift the bits serially to the Q3
output, as shown in Table below. In the data-entry process, the
LSB, 0, appears on the Q3 output after CLK4. Applying CLK5
clock pulse results in the second bit appearing on Q3 output.
Clock pulse CLK6 transfers the third bit to the output, whereas
CLK7 shifts the fourth bit. As the initial four bits are moved out,
new bits can be pushed in. After CLK8, all zeros are moved in.

Shifting a 4-bit code out of the shift register in Figure above. Data bits are indicated by a beige
screen.

Show the states of the 5-bit register in Figure(a) below for the
specified data input and clock waveforms. Assume that the
register is initially cleared (all 0s).

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 *Related problem
Show the states of the register if the data input is inverted. The
register is initially cleared.
A conventional 8-bit serial in/serial out shift register logic block
symbol is depicted in the figure below. The “SRG 8” label implies
an 8-bit shift register (SRG).

Logic symbol for an 8-bit serial in/serial out shift register.

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 Serial In/Parallel Out Shift Registers
Data is inserted sequentially (least-significant bit first) into a
serial in/parallel out shift register, following the same methods as
serial in/serial out registers. One distinction is how data bits are
extracted from the register. In parallel output registers, the output
of each stage is available.

After storing data, all bits display on their output line

simultaneously, unlike serial output. The figure below displays a
4-bit serial in/parallel out shift register and its logic block symbol.

A serial in/parallel out shift register.

Show the states of the 4-bit register (SRG 4) for the data input
and clock waveforms in Figure (a) below. The register initially
contains all 1s.

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 The register contains 0110 after four clock pulses.

*Related Problem
If the data input remains 0 after the fourth clock pulse, what is the
state of the register after three additional clock pulses?

Parallel In/Serial Out Shift Registers

-In parallel data input registers, bits are entered concurrently on
parallel lines, unlike serial data inputs where bits are entered bit-
by-bit on one line. The serial output is the same as in serial
in/serial-out shift registers after data is fully saved.

-An example logic symbol and 4-bit parallel in/serial out shift
register are shown below. Four data-input lines (D0, D1, D2, and
D3) plus a SHIFT/LOAD input enable for concurrent loading of
four bits of data into the register.

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-LOW SHIFT/LOAD enables gates G1 through G4, applying
each data bit to its flip-flop's D input. A clock pulse sets flip-flops
with D = 1 and resets those with D = 0, storing all four bits
simultaneously.

-SHIFT/LOAD HIGH enables data bits to transfer from stage to

stage by disabling gates G1 through G4 and enabling gates G5
through G7. The OR gates enable regular shifting or parallel data
entry, depending on the level of AND gates activated on the
SHIFT/LOAD input.

-Note that FF0 includes a single AND to deactivate parallel input

D0. There is no need for an AND/OR combination as there is no
serial data.

A 4-bit parallel in/serial out shift register.

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Show the data-output waveform for a 4-bit register with the
parallel input data and the clock and SHIFT/LOAD waveforms
given in Figure below. Refer to Figure (a) above for the logic
diagram.6

Implementation: 8-bit parallel load shift register

The 74HC165 is an example of a fixed-function IC shift register
that has a parallel in/serial out operation (it can also be operated
as serial in/serial out). The figure depicts a common logic block
symbol. A LOW on the SHIFT/LOAD input (SH/LD) allows
asynchronous parallel loading. Data can be entered serially on the

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(Serial) SER input. High on the clock inhibit (CLK INH) input
inhibits the clock whenever. The register's serial data outputs are
Q7 and its complement, differing from the synchronous approach
of parallel loading. This shows that many methods can achieve
the same purpose.

The 74HC165 8-bit parallel load shift register.

Sample timing diagram for a 74HC165 shift register.

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Parallel In/Parallel Out Shift Registers
We've explored simultaneous data entry and output. The parallel
in/ Parallel out register uses both approaches. Once all data bits
are entered simultaneously, they appear on parallel outputs. The
figure below depicts a parallel in/ parallel out shift register.

Implementation: 4-bit parallel-access shift register

The 74HC195 supports parallel in/ parallel out. Due to its serial
input, it is able to perform serial in/serial out and serial in/parallel
out operations. Using Q3 as the output allows parallel in/serial out
operation. The figure below shows a common logic block symbol.

The 74HC195 4-bit parallel access shift register.

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When the SHIFT/LOAD input (SH/LD) is LOW, the parallel
inputs enter data synchronously on the clock's positive transition.
Stored data shifts right (Q0 to Q3) synchronously with the clock
when (SH/LD) is HIGH. Inputs J and K provide serial data to the
first stage of the register (Q0), whereas Q3 outputs serial data.
Asynchronous active-LOW clear input.

Sample timing diagram for a 74HC195 shift register.

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 Bidirectional Shift Registers
Data can be shifted left or right in a bidirectional shift register.
Implemented utilizing gating logic, it transfers data bits between
stages to the right or left based on control line levels.

Four-bit bidirectional shift register.

-The figure illustrates a 4-bit bidirectional shift register. A HIGH

on the RIGHT/LEFT control input shifts data bits to the right,
while a LOW shifts data bits to the left.

-An analysis of the gating logic reveals the operation. Gates G1

through G4 are activated when the RIGHT/LEFT control input is
HIGH, passing the Q output of each flip-flop to the D input of the
next flip-flop.

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-For each clock pulse, the data bits are moved one point to the
right. Gates G5-G8 are activated when the RIGHT/LEFT control
input is LOW, passing the Q output of each flip-flop to the D input
of the previous flip-flop. Each clock pulse shifts the data bits one
position to the left.

Determine the state of the shift register in Figure below after each
clock pulse for the given RIGHT/LEFT control input waveform
in Figure (a). Assume that Q0 = 1, Q1 = 1, Q2 = 0, and Q3 = 1
and that the serial data-input line is LOW.

Related problem
Invert the RIGHT/LEFT waveform, and determine the state of the
shift register in the Figure below after each clock pulse.

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 Implementation: 4-bit bidirectional universal shift register
The 74HC194 functions as a universal bidirectional shift register
in integrated circuit design. The universal shift register has serial
and parallel input and output capabilities. The figure displays a
logic block symbol, and a timing diagram may be seen below.

The 74HC194 4-bit bidirectional universal shift register.

Sample timing diagram for a 74HC194 shift register.

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-Parallel loading, synchronized with a clock-positive transition,
involves applying four bits of data to parallel inputs and a HIGH
to S0 and S1 inputs. Shift right occurs synchronously with the
clock's positive edge when S0 is HIGH and S1 is LOW.

-In this mode, serial data is entered using the shift-right serial
input (SR SER). When S0 is LOW and S1 is HIGH, data bits shift
left with the clock, and fresh data is entered at the shift-left serial
input (SL SER). Input SR SER enters Q0, whereas SL SER enters
Q3.

Shift Register Counters

-A shift register counter uses a shift register with a serial output
coupled to the serial input to generate special sequences. These
devices are commonly referred to as counters due to their specific
state sequence. This section introduces two typical shift register
counters: the Johnson counter and the ring counter.
The Johnson Counter
A Johnson counter connects the complement of the last flip-flop
output to the D input of the first flip-flop (or different flip-flops).

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-When the counter starts at 0, the feedback configuration results
in a distinct state sequence, as illustrated in the Table above for 4-
bit and 5-bit devices. Take note that the 4-bit sequence has eight
states, and the 5-bit sequence has 10 states.
-A Johnson counter typically produces a modulus of 2n, where n
is the number of steps.
The figure below shows 4 and 5-stage Johnson counter
implementations. Implementing a Johnson counter is simple and

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consistent throughout all phases. The Q output of each stage
connects to the D input of the next stage (assuming D flip-flops).

The only difference is connecting the Q output of the last stage to

the D input of the first stage. If the counter starts at 0, it will "fill
up" with 1s from left to right, followed by 0s again, as seen in the
two tables above.

Timing sequence for a 4-bit Johnson counter.

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 Timing sequence for a 5-bit Johnson counter.

The Ring Counter

Ring counters use one flip-flop per state. No decoding gates are
needed, making it advantageous. A 10-bit ring counter produces
distinct outputs for each decimal digit.

A 10-bit ring counter

-Q is fed back from the last stage instead of 𝑄 in a Johnson

counter, but the interstage connections are the same.

-Ten counter outputs show the clock pulse's decimal count.

Example: A 1 on Q0 indicates zero, 1 on Q1 indicates one, 1 on

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Q2 indicates two, 1 on Q3 indicates three, and so on. Check that
the 1 is always kept in the counter and moved "around the ring,"
progressing one stage every clock pulse.

Determine each Q output waveform for a 10-bit ring counter

with an initial state 1010000000, as shown in Figure.

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 Related problem
If a 10-bit ring counter has an initial state 0101001111, determine
the waveform for each Q output.

Shift Register Applications

Shift registers are found in many types of applications, a few of
which are presented in this section.
Time Delay

In a serial in/serial out shift register, the time delay between input
and output is determined by the number of stages (n) and clock
frequency.

The shift register as a time-delay device.

-As demonstrated in the Figure above, a data pulse sent to the

serial input reaches the first stage on the clock pulse's triggering

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edge. After each clock pulse, it is transferred to the next step until
it arrives on the serial output n clock periods later.

This time delay operation is illustrated in Figure above, in which

an 8-bit serial in/serial out shift register is used with a clock
frequency of 1 MHz to achieve a time delay (𝑡𝑑 ) of 8𝜇𝑠 (8x1𝜇𝑠).
This time can be adjusted up or down by changing the clock
frequency.

Determine the amount of time delay between the serial input and
each output in Figure below Show a timing diagram to illustrate.

The clock period is 2 𝜇s. Thus, the time delay can be increased or
decreased in 2 𝜇s increments from a minimum of 2 𝜇s to a
maximum of 16 𝜇s, as illustrated in Figure below.

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The time delay can be increased by cascading shift registers and
lowered by using outputs from lower stages, as seen in the
example above.
*Related Problems
Determine the clock frequency required to obtain a time delay of
24 𝜇s to the Q7 output in Figure above.

IMPLEMENTATION: A RING COUNTER

Connecting the output to the serial input allows a shift register to
function as a ring counter. The figure below shows the application
using a 74HC195 4-bit shift register.

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 74HC195 connected as a ring counter.

The counter may be programmed with a bit pattern of 1000 or any

other pattern by applying it to parallel data inputs, lowering
SH/LD input, and applying a clock pulse. The 1 circulates around
the ring counter after startup, as shown in the timing diagram in
Figure.

A timing diagram showing two complete cycles of the ring counter

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Serial-to-Parallel Data Converter

Serial data transfer of digital systems is often utilized to minimize

wire numbers in transmission lines. One wire can convey eight
bits serially, while eight wires are needed to transfer the same data
in parallel. Serial data transmission is commonly used by
peripherals to transfer data to computers. USB (universal serial
bus) connects keyboards, printers, scanners, and more to
computers.

All computers process data in parallel, requiring serial-to-parallel

conversion. The figure below depicts a basic serial-to-parallel
data converter using two types of shift registers.

Simplified logic diagram of a serial-to-parallel converter.

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The serial data format in the Figure below is used to demonstrate
the operation of this serial-to-parallel converter. The bit count is
11. The start bit is always 0 and starts with a HIGH-to-LOW
transition.

The next eight bits (D7-D0) are data bits (one can be parity), and
the last one or two bits (stop bits) are invariably 1s. The absence
of data results in a persistent HIGH on the serial data line.

Serial data format.

When the start bit transitions from HIGH to LOW, the control
flip-flop activates the clock generator. A specified delay period
triggers the clock generator to generate a pulse waveform for the
data-input register and divide-by-8 counter.

The clock matches the frequency of the incoming serial data, with
the first pulse occurring with the first data bit. These basic
operations are shown in the time diagram below: Eight data bits
(D7-D0) are sequentially shifted into the data-input register.

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 A timing diagram illustrating the operation of the serial-to-parallel data converter.

-After the eighth clock pulse, the terminal count (TC) changes
from LOW to HIGH, signaling the counter's final state. The rising
edge is ANDed with the HIGH clock pulse, resulting in a rising
edge at TC. CLK.
-A parallel load of eight data bits is made from the data-input shift
register to the data-output register. Shortly after, the clock pulse

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transitions from HIGH to LOW, triggering a one-shot pulse that
clears the counter, resets the control flip-flop, and disables the
clock generator.
-To proceed with the next eleven bits, the system awaits the next
HIGH-to-LOW transition at the start bit.
-Reversing the procedure allows parallel-to-serial data
conversion. The sequence needs start and stop bits to create serial
data.
Universal Asynchronous Receiver Transmitter (UART)
-Computers and microprocessor-based systems frequently send
and receive data in parallel. These systems often communicate
with external devices that send/receive serial data.
-The Universal Asynchronous Receiver Transmitter (UART) is
an interface device used for these conversions. The figure below
shows the UART in a typical microprocessor-based system.

UART interface.

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The block diagram below illustrates how a UART converts serial-
to-parallel and parallel-to-serial.

Basic UART block diagram.

A data bus is a parallel conductor system that transfers data
between the UART and the microprocessor system. A buffer
connects the data registers to the data bus.

UART accepts serial data, transforms it to parallel, and transfers

it to the data bus. The UART receives parallel data from the data
bus, translates it to a serial format, and sends it to an external
device.

Keyboard Encoder

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-The keyboard encoder exhibits the usage of a shift register as a
ring counter in combination with other devices. Chapter 6
introduced a simplified computer keyboard encoder without data
storage.

This figure illustrates a simple keyboard encoder that encodes key

closures in an eight-row, eight-column 64-key matrix.

More notes on page 476

Simplified keyboard encoding circuit.

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 Logic Symbols with Dependency Notation
Two examples of ANSI/IEEE Standard 91-1984 symbols using
dependency notation for shift registers are shown. We utilize
two IC shift registers as examples.

Logic symbol for the 74HC164.

Logic symbol for the 74HC194.

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 Troubleshooting

Sample test pattern.

Basic test setup for the serial-to-parallel data converter

Proper outputs for the circuit under test in the Figure above

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 Block diagram of the security system.

Block diagram of the security code logic with keypad.

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Logic diagram of the code-selection logic.

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