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Nov Dec 2017

This document appears to be an exam paper for a digital CMOS design course. It contains 8 questions related to topics in digital CMOS design. The questions cover topics such as technology scaling, CMOS fabrication processes, power dissipation calculations, MOSFET performance parameters, layout dimensions, logic design and implementation, transmission gates, finite state machines, domino logic, dynamic circuits, and high-speed design methodologies. The questions range from derivations and explanations to circuit designs and implementations.

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0% found this document useful (0 votes)
51 views2 pages

Nov Dec 2017

This document appears to be an exam paper for a digital CMOS design course. It contains 8 questions related to topics in digital CMOS design. The questions cover topics such as technology scaling, CMOS fabrication processes, power dissipation calculations, MOSFET performance parameters, layout dimensions, logic design and implementation, transmission gates, finite state machines, domino logic, dynamic circuits, and high-speed design methodologies. The questions range from derivations and explanations to circuit designs and implementations.

Uploaded by

manash
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Total No. of Questions : 8] SEAT No.

P4299 [Total No. of Pages : 2

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3:4
M. E. (E & TC) (VLSI & Embedded Systems)

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DIGITAL CMOS DESIGN

9
01
8 1 30
.23 01 (2017 Pattern)

Time : 3 Hours] 2/1 [Max. Marks : 50


P

Instructions to the candidates:


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1) Answer any five questions.


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2) Assume suitable data if necessary.


3) Neat diagrams must be drawn wherever necessary.

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4) Use of nonprogrammable calculator is allowed.
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3:4
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Q1) a) What is technology scaling? Explain the types & effects in detail. [5]
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b) Explain any one type of CMOS fabrication process in detail. [5]
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2/2
01
2/1

Q2) a) Derive the expressions for static & dynamic power dissipations in CMOS
GP
81

logic. Compare these dissipations. [5]


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b) Explore delay estimation techniques in detail. [5]


CE
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8.2

Q3) a) Draw ac equivalent ckt of MOSFET & explain various performance


parameters. [4]
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2:2

b) Explain various resistances & capacitances pertaining to MOSFET &


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wire interconnect that are involved in layout. [4]


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c) Draw layout cross section diagram of CMOS Inverter and mention the
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30

dimensions. [2]
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Q4) a) Certain logic has load of 10 pF, supply voltage of 1 Volt & operates at
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1GHz. Calculate total dissipation if number of MOSFETs is 100 & leakage


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current per MOSFET is 1 pA. Calculate power delay product for this
CE

logic if propagation delay is 10ps. [4]


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8.2

b) What is cross talk? What are the sources & solutions? [4]
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c) Write note on fan in & fan out. [2]


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P.T.O.
Q5) a) Design CMOS logic for Y=ABC + D + EF. Calculate active area. Assume
technology of 90 nm. [4]
b) Draw a flip flop using Transmission Gates (TG) & its timing diagram.[4]

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c) Explain the concept of tristate logic? [2]

3:4
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9
01
Q6) a) Draw FSM diagram & write HDL code for 1110 Moore sequence detector.[4]
b) 8 1 30
What are the sources of metastability? What are the solutions? Explore
.23 01
with example. 2/1 [4]
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P

c) What are the merits & demerits of Transmission Gates? [2]


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Q7) a) With the help of schematic, explain the concept of ratioed ckts. [4]

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b) Explore domino logic in detail. [4]
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c) Write note on materials for performance improvement. [2]
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2/2

Q8) a) Explain dynamic ckts. [4]


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2/1

b) What are the methodologies for high speed design? Explain any one of
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them. [4]
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CE

c) What is need of BiCMOS? Explain in brief. [2]


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2:2
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GGG
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CE
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[5255]-1054 2

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