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M. E. (E & TC) (VLSI & Embedded Systems)
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DIGITAL CMOS DESIGN
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.23 01 (2017 Pattern)
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4) Use of nonprogrammable calculator is allowed.
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Q1) a) What is technology scaling? Explain the types & effects in detail. [5]
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b) Explain any one type of CMOS fabrication process in detail. [5]
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Q2) a) Derive the expressions for static & dynamic power dissipations in CMOS
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c) Draw layout cross section diagram of CMOS Inverter and mention the
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dimensions. [2]
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Q4) a) Certain logic has load of 10 pF, supply voltage of 1 Volt & operates at
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current per MOSFET is 1 pA. Calculate power delay product for this
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b) What is cross talk? What are the sources & solutions? [4]
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Q5) a) Design CMOS logic for Y=ABC + D + EF. Calculate active area. Assume
technology of 90 nm. [4]
b) Draw a flip flop using Transmission Gates (TG) & its timing diagram.[4]
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c) Explain the concept of tristate logic? [2]
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Q6) a) Draw FSM diagram & write HDL code for 1110 Moore sequence detector.[4]
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What are the sources of metastability? What are the solutions? Explore
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with example. 2/1 [4]
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Q7) a) With the help of schematic, explain the concept of ratioed ckts. [4]
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b) Explore domino logic in detail. [4]
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c) Write note on materials for performance improvement. [2]
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b) What are the methodologies for high speed design? Explain any one of
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them. [4]
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GGG
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