United States Patent (19) (11) 4,137,570

Baker (45) Jan. 30, 1979

(54) WAVEFORMSYNTHESIZER their respective output terminals a voltage having the
(75) Inventor: Richard H. Baker, Bedford, Mass. level of the DC voltage, or about twice the level of the
73) Assignee: Exxon Research & Engineering Co., DC voltage. A first pair of transistorized switches are
included for concurrently and selectively connecting
Florham Park, N.J. the output terminal of one of the level shifters to one
(21) Appl. No.: 846,697 end of a load, and ground to the other end, respectively,
22 Filed: Oct. 31, 1977 for driving current through the load in a particular
direction and obtaining a desired level and polarity of
51) Int. Cl. ............................................ H02M 7/537 voltage thereacross, or the switches are operated to
52 U.S.C. ....................................... 363/43; 363/132 ground both ends of the load. In generating a stepwise
58) Field of Search ....................... 363/17, 41, 43, 59, approximation of a symmetrical AC waveform, such as
363/60, 110, 131, 132 a sinewave, one level shifting stage is charging from the
56) References Cited DC voltage supply while the other level shifting stage is
U.S. PATENT DOCUMENTS discharging into the load, during each half-cycle of the
AC voltage. A second pair of transistorized (or mechan
3,248,633 4/1966 Guarrera ........................... 363/59 X ical) switches are added for selectively connecting each
3,371,232 2/1968 Hannan et al. .................... 363/59 X one of the first pair of transistorized switches in parallel
3,851, 182 11/1974 Wallace ............................. 363/60 X with a transistorized switch of each one of the first and
FOREIGN PATENT DOCUMENTS second level shifting stages, respectively, for operating
2035223 1/1972 Fed. Rep. of Germany ............. 363/59 the waveform synthesizer at half-rated voltage, and
twice-rated current. Also included is a control signal
Primary Examiner-William M. Shoop generator for operating the switches and level shifting
Attorney, Agent, or Firm-Kenneth Watov stages in a manner providing in combination concurrent
(57) ABSTRACT dynamic level shifting and pulse width modulation in
A circuit for inverting a DC voltage to an AC voltage synthesizing a desired AC waveform.
having a predetermined waveform, includes first and
second level shifting stages for providing selectively at 17 Claims, 8 Drawing Figures

-------ONE OFSTAGES
in CASCADED
U.S. Patent Jan. 30, 1979 Sheet 1 of 3 4,137,570
U.S. Patent Jan. 30, 1979 Sheet 2 of 3 4,137,570
ONE OF N CASCADED
STAGES

ONE OF 37' ONE OF N CASCADED

CASCADED --------- --it- STAGES

48 38
U.S. Patent Jan. 30, 1979 Sheet 3 of 3 4,137,570

C3 C4 C5 C C Ca

52
CONTROLLER

- Air. At
 4,137,570
1 2
level of voltage at point B is about Evolts, and capaci
WAVEFORMSYNTHESEZER tor 104 begins taking on charge. If switch 1 is main
tained in its down position for a sufficient period of
The field of the invention relates generally to electri time, capacitor 104 will fully charge, resulting in a volt
cal waveform synthesizers, and more particularly to age drop across capacitor 104 of Evolts. Thereafter, if
DC or AC voltage converters. switch S1 is now operated to connect its pole 3 to its
Many different circuits are known in the art for con upper contact 1, the capacitor 104 is connected in series
verting a DC voltage into an AC voltage. These circuits with the DC voltage supply or battery 100, raising the
tend to be very complex, requiring a large number of level of voltage at point B to 2E volts. Switch S2 is
components, resulting in high cost and reduced reliabil 10 operated to its upper position connecting its pole 3 to its
ity. Also, many of these prior art circuits are limited to upper contact 1, for applying the voltage at point B to
converting a DC voltage into an AC voltage at a given point A, and to its lower position for connecting its pole
frequency, and also the AC voltage is usually high in 3 to its lower contact 5 for applying ground to point A.
harmonics, which is undesirable in many applications. By selectively operating switches S1 and S2 between
The present invention is a waveform synthesizer cir 15 their respective upper and lower positions in different
cuit capable of converting a DC voltage into a desired combinations at different times, the two-level unipolar
AC waveform, such as a sinewave, for example. In a ity notched waveform shown in FIG. 2, can be obtained
first embodiment, a first level-shifting stage is included at point A, for example. Control signals are selectively
for selectively applying a voltage having a level equal applied to the operating terminals 114, 116, and 118,
to or greater than that of a DC voltage supply to a pair 20 120, of SCR's 106, 108, 110 and 112, respectively, for
of transistorized switches. A second level-shifting stage turning on and offin pairs, that is, 106 and 112 together,
is included, permitting the two level shifting stages to be 108 and 110 together, to operate the mixer network for
individually operated during alternate half-cycles of the converting the two-level waveform of FIG. 2 into the
AC waveform, respectively, thereby decreasing the four-level waveform of FIG. 3, for example. In this
duty cycle time for each one of the level-shifting stages. 25 manner, a stepwise approximation of a sinewave can be
The transistorized switches of the two stages are selec generated, for example. A major disadvantage of this
tively operated for applying this voltage across a load SCR mixer circuit is the complexity of the circuitry
and driving current through the load in a given direc necessary to turn off the conducting ones of the SCR's
tion, or for grounding the load. In a second embodi 106-112, 108-110. It should be noted that an SCR is a
ment, in addition to the inclusion of a second level-shift 30 solid-state switching device that can be turned on by
ing stage, a pair of mechanical or transistorized switches applying a control signal to its control terminal, but can
are included with the other pair of transistorized be turned off only by either interrupting the flow of
switches, respectively, and are operated for selectively current to its main current conduction path, or
providing either rated voltage and rated current opera backbiasing the anode-cathode electrodes of its main
tion, or half-rated voltage and twice-rated current oper 35 current path.
ation. In FIG. 4, a waveform synthesizer circuit includes a
In the drawings, where like items are indicated by the DC voltage supply or battery 136 having an output
same reference designation: voltage of level Evolts; at least one level-shifting stage
FIG. 1 is a circuit schematic diagram of a prior art 137 including a switch S3, a diode 138, and a capacitor
DC to AC converter; 40 140; and a pair of switches S4, and S5. The level-shifting
FIG. 2 shows a typical two-level unipolarity wave stage 137 is identical in operation to the level-shifting
form that might be produced at point A in the circuit of stage S1, 102, 104 of FIG. 1. As previously described,
FIG. 1; such a level-shifting stage 137 is capable of either unity
FIG. 3 shows a typical four-level notched stepwise gain level shifting or voltage doubling. As indicated in
approximation of an AC waveform, in this example a 45 FIG. 4, such level-shifting stages 137 can be cascaded
sinewave; for selectively providing at point D, a voltage having a
FIG. 4 is a circuit schematic diagram of a waveform level equal to Evolts 2E volts, 3E volts up to NEvolts,
synthesizer circuit; where N is some integer number equal to the number of
FIG. 5 is a circuit schematic diagram of a first em cascaded level-shifting stages 137. For the purposes of
bodiment of the invention; 50 this discussion, it is assumed that only one stage of level
FIG. 6 is a circuit schematic diagram of a second shifting is provided (N= 1). The switches S3 and S4
embodiment of the invention; correspond to the switches S1 and S2, whereas the
FIG. 7 is a circuit schematic diagram of a high-power switch S5 replaces the entire SCR mixercircuit 106,108,
switching amplifier; and 110, 112, 122, 124, 126, 128 of FIG. 1.
FIG. 8 is a block diagram of a controller for provid 55 In operation, switch S3 is operated to connect its pole
ing control signals for operating the various transistor 41 to its upper contact 45, or lower contact 43, for
ized switches of the present invention. applying either E or 2E volts at point C, respectively. A
In FIG. 1, a prior art DC to AC converter includes a typical waveform that can be so generated at point C is
DC voltage supply 100 (shown as a battery) having a shown in FIG. 2, for example. The time duration for the
level of voltage equal to E volts, a level-shifting stage waveform to be at any given level is determined by the
including a pair of switches S1, S2, a diode 102, and a length of time that the switch S3 is held in either its
capacitor 104; and a bridge-connected SCR mixer net upper or lower position. In this manner, dynamic level
work including SCR's 106, 108, 110 and 112, each hav shifting is provided, concurrent with pulse width modu
ing a control terminal 114, 116, 118, 120, respectively; lation of the voltage steps between the +E and +2E
four diodes 122, 124, 126, 128; and a pair of output 65 levels of voltage. The switch S4 is operated to its upper
terminals 130 and 132 between which a load impedance position (arm 41 connected to contact 45) concurrent
134 may be connected. In operation, when switch S1 is with switch S5 being operated to its lower position (arm
operated to connect its pole 3 to its lower contact 5, the 41 connected to contact 43) for a direction of current
 4,137,570
3 4.
flow from switch 4 to output terminal 142, through load forms are generated, then one or the other of the level
144, into output terminal 146, through switch S5, to shifting stages 137 and 137" will be operated for more
ground terminal 148, causing a voltage drop across the than half of the period of the nonsymmetrical waveform
load 144 of the polarity indicated. For opposite direc generated, in most instances. Accordingly, the circuit of
tion of current flow through the load and a resultant FIG. 5 can be operated for generating a broader range
opposite polarity of voltage across the load, switch S4 is of frequencies of synthesized waveforms, because the
operated to its lower position (arm 41 connected to capacitors 140 and 150 are kept at a higher level of
lower contact 43) concurrent with switch S5 operated charge throughout the period of the generated wave
to its upper position (arm 41 connected to contact 45). form.
For applying zero volt across the load, that is, ground 10 In FIG. 6 a second embodiment of the invention is
ing both output terminals 142 and 146, switches S4 and shown. In comparison to the embodiment shown in
Ss are concurrently operated to their downward posi FIG. 5, a pair of switches S7 and S8 have been added as
tions (arms 41 connected to contacts 43). In this manner, shown. In operation, if the switches S7 and S8 are oper
the bipolar waveform shown in FIG. 3 can be obtained, ated to their upper positions, the operation of the circuit
for example, from a waveform such as shown in FIG. 2 15 of FIG. 6 is identical to that of the circuit of FIG. 5. If
being generated at point C, as previously described. the switches S7 and Ss are operated to their lower posi
Such operation of the switches S4 and S5 also provides tions, the switches S5 and S6 are connected in parallel
for pulse width modulation of the first steps or levels of operation with respect to output terminal 146, and simi
voltage occurring between zero and --E and zero and larly, the switches S3 and S4 are connected in parallel
-E. The waveform shown in FIG. 3 is as previously 20 with respect to ouput terminal 142. Accordingly, when
mentioned a stepwise approximation of a sinewave, but switches S5 and S6 are operated to their upper positions,
it should be noted that through proper control of the concurrent with switches S3 and S4 operated to their
switches S3, S4, S5 many other non-sinusoidal stepwise lower positions, current will flow from the battery 136
approximated AC voltage waveforms, the frequency of through switches S6 and S7 to output terminal 146, and
which can be selectively varied, can be synthesized. In 25 from battery 136 through diode 148 and switch S5 to
FIG. 3, the notches are placed at predetermined times output terminal 146, through the load 144 into output
and have predetermined widths, for reducing the har terminal 142, and therefrom both through switch S4 to
monic content of the approximated waveform. ground and through switches S8 and S3 to ground. As
In FIG. 5, a first embodiment of the invention is suming that the switches S3, S4, S5, S6, S7 and S8 all have
shown. The circuit is substantially identical to the cir 30 the same current rating, it should be clear that a magni
cuit of FIG. 4, with the addition of a second stage of tude of current twice that obtainable from the circuit of
level shifting 137' or N'-cascaded stages of level shifting FIG. 5 can be supplied to the load 144, but only at a
137 (for purposes of this discussion N'=1). This addi voltage level of Evolts, for be necessity the capacitors
tional stage of level shifting 137 is connected between 150 and 140 are out of the circuit. For reversing the
the upper contact 45 of switch S5 and the battery 136. 35 flow of twice rated current through the load 144, the
The advantage of the circuit of FIG. 5 over that of FIG. switches S5 and S6 are operated to their lower positions,
4 is that in generating a symmetrical waveform such as and the switches S3 and S4 are operated to their upper
shown in FIG. 3, during a period of time T1, switches positions. For applying zero volts across the load,
S3 and S4 are operated to their upper positions, and switches S3 through S6 are operated to their lower posi
switches S5 and S6 to their lower positions, for driving tions, for example, thereby grounding output terminals
current through the load 144 in a direction to produce 142 and 146. In other words, in operating the circuit of
the polarity of voltage indicated, whereby capacitor 140 FIG. 6, with switches S7 and S8 in their upper positions,
is discharging through the load and connected in series a voltage of up to --2E volts can be applied across the
with the battery E, for producing the voltage steps load 144, and a magnitude of current equal to the cur
+2E, for example. If switch S3 is operated to its lower 45 rent rating of the switches S3 through S8 can be driven
position, a voltage level of +E is applied across the through the load. With switches S7 and S3 operated to
load 144 and the capacitor 140 takes on charge from the their lower positions, a voltage level of Evolts can be
battery 136 via diode 138. During this period of time T1, applied across the load 144, and a current having a
the capacitor 150 of the second level shifting stage is magnitude equal to twice the rated current magnitude
permitted to fully charge to the point where the voltage 50 of the switches S3-S8 can be supplied to the load 144.
drop across capacitor 150 is substantially equal to E Such a circuit may be useful in operating an electric
volts. During the time period T2 of the next half-cycle motor, for example, through a range of speeds at differ
of the stepwise approximated AC waveform shown in ent levels of torque.
FIG. 3, switches S3 and S4 operated to their lower posi It should be noted that capacitors 140 and 150 can
tions, switch S5 to its upper position, and switch S6 55 each be replaced by either a solar cell, a solar cell panel,
between its upper and lower positions for generating a battery, a fuel cell, or any other electrical energy
the -E and -2E levels of steps of voltage. By using at storage means. When any such substitution is made for
least two level-shifting stages 137, 137" in the manner capacitors 140 and 150, the diodes 138 and 148 can be
shown in FIG. 5, in generating symmetrical waveforms eliminated (assume n = 1 for FIG. 5). However, when
such as shown in FIG. 3, the levelshifting stages 137 and batteries are substituted for the capacitors 140, 150 in
137" are required for active use during only alternate many applications it is desirable to retain the diodes 138,
half-cycles of the AC waveform. Contrarywise, in the 148 to permit recharging of the batteries at such times
circuit of FIG. 4, the level-shifting stage 137 must be that the analogous one of capacitors 140 and 150 are
operated over the entire period or full cycle (T + T2) charging, as previously described. Similarly, the battery
of the AC waveform. Accordingly, the circuit of FIG. 65 136 of FIGS. 5 and 6 can be replaced by either a solar
5, in generating symmetrical waveforms, reduces the cell, solar cell panel, fuel cell, and so forth.
duty cycle of the level-shifting stages 137, 137" by a In FIG. 7, a high-power switching amplifier circuit is
factor of one-half. Of course if nonsymmetrical wave shown, suitable for serving as each one of the switches
 5
4,137,570 6
S3 through S8 (see FIGS. 4-6). Of course, as previously ing terminal 45 through the main current path of the
mentioned, in FIG. 6 the switches S7 and S8 can each be Darlington amplifier 27, 29 to the output terminal 41,
mechanical or electromechanical, if desired. A detailed raising the level of voltage at the output terminal to a
explanation of the operation of the switching circuit of positive level, permitting capacitor 73 to begin dis
FIG. 7 is found in my copending application U.S. Ser. charging initially through the circuit of resistor 81 in
No. 829,334, filed Aug. 31, 1977, for HIGH-POWER parallel with a series circuit of resistor 79 and capacitor
SWITCHING AMPLIFIER. Reference is made to 77, the main current path of transistor 83, into the base
FIG. 6 of this high-power switching amplifier applica electrode of NPN transistor 27. Once the speedup ca
tion, which figure is identical to the circuit shown in pacitor 77 becomes appreciably charged, it appears as
FIG. 7 of the present application, even as to reference 10 an open circuit, effectively removing resistor 79 and
designations. For purposes of this discussion, it should itself from the parallel connection with resistor 81.
be noted that the switching circuit of FIG. 7 is preferred Therefore, when this occurs, the effective resistance of
for use in providing the switching functions of each one the parallel circuit is increased to the value of resistance
of the switches S3-S8, for switching current levels up to of resistor 81 through which all of the current is now
about 100 amperes at voltages at about 600 volts. For 15 passing. The speedup circuit of resistor 79 and capacitor
lower power applications, other transistorized switch 77 is known in the art, enhances the turnon time for
ing circuits can be applied for use for providing each transistor 83, and accordingly also the turnon time of
one of the switches S3-S8. the Darlington amplifier 27, 29. The capacitor 73, while
In FIG. 7, when a control signal having a positive discharging into the Darlington amplifier 27, 29, acts to
level of voltage (hereinafter referred to as a level of "1") 20 increase the level of voltage applied to the base elec
is applied to the control terminal 33, the NPN Darling trode (voltage at terminal 41 plus voltage across capaci
ton amplifier 37, 39 responds by turning on for substan tor 73) of NPN transistor 27 to ensure that the Darling
tially connecting output terminal 41 to ground via the ton amplifier 27, 29 goes into saturation for substantially
main conduction path of the Darlington 37, 39, and the applying the operating voltage connected to terminal 45
high voltage inverting amplifier 59 responds by produc 25 to output terminal 41. Resistors 69 and 38 are current
ing a low-level or ground signal at point A. At this time, limiting resistors, and resistor 61 serves as an isolation
NPN transistor 83 is turned off, and diodes 62, 63, 65 resistor.
and 67 are forward biased, permitting capacitor 73 to Assume that each one of the switches S3 through S3
take on charge from the voltage source supplying the are provided by a transistorized switching circuit such
voltage applied to operating voltage terminal 45. When 30 as shown in FIG. 7. In such a case, six individual control
the control signal goes low (hereinafter referred to as signals herein designated as C3 through C8, must be
level "0", the Darlington amplifier 37, 39 turns off, and applied to the respective control terminals 33 of each
the inverting amplifier 59 responds by changing the one of the switches S3 through S8, respectively, for
level of its output signal to a positive voltage. When operating these switches to produce a desired wave
point B is allowed to go positive (no longer held at a 35 form. A controller, such as the block 152 shown in FIG.
negative potential), diode 62 becomes back biased, and 8, is required to supply the control signals C3 through
the current flowing through resistor 75 flows into the C8. In those applications where programmability is not
base electrode of and causes NPN transistor 83 to turn important, that is, where only a single waveform is
on. At the time of turnon of transistor 83, the speedup desired to be synthesized from a DC voltage source 136,
capacitor 77 appears as a short-circuit or closed conduc the controller 152 can be hardwired digital logic. If it is
tion path, causing resistors 79 and 81 to be placed in required that any given one of a plurality of waveforms
parallel at the instant of turnon, and current flows from be synthesized at a given time, the controller 152 can be
operating terminal 45 through the conduction paths provided by a microprocessor, the microprocessor
including resistors 81, and resistor 79, in series with being programmed for producing the desired wave
capacitor 77, the main conduction path of NPN transis 45 form. As shown in the State Table given below, the
tor 83 (collector-emitter current path), into the base level of the output signal produced across a load for
electrode of NPN transistor 27, thereby turning on the different combinations of a '1' state or "O' state for the
Darlington amplifier 27, 29. When the Darlington am control signals C-C8 for FIGS. 4-6, are as follows:
plifier 27, 29 so turns on, current flows from the operat
STATE TABLE
Circuit Control Signal Level of Output Voltage
Figure No. C3 C4 C5 C6, C7 C8 Across Terminals 142, 146
1 1 O
k
--E
FIG. 4 --2E

FIG. 5
Normal
Operating
: 1
1
0s
-E
-2E
O
-E
-2E
Range 1 --E
l --2E
--E
0. O
O -E
1 1
0

i:
Normal -E
Operating -2E
FIG. 6 Range --E
--2E
--E
O
-E
 7
4,137,570
w 8
STATE TABLE-continued
Circuit Control Signal Level of Output Voltage
Figure No. C3 C4 C5 C5 C, C8 Across Terminals 142, 146.
Normal ( 1 1 0 0 1 1 -E Twice rated
Oper. Range 0 0 , 1- 1 1 1 ---E Current Operation
"Changed to a "1" state and back to "0" state to provide notching. Period of time in "1"'state determines width
of notch,

The high-power switching amplifier circuit of FIG. 7 10 switching means connected between said first and
is an inverting switching amplifier. Accordingly, if a second input terminals of said respective stages,
noninverting transistorized switching amplifier is ap providing a single-pole-double-throw switching
plied for use for providing the switching functions of action, the pole being coupled to the other end of
the switches S3 through S8, the levels of the control said energy storage means, said switching means
signals given in the State Table above must be inverted, 15 being operable to a first state for connecting the
that is, '1' levels will become 'O' levels, and "O' levels other end of said energy storage means to said
will become '1' levels. second input terminal of its stage, permitting said
What is claimed is: energy storage means to charge concurrently with
1. A circuit for inverting a DC voltage to an AC applying the DC voltage to said output terminal of
voltage having a predetermined waveform, comprising: 20 its stage, thereby establishing the first condition for
first and second terminals for receiving said DC volt the stage, and operable to a second state for con
age, said second terminal also being connected to a necting the other end of said energy storage means
point of reference potential; to said first input terminal of said stage, placing the
first and second level shifting stages each having first voltage developed across said energy storage
and second input terminals connected to said first 25 means in series with said DC voltage, said unidirec
and second terminals of said inverting circuit, re tional current means being poled for ensuring that
spectively, and an output terminal, each being op said energy storage means cannot discharge
erable to a first condition for applying said DC through said unidirectional means, thereby estab
voltage to its respective output terminal, and to a lishing the second condition for the stage, at which
second condition for applying a voltage greater in 30 time a level of voltage about twice that of said DC
level than said DC voltage to its respective output voltage is applied to the output terminal of the
terminal; respective level shifting stage.
first and second switching means each having a first 4. The inverter circuit of claim 3, wherein said unidi
input terminal connected individually to the output rectional current means includes a diode.
terminals of said first and second level shifting 35 5. The inverter circuit of claim3, wherein said electri
stages, respectively, a second input terminal con cal energy storage means includes a capacitor.
nected in common to said second terminal of said 6. The inverter circuit of claim3, wherein said electri
inverting circuit, and an output terminal for indi cal energy storage means includes a battery.
vidual connection to one and the other ends of a 7. The inverter circuit of claim 3, wherein said
load, respectively, each one of said switching switching means of each one of said first and second
means providing a single-pole-double-throw level shifting stages, and said first and second switching
switching action, each one of said switching means means of said inverter circuit each include a bilateral
being operable to a first condition for providing a solid-state switching circuit means.
current conduction path between their respective 8. The inverter circuit of claim 1, wherein each one of
first input and output terminals, and to a second 45 said first and second level shifting stages includes:
condition for providing a current conduction path a plurality of n cascaded voltage source stages, each
between their respective second input and output including:
terminals; and unidirectional current means;
means for selectively operating said first and second electrical energy storage means;
level shifting stages, and said first and second 50 switching means providing a single-pole-double
switching means, into different combinations of throw switching function, having first and sec
their first and second conditions, for obtaining said ond power terminals, and an output terminal,
AC voltage. said unidirectional current means and energy
2. The inverter circuit of claim 1, wherein said oper storage means being connected in a series circuit
ating means operates said first and second level shifting 55 between said first power and output terminals,
stages, and said first and second switching means, for said second power terminal being connected to
concurrently providing both dynamic level shifting and said second terminal of said inverter circuit, the
pulse width modulation, for obtaining said AC voltage common connection of said unidirectional cur
having a selectively notched waveform for reducing rent means and energy storage means being con
harmonies. 60 nected to the first power terminal of the next
3. The inverter circuit of claim 1, wherein each one of succeeding voltage source stage, the other end of
said first and second level shifting stages, includes: said energy storage means being connected to
unidirectional current means connected between said said output terminal, the first voltage source
first input and output terminals of said respective stage of said cascaded stages having its first
stages; 65 power terminal connected to the first terminal of
electrical energy storage means having one end con said inverter circuit, and the last voltage source
nected to said output terminal of said respective stages of each one of said first and second level
stages; and shifting stages having the common connection of
 4,137,570
10
its unidirectional current means and energy stor connecting the second output terminal of said DC
age means connected to the first input terminals voltage supply means to said second input terminal
of said first and second switching means, respec of its stage, thereby applying the output voltage of
tively; said DC voltage supply means to said output termi
said switching means of each one of said voltage nal of its stage, establishing the first condition for
source stages being operable in said first condition the stage, and operable to a second state for con
of its respective level shifting stage for providing a necting the second output terminal of said DC
main current path between its output and second voltage supply means to said first input terminal of
power terminals, for charging its energy storage said respective stage, thereby establishing the sec
means and applying said DC voltage to the com 10 ond condition for the stage, at which time a level of
mon connection of its association energy storage voltage equal to the sum of said DC voltage and
means and unidirectional current means, and being the output voltage from said supply means is ap
selectively operable by said operating means in said plied to the output terminal of the respective level
second condition of its respective level shifting shifting stage.
stage, for providing a main current path between 15 11. The inverter circuit of claim 10, further including:
its first power and output terminals, for connecting third switching means having a first input terminal
its associated energy storage means in a series cir connected to the second terminal of said DC volt
cuit with other selected ones of the energy storage age supply means of said first level shifting stage, a
means of said voltage source stages, for applying a second input terminal connected to the output
voltage having a level equal to the level of said DC 20 terminal of said first switching means, and an out
voltage plus the sum of the voltages across each put terminal connected to the output terminal of
one of the series-connected energy sources to the said switching means of said first level shifting
common connection of said unidirectional current stage; and
means and energy storage means of the nth voltage fourth switching means having a first input terminal
source stage. 25 connected to the second terminal of said DC volt
9. The inverter circuit of claim 3, further including: age supply means of said second level shifting
third switching means having a first input terminal stage, a second input terminal connected to the
connected to the other end of said energy storage output terminal of said second switching means,
means of said first level shifting stage, a second and an output terminal connected to the output
input terminal connected to the output terminal of 30 terminal of said switching means of said second
said first switching means, and an output terminal level shifting stage.
connected to the output terminal of said switching said third and fourth switching means each being
means of said first level shifting stage; and operable to a first condition for providing a current
fourth switching means having a first input terminal conduction path between their respective first
connected to the other end of said energy storage 35 input and output terminals, and to a second condi
means of said second level shifting stage, a second tion for providing a current conduction path be
input terminal connected to the output terminal of tween their respective second input and output
said second switching means, and an output termi terminals, whereby when said third and fourth
nal connected to the output terminal of said switch switching means are concurrently operated to their
ing means of said second level shifting stage, first conditions, said inverter circuit is enabled for
said third and fourth switching means each being supplying rated current and voltage to said load,
operable to a first condition for providing a current and when said third and fourth switching means
conduction path between their respective first are concurrently operated to their second condi
input and output terminals, and to a second condi tions, said inverter circuit is enabled for supplying
tion for providing a current conduction path be 45 twice-rated current and half-rated voltage to said
tween their respective second input and output load.
terminals, whereby when said third and fourth 12. The inverter circuit of claim 10, where DC volt
switching means are concurrently operated to their age supply means includes a battery.
first conditions, said inverter circuit is enabled for 13. The inverter circuit of claim 10, where DC volt
supplying rated current and voltage to said load, 50 age supply means includes a solar cell panel.
and when said third and fourth switching means 14. The inverter circuit of claim 10, where DC volt
are concurrently operated to their second condi age supply means includes a fuel cell.
tions, said inverter circuit is enabled for supplying 15. A circuit for converting a DC voltage to a prede
twice-rated current and half-rated voltage to said termined AC voltage having a desired amplitude, fre
load. 55 quency, and waveshape, comprising:
10. The inverter circuit of claim 1, wherein each one first and second primary output terminals for connec
of said first and second level shifting stages includes: tion to a load;
DC voltage supply means having first and second first and second secondary output terminals;
output terminals across which a DC output voltage a first power terminal and a second power terminal
is produced, said first output terminal being con for receiving said DC voltage, said second terminal
nected to said output terminal of said respective also being connected to a point of reference poten
stage; and tial;
switching means connected between said first and first level shifting means connected between said first
second input terminals of said respective stages, and second terminals, including electrical energy
providing a single-pole-double-throw switching 65 storage means, a control terminal for receiving a
action, the pole being coupled to said second out first control signal, responsive to said first control
put terminal of said DC voltage supply means, said signal being "high' for concurrently connecting
switching means being operable to a first state for said first power terminal to said first secondary
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output terminal, and said energy storage means for means each having their second power terminals
charging between said first secondary output ter connected to said common terminal, the second
minal and said second power terminal, and respon power terminal of said fifth switching means being
sive to said first control signal being “low” for connected in common to the output terminal of
connecting said energy storage means between said said third switching means and said third terminal
first power terminal and first secondary output of said converter, the output terminals of said first
terminal, for applying a voltage greater in level and fifth switching means being connected to
than said DC voltage to said first secondary output gether, the output terminals of said second and
terminal, during portions of one-half cycle of said sixth switching means being connected together,
AC voltage; 10 the second power terminal of said sixth switching
second level shifting means connected between said means being connected in common to the output
first and second power terminals, including electri terminal of fourth switching means and fourth
cal energy storage means, a control terminal for terminal of said converter, each one of said switch
receiving a second control signal, responsive to ing means being responsive to their associated con
said second control signal being "high' for con 15 trol signal being "high', for individually establish
necting said first power terminal to said second ing a current conduction path between their re
secondary output terminal, concurrent with con spective output and second power terminals, and
necting its energy storage means for charging be being responsive to their respective control signal
tween said second output terminal and said second being "low", for individually establishing a current
power terminal, and responsive to said second con 20 conduction path between their respective output
trol signal being "low', for connecting its energy and first power terminals;
storage means between said first power terminal first unidirectional current means connected between
and said second secondary output terminal, for and poled for passing current from said operating
applying a voltage greater in level than said DC voltage terminal to said first power terminal of said
voltage to the latter terminal, during portions of 25 third switching means;
the other half-cycle of said AC voltage; second unidirectional current means connected be
first switching means connected between said first tween and poled for passing current from said op
secondary output terminal and said second power erating voltage terminal to said first power termi
terminal, having a control terminal for receiving a nal of said fourth switching means;
third control signal, responsive to said third control 30 first electrical energy storage means connected di
signal being "high' for connecting said second rectly between the first power terminals of said
power terminal to said first primary output termi third and fifth switching means, respectively;
nal, and to said third control signal being "low' for second electrical energy storage means connected
connecting said first secondary and primary output directly between the first terminals of said fourth
terminals together; 35 and sixth switching means, respectively; and
second switching means connected between said sec control signal generator means for producing said
ond secondary output terminal and said second first through sixth control signals in different com
power terminal, having a control terminal for re binations of "high' and “low” levels at predeter
ceiving a fourth control signal, responsive to said mined times within given periods of time, for oper
fourth control signal being "high' for connecting ating said first through sixth switching means to
said second power terminal to said second primary produce said AC voltage, whereby said third and
output terminal, and to said fourth control signal fourth control signals are made “low” and "high',
being “low” for connecting said second secondary respectively, for passing current through said load
output terminal to said second primary output ter in one direction, and contrariwise for passing cur
minal; and 45 rent through said load in the opposite direction,
controller means for generating said first through said fifth and sixth control signals are each made
fourth control signals for producing said predeter “low” for placing said converter in its first mode of
mined AC voltage across said first and second operation, in which mode said first control signal is
primary output terminals. made "high' for charging said first energy storage
16. A DC voltage to AC voltage converter capable of 50 means and applying said DC voltage to the first
synthesizing a predetermined AC waveform at a given power terminal of said third switching means, said
rated current and voltage in a first mode of operation, first control signal is made 'low' for connecting
and at twice-rated current and one-half rated voltage in said first energy storage means between said oper
a second mode of operation, comprising: ating voltage terminal and the first power terminal
an operating voltage terminal for receiving said DC 55 of said third switching means, for applying a volt
voltage; age having a level greater than said DC voltage to
a common terminal for connection to a point of refer said first power terminal of said third switching
ence potential; means, said second control signal is made high for
third and fourth terminals across which said AC concurrently charging said second energy storage
waveform is produced, and for connecting a load 60 means and applying said DC voltage to the first
therebetween; power terminal of said fourth switching means,
first through sixth switching means each having a said second control signal is made low for connect
control terminal for receiving a first through sixth ing said second energy storage means between said
control signals, respectively, an output terminal, operating voltage terminal and the first power
and first and second power terminals, said first and 65 terminal of said fourth switching means, for apply
second switching means each having then first ing a voltage having a level greater than said DC
power terminals connected to said operating volt voltage to said first power terminal of said fourth
age terminal, said first through fourth switching switching means, and said fifth and sixth control
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signals are each made "high" for placing said con 17. A method for stepwise synthesizing from a DC
verter in its second mode of operation, in this sec voltage an AC voltage waveform, having a reduced
ond mode said first and third control signals are harmonic content, comprising the steps of:
each made "low" for connecting said DC voltage dynamically level shifting said DC voltage for obtain
to said third terminal of said converter, and are 5 ing alternatively but not necessarily successively
each made "high" for connecting said reference two different levels of both positive and negative
potential to this latter terminal, said second and polarity pulses at different times within the time
fourth control signals are each made "low' for period of said synthesized AC voltage waveform,
applying said DC voltage to said fourth terminal of for selectively providing a notched waveform; and
said converter, and are each made "high" for con 10 pulse width modulating said pulses substantially si
necting said reference potential to said fourth ter multaneously with said level shifting step for selec
minal, accordingly in this second mode of opera tively obtaining notch widths and pulse widths in a
tion said first and third switching means are oper combination substantially reducing undesired har
ated in parallel, similarly for said second and fourth monics.
switching means. 15

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