Instruction Set 21
Instruction Set 21
CREDITS - 4 (LTP:3,0,1)
0
instruction
1
Addressing mode
2
Register Addressing Mode –
In register addressing mode, the data to be operated is
available inside the register(s) and register(s) is(are) operands.
Therefore the operation is performed within various registers of
the microprocessor.
Examples:
MOV A, B (move the contents of register B to register A)
ADD B (add contents of registers A and B and store the result
in register A)
INR A (increment the contents of register A by one)
3
Direct Addressing Mode –
In direct addressing mode, the data to be operated is available
inside a memory location and that memory location is directly
specified as an operand.
Examples:
LDA 2050 (load the contents of memory location into
accumulator A)
LHLD address (load contents of 16-bit memory location into H-L
register pair)
IN 35 (read the data from port whose address is 35)
LHLD 2500H 2500 32 > L
2501 25 > H
4
q Register Indirect Addressing Mode –
In register indirect addressing mode, the data to be
operated is available inside a memory location and that
memory location is indirectly specified by a register
pair. Examples:
MOV A, M (move the contents of the memory location
pointed by the H-L pair to the accumulator)
LDAX B (move contents of B-C register to the accumulator)
q STAXB
q LDAXD STAXD
5
Implied/Implicit Addressing Mode –
In implied/implicit addressing mode the operand is
hidden and the data to be operated is available in the
instruction itself. Examples:
CMA (finds and stores the 1’s complement of the contains
of accumulator A in A)
RRC (rotate accumulator A right by one bit)
RLC (rotate accumulator A left by one bit)
6
Addressing mode
7
8
9
Which of the following addressing modes
are suitable for program relocation at run
time?
1.Absolute addressing
2.Based addressing
3.Relative addressing
4.Indirect addressing
5.I and IV
6.I and II
7.II and III
8.I, II and IV
10
Instruction word size
11
Opcode format
12
Opcode format
q MOV
q 01DDDSSS
q E.g. MOV C,A 01001111 4FH
q ADD
q 10000SSS
q ADD B
q 10000000 80H
q MVI A,35H
q 3E 35
q 00DDD110
q LXI Rp,16bit LXI H,2500H
q 00DD0001 00100001 21 00 25
13
A computer uses a memory unit with 256K words of 32 bits each. A binary
instruction code is stored in one word of memory. The instruction has four
parts: an indirect bit, an operation code, a register code part to specify one of
64 registers, and an address part.
1. How many bits are there in operation code, the register code part, and the
address part?
2. How many total operation codes are possible?
3. How many bits are there in the data and address inputs of the memory?
14
6 bit for register, 1bit for indirect, 18bit address so 7 bit for opcode
Total 128 operation codes are possible
32 bit for data and 18 bit for address
15
Instruction cycle & Machine cycle
16
17
18
19
20
21
22
q Draw instruction cycle of MVI A,32H
23
24
25
26
27
q Draw insteuciton cycle of STA 8000H
28
29
30
q Draw instruction cycle of MOV M,reg
31
32
q Draw instruction cycle of MOV reg,M
33
34
35
q Find out no of bytes, machine cycles, addressing mode
q Draw instruction cycle of LDAXB instruction
q Draw instruction cycle of LXI H,2500H
q Draw instruction cycle of INR M
q Draw instruction cycle of LHLD 2600H
q Draw instruction cycle of MVI M,25H
36
Instruction No of bytes No of machine Addresing mode
cycles
LDAXB 1 2 (7 Tstates) Indirect
LXI H,2500H 3 3 (10 Tstates) immediate
37
Memory
38
Memory
39
40
41
q RAM
q 6116 or 6132….
q ROM
q 2716,2732,….
42
Memory map
43
44
45
46
47
48
49
q How many address lines required for an 8Kbyte memory chip
50
51
q Interface 8Kbyte RAM and 8Kbyte EPROM with 8085
q EPROM starting address 0000 and RAM starting address
q RAM starting address 2000H
52
53
54
55
56
57
In a system where some address lines are not decoded resulting
multiple addresses, is called partial decoding. Used in small system
Advantage is cost saving
58
Absolute or exhaustive decoding
59
60
q Interface 4 kbyte EPROM with starting address 0000 and
2kbyte RAM with starting address 2000H
61
62
63
64
65
66
67
68
69
The chip select logic for a certain DRAM chip in a memory system design
is shown below. Assume that the memory system has 16 address lines
denoted by A15 to A0. What is the range of addresses (in hexadecimal) of
the memory system that can get enabled by the chip select (CS) signal?
(assume active high chip select)
70
q Interface 4Kbyte EPROM using 2Kbyte chip starting at
0000 and 8Kbyte RAM using 2Kbye chip starting at 2000H
71
72
73
q Interface 4Kbyte EPROM using 4KX4 chip starting address
0000H
74
75
One byte instruction
76
Two byte instruction
77
78
79
80
3 byte instruction, register pair can be H/B/D/SP
LXI B,2300H
81
5 machine cycle and 16 T-state
82
83
B or D can be used
84
85
One machine cycle and four T-states
86
q Data transfer between 8085 and mmmory
87
88
q Data transfer between Microprocessor and I/O
89
90
91
92
93
94
95
96
97
98
99
Peripheral I/o or IO mapped IO
100
101
102
103
104
IN FAH
OUT F8H
105
Memory Mapped I/O
106
107
108
109
110
111
8085 based system
112
ADD M one byte, two machine cycle, 7 T states
113
114
What are the states of the Auxiliary Carry (AC) and
Carry Flag (dCY) after executing the following 8085
program?
MVI L, 5DH
MVI H, 6BH
MOV A, H
ADD L
(A) AC = 0 and CY = 0
(B) AC = 1 and CY = 1
(C) AC = 1 and CY = 0
(D) AC = 0 and CY = 0
115
116
2 byte, 2 Machine cycle and 7 States
117
118
Add two 8 bit data
q MVI A,93H
q MVI C,B7H
q ADD C
q MOV B,A
q MVI A,00H
q ACI 00
q HLT
119
q Add two 16 bit data
q LXI H,2500H
q LXI D,2600H
q MOV A,L
q ADD E
q MOV C,A or STA 2700H
q MOV A,H
q ADC D
q MOV B,A or STA 2701H
q MVI A,00
q ACI 00 STA 2702H
120
Register pair can be B, D, H,SP
It is one byte instruction and required 3 machine cycle and 10 T states
121
q Opcode fetch
q Second machine cycle
q T1 rpl->A
q T2 L->Tmp
q A+TMP->ALU
q T3 ALU->L
q Third Machine cycle
q T1 rpH->A
q T2 H->Tmp
q A+TMP->ALU
q T3 ALU->H
122
q DAD H
q Suppose H is 0242H then it become 0484H so multiply by 2
q Bring SP into HL pair
q LXI H,0000
q DAD SP
123
124
subtraction
125
126
127
128
129
130
131
132
S, Z,P and AC are modified to reflect the result of operation but CY is
not modified
INR M one byte, 3 Machine cycles and 10T states 133
q Register D contains FF. what is the content of register
after increment
q D become zero so zero flag become 1 but cy flag is not
affected
134
1 byte instruction and required one machine cycle but 6 T state
required. No flags are affected
Pair can be B,D,H and SP
135
q HL consists of 9FFFH what is after INX H
q Hl becomes A000H
136
S, Z,P and AC are modified to reflect the result of operation
but CY is not modified
137
q B is zero what is B after DCR B
138
q Find flag after execution of following instructions
q A B S Z CY
SUB A
MOV B, A
DCR B
INR B
SUI 01H
HLT
139
140
1 byte instruction and required one machine cycle but 6 T state
required. No flags are affected
Pair can be B,D,H and SP
141
142
143
144
q ANA R
q ANA M
q ANI 8bit
q S, Z and P are modifies to reflect the operation .CY is reset
and AC flag is set
q APPLICATION
q Masking bit
q E..g separate lower nibble form 8 bit
q ANI 0FH
145
Assume on-off switches are connected to input port 00.
turn on A.C. if switch s7 is on ignore all other switches
146
q Assume on-off switches are connected to input port 00. turn
on A.C. if switch s7 is on ignore all other switches
q IN 00H
q ANI 80H
q OUT 01H
q HLT
147
148
q ORA R
q ORA M
q ORI 8bit
q Z, S and P are modified to reflect the result of the
operation , AC and CY are reset
q ORA A clear carry flag
q Application : set bits
q E.g. A=03H
q B=50H
q ORA B
149
Radio is connected on D4 line of out put port. Keep radio on
irrespective of switches pressed
150
q Radio is connected on D4 line of out put port. Keep radio on
irrespective of switches pressed
q IN 00
q ORI 10H
q OUT 01H
q HLT
Turn off a.c. without affecting other devices given that ac is
connected with D7
IN 00
ANI 7FH
Out 01
151
TWO input port and one output port. Turn on devices form any
port
IN 00H
MOV B,A
IN 01H
ORA B
Out 02h
HLT
152
153
q XRA Reg
q XRA M
q XRI 8 bit
q Z,S and P are modified to reflect the result, CY and AC are
reset
q XRA A single instruction clear Accumulator and carry flag
154
Comparison is done using subtraction but source and destination
are not changed. S,P,AC are modified in addition to Z and CY flag
155
156
157
158
159
q
160
161
162
q Unpacked to packed BCD e.g. 03 and 05 should 35H
q MVIA,03H
q MVI B,05H
q RLC
q RLC
q RLC
q RLC
q ORA B
q HLT
163
q Write an alp two unpacked 8 bit BCD data
q E.g. 35H converted to 03 and 05
q MVI A,35H
q MOV B,A
q ANI 0FOH
q RLC
q RLC
q RLC
q RLC
q MOV C,A
q MOV A,B
q ANI oFH
164
165
166
167
168
q Applications
q Rotate is used for multiplication and division
q E.g A=08
q RAL become 16H multiplication
q RAR become 04 division
q But it become invalid in case of E.g. 80H become 01 when
RLC is sued
q Two bring carry into register
q MVI A,00
q RAL
169
q Rotate 16bit number
170
16bit rotation without carry
q LHLD 2500H
q XRA A
q MOV A,L
q RAL
q MOV L,A
q MOV A,H
q RAL
q MOV H,A
q JNC ok
q INR L
q OK: HLT
171
8085 program to reverse 16 bit number
172
q Logical Shift
q • A Left Logical Shift of one position moves each bit to
the left by one. The vacant least significant bit (LSB) is
filled with zero and the most significant bit (MSB) is
discarded.
q • A Right Logical Shift of one position moves each bit to
the right by one. The least significant bit is discarded and
the vacant MSB is filled with zero.
q
173
Arithmetic Shift
•A Left Arithmetic Shift of one position moves each bit to the left by
one. The vacant least significant bit (LSB) is filled with zero and the
most significant bit (MSB) is discarded. It is identical to Left Logical
Shift.
•A Right Arithmetic Shift of one position moves each bit to the right by
one. The least significant bit is discarded and the vacant MSB is filled
with the value of the previous (now shifted one position to the
right) MSB.
174
175
Arithmetic Shift operations can be used for dividing or multiplying an
integer variable
For unsigned representation, when the first “1” is shifted out of the left
edge, the operation has overflowed. The result of the multiplication is
larger than the largest possible.
Shifting left on signed values also works, but overflow occurs when the
most significant bit changes values (from 0 to 1, or 1 to 0).
If we have the binary number 01110101 (117 decimal) and we
perform arithmetic right shift by 1 bit we get the binary
number 00111010 (58 decimal). So we have divided the original
number by 2.
If we have the binary number 1010 (-6 decimal) and we
perform arithmetic right shift by 1 bit we get the binary
number 1101 (-3 decimal). So we have divided the original negative
number by 2.
176
177
178
179
180
3 byte instruction, 3machine cycle and 10 Tstates
181
182
q It take only 2 machine cycle and 7 T-states when condition
is not true but condition is true then 3 machine cycle and 10
t state
183
q Compare two 16 bit numbers
184
q LXI H,2345H
q LXI D,3456H
q MOV A,H
q CMP D
q JC seocnd
q Jnz first
q MOV A,L
q CMP E
q JC second
q Jnz first
q MOV B,00
Jmp last
q SECOND: Mov B,02
q Jmp last
q FIRST:MOV B,01
q Last: HLT
185
q Multibyte data addition (64bit data addition)
q MVI B,8
q LXI H,2500H
q LXI D,2600H
q XRA A
q CONTI:LDAXD
q ADC M
q STAXD
q INXH
q INXD
q DCR B
q JNZ CONTI
q hlt
186
q A SET OF 10 READING IS STORED AT MEMEORY
LOCATIONS STARTING AT 2500h. ADD ALL POSITVE
DATA
187
q MVI B,00
q MVI D,0Ah
q MVI C,00H
q LXI H,2500H
q NEXT:MOV A,M
q RAL
q JC REJECT
q RAR
q ADD C
q JNC X
q INR B
q X: MOV C,A
q REJECT: INXH
q DCR D
188
q JNZ NEXT
q A set of 10 reading is stored memory locations staring at
2600H. Write an 8085 alp to Count odd number and even
number
189
q Write an ALP program to sort given array in ascending order
Bubble sort
190
q MVI C,05
q Again:LXI H,2000H
q DCR C
q JZ LAST
q MOV B,C
q LOOP: MOV A,M
q INXH
q CMP M
q JC NEXT
q MOV D,M
q MOV M,A
q DCXH
q MOV M,D
q INXH
q Next:DCR B
q JNZ LOOP
q JMP again
q LAST:HLT 191
BCD addititon
195
MVI B,00
MVI D,0Ah
XRA A
LXI H,2500H
NEXT:ADD M
DAA
JNC X
MOV C,A
MOV A,B
ADI 01
DAA
MOV B,A
MOV A,C
X: INXH
DCR D
JNZ NEXT
196
q ADD TWO 16BIT bcd DTATA
q LXI H,2546h
q LXI D,2345h
q MOV A,L
q ADD E
q DAA
q MOV C,A
q MOV A,H
q ADC D
q DAA
q MOV B,A
q MVI A ,00
q ACI 00
q DAA
197
q HLT
q An array of six data byte is stored starting from memory
location 2050H. Write a program to eliminate zero from the
array
q Assume an array of sorted 10 byte. Insert given element at
appropriate position
198
LXI H, 2500H
MVI C,05H
MVI B,28
AGAIN: MOV A,M
CMP B
JC NEXT
MOV A,L
ADD C
MOV L,A
CONT: DCX H
MOV A,M
INX H
MOV M,A
DCX H
DCR C
JNZ CONT
MOV M,B
HLT
NEXT: INX H
DCR C
JNZ AGAIN
MOV M,B
HLT 199