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/ 13
MEMORY ORGANIZATION
Q.4. Describe memory hierarchy in
a computer system, with the heip
of a diagram.
[UP Tech 2005-2006)
‘Ans. The memory hierarchy system con-
‘sists ofall storage units placed ina computer
system from stow auxiliary memory to fast
cache memory. Afive tevel memory hierarchy
is shown n figure given below:
Fig Fvetevel Memory Hierarchy.
Atthe top CPU registers are present which
are smallest in capacity but fastest in access,
Nextis cache memory which is normally ofthe
‘order of 32KB to few MBs. Cache memory Is
very smatt, expensive and it has very high ag.
cess speed. Next is main memory whose size
‘normally in Giga bytes. Next aro magnetic disk
and finally magnetic tape and optical tape.
Magnetic disks and tapes are also called auxik
lary memory. They are used for storing large
dota files and other backup information. The
programs end data currently needed by the pro-
cessor reside in main memory. Allother infor-
‘mation igstored in auxiliary memory and trans-
ferred to main memory when required.
tHerarchy deperids upon three parameters.
( Accesstime
Storage capacity
(i) Cost
The average time required to reach a stor.
‘ge locaton in memory and obtain ts contents
fs called.accesstime.
‘As the storage capacity ofthe memory in-
creases, the cost per bit ferstoring binary infor-
mation decreases, Gut as storage capacity in-
‘creases, access time also increases.
Q.2. Discuss the various organiza-
tion of RAM. A computer uses RAM
chip of 1024 * 4 capacities. How
many chips are needed and how
should their address lines be con-
nected to provide a memory ¢apac-
ity of 1024 bytes?
[UP Tech 2008-2006)
‘Ans. RAM is of two types: Static random
‘access memory (SRAM) and Dynamicrandom
access memory (ORAM).
Statle random access memory
(GRAM): memory which consist of circuits ce:
(able of retaining their state as ongas powers
applied are known as Static random access
‘memory. SRAM is made up of tip flops. Dsta
remains in SRAM as long as power remains. As
data remains in flp flop til power remains
hence no refreshing circu is required in SRAM.
Heat dissipation is tess in SRAM. Packing den-
sity is high (aumber of flipflops piaced on a
single chip) in SRAM. tt is expensive as con-
aredto DRAM. :
tain their state indefinitely are known a Dy-
namie random aceess memory. Information is
stored ina dynamic memory cellinthe form of
a charge on a capacitor. DRAM is made up of
‘capacitors, DRAM tends to loose data because
capacitors discharge with time, Hence refresh-
ing circuits are needed in DRAM to restore the
decoying charge. Heat dissipation is more in
DRAM because of capacitors. Packing density, is less in DRAM Decause DRAM Is made up of
capacitors and capacitors continuously atest
pata heat. Hence they cannet be placed close
together closely.
‘Numerical
‘Totalmemory capactty required
= 4024 bytes = (1024 + 8) bits
‘Size of each RAM chip = 1024 * 2 bits
Hence number of RAM chips required
= (2024 * 8 (4024 * 4)
-8
‘Total RAM chips of size 4024 * dare required
to provide a memory capacky of 024 bytes.
Address fines areto be connected in parallel.
Q3. Write the differences between
Static RAM and Dynamic RAM.
[UP Tech 2004-2005}
‘Ans. The main memoryis the central stot
‘age unit in @ computer system. It stores pro-
grams and data during computer operation.
Ramis of twotypes: SRAM (static random ac-
‘cess memory) and DRAM (Dynamic random
‘access memory). There are many differences.
between SRAM and DRAM which are.2s fol
tows:
1 SRAM s made up of flipflops where
‘as DRAMIs made up of capacitors.
i, Data remains in SRAM as tong as
power remaing whereas DRAM tends,
to loose data because capacitors dis-
charge with time.
No refreshing circult is required in
SRAM where as refreshing circuits are
‘needed in DRAM to restore the decay-
ing charge.
Heat dissipation stess in SRAM where:
{as heat dissipation ts more in DRAM
because of capacitors.
Packing densityshigh (number of flp-
‘hops placed on a single chip)in SRAM
where as packing density is less in
DRAM because DRAM is made up of
cepectors and capacitors continuously
dissipate heat, Hence they cannot be
+ placed close together closely.
YL. SRAM is expensive as compared to
DORAN.
a
Q.4. How many 428 bytes RAM
chips are required to provide a
memory of 2048 bytes?
[UP Tech 2004-2008)
‘Ans. Sizeof one RAM chip = 128 bytes
‘Size of memory * 2048 bytes
+ Totalnumber of RAM chips required =
2048/128 = 16
Hence 16 RAM chips of size 128 bytes are
required toform a memory of size 2048 bytes,
Q.5. A computer employees RAM
chip of 266*8 and ROM chips of
1024*8, The computer system
needs 2K bytes of RAM, 4K bytes
of ROM and four interface units,
each with four registers. A memory
mapped configuration Is used. The
two highest order bits of the ad-
dress bus are assigned 00 for
RAM, 04 for ROM and 10 for inter-
face registers: [UP Tech 2007-2008]
() How many ROM and RAM
‘hips are needed?
(ii) Draw & memory address map
for the system.
(ill) Give the address range in hexa-
decimal foe RAM, ROM and inter-
face.
‘Ans. ())Size of RAM chip = 256 * 8
Memory sité required = 2K bytes = 2 *
4024 bytes =2 + 1024+ 8,
Total number of RAM chips requited = (2 *
1024 * By (256 * 8)= 8 chips
‘Size of ROM chip = 1024* 8
Memory size required = 4K bytes = 4 *
1024 bytes =4* 1024 * 8.
‘Total number of ROM chips required =(4 *
1024 * 8 (1024 * 8)= 4 chips
Hence 8 RAM chips and 4 ROM chips are
(ivand (it) RAM size = 266 bytes = 2°
Sbits for RAM address
ROM size = 1024 bytes = 2°
‘20 bits for ROM address
Memory address map will bo as shown
below . Compouent Address 25-15 «A a HOO @ 7 6S 4 3 2 2
mam wooo 0 0 0 0 0 sve Xx XXX XXX
ROM “aQOOaR 0 1 6 0 aeabeOx KX XX XXX XX
tetas so0oear 2 00000000000 xx x
‘There are 8 RAM chips so 38 decoder is needed to select 1 RAM chip.
‘There are 4 ROM chips so 2*4 decoder is needed to select 1 ROM chip.
16 address lines willbe in use as shown above, Address are represented in hexadecimal
Q6. A ROM chip of 1024 * 8 bits has four select inputs and operated
from a 5-volt power supply. How many pins are needed for the IC pack-
age? Draw a block diagram and tabel all input and output terminals in
the ROM. [UP Tech 2008-2009}
‘Ans. Total 24 pins are needed f0F crip select
the IC package: Tse pins are avicea MP = -
astolows: : no |
20 pins forinput vectra} 2028 | Sbitaata us
Apinstorchipsetect Ch select _,| Rom (output lines)
Spins or output ,
2pinstorpower ——s0 ot auress
‘The block diagram of ROM having ROM chip
allthe input and output terminalis 6
fotows: :
Q7. Write a short note on cache | pce
memory. ' Main
‘Ans. The speed of main memory Is ow Come Memoe
ascompaedtote spent moter ose :
sors, processor spends much of its time
waiting to access instructions and data’ in
"main memory then it affects processors performance. active portion of program and data are
placed in. fast small memory then average access time can be reduced thus reducing the total
‘execution time of the program, This small memory s called cache memory. itis placed in between
CPU and main memory. tis considered as fastest memory. ts size is just fraction of main memory.
asic operation: when CPU needs to access memory, the cache is exarhined. tthe required
‘word is found in cache, itis read from there otherwise main memory is accessed. Then a block of
‘words including the main requests transferred from main memory to cache. Now cache contains
the requested word as well as the future references also,
Performance of cacte memory Is measured in terms of e quantity called Hit ratio. When CPU.
refers to memory and finds the wordin cache, its celled a it: When It does not find the word then’
itisamiss.
Hit eatlor Ratio Of ruriber oF hits divided by the total CPUreferencestomemoryiscalled Hit ratio.
Incache memory write operation can be performed in two ways.
‘+ Wrie through policy
+ Write back policy :
‘write through policy the cache location and the main memory location are updated simatononi, Mem hen orate ay hanes int as memory ose
Shanes ae tied nthe ma ra. fay ep tut eas
ines oan nthe nan rai mene Gren wrt pase
sat
Inwrite back policy onty cache memory location Is updated and the changed locetion Is
marked with an associated flag bit commonly known as dirty bit or modified bit. The main memory
Jocation is updated later when the marked word is to be removed from cache.
Q8. What are the different procedures for mapping cache memory?
[Up Tech 2005-2006]
fos hevantomaonotélaomnan aman oete mention snags
Tar sone anon cers CP as 8)
‘+ Direct mapping
+ Setassoclative mapping.
Associative mapping: in associative memory both address
anttatae oes Redogumsnos Suis peaeny Sei | “asia a
cache, All the numbers are represented in octal.
CPU places 15 bit address in the argument register and assoria-
tive memory is searched for a matching address. If that address is
found, then corresponding 12 bit data is read from it and sent to the
‘CPU. If no match is found then main memory is accessed for the word.
Direct mapping: In direct mapping RAM is used for cache
memory as described below.
CPU address is of 45 bits; hence size of main memory is: 32K, This address is divided into 2
fields; index and tag.
"2" words in main memory and 2* words in cache memory. Then kbits are there in Index leld
and (rk) bits are there In tag field. For example 2" words in main memory and 2° words in cache
memory so size of index is 9 bits and tag Is (15-9)=6 bits,
Addressing relationship ‘between main and cache memory is shown with the help of figure
Biven below,
ty in
(Cie [ner
‘Argument reyisier
Cr
0385 | 7564
32K x 12" sx
Cache memory
Address = 9 bits
Main memory
Address = 15its Data 12 bits
Data = 12 bits
nim .
Fig. Addressing relationships botween main and eache memories. Memory
dB emory deta
‘e0000{ 1220
i—— tren
cderess _Teg__Data
‘000("00 [1220
oo777 | 3340
01000 | 2450
ox77[ 4560
‘020008670
moa | e7i0
oars | eT a0 (echo memory
a) Malo memory
Fig. Direct mapping chache organization.
Each word in cache consists of tag field and data.
‘When CPU generates a memory request, theindexfield Index Teg Dota Teg__Doa
is usedtorthe addressto.access the cache. Afterthat 900 04 | 3480 [] 02 | 5670
tag field is compared with the tag in the word read from
cache, ft matches then its @ hit otherwise miss It
rss then required words read from main memory end
‘stored incache, wih anew tagreplocing previous value,
_ ‘Set associative mapping: It is an improvement
“over direct mapping, In this mapping each word of cache
can store two or more words of memory under the same
index address. Each data word is stored together with 777] 02 |. 6710 || 00 | 2340
is (08, Total numberof tae-data Roms none Word of g, Twoway: ive ‘cache.
Each tag requires 6 bits and each data word has 12 bits. If there are two tag fields present in.
cache then word length of cache wilt be 2 * (6+12) = 36 bits.
‘The hit ratio will improve as the set size increases because more words with the same index,
but differant tags can be presentin cache.
Q.9. Differentiate Direct Mapping and Associative mapping procedures
for organization’ of cache memory with example. Give merits and demer-
its of both mapping procedures. {UP Tech 2004-2005}
Ans. Differences between associative mapping and direct mapping are as follows:
'* Associative mapping technique is expensive than direct mapping because of added logic as-
sociated witheach cell
'* Hit ratio is low in associative as compared to direct mapping.
+ Associative mapping technique is faster in access than direct mapping,
Advantages of associative mapping .
+. Roquired data word can be accessed ina fost way as compared to other tchniques.
Disadvantages of associative mapping
'* Hit raticis low. Means chances of getting required word in memory are lessas compared
toother techniques. ‘« Itisexpensive because this mapping
requires added logic associated with
‘each coll
Advantages of direct mapping:
‘+ Hit rato is high, Means chances of
getting required word in memory are
more as compared to other tech-
niques,
‘+ Its cheaper as compared to other
techniques.
Disadvantages of direct mapping:
‘+ Required data word eearchingis siow
ascomparedto other techniques.
Q10. A block set associative
memory consists of 128 blocks di-
vided into four block sets. The
main memory consists of 16384
blocks and each block contains
256 eight bit words.
(i) How many bits are required
for addressing the main
memory?
(il) How many bits are needed
for addressing the cache
memory? [UP Tech 2004-2005)
Ans. () Size of main memory = 16384
blocks «2
» Size of one block #256 words = 2°
‘Totat number of words thet memory contains
agit 28 27
Hence 22 bits are required for addressing
mainmemory. .
{§) Size of cache memory = 428 blocks = 2
‘Size of one block = 256 words = 2°
‘Total number of words that cache contains
927 # 28 = 21
Hence 15 bits are required for addressing
cache memory. -
Q.44. Explain various cache map-
ping techniques. A computer sys-
tom has a 4K word cache organized
in block set associative manner
with 4 blocks per set, 64 words per
block. The main memory contained
65536 blocks. How many bits are
there In each of TAG, SET and
WORD fields?” {UP Tech 2005-2006)
‘Ans. The transformation of data from main
memory to cache memory is known as mapping:
process. There sre three mapping procedures.
© Associative mapping:
* Drectmapping
‘= Set associative mapping
‘Riiress [a
craze | 67s
Tass | —7s68
CPU ares (1S)
‘guneat ogee
Associative mapping: in associative
‘memory both address and data are stored. The
diagram shows 2 words presently stored in
‘cache. Ailthe numbers are represented in octal.
(CPU piaces 15 bit address in the argument
register and associative memory i searched
‘fora matching address. that address is found,
‘then corresponding 42 bit data is read fromit
and sent tothe CPU. ifno match is found then,
maln memory is accessed forthe word.
Direct mapping: In direct mapping RAM
(a used for cache memory as described below.
CPU address is of 45 bits; hence size of
malin memory is 32K. This address ts divided
tnto2 elds; index and tag.
2" words in main memory and words in
‘cache memory. Then k bits are there in Index
fleld and (mk) bits are therein tag etd.
For example 2°° words in main memory and
2? words In cache memory so size of indexis 9
ditsandtagi 69-0 be
Addressing relationship between main and
‘cache memory is shown with the help of figure
given below.
mn
se
Sok
a
° arr! wcaene mamnory
(ia rama
Fig. Direct mapping chache organization. ach worn cache consists of tag fle and data, When CPU generates a memory request, the
incon tells used forte address to access the cache. After that ig lel is compared withthe tg.
ine werd eed from eache,{ritmathes thenitsaikcthorwise miss, issn requved word
‘Greac trom main memory and stored in eache, with
anew tag replacing previous value. index _Teé_ _Data Tag__ Data
‘Set ausoriative mapping: fis an improve. o00[ 0a | 486 || 02 | se70
sent over direct mapplng.Inthi mapping each word
Of ache can store two or more words of memory
‘onder the same index adress. Each data word I
‘stored together with its tag. Total number of tagdata
itomsinone word of cache s saldtoforma set.
Each tg requtes GbKs ana each data wordhas
12bits, Ifthere aretwo tagfields presentincachethen
word length of cache willbe 2 * (6+12)= 36 bits.
Tehitatowilimprovestnesetseelneremes 777[ 07 | @ra0 {[ 66 | 2340
: ‘words with the same index ut der
en'iagsconberesentincache. Fig, Two-way setassociative mapping
umercat
Main memory size = 65596 =2°°
m=16
Cache memory size = 64 biocks =2°
m8
Set size = 4 blocks = 2?
s=2
TAGs ments= 16-6422 bits
Q.2.2. Drive the logic of one ceil and of an entire word for an associative
memory that has an output indicator when the unmasked argument is
greater than (but not equal to} to word in the associative: memory.
[UP Tech 2006-20071
Ans. Let x= AF A/F,’
Output Geshe .
Ayn d and kyw 4 firstbitin As awhile F,:
—atagAaFia = Tank, <2
first pair of bits are equal and second bit in A =4 while f,,= 0)
p= (Aa * WD (x, AaFia + KS) Ota Xa Aan +H) (Raa om Mp aAahin +a)
al| oI
Taf
rae Q13. A two-way set associative
cache memory used blocks of four
words. The cache can accommodate
a total of 2048 words, the main
memory. The main memory size is
128 K * 32.
(i) Formulate all pertinent infor-
mation require constructing the
cache memory.
(ii) What Is the size of the cache
memory? (UP Tech 2006-2007}
‘Ans. Size of main memory = 128K = 257
Hence address is of 27 bits.
Cache can accommodate 2048 words,
Set size=2
(Hence cache can accommodate 2048/
2 1024 words with set size of 2.
1024 words = 21°
mdex address needs 40
TAG
oe =
c= 76
Index 40 bits which is divided into
Brock and word
Block = 8 bits
Word = 2bits
{8} One word of cache memory willbe like
shown delow
TAG 2 | DATA 4]
TAG 1=TAG2~7 bits
DATA 1.=DATA2 = 2 bits
‘There are 1024 words in cache memory.
Obits 9 bit
Toe [ten
T
TAG 2 | DATAZ
' 3KX LD
Octad Main memory
ares
Address © 15 nts
Dats 1 bite
wm
7 {==
In one word there-are 2(7#32)bits,
Hence stze of cache memory= 4024 * 78,
bts
Q14. Explain the direct mapping
technique. Consider a digital com-
puter has a memory unit of 64
K*46 and a cache memory of 1K
words, The cache uses direct map-
ping with a block size of four
words:
(i) How many bits are there in
the TAG, index, block and
word fields of the address
format?
Gi) How many blocks the cache
can accommodate? {UP Tech
2007-2908)
Ans, Direct mapping: In direct mapping
RAMs used for cache memory as described
below.
CPU address is of 45 bits: hence size of
main memory is 32K. This address is divided
Ito 2flelds; index and tag.
2 words in main memoryand 2 words in
‘cache memory. Thon k bits aro there in index
fekd and (ork) bits are there in tag field,
For example 2"° words in main memory and
2° words in cache memoty so size of index is 9
bits and tag is (25-9)6 bits.
Addressing relationship between mainand
‘cache memory is shown with the help of figure
ven below.
sox
eta caster, |
sisi :
Jf attest ni
Beets
mm
|
Fig. Addressing relationships between main and cache memories. 481035 Memory data
‘o0000{" 2220 .
‘scares Tag___Dato
}___} ooo("90 | 1220
‘oor | 2340, °
scoo| 3460,
on77 | 4560
‘e200 "5670"
amor | e730
(8) Cache memory
arn [ert
(2) Main memory
Fig. Direct mapping cache organization,
Each word in eache consists of tag field and data. When CPU generates 2 memory request,
‘the index field Is used for the address to access the cache. After thattagfield is compared with the
‘agin the word readfrom cache. fit matches then itis hit atherwise miss. miss then required
‘words read from main memory and stored in cache, with anew tag replacing previous value,
‘Size of mainmemory = 64 k x 16
Adress lines = 16
Wordiength = 16 so, data lines = 16
‘Stzeotcachememory = 1K x16
address = 40 bits
(@Henee
Tag | BLooK | woRD
Bois | Soi 2 bits
Index = 40 bit cache address
‘iG =6bits
BLOCK 8 bits
WORD= 2 bits
NNDEX= 10 bits,
(2) Sve of cache memory = 4 k words = 1024 « 16
‘Slzeof one block = 4 words= 4% 46
4024 x46
Heme cachecan accommodate = —Z-gg— =256 blocks
‘Cache memery can accommodate 256 blocks of 4 words each.
Q.45. Define the terms address space and memory space. An address space
is specified by 24 bits and the corresponding memory space by 16 bits.
(a) How many words are there in the address space?
(b} How many words are there In the memory space?
(c) If 8 page consists of 2K words, how many pages and blocks are
there in the system? 1UP Tech 2008-2009) ‘ns. Address space: An address used by
programmer is called Virtual address. The set of
vituat addresses is called address space.
Memory space: An address In main
memory is called physical address and set of
‘such addresses called memory space.
The address space is allowed to.be larger
than the memory space in computers with the
‘help of virtual memory.
(@) Address space = 2 bits
Number of words present in address space
= 22 = 16 Mwords
4b) Memory space = 46 bits
‘Number of words in memory space.
= 2! = 64 kwords
(eOne page= 2 k words
16M
Yotalnumber of pages= “BA = k pages
Total S k pages are present
6k
‘Total number of blocks = 3j- = 32 blocks
‘Total 32 blocks are presenti the system.
Q46. Write short notes on the fol-
lowing:
{a) Auxillary memory
(b) Memory hierarchy
(©) Cache memory
(d) Vietual memory
IUP Tech 2008-2009)
‘Ans, Aunty memory: Memories which
«are used for beckup storage are called euxtiny
‘memory. They are used for storing system pro-
‘grams, large data files and other bactaup infor:
‘mation. During execution, programs and data
required by CPU reside in rain memory and
‘other information is stored in auxiliary memory
and transferred to main mvemiory only when re-
‘ulred, Most commonly auxitary memory de:
vices are magnetic dks and magnetic tapes.
‘Some other examples of auxiliary memory do-
vices are magnetic drums, magnetic bubble
‘memory and optical dite. The important propes-
ties of any memory device are its access time,
traneterrate capacity and ts cost. The average
time required to reach a storage location in
‘memory and obtain ks contents is called access
time. Number of words transterred per unit time
Istransterrate. Time required to transfer data to
‘and from any device letrenefer time.
Magnetic dicks: i consists of a circular
plate made up of metal or plastic which fa
Coated with magnetized material. Many diss
are placed together on one spindte with read/
write heads on each surface because normaly
Doth shdes of disk are used. Bits are stored in
the maghettzed surface n spots along concer
trl ocles called tracks. Tracks are divided into
sections which are called sectors, Disks which
‘are permanently attached in computer system
‘recalled hard disks.
‘Magnetic Tape: Its a plectic strip witn a
‘coating of magnetic medium. Bks are recorded
_3s magnetic spots on the tape along several
‘racks. Read/ write tracks are mounted one in
‘each track so that data can be recorded and
read as.a sequence of characters. In tapes ir
formation (data) ls recorded in blocks. A tape
‘unit ts addresses by specifying record num
‘ber and the numberof characters inthe record.
Records can be of fixed length or they can be af
variable length.
‘Memory hierarchy: The memory hlerar-
‘chy system consists of al storage units placed
{tn a computer system from slow auxliary
‘memory to fast cache memory.
‘tthe top CPU registers are present which
‘are smaltestin capacity but fastestin access.
‘Nextls cache mertory which is normally ofthe
‘order of 32KB to few MBs, Cache memory Is
‘very smait, expensive and it has very high 20-
‘cess speed. Next ls main memory whose size
‘normally in Giga bytes, Next are magnetic disk
‘and finally magnetic tape and optical tape.
(Magnetic disks and tapes are also called aud
tary memory. They are used for storing large
‘data files and other beckup information. The
programe and data currently needed by the pro-
‘cessor reside in main memory. All other infor-
_matlon i stored in awiary momory and trant-
‘erred to miain memory wien required.
‘There are three parameters in memory to
‘compare between different types of memory
‘which are acceas time, storage capacity and
‘oat. The avernge time required to reach 8 stor
‘age location In memory and obtain ts contents
‘scaled access time. ‘As the storage capacity ofthe memory In-
‘ereasos, the cost per bit or storing binary infor.
‘mation decreases, But as storage capacity n-
‘creases, access time also increases.
‘Cache memory: if ective portion of pro-
‘gram and data ave placed inafest malimemory
‘then average access time can be reduced thus
reducing the total execution time of the pro-
gram. This smatl memory is called cache
‘memory. itis placed in between CPU and main
_memory is considered as fastest memory. tts
‘size is just fraction of main memory.
Basic operation: when CPU needs to ac-
‘cess memory, the cache is examined. tt the ro-
‘quired word Is found in cache, its read from
‘there otherwise moin metnoryis accessed. Then
block of words including the main request Is.
transferred from main memory to cache. Now
‘cache contains the requested word as well as
the future references also. ~
Performance of cache memory is mea-
‘suredin terms of a quantity called Hitratio. When
‘CPU refers to memory and finds the word in
‘cache, itis called a nit. When it does nat find
the word then! isa miss.
Ratio of number of hits divided by the total
‘CPU references to memory is called Hit ratio.
‘Virtual memory: This concept allows its
serstoconstruct programs.as flarge amount
of memory is avaliable. It gives illusion to its
programmers asi they haves large memory
for theie use, where there is relatively small
‘mainmemory. itis a combination of hardware
and software techniques. A virtual memory sys
tem provides a mechanism for translating pro-
ram generated addresses into correct main
‘memory locations. This is dynamically, while
programs are being executed in the CPU. The
‘tansiation or mappings handled automaticelty
by the hardware by means of a mapping table.
An address used by programmeriseatied
‘Virtual address. The set of vital addresses is
called address space. An eddress in main
_momory is catled physical address and set of
such addresses Is called memory space. The
‘address space is allowed to be targer than the
memory space in computers with the help of
virtual memory.
Q47. A virtual memory has page
size of 4K words. There are eight
pages and four blocks. The asso-
the following entries.
Page Block
oO 3
a £
4 2
6 o
Make a list’ of all virtual ad-
dresses (in decimal) that will cause
a page fault if used by CPU.
{UP Tech 2006-2007}
‘Ans. Page size = 1K words
‘otal 8 pages are there outof which only 4
pages (0, 4, 4, and 6) are present in main
memory.
Pages which are not present are 2, 3, 5, and 7.
Page wa. Address Address that will
cause page fault
2 2K 2048-3074
35 3K 90724095
8 aK 51206143
7 7 7168-8191
Q.48. Draw and explain the block
jagram of simple up based sys-
tem.
Ans.
Microprocessor: It is a semiconductor
device consisting of electronic logic circuits.
‘manufactured by using elther LSI or V.Sttech-
nique. It is capable of performing computing:
functions and making decisions to change the
‘Sequence of program executions.
Tne three sequents of up are:
Arithmetic/Logic Unit: Computing
functions are performed on data inthis ares. it
performs operations such as addition, subtrac-
‘Uon, fogical operations etc. Register unit; These are used primarly
tostore data temporarily duringthe execution
of aprograrn.
‘onto! unit: in provides the necessary
‘imingand control signals to athe operetions,
Input Device: The Input section tranéfers
