Design of Majority Logic (ML) Based

Approximate Full Adders

Tingting Zhang1, Weiqiang Liu1*, Emma McLarnon2, Maire O’Neill2, and Fabrizio Lombardi3
1College of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing, China
2ECIT, Queen’s University Belfast, Belfast, UK
3Department of Electrical and Computer Engineering, Northeastern University, USA

Email: {ztt0416, liuweiqiang}@nuaa.edu.cn, [email protected] , [email protected], [email protected]

Abstract—As a new paradigm in the nanoscale technologies, A, B and C and the output is F. The logic expression of the 3-
approximate computing enables error tolerance in the input majority gate (voter) is given by:
computational process; it has also emerged as a low power design
methodology for arithmetic circuits. Majority logic (ML) is
= , ,  =  +  +  (1)
applicable to many emerging technologies and its basic building A
block (the 3-input majority voter) has been extensively used in B M F
C
digital circuit design. In this paper, we propose the design of a one-
bit approximate full adder based on majority logic. Furthermore, Fig. 1. Majority gate (3-input voter)
multi-bit approximate full adders are also proposed and studied;
Research on the design of ML approximate circuits has only
the application of these designs to quantum-dot cellular automata
(QCA) is also presented as an example. The designs are evaluated
recently been pursued; In [3] the authors proposed a one-bit full
using hardware metrics (including delay and area) as well as error adder circuit. In this paper, we propose a few ML-based
metrics. Compared with other circuits found in the technical approximate full adders; one-bit as well as multi-bit approximate
literature, the optimal designs are found to offer superior adders are considered. QCA technology is used as a case study
performance. to show the validity of the proposed designs. Hardware
evaluation and error analysis are also provided.
Keywords—Approximate computing; majority logic; full adder;
The rest of this paper is organized as follows. Section II
quantum-dot cellular automata
reviews the basic principles of QCA, the relevant contributions
I. INTRODUCTION and the error metrics used in this paper. Section III presents the
design of the proposed one-bit approximate full adder based on
Power dissipation is increasingly becoming a challenge for ML. Multi-bit designs are studied by combining the proposed
advanced integrated circuit design; although emerging and existing one-bit approximate full adders in Section IV.
nanoscale technologies have been proposed to replace CMOS at Section V concludes the paper.
the end of Moore’s Law, the issue of power consumption
remains unabated, because integration density of these II. BACKGROUND
nanoelectronic devices continues to increase at a high rate.
Approximate computing is a promising technique to reduce A. Quantum-dot Cellular Automata
power consumption and improve performance of circuits and QCA makes use of the polarization state of cells to encode
systems by allowing computational errors in error-tolerant binary information and Coulombic force interactions between
applications, such as multimedia signal processing, machine cells to achieve circuit functionality; these features make this
learning and pattern recognition [1-2]. technology substantially different from CMOS. As shown in
Approximate computer arithmetic circuits based on CMOS Fig. 2a, a QCA cell consists in its simplest form of four quantum
technology have been extensively studied. Designs of dots and two electrons that can tunnel between them. Due to
approximate adders, multipliers and dividers for both fixed- Coulombic repulsion, electrons are forced to occupy the
point and floating-point formats have been proposed [3-7]. Error opposite diagonal vertices (dots). This forms two different
metrics such as the mean error distance (MED), the normalized polarization states (i.e., -1, +1) for each cell, thus representing
MED (NMED) and the relative MED (RMED) [8] have been logic values of 0 and 1.
proposed to analyze the errors introduced in the operations of QCA requires a clocking scheme with four different
approximate arithmetic circuits. operational phases, i.e. Switch, Hold, Release, and Relax; each
However, the approximate designs of CMOS circuits adjacent so-called zone is shifted in phase by 90 degrees to
cannot be immediately applied to many emerging technologies control the flow of information. For a majority gate in QCA,
such as QCA [9-10], nanomagnetic logic (NML) [11], and spin- which can be seen in Fig. 2b, there is a 0.25 clock delay in each
wave devices (SWD) [12] due to the very different underlying clocking zone. As another basic gate in QCA, an inverter is
logic structure of these devices. Emerging devices rely on shown in Fig. 2c. More information on the clocking scheme and
majority logic (ML) which is a substantially different framework QCA technology can be found in [9-10].
from conventional Boolean logic. The majority gate performs a
multi-input logic operation and is shown in Fig. 1; the inputs are

This work is supported by grants from National Natural Science Foundation of

China (61401197 and 61771239), and Natural Science Foundation of Jiangsu
Province (BK20151477).

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 A
= | − | (6)
∑
 = (7)
B F A F

P=+1 P=-1
 = (8)
C where X, Y, n and MAX denote the accurate result, the
approximate result, the counts of all possible inputs and the
(a) (b) (c)
maximum value of the result, respectively.
Fig. 2. QCA basic elements: (a) QCA cell, (b) QCA majority gate (voter), and
(c) QCA inverter. III. PROPOSED ONE-BIT APPROXIMATE FULL ADDER
B. ML based One-Bit Exact and Approximate Full Adders In this section, a one-bit approximate full adder is proposed,
Fig. 3 shows a one-bit accurate full adder based on ML; it which is presented and compared with one-bit accurate full
consists of 3 majority gates and 2 inverters [14]. The inputs to adder and an existing one-bit approximate full adder.
the one-bit adder are given by A, B, C while S and C
 are the A. Proposed One-bit Approximate Full Adder
outputs. The outputs C
 and S are expressed as follows:
Inspired by [3], we propose a new one-bit approximate full
 =  +  +  = (, , ) (2) adder, namely, AFA2. Consider the truth table in Table I, C

is nearly the same as C except in two of the 8 input combinations.
 = ⨁⨁ = ( , , , ̅ , ) (3) Therefore, as in Eq. (9), C can be approximately considered as
A B A B C
 to save a majority gate compared with the one-bit accurate
M
full adder when computing the carry out of a one-bit full adder.
M C
C
 =  (9)
Cout M Cout
Based on Eq. (9), the inexact output C
 is substituted into
S S
Eq. (3) to find the approximate output S as follows:
(a) (b)
 =  , , , ̅ ,  = , , ̅  (10)
Fig. 3. One-bit accurate full adder: (a) schematic of accurate adder, (b) layout of
accurate adder in QCA [14]
TABLE I. ONE-BIT APPROXIMATE FULL ADDER TRUTHTABLE
Labrado et al have proposed a one-bit approximate full adder Inputs Accurate AFA1[3] AFA2
(AFA1) in [3], whose schematic and layout are shown in Fig. 4. A B C ࡯࢕࢛࢚ S ࡯࢕࢛࢚ S ࡯࢕࢛࢚ S
AFA1produces the output S as the complement of C
 but 0 0 0 0 0 0 1 0 0
introduces 2 errors(among the 8 input combinations)when 0 0 1 0 1 0 1 1 0
computing the output S, (as shown in Table I). The circled 0 1 0 0 1 0 1 0 1
0 1 1 1 0 1 0 1 0
entries in the truth table denote the instances in which the outputs 1 0 0 0 1 0 1 0 1
of the approximate full adder differ from the accurate full adder. 1 0 1 1 0 1 0 1 0
The equations for the carry out and the sum are as follows: 1 1 0 1 0 1 0 0 1
1 1 1 1 1 1 0 1 1
 = (, , ) (4)
To evaluate the accuracy of the proposed design, the MED
 =  (5)
and NMED are given by:
ABC B

   = 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 = 0.25(11)
M
A C 

Cout  ಲಷಲమ
Cout    = = 0.083 (12)


S S Fig. 5 shows the schematic and layout of the proposed

approximate full adder AFA2.
(a) (b)
ABC B
Fig. 4. One-bit approximate full adder: (a) schematic of AFA1, (b) layout of Cout
AFA1 in QCA [3]. Cout
M
A C
C. Error Metrics for Approximate Circuits
As approximate computing introduces errors, error metrics S S
are required to evaluate the accuracy of approximate circuits. In
(a) (b)
this paper, we evaluate approximate designs using the Mean
Error Distance (MED) and the Normalized Mean Error Fig. 5. Proposed one-bit approximate full adder: (a) schematic of AFA2, (b)
layout of AFA2 in QCA.
Distance (NMED). The MED is defined as the average of the
Error Distance(ED) which is the absolute difference between B. Comparison and Discussion
the approximate and the accurate results across all possible A comparison in terms of number of majority gates (MV),
inputs. The NMED is the normalized MED. The definitions of number of inverters (INV), MED, NMED, delay (D) and area
ED, MED and NMED are as follows: (A) between the accurate adder [14], AFA1 [3] and the proposed

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approximate full adder AFA2 is reported in Table II. Compared In terms of the delay, AFA21 needs 0.25 less clocking zones
with the accurate adder [14], AFA2 saves 2 majority gates, 1 than AFA12.
inverter and 0.25 clock cycles of delay and improves the area of
the design by up to 72%. Moreover, AFA2 has a smaller area TABLE III. TWO-BIT APPROXIMATE ADDER COMPARISON
than AFA1[3] in QCA. ADDER TYPE MV INV D A(࢔࢓૛) MED NMED
AFA11 2 2 0. 5 44073 0.75 0.107
TABLE II. ONE-BIT APPROXIMATE FULL ADDER COMPARISON AFA22 2 1 0.25 35383 0.75 0.107
AFA12 2 1 0.5 39267 0.625 0.089
ADDER TYPE MV INV D A(࢔࢓૛) MED NMED
AFA21 2 2 0.25 41069 0.625 0.089
Accurate [14] 3 2 0.5 60050 0 0
AFA1[3] 1 1 0.25 18902 0.25 0.083 Fig. 8 shows the comparison results by considering both
AFA2 1 1 0.25 16284 0.25 0.083
the area-delay product and the NMED; AFA21 is the best
IV. PROPOSED MULTI-BIT APPROXIMATE ADDERS design as it is the closest to the origin. Generally, AFA12 and
AFA21 (with mixed types of one-bit approximate full adders)
In this section, multi-bit approximate full adders are proposed
show better performance compared with those with only a
by merging the proposed and the existing one-bit approximate
full adders. Both the corresponding hardware designs and error single type of approximate full adders.
metrics are evaluated. Fig. 8. Evaluation of proposed 2-bit approximate full adders (NMED vs delay-
area product).
A. Proposed Two-bit Approximate Adders
The inputs to the two-bit adder are given by A = a a, B =
b b , C ,while S = s s , and C are the outputs. By cascading
two one-bit approximate full adders (AFA1 and AFA2), four
different combinations are possible for the two-bit approximate
full adder; they are shown in Fig.6. AFA1 cascaded with AFA1
results in the two-bit AFA11 design. Similarly, AFA2 cascaded
with AFA2 results in AFA22 design. AFA12 consists of AFA1
and AFA2, in which AFA1 is used to compute the LSB; the
opposite is applicable to AFA21. The layouts of these two-bit B. Proposed Four-bit Approximate Adders
approximate QCA adders are shown in Fig. 7.
Consider a four-bit adder with inputs given by A =
a0b0Cin a0b0Cin
a1b1 a 0b0Cin aଷ aଶ aଵa଴ , B = bଷ bଶ bଵ b଴ , C୧୬ and outputs given by S =
a1b1 M
a1b1 a 0b0Cin
a1b1 M
sଷ sଶ sଵ s଴ , Cସ . Similar to the two-bit approximate full adder, we
C2
C2 M can design a four-bit approximate full adder by cascading two
M
M M C2 M two-bit approximate full adders. AFA12 and AFA21 are
C2 s0 M
s0 selected from these two two-bit approximate full adders as these
s1 s1 s0 s1 s1 s0 designs show better overall performance than the other two
schemes. These four combinations are shown in Fig. 9, while
(a) (b) (c) (d) their implementations in QCA are shown in Fig. 10.
Fig. 6. Schematics of proposed 2-bit approximate full adders: (a) AFA11, (b)
AFA22, (c) AFA12 and (d) AFA21.
Table IV shows that the proposed designs require fewer
gates than an accurate full adder, but at the cost of a reduced
a1 b1 a0 b0 Cin a1 b1 a0 b0 Cin accuracy. An improvement of up to 50% in delay and up to 67%
a1 b1 a0 b0 Cin
a1 b1
C2
a0 b0 Cin in area is achieved. Although AFA1221 has advantages in terms
C2 of the reduced number of gates and delay, its MED/NMED is
C2 C2
the largest. AFA2121 and AFA2112 have the same
s1
s1 s0 s0 s1 s0 s1 s0 MED/NMED, but AFA2121 has less delay. Compared with
AFA2112, AFA1212 requires one less inverter with a reduction
(a) (b) (c) (d) in MED.
a1b1 a0b0Cin
Fig. 7. Layouts of proposed 2-bit approximate full adders in QCA:(a) AFA11, a1b1 a0b0Cin
a0b0Cin
(b) AFA22, (c) AFA12 and (d) AFA21. M a0b0Cin
a2b2
a2b2 a1b1 M a3 b3 a M
M
2b2 a 3b3 a
The proposed two-bit approximate adders introduce errors M
a3 b3
M
2b2 a1b1 M

a 3 b3 M
for 14 of the 32 input combinations; the MED and NMED of the C4 M
s0
M C4 s1 s0
M
C4
four approximate adders are provided in Table III. The error M s1
M
s1 s0 M
s2
C4 M M
s0
s2
results show that by cascading two of the same type of one-bit s3 s3 s2 s3 s3 s2 s1
approximate full adder, the MED and NMED are larger than
(a) (b) (c) (d)
cascading two different types of one-bit approximate full adder;
however, AFA22 incurs in the smallest area and has less delay Fig. 9. Schematics of proposed 4-bit approximate full adders: (a) AFA1212, (b)
than AFA12. Considering the number of gates required in an AFA2121, (c) AFA2112 and (d) AFA1221.
implementation, AFA12 requires one less inverter than AFA21.

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 a3 b3 a2 b2 a1 b1 a0 b0 Cin a3 b3 a2 b2 a1 b1 a0 b0 Cin a3 b3 a1b1 a 0b0Cin
a3 b3 a2 b2 a1 b1 a0 b0 Cin a2 b2 a1 b1 a0 b0 Cin a0b0Cin
a3b 3 M
a2b 2
M M
a2b2 a1b1
M
C4 C4 C4 C4 a4b4
M
s1 s 0 a5b5 M
a4b4 a3b3
s3 s2 s1 s0 s3 s2 s1 s0 s3 s2 s1 s0 s3 s2 s1 s0 a 6b6 a 5b5 M M
s0
s3 s2
a7b7 a b M
6 6
M
a7b7 M M s1
(a) (b) (c) (d) C8 M
s4 M s2
M s5 C8 M
s5 s4 s3
s6
Fig. 10. Layouts of proposed 4-bit approximate full adders in QCA: (a)
s7 s7 s6
AFA1212, (b) AFA2121, (c) AFA2112 and (d) AFA1221.

Fig. 11 shows that AFA2121 is the best design. The NMED (c) (d)
for AFA1221 is rather large and the values for NMED of
AFA1212, AFA2121, AFA2112 are very close, but AFA2112 Fig. 12. Schematics of proposed 8-bit approximate full adders: (a) AFA1212-
1212, (b) AFA2121-2121, (c) AFA2121-1212 and (d) AFA1212-2121.
and AFA1212 require more delay. For four-bit designs, the
schemes in which two of the same type of the proposed two-bit a7 b7 a6 b6 a5 b5 a4 b4 a3 b3 a2 b2 a1 b1 a0 b0 Cin a7 b7 a6 b6 a5 b5 a4 b4 a3 b3 a2 b2 a1 b1 a0 b0 Cin

approximate full adders are cascaded have better performance

than cascading different types of approximate full adders. C8
C8 s2 s1 s0
s3 s2 s1 s0 s3
TABLE IV. FOUR-BIT APPROXIMATE ADDER COMPARISON s7 s6 s5 s4 s7 s6 s5 s4

ADDER TYPE MV INV D A(࢔࢓૛) MED NMED (a) (b)

CFA4[14] 12 8 1.5 405000 0 0 a7 b7 a6 b6 a5 b5 a4 b4 a3 b3 a2 b2 a1 b1 a0 b0 Cin a7 b7 a6 b6 a5 b5 a4 b4 a3 b3 a2 b2 a1 b1 a0 b0 Cin
RCA4[15] 12 4 1.75 254200 0 0
AFA1212 4 2 0.75 76120 2.83 0.091
AFA2121 4 3 0.5 82619 2.87 0.092 C8 s3 s2 s1 s0 C8
AFA2112 4 3 0.75 83936 2.87 0.092 s3 s2 s1 s0
s7 s6 s5 s4 s7 s6 s5 s4
AFA1221 4 2 0.5 82085 5.45 0.175
(c) (d)

Fig. 13. Layouts of proposed 8-bit approximate full adders in QCA: (a)
AFA1212-1212, (b) AFA2121-2121, (c) AFA2121-1212 and (d) AFA1212-
2121.
TABLE V. EIGHT-BIT APPROXIMATE ADDER COMPARISON
ADDER TYPE MV INV D A(࢔࢓૛) MED NMED
CFA8[14] 24 16 2.5 948700 0 0
Fig. 11. Evaluation of proposed 4-bit approximate full adders (NMED vs delay- RCA8[15] 24 8 2.75 745200 0 0
area product). AFA1212-1212 8 4 1.25 184640 46.20 0.090
AFA2121-2121 8 5 1 206425 47.02 0.092
C. Proposed Eight-bit Approximate Adders AFA2121-1212 8 5 1.25 218257 46.40 0.091
Consider an eight-bit adder with inputs, A = AFA1212-2121 8 4 1 191126 46.82 0.092
a଻ a଺ aହ aସ aଷ aଶ aଵa଴ , B = b଻ b଺ bହ bସ bଷ bଶ bଵ b଴ , C୧୬ and outputs, Fig. 14 shows that AFA1212-1212 is the best design by
S = s଻ s଺ sହ sସ sଷ sଶ sଵ s଴ , C଼ . We have designed eight-bit considering both the area-delay product and the NMED.
approximate adders by cascading two four-bit approximate
adders by using AFA1212 and AFA2121, as they show better
overall performance than the other two designs.
The proposed eight-bit approximate adders are shown in Fig.
12; their implementations in QCA are shown in Fig. 13. The
comparison results are detailed in Table V. The proposed
designs significantly reduce the number of gates and delay but
at the cost of a decrease in accuracy. In terms of gates,
AFA1212-1212 and AFA1212-2121 require one less inverter Fig. 14. Evaluation of proposed 8-bit approximate full adders (NMED vs delay-
area product).
than the other adders; AFA2121-2121 and AFA1212-2121
incur less delay than the other adders. V. CONCLUSION
a 0b0C in a1b1 a0b0Cin
a 2b2 a1b1 M
a3b3 a
The paper has proposed ML based one-bit and multi-bit
2b2 M

a 4b4
a 3b3 M
a5b5
M approximate full adders; these designs show considerable
M M
s0
a 6b6 a 5b5 M
s1
a4b4
M
s1 s0
savings in area, delay and number of gates while only incurring
M
s2 a7b7 a6b6 M

a 7b7 M
s3 M
a modest loss in accuracy. Compared with the accurate full
C8 M
s4 M s3 s2
C8 M
s5 s4
adder, the proposed designs result in an improvement of at least
M s5

s7
s6

s7 s6
up to 50% in delay and up to 67% in area for the 4-bit design.
An improvement of at least up to 50% in delay and up to 71%
(a) (b) in area is achieved for the 8-bit scheme.

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