8085 M ICROPROCESSOR BHARAT ACHARYA EDUCATION

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INTERRUPTS OF 8085
¶ An interrupt is a special condition that arises during the working of a µP.
¶ In response, the µP services the interrupt by executing a subroutine called as the Interrupt
Service Routine.
¶ The µP checks for interrupts during every instruction.
¶ When an interrupt occurs, the µP first finishes the current instruction.
¶ It then Pushes the address of the next instruction (contents of PC) on the STACK.
¶ It resets the INTE flip-flop so that no more interrupts are recognized.
¶ Thereafter the program control transfers to the address of the Interrupt Service Routine (ISR)
and the µP thus executes the ISR.

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Interrupts are of two types:

§ Software Interrupts
§ Hardware Interrupts

Software Interrupts:
Interrupts that are initiated through program (software) are called as software interrupts.
8085 supports 8 software interrupts:
RSTn where n = 0,1,2, … 7 i.e. RST0, RST1 … upto RST7.
− This instruction causes a service routine to be Called from the address (n*8).
− Hence, if RST1 occurs then the program control moves to location 0008 (1*8 = 0008).
The respective addresses for software interrupts are given below.

S/W Interrupt ISR Address

RST0 0000H
RST1 0008H
RST2 0010H
RST3 0018H
RST4 0020H
RST5 0028H
RST6 0030H
RST7 0038H

Hardware Interrupts:
Interrupts that are initiated through a hardware pin are called as hardware interrupts.
8085 supports the following hardware interrupts:
− TRAP
− RST 7.5
− RST 6.5
− RST 5.5
− INTR

Vectored Interrupts:
− Interrupts that have a FIXED Address for their ISR (Interrupt Service Routine) are called as
Vectored Interrupts.
− Eg: TRAP is a vectored interrupt. Its vector address is 0024H.

Non-Vectored Interrupts:
− Interrupts that have a Variable Address for their ISR are called as Non-Vectored Interrupts.
− Eg: INTR is a Non-Vectored Interrupt.

Methods of preventing an interrupt from occurring.

− MASK Individual Bits through SIM Instruction
− Disable all Interrupts through DI Instruction

MASKING:
− We can prevent an interrupt from occurring by MASKING its individual bit through SIM
Instruction.
− If an interrupt is masked it will not be serviced.
− One of the main advantages of masking as opposed to disabling interrupts is that by masking
we can selectively disable a particular interrupt while keeping other interrupts active,
whereas through DI instruction all interrupts are disabled.
− ONLY RST 7.5, RST 6.5 and RST 5.5 can be masked by this method.

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DISABLING INTERRUPTS:
− Interrupts can be disabled through the DI Instruction.
− This instruction resets the INTE Flip Flop and hence none of the interrupts can occur (Except
TRAP).
I.e. INTE F/F ß 0.
− Once disabled, these interrupts can be re-enabled through EI instruction, which sets the INTE
Flip Flop.
I.e. INTE F/F ß 1.

Hardware Interrupts (In detail)

TRAP:
− TRAP has the highest priority.
− It is Edge as well as Level triggered hence the signal must go High and also Remain high for
some time for it to be recognized. This prevents any noise signal from being accepted.
− It is a Non-Maskable Interrupt i.e. it can neither be masked nor be disabled.
− It is a vectored interrupt and has a vector address of 0024H.

RST 7.5:
− RST 7.5 has the priority lower than TRAP.
− It is Edge triggered.
− It is a Maskable Interrupt i.e. it can be masked through the SIM Instruction.
− It can also be disabled though the DI Instruction.
− It is a vectored interrupt and has a vector address of 003CH.
− RST 7.5 can also be reset through the R 7.5 bit in the SIM Instruction irrespective of whether
it is Masked or not.

RST 6.5:
− RST 6.5 has the priority lower than RST 7.5.
− It is Level triggered.
− It is a Maskable Interrupt i.e. it can be masked through the SIM Instruction.
− It can also be disabled though the DI Instruction.
− It is a vectored interrupt and has a vector address of 0034H.

RST 5.5:
− RST 5.5 has the priority lower than RST 6.5.
− It is Level triggered.
− It is a Maskable Interrupt i.e. it can be masked through the SIM Instruction.
− It can also be disabled though the DI Instruction.
− It is a vectored interrupt and has a vector address of 002CH.

INTR:
− INTR has the priority lower than RST 5.5.
− It is Level triggered.
− It can only be disabled though the DI Instruction.
− It cannot be masked through the SIM Instruction.
− It is a Non-Vectored interrupt.

Response to INTR:
− When INTR occurs the µP, in response, issues the first INTA cycle.
− The External Hardware sends an opcode, which can be of RSTn Instruction or of CALL
instruction.
a) If opcode of RSTn is sent by the external hardware
¶ The µP calculates the address of the ISR as n*8.
b) If opcode of CALL is sent:
¶ As Call is a 3-Byte Instruction the µP send 2 more INTA signals
¶ In response to the 2nd and the 3rd INTA cycle the external hardware returns the lower
and the higher byte of the address of the ISR respectively.

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− This is how the address is determined when INTR occurs.

INTA : (Interrupt Acknowledge)

− This is an active low acknowledge signal going out of 8085.
− This signal is given in response to an interrupt on INTR ONLY.
− After the first INTA is given, the interrupting peripheral sends an opcode.
− If the Opcode is of RSTn, then the ISR address is calculated as n × 8.
− If the Opcode is of CALL, then two more INTA signals are given and, the lower byte, and
then the higher byte of the ISR address are sent by the peripheral.
#Please refer Bharat Sir's Lecture Notes for this ...

EI and DI Instructions:

INTE F/F : (Interrupt Enable Flip Flop)

− This flip-flop decides if interrupts are enabled in the µP i.e. if it is set, all interrupts are
enabled.
− It is set by the EI Instruction.
− It is reset in the following 3 ways:
i. If µP is reset.
ii. If DI instruction is executed.
iii. If any other interrupt is recognized by the µP. In this case the INTE F/F is later set in the
ISR by EI. J In case of doubts, contact Bharat Sir: - 98204 08217.
− The INTE F/F affects all interrupts EXCEPT TRAP, as it cannot be disabled.

SIM Instruction: (Set Interrupt Mask)

This instruction is used for the following purposes:

i. To Mask or Un-Mask the RST7.5, RST6.5 and RST5.5 interrupts.
ii. To send the data out serially (bit - by - bit) through the SOD line of the µP.
iii. To reset RST7.5 interrupt irrespective of whether it is masked or not.

Serial Comm'n Masking

SOD SDE X R 7.5 MSE M 7.5 M 6.5 M 5.5

Serial Data Enable

1 è Enable Serial Data Mask Set Enable
0 è Disable Serial Data 1 è Enable Masking
0 è Disable Masking Mask Respective Interrupt
1 è Mask respective interrupt
Serial Out Data 0 è Unmask respective interrupt
1 è Data AT SOD = 1 Reset RST 7.5 X è if MSE = 0
0 è Data AT SOD = 0 1 è Reset RST 7.5
X è if SDE = 0 0 è do not Reset RST 7.5

Method of execution:
− The appropriate byte is formed and loaded into the Accumulator.
− Then the SIM Instruction is executed.
− The µP reads the contents of the accumulator in the above order.

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RIM Instruction: (Read Interrupt Mask)

This instruction is used for the following purposes:

i. To read the Interrupt Mask of the µP.
ii. To accept data serially through the SID pin.
iii. To see the "Pending Interrupts" of the µP.
Pending Interrupts Masking

SID I 7.5 I 6.5 I 5.5 IE M 7.5 M 6.5 M 5.5

Interrupt Enable
Serial In Data 1 è Interrupts are Enabled
1 è Data AT SID = 1 0 è Interrupts are Disabled
0 è Data AT SID = 0
Respective Interrupt Masked
Pending Interrupts
1 è Respective interrupt masked
1 è Respective interrupt is pending
0 è Respective interrupt unmasked
0 è Respective interrupt is NOT pending

Pending Interrupts:
Pending interrupts are those interrupts, which are waiting to be serviced.
An interrupt becomes pending as a higher priority interrupt is currently being serviced.
RIM Instruction indicates the Pending Status of RST7.5, RST6.5 and RST5.5.

Method of execution:
− Then the RIM Instruction is executed.
− The µP loads the appropriate byte into the Accumulator.
− The programmer reads the contents of the Accumulator.

Interrupt Properties

Maskable Disabled Vector

Interrupt Priority Triggering Vectored
by SIM by DI Address

TRAP 1 Edge / Level No No Yes 0024 H

RST 7.5 2 Edge Yes Yes Yes 003C H

RST 6.5 3 Level Yes Yes Yes 0034 H

RST 5.5 4 Level Yes Yes Yes 002C H

Get ISR
Address
INTR 5 Level No Yes No from
External
Hardware

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