EC101: BASIC ELECTRONICS (3-0-2:4)

1. Diode:
Basic Diode Theory, Zener Diode, Photodiode, Light Emitting Diode, Varactor Diode, Schottky Diode, Half
Wave Rectifier Circuit, Full Wave Rectifier Circuit and Bridge Rectifier Circuit, Filtering Circuits (C, L, L-C &
π filters), Voltage Multipliers.

2. Transistor:
Transistor Theory, Transistor Action, Transistor Symbols, Common Collector, Common Emitter and Common
Base Configurations, Different Biasing Techniques, Concept of Transistor Amplifier.

3. Digital Electronics:
Boolean Algebra, Logic Gates, Combinational Circuits.

4. Electronic Communication:
Introduction to Radio Frequency Spectrum, Modulation, Need of Modulation, Different Types of Modulation,
Basic Circuits and Blocks of Modulation and Demodulation, Transmitters and Receivers, Application of
Modulation.

5. Electronic Instruments:
Cathode Ray Oscilloscope & Digital Storage Oscilloscope: Theory and Applications, Function Generator,
Power Supply, Digital Multimeter.

Suggested Practical:

1. I-V characteristics of forward biased P-N junction Diode.

2. Reverse characteristics of Zener Diode
3. Zener Diode as a reference Diode.
4. Half-wave rectifier using diode
5. Full-wave rectifier using diode.
6. Bridge rectifier.
7. Truth Table verification of Logic Gates.
8. Design of basic logic gates using NAND & NOR gates.
9. Input & output characteristics of BJT in CB mode.
10. Input & output characteristics of BJT in CE mode.

Text Books:

1. Basic Electronics, Chattopadhyay & Rakshit, New Age Publisher.

References:
1. Electronics Principles, Albert P. Malvino, Publisher: Tata McGraw-Hill
2. Electronics Devices, Thomas L. Floyd, Publisher: Pearson Education
3. Digital Principles & Applications, Albert P. Malvino, Publisher: Tata McGraw-Hill
4. Electronic Communication Systems, John Kennedy & William Devis, Publisher: Tata McGraw-Hill
 NATIONAL INSTITUTE OF TECHNOLOGY
MEGHALAYA

Basic Electronics: Laboratory Manual 2015

 CONTENTS

Sl No Name of Experiment Page No

1. To Study the V-I characteristics of Forward Biased PN junction diode. 1-3

2. To Study the Reverse characteristics of Zener diode. 4-6

3. To Study the working of a diode as half wave rectifier with and without filter. 7-9

4. To Study the working of a diode as Bridge rectifier with and without filter. 10-12

5. To Study the working of a diode as Bridge rectifier with and without filter. 13-15

6. To study the input and output characteristic of BJT in CB configuration. 16-19

7. To study the input and output characteristic of BJT in CE configuration. 20-23

8. Realization of Basic Logic Gates. 24-26

9. Realization of Basic Logic Gates using Universal Gates NAND and NOR. 27-28
 ƒ•‹ Ž‡ –”‘‹ •ƒ„‘”ƒ–‘”›ƒ—ƒŽ

EXPERIMENT NO-1

AIM: To Study the V-I characterristics of Forward Biased PN junction diode.

APPARATUS REQUIRED:

SL Name of Component/Equiipment Specification/Range Quantity

No
1 Regulated DC power suppply 0-30V,1A 1
2 Digital Multimeter 15S 2
3 PN Diode IN4007 1
4 Resistor 100Ÿ 1
5 Breadboard - 1
6 Connecting Wire - As per requirements

THEORY:
p-n junction diode Forw
ward characteristic:

If a positive voltage is applied too the p-type side and a negative voltage to the n-ttype side, current can
flow (depending upon the magnitude of the applied voltage). This configuration is called "Forward
Biased"
At the p-n junction, the "built-in"" electric field and the applied electric field are in
i opposite directions.
When these two fields add, the reesultant field at the junction is smaller in magnittude than the magnitude
of the original "built-in" electric field. This results in a thinner, less resistive dep
pletion region. If the
applied voltage is large enough, tthe depletion region's resistance becomes neglig
gible. In silicon, this
occurs at about 0.6 volts forwardd bias. From 0 to 0.6 volts, there is still consideraable resistance due to
the depletion region. Above 0.6 vvolts, the depletion region's resistance is very sm
mall and current
flows virtually unimpeded.




‡’ƒ”–‡–‘ˆŽ‡ –”‘‹ •ƒ† ‘—‹ ƒ–‹‘‰‹‡‡”‹‰ǡ ‡‰ŠƒŽƒ›ƒͳ

 ƒ•‹ Ž‡ –”‘‹ •ƒ„‘”ƒ–‘”›ƒ—ƒŽ

Calculation for current limiting resistance:

௏
ܴൌ
ூ௠௔௫

Where, V = Supply Voltage V,

Imax =Maximum current rating for diode

CIRCUIT DIAGRAM:

PROCEDURE:

Forward Biased:

1. Make connections as per the circuit diagram.

2. Switch on the power supply.
3. Increase voltage from the power supply from 0V to 7V in step as shown in the observation table.
4. Measure voltage across diode and current through diode
5. Note down readings in the observation table.
6. Plot and draw the V-I characteristic of forward bias on the graph.

‡’ƒ”–‡–‘ˆŽ‡ –”‘‹ •ƒ† ‘—‹ ƒ–‹‘‰‹‡‡”‹‰ǡ ‡‰ŠƒŽƒ›ƒʹ

 ƒ•‹ Ž‡ –”‘‹ •ƒ„‘”ƒ–‘”›ƒ—ƒŽ

OBSERVATION TABLE:

Forward Biased:

SL.NO Supply Voltage V (Volt) Diode Voltage Vd (Volts) Diode Current Id (mA)
1 0
2 0.1
3 0.2
4 0.3
5 0.4
6 0.5
7 0.6
8 0.7
9 0.8
10 0.9
11 1.0
12 1.5
13 2.0
14 2.5
15 3.0
16 3.5
17 4.0
18 4.5
19 5.0
20 5.5
21 6.0
22 6.5
23 7.0

Expected Graph:

CONCLUSION/RESULT: (Wriite your remarks or any difficulties faced during the experiment and how
you have solved them.)

‡’ƒ”–‡–‘ˆŽ‡ –”‘‹ •ƒ† ‘—‹ ƒ–‹‘‰‹‡‡”‹‰ǡ ‡‰ŠƒŽƒ›ƒ͵

 ƒ•‹ Ž‡ –”‘‹ •ƒ„‘”ƒ–‘”›ƒ—ƒŽ

EXPERIMENT NO-2

AIM: To Study the Reverse charracteristics of Zener diode.

APPARATUS REQUIRED:

SL Name of Component/Equiipment Specification/Range Qu

uantity
No
1 Regulated power supply 0-30V,1A 1
2 Digital Multimeter 15S 2
3 Zener diode BZX83-C5V6 1
4 Resistor 1K 1
5 Breadboard - 1
6 Connecting Wire - Ass per the requirements

THEORY: Zener diodes are desiigned to operate in the breakdown region withou
ut damage. By the
varying the doping level, it is posssible to produce Zener diodes with breakdown voltage form 2V
to200V
A p-n junction diode normally dooes not conduct when reversed biased. But if thee reverse bias is
increased, at a particular voltage it starts conducting heavily. This voltage is called breakdown voltage.
High current through the diode can permanently damage it. To avoid high curren
nt, we connect a resistor
is series with it. Once the diode iis starts conducting, it maintains almost constantt voltage across its
terminal whatever may be the current through it. That is, it has very low dynamicc resistance. Hence a
Zener diode is a P-N junction dioode, specially made to work in the breakdown reegion. It is mainly used
in voltage regulators.

‡’ƒ”–‡–‘ˆŽ‡ –”‘‹ •ƒ† ‘—‹ ƒ–‹‘‰‹‡‡”‹‰ǡ ‡‰ŠƒŽƒ›ƒͶ

 ƒ•‹ Ž‡ –”‘‹ •ƒ„‘”ƒ–‘”›ƒ—ƒŽ

Calculation for current limiting resistance:

௏
ܴൌ
ூ௠௔௫

Where, V = Supply Voltage V,

Imax =Maximum current rating for Zener diode

CIRCUIT DIAGRAM:

PROCEDURE:

Reverse Biased:

1. Make connections as per the circuit diagram.

2. Switch on the power supply.
3. Increase voltage from the power supply from 0V to 24 V in step as shown in the observation table.
4. Measure voltage across diode and current through diode
5. Note down readings in the observation table.
6. Plot and draw the reverse biased characteristic on the graph.

‡’ƒ”–‡–‘ˆŽ‡ –”‘‹ •ƒ† ‘—‹ ƒ–‹‘‰‹‡‡”‹‰ǡ ‡‰ŠƒŽƒ›ƒͷ

 ƒ•‹ Ž‡ –”‘‹ •ƒ„‘”ƒ–‘”›ƒ—ƒŽ

OBSERVATION TABLE:
Reverse Biased:

SL.NO Supply Voltage V (Voltss) Diode Voltage Vz (Volts) Diode

D Current Iz (mA)
1 0
2 1
3 2
4 3
5 4
6 5
7 6
8 7
9 8
10 9
11 10
12 11
13 12
14 13
15 14
16 15
17 16
18 17
19 18
20 19
21 20
22 21
23 22
24 23
25 24

Expected GRAPH:

CONCLUSION/RESULT: (Wriite your remarks or any difficulties faced during the experiment and how
you have solved them.)

‡’ƒ”–‡–‘ˆŽ‡ –”‘‹ •ƒ† ‘—‹ ƒ–‹‘‰‹‡‡”‹‰ǡ ‡‰ŠƒŽƒ›ƒ͸

 ƒ•‹ Ž‡ –”‘‹ •ƒ„‘”ƒ–‘”›ƒ—ƒŽ

EXPERIMENT NO-3

AIM: To Study the working of a diode as half wave rectifier with and without filter.

APPARATUS REQUIRED:

SL Name of Component/Equipment Specification/Range Quantity

No
1 Transformer 12-0-12V, 500mA 1
2 Digital Multimeter 15S 1
3 PN diode IN4007 1
4 Resistor 1K 1
5 Capacitor 100uF 1
6 Breadboard - 1
7 Connecting Wire - As per requirements

THEORY: A diode is a unidirectional conducting device, It conducts only when it anode is at higher
voltage w r t its cathode in a half wave rectifier circuit, during positive half cycle of the input, the diode
get forward biased and it conducts. Currents flows through the load resistor RL and voltage is developed
across it. During the negative half cycle of the input, the diode gets reversed biased. Now no current
(except the leakage current which is very small) flows. The voltage across the load resistance during this
period of input cycle is zero. Thus a pure ac signal is converted into a unidirectional signal. It can be
shown that:

௏௠
i) ܸ݀ܿ ൌ Where, Vdc is the output voltage and Vm is peak ac voltage at the input of the rectifier.
గ
௔௖௩௢௟௧௔௚௘௔௧௧௛௘௢௨௧௣௨௧
ii)ܴ݅‫ ݎ݋ݐ݂݈ܿܽ݁݌݌‬ൌ  = 1.21
ௗ௖௩௢௟௧௔௚௘௔௧௧௛௘௢௨௧௣௨௧

CIRCUIT DIAGRAM:

WITHOUT FILTER

‡’ƒ”–‡–‘ˆŽ‡ –”‘‹ •ƒ† ‘—‹ ƒ–‹‘‰‹‡‡”‹‰ǡ ‡‰ŠƒŽƒ›ƒ͹

 ƒ•‹ Ž‡ –”‘‹ •ƒ„‘”ƒ–‘”›ƒ—ƒŽ

WITH FILTER:

PROCEDURE:

1. Make connections as per the circuit diagram.

3. Switch on the power supply.
4. Using DMM measured ac input voltage of the rectifier, ac and dc voltage at the output of the rectifier.
5. Using CRO measured the rectified output voltage.
6. Calculate the ripple factor and rectifier Efficiency.
7. Draw the input and output voltage waveform on the graph.
8. Connect the capacitor across the load resistor.
9. Measured the output voltage using DMM and CRO and note down the value.
10. Draw the output voltage waveform

OBSERVATION TABLE:

WITHOUT FILTER:
SL. Using DMM Using CRO
NO Measured Measured Ripple factor Amplitude Calculated Calculated Ripple factor
ܸ݀ܿሺܸ‫ݏݐ݈݋‬ሻ ܸܽܿሺܸ‫ݏݐ݈݋‬ሻ ߛ ൌ ܸܽܿȀܸ݀ܿ ܸ݉ሺܸ‫ݏݐ݈݋‬ሻ ܸ݀ܿሺܸ‫ݏݐ݈݋‬ሻ ܸ‫ݏ݉ݎ‬ሺܸ‫ݏݐ݈݋‬ሻ ߛ ൌ
ξሺܸ‫ݏ݉ݎ‬Ȁ
ܸ݀ܿሻ2െͳ

WITH FILTER

Sl No Using DMM
Measured Measured Ripple factor Ripple factor
ܸ݀ܿ(Volts) ܸܽܿ(Volts) ߛ ൌ ܸܽܿȀܸ݀ܿ ߛ ൌ ͳȀሺʹξ͵݂‫ܴܥ‬ሻ

‡’ƒ”–‡–‘ˆŽ‡ –”‘‹ •ƒ† ‘—‹ ƒ–‹‘‰‹‡‡”‹‰ǡ ‡‰ŠƒŽƒ›ƒͺ

 ƒ•‹ Ž‡ –”‘‹ •ƒ„‘”ƒ–‘”›ƒ—ƒŽ

THEORITICAL CALCULATIION:

Average DC voltage at the load, ܸ݀ܿ ൌ ܸ݉Ȁߨ

Average DC current att the load, ‫ ܿ݀ܫ‬ൌ ‫݉ܫ‬Ȁߨ
R.M.S value of load Voltage ,ܸ‫ ݏ݉ݎ‬ൌ ܸ݉Ȁʹ
R.M.S value of load Cuurrent ,‫ ݏ݉ݎܫ‬ൌ ‫݉ܫ‬Ȁʹ
mponent ܸܽܿ ൌ ξሺܸ‫ݏ݉ݎ‬2െܸ݀ܿ 2)
R.M.S value of AC com

Without filter,
Ripple factor ߛ
ߛ ൌ ξሺܸ‫ݏ݉ݎ‬Ȁܸ݀ܿሻ2െͳ = 1.21
With filter,
Ripple factor, ߛ ൌ ͳȀሺʹξ͵݂‫ܴܥ‬ሻ
ܹ
ܹ݄݁‫ ݂݁ݎ‬ൌ ͷͲ‫ݖܪ‬
‫ ܥ‬ൌ ͳͲͲɊ‫ܨ‬
ܴ‫ ܮ‬ൌ ͳ‫ߗܭ‬
Rectifier Efficiency : ߟ ൌ ܲ݀ܿȀܲܽܿ
ܲܽܿ ൌ ‫ݏ݉ݎܫ‬2‫ܴݔ‬
ܲ݀ܿ ൌ ‫ ܿ݀ܫ‬2‫ܴݔ‬

Expected Graph:

RESULT/ CONCLUSION: (W Write your remarks or any difficulties faced durin

ng the experiment and
how you have solved them.)

‡’ƒ”–‡–‘ˆŽ‡ –”‘‹ •ƒ† ‘—‹ ƒ–‹‘‰‹‡‡”‹‰ǡ ‡‰ŠƒŽƒ›ƒͻ

 ƒ•‹ Ž‡ –”‘‹ •ƒ„‘”ƒ–‘”›ƒ—ƒŽ

EXPERIMENT NO-4

AIM: To Study the working of a diode as Bridge rectifier with and without filterr.

APPARATUS REQUIRED:

SL Name of Component/Equiipment Specification/Range Quantity

No
1 Transformer 12-0-12V, 500mA 1
2 Digital Multimeter 15S 1
3 PN diode IN4007 2
4 Resistor 1K 1
5 Capacitor 100uF 1
6 Breadboard - 1
7 Connecting Wire - As per requirements

THEORY: In a full-wave rectifiier circuit there are two diodes, a transformer and a load resistor. The
transformer has a center-tap in its secondary winding. It provides out-of-phase to
o the two diodes. During
the positive half-cycle of the inpuut, the diode D2 is reverse biased and it does not conduct. But D1 is
forward biased and it conducts. T
The current flowing through diode D1 also passeed through the load
resistor and a voltage is developeed across it. During the negative half-cycle, the diode
d D2 is forward
biased and D1 is reverse biased. Now current flow through diode D2 and load reesistor RL. The current
flowing through the load resistorr passed in the same direction in both the half-cy
ycles. The dc voltage
obtained at the output is given ass:

ଶ௏௠
i) ܸ݀ܿ ൌ Where, Vdc is thhe output voltage and Vm is peak ac voltage at the
t input of the rectifier
గ
of the ceenter tapped transformer.

௔௖௩௢௟௧௔௚
௚௘௔௧௧௛௘௢௨௧௣௨௧
ii)ܴ݅‫ ݎ݋ݐ݂݈ܿܽ݁݌݌‬ൌ  = 0.482
ௗ௖௩௢௟௧௔௚
௚௘௔௧௧௛௘௢௨௧௣௨௧

CIRCUIT
DIAGRAM:

WITHOUT FILTER

‡’ƒ”–‡–‘ˆŽ‡ –”‘‹ •ƒ† ‘—‹ ƒ–‹‘‰‹‡‡”‹‰ǡ ‡‰ŠƒŽƒ›ƒͳͲ

 ƒ•‹ Ž‡ –”‘‹ •ƒ„‘”ƒ–‘”›ƒ—ƒŽ

WITH FILTER:

PROCEDURE:

1. Make connections as per the circuit diagram.

3. Switch on the power supply.
4. Using DMM measured ac inpuut voltage of the rectifier, ac and dc voltage at th
he output of the rectifier.
5. Using CRO measured the rectiified output voltage.
6. Calculate the ripple factor andd rectifier Efficiency.
7. Draw the input and output volttage waveform on the graph.
8. Connect the capacitor across thhe load resistor.
9. Measured the output voltage uusing DMM and CRO and note down the value.
10. Draw the output voltage wavveform 

OBSERVATION TABLE:

WITHOUT FILTER:

SL. Using DMM Using CRO

C
NO Measured Measured Rippple factor Amplitude Calculated Callculated Ripple factor
ܸ݀ܿሺܸ‫ݏݐ݈݋‬ሻ ܸܽܿሺܸ‫ݏݐ݈݋‬ሻ ߛ ൌ ܸܽܿȀܸ݀ܿ ܸ݉ሺܸ‫ݏݐ݈݋‬ሻ ܸ݀ܿሺܸ‫ݏݐ݈݋‬ሻ Vrmms (Volts) ߛ ൌ
ξሺܸ‫ݏ݉ݎ‬Ȁ
ܸ݀ܿሻ2െͳ

WITH FILTER:
Sl No Using DMM
Measured Measured Ripple factor Ripple factor
ܸ݀ܿ(Volts) ܸܽܿ(Voltts) ߛ ൌ ܸܽܿȀܸ݀ܿ ߛ ൌ ͳȀሺʹξ͵݂‫ܥ‬‫ܴܥ‬ሻ

‡’ƒ”–‡–‘ˆŽ‡ –”‘‹ •ƒ† ‘—‹ ƒ–‹‘‰‹‡‡”‹‰ǡ ‡‰ŠƒŽƒ›ƒͳͳ

 ƒ•‹ Ž‡ –”‘‹ •ƒ„‘”ƒ–‘”›ƒ—ƒŽ

THEORITICAL CALCULATIION:

Average DC voltage at the load, ܸ݀ܿ ൌ ʹܸ݉Ȁߨ

Average DC current att the loadǡ ‫ ܿ݀ܫ‬ൌ ʹ‫݉ܫ‬Ȁߨ

R.M.S value of load Voltage ,ܸ‫ ݏ݉ݎ‬ൌ ܸ݉Ȁξʹ

R.M.S value of load Cuurrent , ‫ ݏ݉ݎܫ‬ൌ ‫݉ܫ‬Ȁξʹ

mponent ܸܽܿ ൌ ξሺܸ‫ݏ݉ݎ‬2െܸ݀ܿ 2ሻ

R.M.S value of AC com

Without filter
Ripple factor ߛ
ߛ ൌ ξሺܸ‫ݏ݉ݎ‬Ȁܸ݀ܿሻʹ െ ͳ ൌ ͲǤͶͺʹ
With filter
Ripple factor, ߛ ൌ ͳȀሺͶξ͵݂‫)ܴܥ‬
Where ݂ ൌ ͷͲ‫ݖܪ‬
W
‫ ܥ‬ൌ ͳͲͲɊ‫ܨ‬
ܴ‫ ܮ‬ൌ ͳ‫ߗܭ‬
Rectifier Efficiency Ș=PPdc/Pac

ܲܽܿ ൌ ‫ܴݔʹݏ݉ݎܫ‬
ܴ
ܲ݀ܿ ൌ ‫ܴݔʹܿ݀ܫ‬
Expected Graph:

RESULT/ CONCLUSION: (W Write your remarks or any difficulties faced durin

ng the experiment and
how you have solved them.)

‡’ƒ”–‡–‘ˆŽ‡ –”‘‹ •ƒ† ‘—‹ ƒ–‹‘‰‹‡‡”‹‰ǡ ‡‰ŠƒŽƒ›ƒͳʹ

 ƒ•‹ Ž‡ –”‘‹ •ƒ„‘”ƒ–‘”›ƒ—ƒŽ

EXPERIMENT NO-5

AIM: To Study the working of a diode as Bridge rectifier with and without filter.

APPARATUS REQUIRED:

SL Name of Component/Equipment Specification/Range Quantity

No
1 Transformer 12-0-12V, 500mA 1
2 Digital Multimeter 15S 1
3 PN diode IN4007 4
4 Resistor 1K 1
5 Capacitor 100uF 1
6 Breadboard - 1
7 Connecting Wire - As per requirements

THEORY:

CIRCUIT DIAGRAM: In a bridge rectifier circuit there are four diodes, a transformer and a load
resistor. When the input voltage is positive at point A, diodes D1 and D2 conduct. The current passed
through the Load resistor. During the other half of the input signal, the point A is negative with respect
to the point B. The diodes D3 and D4 conducts. The current passes through the load resistor in the same
direction as during the positive half-cycle. DC voltage is developed across the load. It can be proved that
the output dc voltage is given by:

ଶ௏௠
i) ܸ݀ܿ ൌ Where, Vdc is the output voltage and Vm is peak ac voltage at the input of the rectifier
గ
of the center tapped transformer.

௔௖௩௢௟௧௔௚௘௔௧௧௛௘௢௨௧௣௨௧
ii)ܴ݅‫ ݎ݋ݐ݂݈ܿܽ݁݌݌‬ൌ  = 0.482
ௗ௖௩௢௟௧௔௚௘௔௧௧௛௘௢௨௧௣௨௧

WITHOUT FILTER A

‡’ƒ”–‡–‘ˆŽ‡ –”‘‹ •ƒ† ‘—‹ ƒ–‹‘‰‹‡‡”‹‰ǡ ‡‰ŠƒŽƒ›ƒͳ͵

 ƒ•‹ Ž‡ –”‘‹ •ƒ„‘”ƒ–‘”›ƒ—ƒŽ

WITH FILTER:
A

B
PROCEDURE:

1. Make connections as per the circuit diagram.

3. Switch on the power supply.
4. Using DMM measured AC and DC voltage at the output of the rectifier.
5. Using CRO measured the rectified output voltage.
6. Calculate the ripple factor and rectifier Efficiency.
7. Draw the input and output voltage waveform on the graph.
8. Connect the capacitor across the load resistor.
9. Measured the output voltage using DMM and CRO and note down the value.
10. Draw the output voltage waveform 

OBSERVATION TABLE:

WITHOUT FILTER:
SL. Using DMM Using CRO
NO Measured Measured Ripple factor Amplitude Calculated Calculated Ripple factor
Vdc Vac Ȗ = Vac/Vdc Vm Vdc Vrms Ȗ =¥ (Vrms/ Vdc )2 -1
(Volts) (Volts) (Volts) (Volts) (Volts)

WITH FILTER

SL Using DMM Using CRO

.N Measured Measured Vac Ripple factor Ripple factor
O Vdc (Volts) (Volts) Ȗ = Vac/Vdc Ȗ =1/ (4¥3 f C R)

‡’ƒ”–‡–‘ˆŽ‡ –”‘‹ •ƒ† ‘—‹ ƒ–‹‘‰‹‡‡”‹‰ǡ ‡‰ŠƒŽƒ›ƒͳͶ

 ƒ•‹ Ž‡ –”‘‹ •ƒ„‘”ƒ–‘”›ƒ—ƒŽ

THEORITICAL CALCULATIION:

Average DC voltage att the load, ܸ݀ܿ ൌ ʹܸ݉Ȁߨ

Average DC current att the loadǡ ‫ ܿ݀ܫ‬ൌ ʹ‫݉ܫ‬Ȁߨ

R.M.S value of load Voltage,ܸ‫ ݏ݉ݎ‬ൌ ܸ݉Ȁξʹ

R.M.S value of load Cuurrent, ‫ ݏ݉ݎܫ‬ൌ ‫݉ܫ‬Ȁξʹ

mponent ܸܽܿ ൌ ξሺܸ‫ݏ݉ݎ‬2െܸ݀ܿ 2ሻ

R.M.S value of AC com

Without filter
Ripple factor ߛ
ߛ ൌ ξሺܸ‫ݏ݉ݎ‬Ȁܸ݀ܿሻʹ െ ͳ ൌ ͲǤͶͺʹ
With filter
Ripple factor, ߛ ൌ ͳȀሺͶξ͵݂‫)ܴܥ‬
Where ݂ ൌ ͷͲ‫ݖܪ‬
W
‫ ܥ‬ൌ ͳͲͲɊ‫ܨ‬
ܴ‫ ܮ‬ൌ ͳ‫ߗܭ‬
Rectifier Efficiency Ș = Pdc/Pac

ܲܽܿ ൌ ‫ܴݔʹݏ݉ݎܫ‬
ܴ
ܲ݀ܿ ൌ ‫ܴݔʹܿ݀ܫ‬

Expected Graph:

RESULT/ CONCLUSION: (W Write your remarks or any difficulties faced durin

ng the experiment and
how you have solved them.)

‡’ƒ”–‡–‘ˆŽ‡ –”‘‹ •ƒ† ‘—‹ ƒ–‹‘‰‹‡‡”‹‰ǡ ‡‰ŠƒŽƒ›ƒͳͷ

 ƒ•‹ Ž‡ –”‘‹ •ƒ„‘”ƒ–‘”›ƒ—ƒŽ

EXPERIMENT NO-6

AIM: To study the input and output characteristic of BJT in CB configuration

APPARATUS REQUIRED:

SL Name of Component/Equipment Specification/Range Quantity

No
1 Dual Regulated power supply 0-30V,1A 1
2 Digital Multimeter - 3
3 Resistor 100Ÿ 1
1K 1
4 Bipolar junction Transistor BC107 1
5 Breadboard - 1
7 Connecting Wire - As per requirements

THEORY: A transistor is a three-terminal device. The three terminals are emitter, base and collector. In
common-base configuration, we make the Base common to both input and output. For normal operation,
the emitter-base junction is forward biased and the collector-base is reverse-biased.
The input characteristic is a plot between iE and vEB keeping voltage vCB constant. This
characteristic is very similar to that of a forward-biased diode. The input dynamic resistance is
calculated using the formula
ο௩ா஻
‫ ݅ݎ‬ൌ at vce=constant
ο௜ா
The collector current IC is less than, but almost equal to the emitter current. The current IE divides into IC
and IB. That is:
‫ ܧܫ‬ൌ ‫ ܥܫ‬൅ ‫ܤܫ‬
The Output characteristic curves are plotted between ic and vCB, keeping voltage iE constant. These
curves are almost horizontal. This shows that the output dynamic resistance, defined below is very high.

ο௩௖஻
‫ ݋ݎ‬ൌ at IE = constant
ο௜௖


When the output side is open ( i.e., IE = 0), the collector current is not zero, but has a small (a few μA)
value. This value of collector current is called collector reverse saturation current, ICBO.
At a given operating point, we define the dc and ac gains (Į) as follows:

dc current gain, Įdc =


οூ௖
ac current gain, Į = at vCB = constant.
ο௜ா

‡’ƒ”–‡–‘ˆŽ‡ –”‘‹ •ƒ† ‘—‹ ƒ–‹‘‰‹‡‡”‹‰ǡ ‡‰ŠƒŽƒ›ƒͳ͸

 ƒ•‹ Ž‡ –”‘‹ •ƒ„‘”ƒ–‘”›ƒ—ƒŽ

CIRCUIT DIAGRAM:

PROCEDURE:

Input characteristics (CB):

1. Connect the circuit for BJT in CB mode as per circuit diagram

2. Switch on the Power supply
3. Keep VCB at a constant value by varying VCC.
4. Set the voltage of VBE by varying VEE.
5. Note down IE value
6. Repeat step 3 and 4 for different value of VCB
7. Plot the BJT Input characteristic for its CB mode
Output characteristics (CB):

1. Connect the circuit for BJT in CB mode as per circuit diagram

2. Switch on the Power supply
3. Keep IE at a constant value by varying VEE
4. Set the voltage of VCB by varying VCC gradually
5. Note down IC value
6. Repeat step 3 and 4 for different of IE
7. Plot the BJT Output characteristic for its CB mode.

‡’ƒ”–‡–‘ˆŽ‡ –”‘‹ •ƒ† ‘—‹ ƒ–‹‘‰‹‡‡”‹‰ǡ ‡‰ŠƒŽƒ›ƒͳ͹

 ƒ•‹ Ž‡ –”‘‹ •ƒ„‘”ƒ–‘”›ƒ—ƒŽ

OBSERVATION TABLE:
Transistor Input characteristics (CB)

Sl.No Supply vCB (Volts) = 0 vCB (Volts) = 2 vCB (Volts) = 4

voltage vBE (Volts) IE (mA) vBE (Volts) vBE (Volts) vBE (Volts) IE (mA)
(Volts)
1
2
3
4
5
6
7
8
9
10
11

Transistor output characteristics (CB)

Sl.No IE (mA) = 0 IE (mA) = 5 IE (mA) = 10 IE (mA) = 20

vCB (Volts) IC (mA) vCB (Volts) IC (mA) vCB (Volts) IC (mA) vCB IC (mA)
(Volts)
1 0
2 1
3 2
4 3
5 4
6 5
7 6
8 7
9 8
10 9
11 10

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 ƒ•‹ Ž‡ –”‘‹ •ƒ„‘”ƒ–‘”›ƒ—ƒŽ

Expected Graph:

Input Characteristics

Output Characteristics

RESULT/ CONCLUSION: (W Write your remarks or any difficulties faced durin

ng the experiment and
how you have solved them.)

‡’ƒ”–‡–‘ˆŽ‡ –”‘‹ •ƒ† ‘—‹ ƒ–‹‘‰‹‡‡”‹‰ǡ ‡‰ŠƒŽƒ›ƒͳͻ

 ƒ•‹ Ž‡ –”‘‹ •ƒ„‘”ƒ–‘”›ƒ—ƒŽ

EXPERIMENT NO-7

AIM: To study the input and output characteristic of BJT in CE configuration

APPARATUS REQUIRED:

SL Name of Component/Equipment Specification/Range Quantity

No
1 Dual Regulated power supply 0-30V,1A 1
2 Digital Multimeter - 3
3 Resistor 26K 1
1K 1
4 Bipolar junction Transistor BC107 1
5 Breadboard - 1
7 Connecting Wire - As per requirements

THEORY: A transistor is a three-terminal device. The three terminals are emitter, base and collector. In
common-emitter configuration, we make the emitter common to both input and output. For normal
operation, the emitter-base junction is forward biased and the collector-base is reverse-biased.
The input characteristic is a plot between iB and vBE keeping voltage vCE constant. This
characteristic is very similar to that of a forward-biased diode. The input dynamic resistance is
calculated using the formula

ο௩஻ா
‫ ݅ݎ‬ൌ , at vCE = constant
ο௜஻
The Output characteristic curves are plotted between ic and vCE, keeping voltage iB constant. These

curves are almost horizontal. This shows that the output dynamic resistance, defined below is very high.

ο௩஼ா
‫ ݋ݎ‬ൌ , at IB = constant
ο௜௖

The collector current IC is less than, but almost equal to the emitter current. The current IE divides into IC
and IB. That is:
‫ ܧܫ‬ൌ ‫ ܥܫ‬൅ ‫ܤܫ‬


‡’ƒ”–‡–‘ˆŽ‡ –”‘‹ •ƒ† ‘—‹ ƒ–‹‘‰‹‡‡”‹‰ǡ ‡‰ŠƒŽƒ›ƒʹͲ

 ƒ•‹ Ž‡ –”‘‹ •ƒ„‘”ƒ–‘”›ƒ—ƒŽ

When the output side is open ( i.ee., IB = 0), the collector current is not zero, but has
h a small (a few μA)
nt, ICBO.
value. This value of collector currrent is called collector reverse saturation curren
At a given operating poinnt, we define the dc and ac gains (Į) as follows:


dc current gain, ȕdc =


οூ௖
ac current gain, ȕ = , at VCE = constant.
ο௜஻

CIRCUIT DIAGRAM:

PROCEDURE:

Input characteristics (CE):

1. Connect the circuit for BJT in CE mode as per circuit diagram

2. Switch on the Power supply
3. Keep vCE at a constant value b y varying vCC.
4. Vary the voltage of vBE by varyying vBB gradually
5. Note down IB value
6. Repeat step 3 and 4 for differeent value of vCE
7. Plot the BJT Input characteristtic for its CE mode

‡’ƒ”–‡–‘ˆŽ‡ –”‘‹ •ƒ† ‘—‹ ƒ–‹‘‰‹‡‡”‹‰ǡ ‡‰ŠƒŽƒ›ƒʹͳ

 ƒ•‹ Ž‡ –”‘‹ •ƒ„‘”ƒ–‘”›ƒ—ƒŽ

Output characteristics (CE):

1. Connect the circuit for BJT in CE mode as per circuit diagram

2. Switch on the Power supply
3. Keep IB at a constant value by varying vEE
4. Vary the voltage of vCE by varying vCC gradually
5. Note down Ic value
6. Repeat step 3 and 4 for different of IB
7. Plot the BJT Output characteristic for its CE mode

OBSERVATION TABLE:

Transistor Input characteristics (CE)

Sl.No vCE (Volts) = 0 vCE (Volts) = 2 vCE (Volts) = 5

vBE (Volts) IB(μA) vBE (Volts) IB(μA) vBE (Volts) IB(μA)
1 0.1
2 0.2
3 0.3
4 0.4
5 0.5
6 0.6
7 0.62
8 0.64
9 0.66
10 0.68
11 0.70

Transistor output characteristics (CE)

Sl.no IB (μA ) = 0 IB (μA ) = 10 IB (μA) = 30 IB (μA ) = 50

vCE (Volts) Ic (mA) vCE Ic (mA) vCE Ic(mA) vCE Ic (mA)
(Volts) (Volts) (Volts)
1 0.0
2 0.5
3 1.0
4 1.5
5 2.0
6 2.5
7 3.0
8 3.5
9 4.0
10 4.5
11 5.0

‡’ƒ”–‡–‘ˆŽ‡ –”‘‹ •ƒ† ‘—‹ ƒ–‹‘‰‹‡‡”‹‰ǡ ‡‰ŠƒŽƒ›ƒʹʹ

 ƒ•‹ Ž‡ –”‘‹ •ƒ„‘”ƒ–‘”›ƒ—ƒŽ

Expected Graph:

RESULT/ CONCLUSION: (Write your remarks or any difficulties faced during the experiment and
how you have solved them.)

‡’ƒ”–‡–‘ˆŽ‡ –”‘‹ •ƒ† ‘—‹ ƒ–‹‘‰‹‡‡”‹‰ǡ ‡‰ŠƒŽƒ›ƒʹ͵

 ƒ•‹ Ž‡ –”‘‹ •ƒ„‘”ƒ–‘”›ƒ—ƒŽ

EXPERIMENT NO-8

AIM: Realization of Logic Gates.

APPARATUS REQUIRED:
SL Name of Component/Equipment Specification/Range Quantity
No
1 ICs 7486, 7400, 7432, 7402, 7404, 7408. One Each
2 Digital IC Trainer 1

3 Connecting Wire/ Patch cords As per requirements

THEORY: Circuit that takes the logical decision and the process are called logic gates. Each
gate has one or more input and only one output.
OR, AND and NOT are basic gates. NAND and NOR are known as universal gates. Basic gates form
these gates.
AND GATE: The AND gate performs a logical multiplication commonly known as AND
function. The output is high when both the inputs are high. The output is low level when
any one of the inputs is low.
OR GATE: The OR gate performs a logical addition commonly known as OR function.
The output is high when any one of the inputs is high. The output is low level when both
the inputs are low.
NOT GATE: The NOT gate is called an inverter. The output is high when the input is low.
The output is low when the input is high.
NAND GATE: The NAND gate is a contraction of AND-NOT. The output is high when both
inputs are low and any one of the input is low .The output is low level when both inputs
are high.
NOR GATE: The NOR gate is a contraction of OR-NOT. The output is high when both inputs
are low. The output is low when one or both inputs are high.
X-OR GATE: The output is high when any one of the inputs is high. The output is low when
both the inputs are low and both the inputs are high.

‡’ƒ”–‡–‘ˆŽ‡ –”‘‹ •ƒ† ‘—‹ ƒ–‹‘‰‹‡‡”‹‰ǡ ‡‰ŠƒŽƒ›ƒʹͶ

 ƒ•‹ Ž‡ –”‘‹ •ƒ„‘”ƒ–‘”›ƒ—ƒŽ

Name Circuit diagram: Truth Table:

A B Y
0 0 0
AND Gate (IC 7408)
0 1 0
1 0 0
1 1 1

Truth Table:
A B Y
0 0 0
0 1 1
OR Gate (IC 7432)
1 0 1
1 1 1

Truth Table:

A Y
NOT Gate (IC 7404) 0 1
1 0

Truth Table:

NAND Gate(IC 7400) A B Y

0 0 1
0 1 1
1 0 1
1 1 0

Truth Table:
A B Y
0 0 1
NOR Gate(IC 7402)
0 1 0
1 0 0
1 1 0

Truth Table:
A B Y
0 0 0
XOR Gate(IC 7486) 0 1 1
1 0 1
1 1 0

‡’ƒ”–‡–‘ˆŽ‡ –”‘‹ •ƒ† ‘—‹ ƒ–‹‘‰‹‡‡”‹‰ǡ ‡‰ŠƒŽƒ›ƒʹͷ

 ƒ•‹ Ž‡ –”‘‹ •ƒ„‘”ƒ–‘”›ƒ—ƒŽ

Procedure: -

1. Verify the gates.

2. Make the connections as per the circuit diagram.
3. Switch on VCC and keep it at 5V and apply various combinations of input according to truth table.
4. Note down the output readings and verify their truth tables.

Expected Output: (As per the truth table)

RESULT/ CONCLUSION: (Write your remarks or any difficulties faced during the experiment and
how you have solved them.)

‡’ƒ”–‡–‘ˆŽ‡ –”‘‹ •ƒ† ‘—‹ ƒ–‹‘‰‹‡‡”‹‰ǡ ‡‰ŠƒŽƒ›ƒʹ͸

 ƒ•‹ Ž‡ –”‘‹ •ƒ„‘”ƒ–‘”›ƒ—ƒŽ

EXPERIMENT NO-9

AIM: Realization of Basic Logic Gates using Universal Gates NAND and NOR.

APPARATUS REQUIRED:
Sl. No Name of Component/Equipment Specification/Range Quantity
1 ICs 7400, 7402, As per requirements
2 Digital IC Trainer and Bread Board One Each

3 Connecting Wire/ Patch cords As per requirements

4 Power Supply (0-15V) -----

THEORY: A universal gate is a gate which can implement any Boolean function without need to use
any other gate type.

The NAND and NOR gates are universal gates.

In practice, this is advantageous since NAND and NOR gates are economical and easier to fabricate and
are the basic gates used in all IC digital logic families.

In fact, an AND gate is typically implemented as a NAND gate followed by an inverter not the other
way around!!

Likewise, an OR gate is typically implemented as a NOR gate followed by an inverter not the other way
around!!

Realizations of Different logic gates using NAND and NOR gates:

Circuit diagram:

1) NOT using NAND Gate

2) OR Using NAND Gate

‡’ƒ”–‡–‘ˆŽ‡ –”‘‹ •ƒ† ‘—‹ ƒ–‹‘‰‹‡‡”‹‰ǡ ‡‰ŠƒŽƒ›ƒʹ͹

 ƒ•‹ Ž‡ –”‘‹ •ƒ„‘”ƒ–‘”›ƒ—ƒŽ

3) AND Using NAND Gate

4) AND Using NOR Gate

5) OR Using NOR Gate

6) NOT Using NOR Gate

PROCEDURE:

1. Verify the gates.

2. Make the connections as per the circuit diagram.
3. Switch on VCC and keep it at 5V and apply various combinations of input according to truth table.
4. Note down the output readings and verify their truth tables.

Expected Output: (As per the truth table)

RESULT/ CONCLUSION: (Write your remarks or any difficulties faced during the experiment and
how you have solved them.)

‡’ƒ”–‡–‘ˆŽ‡ –”‘‹ •ƒ† ‘—‹ ƒ–‹‘‰‹‡‡”‹‰ǡ ‡‰ŠƒŽƒ›ƒʹͺ