AX99100

PCIe to Multi I/O Controller

Document No: AX99100/V1.01/03/05/19
Features
Supports to fragment large data block into several
PCI Express
smaller transfers on SPI bus to reduce software
Single-lane (X1) PCI Express End-point loading
Controller with PHY integrated Supports programmable transfer 0 ~ 8 bytes
Compliant with PCI Express 2.0 Gen 1 OP-Code field in each transfer automatically to
Compliant with PCI Express card specifications reduce software loading
Compliant with PCI Power Management 1.2 Supports wakeup by SWAKEn pin from Slave
Supports four PCI Express functions
Supports both legacy and MSI Interrupts
Local Bus Interface
Supports ASPM Power Management
Supports memory or I/O access through PCIe
BAR0/1 to local bus interface, each BAR
Serial Port Interface mapping to local bus' chip select (CS0n and
Dual or Quad UARTs CS1n)
Supports RS-232/RS-422/RS-485 Supports direct access and bus master access
multiprotocol (auto-increment and fixed address)
Bi-directional speeds up to 25 Mbps per port Supports 8-bit or 16-bit data bus width (little
Full Serial Modem Control and big endian bus swap)
Supports Hardware, Software Flow Control Supports up to 2 Kbytes address space and 2
chip select outputs when separated address/data
Supports 5, 6, 7, 8 and 9-bit Serial format
bus style
Supports Even, Odd, None, Space and Mark
Supports up to 64 Kbytes address space and 2
parity
chip select outputs when multiplexed
Supports Custom baud rate by internal PLL or
address/data bus style
external clock
Supports programmable local chip select region
Supports On Chip 256 Byte depth FIFOs in
Supports “Slave Request based DMA” access
Transmit, Receive path of each Serial Port
for interfacing with external device with bus
Supports remote wakeup and power
master
management features
Supports clock out, CLKO, up to 62.5MHz
Serial Port transceiver shutdown support
Supports asynchronous or synchronous Local
Supports Slow IrDA mode (up to 115200bps)
Bus with required clock output, CLKO
on all Serial Ports
Supports programmable bus access cycles,
Supports multi-drop application for 9-bit mode self-terminated bus access cycles and
Supports DMA burst transfer back-to-back turnaround cycles
Supports programmable RSTO, ALE, RDY,
Parallel Port DREQ0/1, DACK0/1, CLKO polarity, and
INT0/1 level/edge trigger
Compatible with IEEE 1284 – SPP/Byte/ECP
Mode Supports wakeup by INT0/1 and DREQ0/1 pins

SPI Master Interface Supports I2C Master Interface

Programmable SPI clock frequency up to 42MHz Up to 24 bi-directional GPIO lines including 8
Supports Mode 0, Mode 1, Mode 2 and Mode 3 dedicated GPIO and 16 multi-function GPIO
timing modes Integrates on-chip power-on reset circuit
Supports MSB/LSB first transfer fashion On Chip 3.3 to 1.2V Regulator
Programmable peripheral chip select, selecting up 68-pin QFN RoHS compliant package
to 7 SPI devices Operating temperature range: 0 to 70°C or -40 to
Supports Non-Burst-Type transfer up to 8 bytes +85°C
and/or Burst-Type transfer via DMA mode for
high performance

ASIX ELECTRONICS CORPORATION Release Date: 03/05/2019

4F, NO.8, Hsin Ann Rd., HsinChu Science Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500
FAX: 886-3-579-9558
http://www.asix.com.tw
 AX99100
PCIe to Multi I/O Controller
Product Description
The AX99100 is a single chip solution that fully integrates PCIe 2.0 Gen 1 end-point controller and SerDes with a
variety of peripherals such as four High Speed Serial Ports, one Parallel Port, I 2C Master, High Speed SPI, Local
Bus (ISA-Like), and GPIOs. It consists of four main configurations such as 4S (PCIe to Quad Serial), 2S+1P (PCIe
to Dual Serial and Single Parallel), 2S+SPI (PCIe to Dual Serial and SPI), and LB (PCIe to Local Bus/ISA-Like)
for different kinds of applications.

The AX99100, in 68-pin QFN, are available with RoHS compliant package and supports commercial grade
operating temperature range from 0 to 70°C and industrial grade from -40 to 85°C.

Target Applications

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 AX99100
PCIe to Multi I/O Controller

Copyright © 2016-2019 ASIX Electronics Corporation. All rights reserved.

DISCLAIMER

No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical,
including photocopying and recording, for any purpose, without the express written permission of ASIX. ASIX
may make changes to the product specifications and descriptions in this document at any time, without notice.

ASIX provides this document “as is” without warranty of any kind, either expressed or implied, including without
limitation warranties of merchantability, fitness for a particular purpose, and non-infringement.

Designers must not rely on the absence or characteristics of any features or registers marked “Reserved”,
“Undefined” or “NC”. ASIX reserves these for future definition and shall have no responsibility whatsoever for
conflicts or incompatibilities arising from future changes to them. Always contact ASIX to get the latest document
before starting a design of ASIX products.

TRADEMARKS

ASIX, the ASIX logo are registered trademarks of ASIX Electronics Corporation. All other trademarks are the
property of their respective owners.

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 AX99100
PCIe to Multi I/O Controller
Table of Contents
1 INTRODUCTION ......................................................................................................................................... 7
GENERAL DESCRIPTION ........................................................................................................................... 7
AX99100 BLOCK DIAGRAM .................................................................................................................... 8
AX99100 PINOUT DIAGRAM ................................................................................................................... 9
SIGNAL DESCRIPTION ............................................................................................................................ 10
1.4.1 GPIO and Mode Setting ................................................................................................................ 12
1.4.2 Serial Interface for COM Port ...................................................................................................... 13
1.4.3 Serial Interface for Multi-Protocol Transceiver ........................................................................... 14
1.4.4 Serial Port with GPIO enabled ..................................................................................................... 15
1.4.5 Serial Port with Function Disabled............................................................................................... 16
1.4.6 Parallel Port.................................................................................................................................. 17
1.4.7 SPI Interface.................................................................................................................................. 18
1.4.8 Local Bus Interface ....................................................................................................................... 19
2 FUNCTION DESCRIPTION ..................................................................................................................... 20
CLOCKS/RESETS AND POWER ................................................................................................................ 20
PCIE OPERATION ................................................................................................................................... 20
I2C CONTROLLER ................................................................................................................................... 22
SERIAL PORT (SP) .................................................................................................................................. 22
PARALLEL PORT (PP)............................................................................................................................. 22
SPI MASTER CONTROLLER (SPI) ........................................................................................................... 23
LOCAL BUS CONTROLLER (LB) ............................................................................................................. 24
GPIO FUNCTION .................................................................................................................................... 25
POWER MANAGEMENT........................................................................................................................... 25
3 CHIP CONFIGURATION ......................................................................................................................... 26
BOOT STRAPPING PINS FOR CHIP MODE ................................................................................................ 26
DTR BOOT STRAPPING PINS FOR SERIAL PORT ..................................................................................... 27
HARDWARE CONFIGURATION EEPROM ............................................................................................... 28
3.3.1 Configuration EEPROM Memory Map for None Local Bus Interface ......................................... 29
3.3.2 Configuration EEPROM Memory Map for Local Bus Interface ................................................... 36
3.3.3 Hardware Default Values Summary .............................................................................................. 45
3.3.4 Disable Unused PCIe Function in HWCFGEE ............................................................................. 48
PCIE CONFIGURATION SPACE MAP........................................................................................................ 51
4 ELECTRICAL SPECIFICATIONS ......................................................................................................... 53
DC CHARACTERISTICS ........................................................................................................................... 53
4.1.1 Absolute Maximum Ratings ........................................................................................................... 53
4.1.2 Recommended Operating Condition ............................................................................................. 53
4.1.3 Leakage Current and Capacitance................................................................................................ 53
4.1.4 DC Characteristics of 3.3V with 5V Tolerant I/O Pins ................................................................. 54
4.1.5 DC Characteristics of Voltage Regulator ..................................................................................... 54
PCIE SPECIFICATIONS ............................................................................................................................ 55
POWER CONSUMPTION ........................................................................................................................... 56
POWER–UP/DOWN AND POWER MANAGEMENT SEQUENCE .................................................................... 57
AC TIMING CHARACTERISTICS .............................................................................................................. 58
4.5.1 PCIe Reference Clock Timing ....................................................................................................... 58
4.5.2 I2C Timing ..................................................................................................................................... 58
4.5.3 Serial Port Timing ......................................................................................................................... 59
4.5.4 SPI Timing..................................................................................................................................... 60
4.5.5 Local Bus Timing .......................................................................................................................... 61
5 PACKAGE INFORMATION .................................................................................................................... 72
6 ORDERING INFORMATION .................................................................................................................. 73
7 REVISION HISTORY................................................................................................................................ 73
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 AX99100
PCIe to Multi I/O Controller

List of Figures
FIGURE 1-1: AX99100 BLOCK DIAGRAM ................................................................................................................ 8
FIGURE 1-2: AX99100 PINOUT DIAGRAM ............................................................................................................... 9
FIGURE 4-1: TXD1 AND RXD1 TIMING DIAGRAM ................................................................................................ 59
FIGURE 4-2: HIGH SPEED SPI MASTER CONTROLLER TIMING DIAGRAM AND TABLE ........................................... 60
FIGURE 4-3: NON-MULTIPLEXED BUS TYPE WITH EXTERNAL RDY TIMING DIAGRAM ......................................... 61
FIGURE 4-4: ISA-LIKE BUS TYPE WITH EXTERNAL RDY TIMING DIAGRAM ......................................................... 62
FIGURE 4-5: NON-MULTIPLEXED BUS TYPE WITH INTERNAL CYCLE COUNT TIMING DIAGRAM............................ 63
FIGURE 4-6: MULTIPLEXED BUS TYPE WITH EXTERNAL RDY TIMING DIAGRAM ................................................. 64
FIGURE 4-7: MULTIPLEXED BUS TYPE WITH INTERNAL CYCLE COUNT TIMING DIAGRAM .................................... 65
FIGURE 4-8: NON-MULTIPLEXED BUS TYPE WITH EXTERNAL RDY TIMING DIAGRAM ......................................... 66
FIGURE 4-9: ISA-LIKE BUS TYPE WITH EXTERNAL RDY TIMING DIAGRAM ......................................................... 67
FIGURE 4-10: NON-MULTIPLEXED BUS TYPE WITH INTERNAL CYCLE COUNT TIMING DIAGRAM.......................... 68
FIGURE 4-11: MULTIPLEXED BUS TYPE WITH EXTERNAL RDY TIMING DIAGRAM ............................................... 69
FIGURE 4-12: NON-MULTIPLEXED BUS TYPE WITH INTERNAL CYCLE COUNT TIMING DIAGRAM.......................... 70

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 AX99100
PCIe to Multi I/O Controller

List of Tables
TABLE 1-1: COMMON PIN DESCRIPTION ................................................................................................................ 10
TABLE 1-2: PCIE PIN DESCRIPTION ....................................................................................................................... 11
TABLE 1-3: POWER/GROUND PIN DESCRIPTION..................................................................................................... 11
TABLE 1-4: GPIO AND MODE SETTING PIN DESCRIPTION ..................................................................................... 12
TABLE 1-5: SERIAL INTERFACE FOR COM PORT PIN DESCRIPTION ....................................................................... 13
TABLE 1-6: SERIAL INTERFACE FOR MULTI-PROTOCOL TRANSCEIVER PIN DESCRIPTION ..................................... 14
TABLE 1-7: SERIAL INTERFACE FOR GPIO ENABLED PIN DESCRIPTION ................................................................ 15
TABLE 1-8: SERIAL INTERFACE WITH PORT2 AND PORT4 DISABLED PIN DESCRIPTION ......................................... 16
TABLE 1-9: PARALLEL PORT PIN DESCRIPTION ..................................................................................................... 17
TABLE 1-10: SPI PIN DESCRIPTION ........................................................................................................................ 18
TABLE 1-11: LOCAL BUS PIN DESCRIPTION ........................................................................................................... 19
TABLE 3-1: CHIP MODE SELECTION PINS .............................................................................................................. 26
TABLE 3-2: CHIP MODE SELECTION TABLE ........................................................................................................... 27
TABLE 3-3: DTR MODE SELECTION PINS ............................................................................................................... 27
TABLE 3-4: CONFIGURATION EEPROM MEMORY MAP FOR NONE LOCAL BUS MODE .......................................... 29
TABLE 3-5: CONFIGURATION EEPROM MEMORY MAP FOR LOCAL BUS .............................................................. 36
TABLE 3-6: HARDWARE DEFAULT VALUES IN EACH CHIP_MODE SETTING ....................................................... 45
TABLE 3-7: THE HWCHGEE CONTENT FOR 1S SETTING ....................................................................................... 48
TABLE 4-1: I2C MASTER CONTROLLER TIMING TABLE.......................................................................................... 58
TABLE 4-2: LOCAL BUS TIMING TABLE ................................................................................................................. 71

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 AX99100
PCIe to Multi I/O Controller
1 Introduction
General Description
AX99100, PCI Express to Multi-I/O Controller, is a single chip solution for PCI express-based high performance
Serial, Parallel port, SPI and Local Bus connectivity. It provides rich features and highly configurability for variety
products.

AX99100 is a fully integrated, single-lane PCI express end-point controller and SerDes with rich high
performance peripherals such as four High Speed Serial Ports, one Parallel Port, I2C Master, one High Speed SPI
and Local Bus interface. AX99100 also provides rich GPIO ports can be controlled by software driver for some
automation control applications.

The High Speed Serial Ports with the throughput up to 25Mbps, it can works with RS-232/RS-422/RS-485
multi-protocol transceivers and allow easy reconfigured Full/Half-duplex, Loopback and Termination resistors by
software. The Parallel Port is compatible with IEEE 1284 and supports SPP, Nibble, Byte and ECP modes. An I2C
interface is provided to configure AX99100 device options through an external EEPROM after chip reset and also
supports to access other I2C device. SPI master provides a full-duplex, synchronous serial communication
interface (4 wires) to flexibly work with numerous SPI peripheral devices. Local Bus interface provides
configurable asynchronous or synchronous, 8 or 16 bits data bus width with specified endian type and address/data
multiplexed or separated bus type access mode to support variety slave interface access types. All the GPIO pins
are programmable and can be used as Input or Output. AX99100 supports 8 dedicated GPIO and every serial port
pins can be configured as GPIO by software.

Generally, the clock source of AX99100 is from PCIe slot. AX99100 don’t need any other clock source for the
main operations. But AX99100 still supports a clock input from external oscillator for those special baud rate
generated for UART, SPI and Local Bus used. AX99100 also integrates power-on reset circuit and 3.3V to 1.2V
voltage regulator on-chip to provide simplifies reset and power supply for the core power of the chip. It supports
single power operation and reduces the overall BOM cost.

AX99100 is available in 68-pin QFN RoHS compliant package and supports commercial grade operating
temperature range from 0 to 70°C and Industrial grade operating temperature range from -40 to 85°C.

AX99100 provides cost effective solution to enable simple, easy, and low cost integration capability for PCIe to
rich interface conversion applications. It could also provide highly programmable flexibility and compatibility for
many applications such as serial, parallel and Bridge for home automation and Industrial control.

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 AX99100
PCIe to Multi I/O Controller

AX99100 Block Diagram

CLKN, CLKP, RXD[4:1],

REXT,
DIN,DIP, PCIe PHY TXD[4:1],
DON, DOP, & CTS[4:1],
WAKEn Controller DSR[4:1]
CLKREQn, Serial Port x 4
RI[4:1],
RSTn
DCD[4:1],
RTS[4:1]
SS[2:0], DTR[4:1]
SCLK,
MOSI, SPI
MISO,
SWAKEn STROBEn,
AUTOLFn
INITn,
CLKO, SELECTINn,
RSTO, ACKn,
CS0n, PCIe Parallel Port
BUSY,
CS1n, Arbiter
PAPEREND,
ALE, SELECT,
A[9:0], PP_DIR
AD[15:0], Local Bus DATA[7:0]
RDn,
WRn,
RDY,
24 GPIO GPIO[23:0]
INT[1:0],
DREQ[1:0],
DACK[1:0]
I2C SCL, SDA
VCC33A_REG,
LDO
VO12

POR &
EXT_CLK, OSC & Reset Gen. RSTn
EXT_CLK_PDn Clock Gen.

Figure 1-1: AX99100 Block Diagram

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 AX99100
PCIe to Multi I/O Controller

AX99100 Pinout Diagram

AX99100 is housed in a 68-pin QFN package.

RXD4 / RDn / SELECTINn / SWAKEn

DTR4 / CS1n / AUTOLFn / SS2
GPIO0 / CLKO / FAULTn

RTS4 / ALE / INITn / SS1

DCD3 / DREQ1 / DATA6

TXD4 / CS0n / STROBEn

DSR3 / DACK0 / DATA5

CTS3 / DACK1 / DATA7

RI3 / DREQ0 / DATA4
RXD3 / A7 / DATA3
TXD3 / A4 / DATA0

DTR3 / A5 / DATA1

RTS3 / A6 / DATA2

VCC33A_REG
VCCIO

VCCK

VO12
51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35
GPIO1 / RSTO / PP_DIR 52 34 RI4 / WRn / ACKn / SS0

GPIO2 / A3 53 33 DSR4 / RDY / BUSY / MISO

GPIO3 / A2 / CHIP_MODE[0] 54 32 DCD4 / INT0 / PAPEREND / MOSI

VCCIO 55 31 CTS4 / INT1 / SELECT / SCLK

GPIO4 / A1 / CHIP_MODE[1] 56 30 SDA

VCCK 57 29 EXT_CLK_PDn

GPIO5 / A0 / CHIP_MODE[2] 58 28 TEST_MODE

GPIO6 / A8 59 27 SCL

GPIO7 / A9 60 26 VCCIO

CTS2 / AD15 61 25 EXT_CLK

DCD2 / AD14 62 24 RSTn

DSR2 / AD13 63 AX99100 23 CLKREQn

RI2 / AD12 64 22 VCCK

RXD2 / AD11 65 21 WAKEn

RTS2 / AD10 66 20 CLKN

DTR2 / AD9 67 19 CLKP

TXD2 / AD8 68 18 VCC12A_AUX

10

11

12

13

14

15

16

17
1

9
RI1 / AD4

DSR1 / AD5
CTS1 / AD7

RTS1 / AD2

DTR1 / AD1

TXD1 / AD0

DON

DIN
DOP

DIP
DCD1 / AD6

RXD1 / AD3

REXT
VCCIO

VCCK

VCC12A_D
VCC12A_TX

Figure 1-2: AX99100 Pinout Diagram

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 AX99100
PCIe to Multi I/O Controller

Signal Description
Following abbreviations are used in “Type” column of following pin description tables. Note that some I/O pins with
multiple signal definitions on the same pin may have different attribute in “Type” column for different signal
definition.

AB Analog Bi-directional I/O O5 Output, 3.3V with 5V tolerant

AI Analog Input PU Internal Pull-Up (75K)
AO Analog Output PD Internal Pull-Down (75K)
B3 Bi-directional I/O, 3.3V CU Controllable internal Pull-Up
B5 Bi-directional I/O, 3.3V with 5V tolerant P Power and ground pin
S Schmitt Trigger
I3 Input, 3.3V T Tri-state
I5 Input, 3.3V with 5V tolerant 4m 4mA driving strength
O3 Output, 3.3V 8m 8mA driving strength

For example, pin 5 in AX99100 package can be RXD1 or AD3. If RXD1 is selected, its Type is I5/PU; if AD3 is
selected, its Type is B5/4m. In other words, the PU (internal pull-up) only takes effect in RXD1 signal mode while
AD3 signal mode doesn’t. User should refer to the table specific to desired function for exact pin type definition.

The multi-function pin settings are configured by pin 54, 56 and 58 to decide the chip operating mode. Please
reference to Section 3 in detailed. The following abbreviations are used in pin description tables.

HWCFGEE I2C Hardware Configuration EEPROM

CHIP_MODE Chip Operating Mode, Setting by external pull the pin 54, 56 and 68

Table 1-1: Common Pin Description

Common Pins
Pin Name Type Pin No Pin Description
TEST_MODE I5/PD 28 Test Mode enable. For normal operation, please always tie to logic low or NC.
EXT_CLK I5 25 External Clock Input from external Oscillator.
Note: The Max. frequency of EXT_CLK is not greater than 60Mhz. This clock is
only for baud rate generation of internal serial port or Local Bus interface.
It cannot be used for Common Clock of PCIe. AX99100 supports the Slot
Clock for PCIe only.
EXT_CLK_PDn B5 29 External Clock Power Down enable.
0: Power down external Oscillator.
1: Enable external Oscillator.
Note: When external Oscillator existed, this pin should be pull down by external
resistor for boot strapping latch. Otherwise, please pull-up by external
resistor to indicate the Hardware there is NO external Oscillator existed.
SCL O5/T/4 27 I2C Serial Clock line for I2C master controller.
m SCL is a tri-stateable output, which requires an external pull-up resistor.
SDA B5/T/4 30 I2C Serial Data line for I2C master controller.
m SDA is a tri-stateable output, which requires an external pull-up resistor.

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 AX99100
PCIe to Multi I/O Controller
Table 1-2: PCIe Pin Description
PCIe interface
Pin Name Type Pin No Pin Description
CLKN AI 20 PCIe PHY differential PLL reference clock.
CLKP AI 19 PCIe PHY differential PLL reference clock.
Bandgap External Resistor
REXT AO 17 Connect this pin to ground through an external resistor of 20KΩ, ±1%. The total
parasitic capacitor of this pin to ground must be less than 10 pF
DIN AI 16 PCIe PHY differential negative serial data input.
DIP AI 15 PCIe PHY differential positive serial data input.
DOP AO 11 PCIe PHY differential positive serial data output.
DON AO 12 PCIe PHY differential negative serial data output.
An open-drain, active low signal that is driven low by a PCI Express function to
WAKEn O5/T/4m 21 reactivate the PCI Express Link hierarchy’s main power rails and reference
clocks.
Reference clock request signal
This pin is an open drain, active low signal that is driven low by the PCI Express
CLKREQn O5/T/4m 23 Mini Card function to request that the PCI Express reference clock be available
(active clock state) in order to allow the PCI Express interface to send/receive
data.
Active low asynchronous reset from PCIe.
I5/PU/S/
RSTn 24 Indicates when the applied main power is within the specified tolerance and
4m
stable.

Table 1-3: Power/Ground Pin Description

Power/Ground Pins
Pin Name Type Pin No Pin Description
6, 26, 39, Digital Power for I/O pins, 3.3V
VCCIO P
55 Please add a 0.1uF bypass capacitor between each VCCIO and GND.
10, 22, Digital Power for core, 1.2V
VCCK P
37, 57 Please add a 0.1uF bypass capacitor between each VCCK and GND.
GND P EPAD Ground for all Analog and Digital Power.
VCC33A_REG P 36 Analog Power for Regulator, 3.3V
1.2V Power Output of on-chip 3.3V to 1.2V Regulator.
VO12 P 35 The regulator requires an external capacitor (at least 3.3 μF) with low ESR for
frequency compensation and stability maintenance.
Analog Power for PCIe Transmitter, 1.2V.
VCC12A_TX P 13
Please add a 0.1 and 10 uF bypass capacitor between VCC12A_TX and GND.
Analog Power for PCIe Transceiver, 1.2V.
VCC12A_D P 14
Please add a 0.1 and 10 uF bypass capacitor between VCC12A_D and GND.
Analog Power for PCIe Auxiliary, 1.2V.
VCC12A_AUX P 18 Please add a 0.1 and 10 uF bypass capacitor between VCC12A_AUX and
GND.

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 AX99100
PCIe to Multi I/O Controller
1.4.1 GPIO and Mode Setting

Table 1-4: GPIO and Mode Setting Pin Description

GPIO and Mode Setting Pins
Pin Name Type Pin No Pin Description
31, 32,
33, 34,
38, 40, General Purpose I/O signal
41, 42, GPIO[15:8] are only valid when CHIP_MODE = 100 and 110.
GPIO[23:8] B5/CU/4m
43, 44, GPIO[23:16] are only valid when CHIP_MODE = 100 and 110 and Port 4 was
45, 46, disabled by HWCFGEE. Please reference to Section 3.
47, 48,
49, 50
General Purpose Output signal
GPIO7 B5/CU/8m 60 GPIO7 has an optional function is external wakeup pin in input direction. When
AX99100 entered to L2 mode, this pin can be used to wakeup AX99100 also.
General Purpose Output signal
GPIO6 has an optional function is a power-down control signal to power down
GPIO6 B5/CU/8m 59 the external transceiver when AX99100 entered to L2 mode. This function can be
enabled by setting bit1 and the polarity selection is bit0 in configuration
EEPROM, offset 0x55.
GPIO5/ O5/ 8m 58
CHIP_MODE[2] General Purpose Output signal when chip exited reset and operating in normal
GPIO4/ functional mode.
O5/8m 56
CHIP_MODE[1] These pins are input direction during chip reset use to bootstrap the mode setting
GPIO3/ O5/8m 54 to decide the chip operation mode. Please reference to Section 3.1.
CHIP_MODE[0]
General Purpose Output signal when chip exited reset and operating in normal
functional mode.
GPIO2 O5/8m 53
This pin should be connected to the AUX 3.3V in PCIe slot via an external
pull-up resistor. It is used to detect the 3.3V AUX is existed or not.
GPIO1 B5/CU/8m 52 General Purpose I/O signal
GPIO0 B5/CU/8m 51 General Purpose I/O signal
Note: Above GPIO[7:0] are only valid when CHIP_MODE ≠ 000.

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 AX99100
PCIe to Multi I/O Controller
1.4.2 Serial Interface for COM Port
Table 1-5: Serial Interface for COM Port Pin Description
Serial Interface for COM Port
Pin Name Type Pin No Pin Description
TXD1 9
TXD2 68
O5/4m Transmit data output to transceiver or IrDA data output to IR LED
TXD3 50
TXD4 42
Data Terminal Ready
DTR1 8 These pins have internal pull-down during reset. If there is the external pull-up
DTR2 67 resisters connected to these pins separately, it will work for RS-232 function with
B5/PD/4m
DTR3 49 active low. Otherwise, it will work for RS-485 function (DXEN) with active high
DTR4 41 and the output can be enabled by register (the default is disabled). Please
reference to Section 3.2.
RTS1 7 Request to send (Active Low)
RTS2 66
O5/4m
RTS3 48 Note: These pins will be changed to RXEN when Software enabled RS-485
RTS4 40 function for the corresponding ports.
RXD1 5
RXD2 65 Serial received data input from transceiver or IrDA data input from IrDA
I5/PU
RXD3 47 detector.
RXD4 38
RI1 3
RI2 64
I5 Ring Indicator (Active Low)
RI3 46
RI4 34
DSR1 4
DSR2 63
I5 Data Set Ready (Active Low)
DSR3 45
DSR4 33
DCD1 2
DCD2 62
I5 Data Carrier Detect (Active Low)
DCD3 44
DCD4 32
CTS1 1
CTS2 61 Clear to send (Active Low)
I5
CTS3 43
CTS4 31
Note 1: Serial Port 1 and 2 are only valid when CHIP_MODE = 001, 011, 101 and 110.
Note 2: Serial Port 3 and 4 are only valid when CHIP_MODE = 011.

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 AX99100
PCIe to Multi I/O Controller
1.4.3 Serial Interface for Multi-Protocol Transceiver
Table 1-6: Serial Interface for Multi-Protocol Transceiver Pin Description
Serial interface for Multi-Protocol Transceiver
Pin Name Type Pin No Pin Description
TXD1 9
TXD2 68
O5/4m Transmit data output to transceiver or IrDA data output to IR LED
TXD3 50
TXD4 42
Driver Enable
DXEN1 8 These pins have internal pull-down during reset. If there is the external pull-up
DXEN2 67 resisters connected to these pins separately, it will work for RS-232 function with
B5/PD/4m
DXEN3 49 active low. Otherwise, it will work for RS-485 function with active high and the
DXEN4 41 output can be enabled by register (the default is disabled). Please reference to
Section3.2.
RTS1 7
RTS2 66
O5/4m Request to send (Active Low)
RTS3 48
RTS4 40
RXD1 5
RXD2 65 Serial received data input from transceiver or IrDA data input from IrDA
O5/PU/4m
RXD3 47 detector.
RXD4 38
485EN1 3
Interface Selection
485EN2 64
O5/4m 1: RS-485 selected
485EN3 46
0: RS-232 selected
485EN4 34
485TE1 4
485TE2 63
O5/4m RS485 Termination Enable for transceiver.
485TE3 45
485TE4 33
Receiver Enable
RXEN1 2
1: Enable Receiver
RXEN2 62
O5/4m 0: Disable Receiver
RXEN3 44
RXEN4 32
Note: Software should enable RS-485 function for the corresponding ports first.
CTS1 1
CTS2 61
I5 Clear to send (Active Low)
CTS3 43
CTS4 31
Note 1: Serial Port 1 and 2 are only valid when CHIP_MODE = 010, 100 and 111.
Note 2: Serial Port 3 and 4 are only valid when CHIP_MODE = 101 and 111.

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 AX99100
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1.4.4 Serial Port with GPIO enabled

Table 1-7: Serial Interface for GPIO Enabled Pin Description
Enable Serial Port for GPIO mode
Pin Name Type Pin No Pin Description
TXD1 9
TXD2 68
O5/4m Transmit data output to transceiver or IrDA data output to IR LED
TXD3 50
TXD4 42
SP1_GPIO0 8
SP2_GPIO0 67
B5/CU/4m Serial Port GPIO
SP3_GPIO0 49
SP4_GPIO0 41
SP1_GPIO1 7
SP2_GPIO1 66
B5/CU/4m Serial Port GPIO
SP3_GPIO1 48
SP4_GPIO1 40
RXD1 5
RXD2 65
O5/PU/4m Serial receives data input from transceiver or IrDA data input from IrDA detector.
RXD3 47
RXD4 38
SP1_GPIO5 3
SP2_GPIO5 64
B5/CU/4m Serial Port GPIO
SP3_GPIO5 46
SP4_GPIO5 34
SP1_GPIO3 4
SP2_GPIO3 63
B5/CU/4m Serial Port GPIO
SP3_GPIO3 45
SP4_GPIO3 33
SP1_GPIO4 2
SP2_GPIO4 62
B5/CU/4m Serial Port GPIO
SP3_GPIO4 44
SP4_GPIO4 32
SP1_GPIO2 1
SP2_GPIO2 61
B5/CU/4m Serial Port GPIO
SP3_GPIO2 43
SP4_GPIO2 31
Note: Above Serial Port GPIO function are valid when Software enabled the GPIO function by register setting in each
function.

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 AX99100
PCIe to Multi I/O Controller

1.4.5 Serial Port with Function Disabled

Table 1-8: Serial Interface with Port2 and Port4 Disabled Pin Description
Serial Interface with Port2 and Port4 Disabled
Pin Name Type Pin No Pin Description

TXD2 68
O5/4m No any function for this pin due to disable.
TXD4 42

SP1_GPIO0 67
B5/CU/4m Serial Port GPIO(Note 2)
SP3_GPIO0 41

SP1_GPIO1 66
B5/CU/4m Serial Port GPIO
SP3_GPIO1 40

RXD2 65
O5/PU/4m No any function for this pin due to disable.
RXD4 38

SP1_GPIO5 64
B5/CU/4m Serial Port GPIO
SP3_GPIO5 34

SP1_GPIO3 63
B5/CU/4m Serial Port GPIO
SP3_GPIO3 33

SP1_GPIO4 62
B5/CU/4m Serial Port GPIO
SP3_GPIO4 32

SP1_GPIO2 61
B5/CU/4m Serial Port GPIO
SP3_GPIO2 31
Note 1: If Port 2 or Port 4 are disabled by setting HWCFGEE when CHIP_MODE setting for those serial port
interface, all pins for Port 2 or Port 4 (excluded TXD and RXD) will be re-directed to the GPIO function of
Port 1 and Port 3. Thus, the pins of Port 1 and Port 3 cannot be set for GPIO function by software register
setting.
Note 2: Pin 67 and 41 will be re-directed to DTR1/DXEN1 and DTR3/DXEN3 also. However, software can enable it
to GPIO function as SP1_GPIO0 and SP3_GPIO0.

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 AX99100
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1.4.6 Parallel Port
Table 1-9: Parallel Port Pin Description
Parallel Port Interface
Pin Name Type Pin No Pin Description
SPP:
Set active low by the host to transfer data into the input latch of the peripheral.
O5/T/4m
Data are valid while STROBEn is low.
STROBEn 42
The pin is open-drain when operation in SPP mode, otherwise, is direct drive
Others:
logic 0 or logic 1.
O5/4m
SPP:
The interpretation of this signal varies from peripheral to peripheral. Set low by
O5/T/4m
host to put some printers into auto-line feed mode
AUTOLFn 41
The pin is open-drain when operation in SPP mode, otherwise, is direct drive
Others:
logic 0 or logic 1.
O5/4m
SPP:
Pulsed low by the host in conjunction with IEEE 1284 Active low to reset the
O5/T/4m
interface and force a return to Compatibility Mode idle phase
INITn 40
The pin is open-drain when operation in SPP mode, otherwise, is direct drive
Others:
logic 0 or logic 1.
O5/4m
SPP:
O5/T/4m Set low by host to select peripheral
SELECTINn 38 The pin is open-drain when operation in SPP mode, otherwise, is direct drive
Others: logic 0 or logic 1.
O5/4m
PP_DIR O5/4m 52 Parallel Port Data Transfer Direction Indications
ACKn I5 34 Pulsed low by the peripheral to acknowledge transfer of a data byte from the host
BUSY I5 33 Driven high by the peripheral to indicate that it is not ready to receive data
Driven high by the peripheral to indicate that is has encountered an error in its
PAPEREND I5 32 paper path. The meaning of this signal varies from peripheral to peripheral.
Peripherals shall set FAULTn low whenever PAPEREND is set high
SELECT I5 31 Set high to indicate that the peripheral is online
Set low by the peripheral to indicate that an error has occurred. The meaning of
FAULTn I5 51
this signal varies from peripheral to peripheral
43, 44,
45, 46, Driven by the host in Compatibility Mode and the negotiation phase, not used in
DATA[7:0] B5/4m
47, 48, Nibble Mode, and bidirectional in all other modes
49, 50
Note: Above signals are only valid when CHIP_MODE = 010 and 001.

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 AX99100
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1.4.7 SPI Interface
Table 1-10: SPI Pin Description
SPI Interface
Pin Name Type Pin No Pin Description
SPI Slave Select for SPI master.
SS[2:0] O5/4m 41, 40, 34
SS[2:0] is a tri-stateable output, which requires an external pull-up resistor.
SPI CLocK for SPI master.
SCLK O5/4m 31 SCLK is a tri-stateable output. At Mode 0 or 2, SCLK requires external pull-down
resistor; while at Mode 1 or 3, SCLK requires external pull-up resistor.
SPI Master Output Slave Input line for SPI master.
MOSI O5/4m 32 When High Speed SPI controller is operating in master module, MOSI is used to
transmit serial data and is a tri-stateable output.
SPI Master Input Slave Output line for SPI master.
MISO I5 33 When High Speed SPI controller is operating in master module, MISO is used to
receive serial data.
SPI External Wakeup
SWAKEn I5/PU 38
SWAKEn is external wakeup for SPI interface.
GPIO16 B5/8m 42 General Purpose I/O signal
Note: Above signals are only valid when CHIP_MODE = 100 and 110.

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 AX99100
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1.4.8 Local Bus Interface
Table 1-11: Local Bus Pin Description
Local Bus Interface
Pin Name Type Pin No Pin Description
A0/ CHIP_MODE[2] O5/4m 58 Local Bus Address Bus, A[2:0]
These pins are input direction during chip reset use to bootstrap the mode setting
A1/ CHIP_MODE[1] O5/4m 56 to decide the operation mode. Please reference to Section 3.1.
In Local Bus mode, These pins should always use external pull-down resistors to
A2/ CHIP_MODE[0] O5/4m 54
ground.
Local Bus Address Bus, A[3]
A3 O5/4m 53 This pin should be connected to the 3.3V AUX in PCIe slot via an external
pull-up resistor. It is used to detect the 3.3V AUX is existed or not.
60, 59, Local Bus Address Bus, A[9:4]
A[9:4] O5/4m 47, 48, The A[9:0] are outputs and provide up to 10 Local Bus address lines in
49, 50 non-multiplexed address and data bus format
61, 62,
63, 64,
65, 66, Data and Address bus
67, 68,
AD[15:0] B5/4m Multiplexed mode: address on bus when ALE issued, other time data on bus
1, 2,
4, 3, Non-multiplexed mode: data always on bus
5, 7,
8, 9
Local Bus Reset Output
The output polarity can be decided by adding external pull up/down resistor. If
RSTO B5/4m 52
connected this pin to VCCIO via external pull-up resistor, means RSTO is active
high. If pull-down to ground, means active low.
CLKO B5/8m 51 Local Bus Clock Output
CS1n 41 Local Bus Chip Select 1
O5/4m
CS0n 42 Local Bus Chip Select 0
DREQ[1:0] I5 44, 46 DMA Request
DACK[1:0] O5/4m 43, 45 DMA Acknowledge
INT[1:0] I5 31, 32 Interrupt
Address Latch Enable
When in non-multiplexed mode, ALE can choice remap to A[10] (detail
ALE O5/4m 40
description same as above A[9:0]) or address latch enable for ISA bus type
When in multiplexed mode, ALE for address latch enable
RDn O5/4m 38 Local Bus Read Cycle
WRn O5/4m 34 Local Bus Write Cycle
RDY I5 33 Local Bus Device Ready
Note: Above signals are only valid when CHIP_MODE = 000.

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 AX99100
PCIe to Multi I/O Controller
2 Function Description
Clocks/Resets and Power
The AX99100 requires an external clock from PCIe connector (CLKP and CLKN) as the main clock source. PCIe
PHY feeds this 100 MHz differential clock to internal PLL to generate the 125MHz clock for PCIe PHY and
Controller or other peripherals used. The AX99100 also supports a clock input from external oscillator for those
special baud rate generated for UART, SPI and Local Bus used if needs. Thus there are three different clock sources
(100Mhz, 125Mhz and EXT_CLK) in this chip can be selected for some interfaces to generate the desired baud rate to
meet the application requirement.

There are two reset sources in the AX99100. During the VCCK power-on, the internal Power-On-Reset (POR) can
generate a reset pulse to reset all the function blocks when the VCCK power pin rise to certain threshold voltage level.
Another reset is RSTn pin, which is from PCIe slot to perform the PCIe Fundamental Reset. If AX99100 is not in L2
power sate, this reset pin will logical and with POR reset to reset all the function blocks also. AX99100 is designed to
meet the PCIe standard for Power Management State.

The AX99100 contains an internal 3.3V to 1.2V low-dropout-voltage regulator. The internal regulator provides up to
150mA of driving current for the 1.2V core and analog power of this chip to satisfy the worst-case power
consumption scenario.

In order to support PCIe power management, all VCCIO power and the regulator power supply should connect to
PCIe Auxiliary Power (3.3Vaux) to maintain the deep sleep and wakeup event.

PCIe Operation
PCIe is divided into three major blocks as Physical layer, Data link layer and Transaction layer. Physical link layer
and Transaction layer together comprises PCIe core. Their functionality is explained below.

PCIe PHY
The Physical Layer isolates the Transaction and Data Link Layers from the signaling technology used for Link data
interchange. The Physical Layer is divided into the logical and electrical functional sub-blocks.

The logical sub-block has two main sections: A transmit section that prepares outgoing information passed from the
Data Link Layer for transmission by the electrical sub-block, and a receiver section that identifies and prepares
received information before passing it to the Data Link Layer. The logical sub-block and electrical sub-block
coordinate the state of each transceiver through a status and control register interface or functional equivalent. The
logical sub-block directs control and management functions of the Physical Layer.

The electrical sub-block contains a Transmitter and a Receiver. The Transmitter is supplied by the logical sub-block
with Symbols which it serializes and transmits onto a Lane. The Receiver is supplied with serialized Symbols from
the Lane. It transforms the electrical signals into a bit stream which is de-serialized and supplied to the logical
sub-block along with a Link clock recovered from the incoming serial stream.

The Physical Layer is responsible for the following

• Power management
• Width and lane negotiation
• Reset/hot-plug control
• 8-bit/10-bit encoding/decoding
• Scrambling/de-scrambling
• Embedded clock tuning and alignment
• Transmission and reception circuit
• Elastic buffer
• Data Link Layer

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 AX99100
PCIe to Multi I/O Controller
The Data Link Layer
The Data Link Layer acts as an intermediate stage between the Transaction Layer and the Physical Layer. The Data
Link Layer is responsible for reliably conveying Transaction Layer Packets (TLPs) supplied by the Transaction
Layer across a PCI Express Link to the other component’s Transaction Layer

The Data Link Layer is responsible for the following

• Link management including TLP acknowledgment
• Retry mechanism in case of a non-acknowledged packet
• Flow control across the Link (transmission and reception)
• Power management
• CRC generation and CRC checking
• Error reporting

Transaction Layer/User Interface Layer

Transaction layer and User interface layer together perform all transaction layer functionalities. User interface layer
defines a plug-and-play type interface mechanism to accept TLPs from user space for transmission, and to pass
received TLPs on reception.

The Transaction Layer is primarily responsible for the following

• Assembly and disassembly of Transaction Layer packets (TLPs)
• Storage of configuration information
• Converts received Completion packets into data payloads,
• Updates status information
• Responsible for flow control services
• Ordering rules
• Power management services
• PCIe Bridge
• Master Slave Bridge is divided into PCIe packet formatter, PCIe target interface block, Mater arbiter, Slave
de-mux and VCI interface block.

All detail description for PCIe operation, please reference to the standard of “PCI Express Base Specification”.

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 AX99100
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I2C Controller
The I2C Controller of AX99100 contains of an I2C master to support communication to external I2C devices and an
I2C Hardware Configuration EEPROM Loader to support loading chip configuration data from external I2C
EEPROM during chip reset.

Serial Port (SP)

The AX99100 supports up to 4 Serial Ports, namely, Serial Port 1/2/3/4. Each serial port is compatible with standard
16C450, 16C550 and Extend 16C550, 16C650, 16C750 and 16C950 device architectures and the default operating
mode is set to 16C450. Each serial port provides serial communication capabilities to communicate with Modem or
other external device (e.g. computer) using RS-232, RS-422 or RS-485 protocols and support slow IrDA mode (up to
115200bps). It supports customized transfer baud rate (up to 25Mbps) by programming internal divider register or
external clock, provides 256-byte Transmitter and Receiver FIFO for data buffering, supports DMA mode burst
transfer for data receive and transmit process, and supports Auto-hardware flow control (Auto-RTS and Auto-CTS)
and Auto-software flow control (Auto-send and Auto-detect XON and XOFF characters) to reduce CPU/software
loading.

Each serial port supports 5, 6, 7, 8 bit Serial format. In addition, it also supports 9 bit serial format to accomplish
multi-drop function. Each serial port supports Even, Odd, None, Space and Mark parity. Furthermore, it also supports
remote wakeup, power management and transceiver shutdown features.

Parallel Port (PP)

The Parallel Port of AX99100 is a bidirectional extension of the existing PC parallel interface. The interface supports
a number of distinct communication modes, and the interpretation of interface signals depends on the current mode.
The different modes are Compatibility, Nibble, Byte and ECP modes. Not all devices support all communication
modes. A mechanism is provided for the host and peripheral to negotiate the mode to be used for data transfers and to
renegotiate as needed. The host may return the link to the Compatibility Mode whenever the interface is in a valid
state, which is uniquely specified for each mode.

Compatibility Mode: This is an asynchronous data transfer mode, byte-wide forward (host-to-peripheral) channel
with data and status lines. This Mode provides host-to-peripheral communication in a manner compatible with the
traditional unidirectional interface.

Nibble Mode: This is an asynchronous data transfer mode, reverse (peripheral-to-host) channel, under control of the
host.

Byte Mode: This is an asynchronous, byte-wide reverse (peripheral-to-host) channel using the eight data lines of the
interface for data and the control/status lines for handshaking.

Extended Capabilities Port (ECP) Mode: This is an asynchronous byte-wide mode, bidirectional channel.

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 AX99100
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SPI Master Controller (SPI)

The AX99100 contain the High Speed Serial Peripheral Interface (SPI) Master Controller provides a full-duplex,
synchronous serial communication interface (4 wires) to flexibly work with numerous SPI peripheral devices. The
High Speed SPI Controller consists of a High Speed SPI master controller with 3 slave select pins, SS[2:0], to connect
up to 7 SPI devices.

This High Speed SPI master controller supports 4 types of interface timing mode, namely, Mode 0, Mode 1, Mode 2,
and Mode 3 to allow working with most SPI devices available. It supports MSB/LSB first data transfer. The SCLK
SPI clock is programmable by software and can run up to 42MHz. The AX99100 also provides many programmable
registers can be used to adjust the bus timing to fit the variety Slave timing requirements. Please reference the section
4.5.4.

The AX99100 SPI master supports four kinds of access types below.
Non-Burst-Type Transfer: Supports up to 8 bytes registers can be read and written by Software with none DMA
access.

Burst-Type Transfer: Supports TX/RX DMA transfer. Upon configured by software and one DMA length up to
64K bytes, SPI RX DMA supports moving data from SPI bus through SPI RX FIFO into PCIe BUS; SPI TX DMA
supports moving data from PCIe BUS through SPI TX FIFO to SPI bus.

Burst-Type with OP-code Transfer: supports up to 8 bytes pre-programmable OP code automatic insertion in each
Burst-Type Transfer with successive chip select assertion, to reduce CPU/software loading.

Fragmentation: supports to fragment large data block into several smaller transfers on SPI bus with programmable
length for each small transfer fragment, to reduce CPU/software loading.

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 AX99100
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Local Bus Controller (LB)
The AX99100’s Local Bus mode provides a PCIe bus target (slave) for adapter boards, in others words, AX99100 can
connect a wide variety local bus design to PCIe bus.

The local bus mode provides four PCIe BARs for access, BAR0 and BAR1 direct mapping to local bus’s chip select
(CS0n and CS1n), configurable with Memory or I/O access with Hardware Configuration EEPROM setting. Software
can use PCIe memory or I/O command through BAR0/1 to access device with local bus directly or active bus master
function (DMA) to transfer large data between PCIe and device. The bus master’s access can be programmed for port
mapping (fixed address) or memory mapping (auto-increment address) also. Another two BARs are BAR4 (I/O
access) and BAR5 (memory access) serve software and driver handle whole PCIe and local bus function. These two
BARs are mapped to same registers to provide local bus access timing adjustment, control pins setting (polarity,
remapping etc.), interrupt control and status response, DMA engine (bus master controller) handling, and I2C
controller assessment.

The local bus can be configured to asynchronous or synchronous mode, 8 or 16 bits data bus width, data bus
alignment with MSB or LSB when bus width 8 bits and endian type with big or little mode. The address/data of local
bus can be set to Multiplexed or Separated bus type, address/data setup timing, address/data hold timing, address latch
enable timing, read cycle timing and write cycle timing, control pin polarity, and output enable. Above all parameters
can be loaded from EEPROM, and most timing parameters and bus configuration could be adjusted by BAR4/5
related registers too. The BAR0/1 space size could up to 64K Bytes when local bus use address/data multiplex bus
type. If use the separated bus type, the largest size of BAR0/1 are only to 2K Bytes (remapping ALE to A[10]) or 1K
Bytes with ISA bus type (ALE presented access).

The Local Bus of AX99100 also supports clock output (CLKO), which can be configured to generate up to 62.5MHz
with internal 125 MHz clock source or 60MHz with external clock source from EXT_CLK, and reset output (RSTO),
which can be controlled by Software Driver to reset the related off-chip components.

The Local Bus supports address shift feature with local bus shift base register, used for those devices with small BAR
space match to local bus with non-zero starting address (like ISA bus device), the chip select also supports starting
address shifting and range resizing feature too.

To enhance the performance, local bus supports “Slave Request based DMA” mode. After software configured
external device and DMA engine was ready, bus master transfer data between PCIe bus and local bus’s device
followed device request to reduce the efforts for the Software checking device status timing.

The Local Bus of AX99100 supports the remote wakeup in L2 power state for PCIe. Application can use INT0/1 and
DREQ0/1 pins to generate the wakeup event to PCIe bus to exit L2 power state.

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 AX99100
PCIe to Multi I/O Controller
GPIO Function
There are up to 24 General Purpose Input/output pins (GPIO[23:0]) in AX99100, reference section 1.4.1, Table 1-4,
in none Local Bus mode. The driving strength of GPIO[7:0] are 8mA and GPIO[23:8] are 4mA only. Each GPIO pin
is independent and can be configured for input or output, open drain or direct drive, internal pull-up enabled and event
mode detection for IRQ generation. Due to GPIO[5:2] have been used for CHIP_MODE and 3.3Vaux detection,
these pins can be used as the directed drive output pin without internal pull-up feature.

Power Management
The AX99100 supports the following power management and budgeting features.

• Compliant with PCI Power Management Interface Specification 1.2

• Supports Native Active State Power Management L0s state
• Supports Power Management Event (PME message)
• Supports CLK_REQ mechanism for Express card interface
• Supports wakeup from D3 hot and D3 cold states

AX99100 supports all the device power management states defined in PCI Bus Power Management Interface
Specification 1.2. Power Management capabilities are mentioned in Power Management Capability (PMC) register
of configuration space which provides information on the capabilities of the function related to power management.
Bit[15] of PMC, i.e. wake from D3 cold is supported only if auxiliary power is present, this bit is updated through
bootstrap option on pin “GPIO2” or “A3” (weak pull-up with supply 3.3V AUX is connected to pin “GPIO2” or
“A3”) and logic AND with the contents in Bit[2] of EEPROM offset 0Fh(Func0), 23h(Func1), 37h(Func2) and
4Bh(Func3) corresponds to Bit[15] of PMC, please reference section 3.3.1, Power Management Capabilities_Fx, in
detail.

AX99100 Supports wakeup from any power management capable device connected to AX99100 from both D3 hot
and D3 cold states.

D3 hot: Any device connected to AX99100 can wakeup the system from D3-hot state (Standby) through WAKEn
(referred as WAKE# in PCIe base specification 1.1) or through PME message. Default wakeup is through WAKEn.
EEPROM should be configured in order to wake the PC through PME message from D3 hot state.

D3 cold: Any devices connected to AX99100 can wakeup the system from D3-cold state (Hibernate) through
WAKEn only (referred as WAKE# in PCIe base Specification 1.1).

Note: There is NO power plane separation between 3.3V AUX and VCCIO in AX99100. In D3 Cold, the chip
VCCIO and VCC33A_REG should be powered from 3.3V AUX to support remote wake up.

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 AX99100
PCIe to Multi I/O Controller
3 Chip Configuration
Boot Strapping Pins for Chip Mode
The AX99100 is able to configure to 8 different chip modes by pull up or pull down the Pin 54, 56 and 58. These pins
will be pulled up internally during reset. Therefore, user just needs to use external resistor to pull down these pins for
the chip mode setting to ‘0’. But it is still accepted if user would like to use the external resistor to pull up these pins
for the mode setting to ‘1’.

Pins Signal Name Description

54 CHIP_MODE[0] Chip Mode Select bit 0
0: Added external pull-down resistor to this pin.
1: Otherwise.
56 CHIP_MODE[1] Chip Mode Select bit 1
0: Added external pull-down resistor to this pin.
1: Otherwise.
58 CHIP_MODE[2] Chip Mode Select bit 2
0: Added external pull-down resistor to this pin.
1: Otherwise.
Table 3-1: Chip Mode Selection Pins

There are 8 chip modes (4MP, 2S1SPI, 2S2MP, 2MP1SPI, 4S, 2MP1P, 2S1P and LB) can be selected by different
pull-down for CHIP_MODE. It is the detail descriptions for the each chip mode abbreviations below.

4MP Means to support four Serial Ports with Multi-Protocol transceivers in PCIe function 0~3.
2S1SPI Means to support two general Serial Ports in function 0~1 and one SPI master in PCIe function 3.
2S2MP Means to support two general Serial Ports in function 0~1 and two Serial Ports with Multi-Protocol
transceivers in PCIe function 2~3.
2MP1SPI Means to support two Serial Ports with Multi-Protocol transceivers in function 0~1and one SPI
master in PCIe function 3.
4S Means to support four general Serial Ports in PCIe function 0~3.
2MP1P Means to support two Serial Ports with Multi-Protocol transceivers in function 0~1and one Parallel
Port in PCIe function 2.
2S1P Means to support two general Serial Ports in function 0~1 and one Parallel Port in PCIe function 2.
LB Means to support one Local Bus interface in PCIe function 0.

Following table specified abbreviation of all chip modes with CHP_MODE[2:0] decode and port mapping. “GPIO”
is for GPIO[15:8], it occupies the 8 pins in Port 3 and controlled by BAR5 in each function same as GPIO[7:0] pins.
“Parallel Port” occupies the pins of Port 3 and 4 and controlled by function 2 in PCIe. “SPI” occupies the pins of Port
4 and controlled by function 3 in PCIe. “LB” is for Local Bus interface, it occupies all pins from Port 1 to Port 4 but
only controlled by function 0 in PCIe. In “Serial Port” and “Multi-protocol”, Port 1 will be controlled by function 0,
Port 2 controlled by function 1, Port 3 controlled by function 2 and Port 4 controlled by function 3 in PCIe.

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 AX99100
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Table 3-2: Chip Mode Selection Table

CHIP_ 4MP 2S1SPI 2S2MP 2MP1SPI 4S 2MP1P 2S1P LB

Mode[2:0] 111 110 101 100 011 010 001 000

Port 1 Multi- Serial Serial Multi- Serial Multi- Serial

Protocol Port Port Protocol Port Protocol Port
Port 2 Multi- Serial Serial Multi- Serial Multi- Serial
Protocol Port Port Protocol Port Protocol Port Local
Port 3 Multi- Multi- Serial Bus
GPIO GPIO
Protocol Protocol Port Parallel Parallel
Port 4 Multi- Multi- Serial Port Port
SPI SPI
Protocol Protocol Port
Note: The AX99100 Multi-protocol Mode is designed to support the Multi-protocol transceiver. Please contact ASIX
product support for the detail.

DTR Boot Strapping Pins for Serial Port

Each Serial Port or Serial Port with multi-protocol transceivers mode can support for RS-232 or RS-485 function, the
DTR/DXEN pin will has different behavior for the both mode. In Hardware design, each DTR/DXEN pin has internal
pull-down during reset. User may use the external pull-up resister to decide which mode is selected for operation.

Pins Signal Name Description

8 DTR_MODE[0] DTR Mode Select bit 0 for Serial Port 1
1: Added external pull-up resistor to this pin. It works for RS-232
mode with active low.
0: Otherwise, means to use internal pull-down to this pin. It works
for RS-485 mode with active high.
67 DTR_MODE[1] DTR Mode Select bit 1 for Serial Port 2
1: Added external pull-up resistor to this pin. It works for RS-232
mode with active low.
0: Otherwise, means to use internal pull-down to this pin. It works
for RS-485 mode with active high.
49 DTR_MODE[2] DTR Mode Select bit 2 for Serial Port 3
1: Added external pull-up resistor to this pin. It works for RS-232
mode with active low.
0: Otherwise, means to use internal pull-down to this pin. It works
for RS-485 mode with active high.
41 DTR_MODE[3] DTR Mode Select bit 3 for Serial Port 4
1: Added external pull-up resistor to this pin. It works for RS-232
mode with active low.
0: Otherwise, means to use internal pull-down to this pin. It works
for RS-485 mode with active high.

Table 3-3: DTR Mode selection Pins

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 AX99100
PCIe to Multi I/O Controller
Hardware Configuration EEPROM
AX99100 can use the I2C Hardware Configuration EEPROM (HWCFGEE) to overwrite some hardware default
values during boot up if the Configuration EEPROM existed and the checksum is correct. If EEPROM not existed or
checksum uncorrected, Hardware will skip to load the content or give up the loaded values from EEPROM then still
use the hardware default values in each chip mode for the chip operation. It uses a serial EEPROM with I2C interface
with at least 256x8 (1024 bits), for example Atmel AT24C02. The 7-bit device address of the I2C Hardware
Configuration EEPROM on application circuit must be set to 1010000b. Note that the Hardware will only use the
“8-bit Device Memory Address Format” to load HWCFGEE when boot up.

Following sections show the I2C Hardware Configuration EEPROM memory maps with the different layouts between
none Local Bus and Local Bus in EEPROM.

Following are the abbreviations for each interface function for further descriptions.

SP For those PCIe functions which be configured to support general Serial Ports or Serial Ports with
Multi-Protocol transceivers in Port 1, 2, 3 or 4.
SPI For the PCIe function 3 which be configured to support SPI master in Port 4.
PP For the PCIe function 2 which be configured to support Parallel Port in Port 3 and 4.
LB For the PCIe function 0 which be configured to support Local Bus interface.

Note1: Some “Reserved” fields in HWCFGEE may preserve for design optimization. User should use ASIX
provided EEPROM utility to modify or create the new EEPROM contents to avoid the incorrected value to
cause system unstable.

Note2: Boot strapping pins and HWCFGEE will be reloaded in following conditions.
◆ Power OFF (includes 3.3VAUX) then Power ON.
◆ Perform PCIe reset in none L2 state.

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3.3.1 Configuration EEPROM Memory Map for None Local Bus Interface
Table 3-4: Configuration EEPROM Memory Map for none Local Bus mode
EEPROM
Parameter Note
Offset
0x00 Divide Clock Selection SPI interface
0x01 Clock Divider used
0x03~0x02 Vendor ID_F0
0x05~0x04 Device ID_F0
0x06 Revision ID
0x07 Programming IF_F0
0x08 Sub-Class Code_F0
Function0
0x09 Base Class Code_F0
0x0B~0x0A Subsystem Vendor ID_F0
0x0D~0x0C Subsystem Device ID_F0
0x0F~0x0E Power Management Capabilities_F0
0x16~0x10 Reserved
0x18~0x17 Vendor ID_F1
0x1A~0x19 Device ID_F1
0x1B Programming IF_F1
0x1C Sub-Class Code_F1
0x1D Base Class Code_F1 Function1
0x1F~0x1E Subsystem Vendor ID_F1
0x21~0x20 Subsystem Device ID_F1
0x23~0x22 Power Management Capabilities _F1
0x2A~0x24 Reserved
0x2C~0x2B Vendor ID_F2
0x2E~0x2D Device ID_F2
0x2F Programming IF_F2
0x30 Sub-Class Code_F2
0x31 Base Class Code_F2 Function2
0x33~0x32 Subsystem Vendor ID_F2
0x35~0x34 Subsystem Device ID_F2
0x37~0x36 Power Management Capabilities_F2
0x3E~0x38 Reserved
0x40~0x3F Vendor ID_F3
0x42~0x41 Device ID_F3
0x43 Programmable IF_F3
0x44 Sub-Class Code_F3
0x45 Base Class Code_F3 Function3
0x47~0x46 Subsystem Vendor ID_F3
0x49~0x48 Subsystem Device ID_F3
0x4B~0x4A Power Management Capabilities_F3
0x52~0x4C Reserved
0x54~0x53 INT Mask
0x55 Port Disable Register
0x56 Global Setting
For each function
0x5A~0x57 Reserved
0x5B Check-Sum
0x7F ~ 0x5C Reserved
Note: Function 2 should be disabled in SPI mode and Function 3 should be disabled in PP mode.

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Divide Clock Selection (0x00)
Bit Description
1:0 Clock source select for LB or SPI used.
00: 125MHz from internal PLL.
01: 100MHz from PCIe reference clock.
1x: EXT_CLK.

Hardware Default Value:

01: In LB and SPI mode.
00: Others.
2 Divide Enable.
0: Disabled clock divider to LB and SPI module.
1: Enabled clock divider to generate desired clock frequency for LB or SPI module.

Hardware Default Value:

1: In LB and SPI mode.
0: Others.
7:3 Reserved
Note: “ Hardware Default Value” means HWCFGEE load failed for without Hardware Configuration EEPROM
or checksum failed.

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Divide Register (0x01)
Bit Description
7:0 Clock Divider N Register.
The number of N in this field is used to generate the desired clock frequency and the frequency will
follow following equation:

Desired clock frequency = (125MHz or 100MHz or EXT_CLK) / N

Note:
◎ N equal to 0x00 or 0x01 is divided by 1, N = ‘2’ is divided by 2, and so on.
◎ This value N should >= 2 when the clock source from 125MHz and 100MHz for SPI.

Hardware Default Value:

0x02: In LB and SPI mode.
0x00: Others.

Vendor ID_Fx (0x03~0x02, 0x18~0x17, 0x2C~0x2B, 0x40~0x3F)

Bit Description
15:0 Vendor ID_Fx.
This field will be loaded into PCIe Configuration Space offset 0x00 (Vendor ID).

Hardware Default Value: 0x125B.

Note 1: Vendor ID_F3 = 0xFFFF In PP mode, Vendor ID_F2 = 0xFFFF In SPI mode.
Note 2: Only “Vendor ID_F0” existed in LB mode.
Note: “ x” is from 0~3 means PCIe function 0~3.

Device ID_Fx (0x05~0x04, 0x1A~0x19, 0x2E~0x2D, 0x42~0x41)

Bit Description
15:0 Device ID_Fx.
This field will be loaded into PCIe Configuration Space offset 0x02 (Device ID).

Hardware Default Value: 0x9100

Note 1: Device ID_F3 = 0xFFFF In PP mode, Device ID_F2 = 0xFFFF In SPI mode.
Note 2: Only “Device ID_F0”=(0x9110) existed in LB mode.

Revision ID (0x06)
Bit Description
7:0 Revision ID.
This field will be loaded into PCIe Configuration Space offset 0x08 (Revision ID).

Hardware Default Value: 0x00

Programming IF_Fx (0x07, 0x1B, 0x2F, 0x43)

Bit Description
7:0 Programming Interface_Fx.
This field will be loaded into PCIe Configuration Space offset 0x09 (Programming Interface).

Hardware Default Value:

0x02: For all SP mode.
0x03: For “Programming Interface_F3” in PP mode.
0x00: Others (includes “Programming Interface_F0” in PP or LB mode and “Programming
Interface_F2” in SPI mode).
Note: Only “Programming Interface_F0” existed in LB mode.

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Sub-Class Code_Fx (0x08, 0x1C, 0x30, 0x44)
Bit Description
7:0 Sub-Class Code_Fx.
This field will be loaded into PCIe Configuration Space offset 0x0A (Sub-Class).

Hardware Default Value:

0x80: For “Sub-Class Code_F0” in LB mode.
0x01: For “Sub-Class Code_F2” in PP mode.
0x00: Others (includes “Sub-Class Code_F3” in SPI mode and all SP mode).
Note: Only “Sub-Class Code_F0” existed in LB mode.

Base Class Code_Fx (0x09, 0x1D, 0x31, 0x45)

Bit Description
7:0 Base Class Code_Fx.
This field will be loaded into PCIe Configuration Space offset 0x0B (Base Class).

Hardware Default Value:

0x07: For all SP mode and “Base Class Code_F2” in PP mode.
0x06: For “Base Class Code_F0” in LB mode
0xFF: For “Base Class Code_F3” in SPI mode
0x00: Others
Note: Only “Base Class Code_F0” existed in LB mode.

Subsystem Vendor ID_Fx (0x0B~0x0A, 0x1F~0x1E, 0x33~0x32, 0x47~0x46)

Bit Description
15:0 Subsystem Vendor ID_Fx.
This field will be loaded into PCIe Configuration Space offset 0x2C (Subsystem Vendor ID).

Hardware Default Value: 0xA000

Note: Only “Subsystem Vendor ID_F0” existed in LB mode and if the function has been disabled
this file should be set to 0x0000.

Subsystem Device ID_Fx (0x0D~0x0C, 0x21~0x20, 0x35~0x34, 0x49~0x48)

Bit Description
15:0 Subsystem Device ID_Fx.
This field will be loaded into PCIe Configuration Space offset 0x2E (Subsystem Device ID).

Note:
◎For SP related PCIe function, bit15~12 should be set to 0x1.
◎For PP related PCIe function, bit15~12 of “Subsystem Device ID_F2” should be set to 0x2.
◎For SPI related PCIe function, bit15~12 of “Subsystem Device ID_F3” should be set to 0x6.

Hardware Default Value:

0x1000: For all SP function.
0x2000: For “Subsystem Device ID_F2” in PP mode.
0x6000: For “Subsystem Device ID_F3” in SPI mode.
0x7000: For “Subsystem Device ID_F0” in LB mode.
Note: Only “Subsystem Device ID_F0” existed in LB mode and if the function has been disabled this
file should be set to 0x0000.

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Power Management Capabilities_Fx (0x0F~0x0E, 0x23~0x22, 0x37~0x36, 0x4B~0x4A)
Bit Description
0 No Soft Reset.
This field will be loaded into PCIe Configuration Space offset 0x7C (Power Management
Status/Control Register), bit 3.

Hardware Default Value:0x1.

3:1 Maximum Current Required.
This field will be loaded into PCIe Configuration Space offset 0x78 (Power Management
Capabilities Register), bit 24:22.

Hardware Default Value:0x7 (375 mA).

4 D1 Support.
This field will be loaded into PCIe Configuration Space offset 0x78 (Power Management
Capabilities Register), bit 25.

Hardware Default Value:0x1.

5 D2 Support.
This field will be loaded into PCIe Configuration Space offset 0x78 (Power Management
Capabilities Register), bit 26.

Hardware Default Value:0x1.

10:6 PME Support.
This field will be loaded into PCIe Configuration Space offset 0x78 (Power Management
Capabilities Register), bit 31:27. {D3 cold, D3 hot PME, D2 PME, D1 PME, D0 PME}.

Note: Bit10, D3 cold, will be “and” logic operation with the 3.3V AUX detect (GPIO2/A3 pull-up
Aux3.3V).

Hardware Default Value:0x1F.

Note 1: Only “ Power Management Capabilities_F0” existed in LB mode.
Note 2: This field should be set to 0x0000 if this function is disabled.

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INT Mask (0x54~0x53)
Bit Description
3:0 Setting INT A bit mapping (0x1) for Function 0.

Hardware Default value: 0x1.

7:4 Setting INT B bit mapping (0x2) for Function 1.

Hardware Default value:

0x0: for LB mode.
0x2: Others.
11:8 Setting INT C bit mapping (0x4) for Function 2.

Hardware Default value:

0x0: For LB and SPI mode.
0x4: Others.
15:12 Setting INT D bit mapping (0x8) for Function 3.

Hardware Default value:

0x0: For LB and PP mode.
0x8: Others.

Port Disable Register (0x55)

Bit Description
0 XCVR Polarity Selection.
1: XCVR is active Low when AX99100 enter L2(D3) power saving mode
0: XCVR is active High when AX99100 enter L2(D3) power saving mode
Note: This bit is valid when set Bit1 to ‘1’.

Hardware Default value: 0x0

1 XCVR Function Enable
Enable the output of GPIO6 as “XCVR” function to shutdown external Serial Port transceiver in L2
power state.
1: Enable XCVR function output to GPIO6
0: Disable XCVR output to GPIO6, the GPIO6 is a generic GPIO function

Hardware Default value:

0: In LB mode
1: Others
2 Serial Port 1 System Clock Disable
1: Disabled Serial Port 1 system clock
0: Enabled Serial Port 1 system clock

Hardware Default value:

1: In LB mode
0: Others
3 Serial Port 2 System Clock Disable
1: Disabled Serial Port 2 system clock
0: Enabled Serial Port 2 system clock

Hardware Default value:

1: In LB mode
0: Others
4 Serial Port 3 System Clock Disable
1: Disabled Serial Port 3 system clock
0: Enabled Serial Port 3 system clock

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Hardware Default value:
1: In LB, PP or SPI mode
0: Others
5 Serial Port 4 System Clock Disable
1: Disabled Serial Port 4 system clock
0: Enable Serial Port 4 system clock

Hardware Default value:

1: in LB, PP or SPI mode
0: Others
6 SPI System Clock Disable
1: Disabled SPI system clock
0: Enabled SPI system clock

Hardware Default value:

0: In SPI mode.
1: Others
7 Reserved

Global Setting (0x56)

Bit Description
3:0 PCIe Function Enable
Indicates the function existed or not in PCIe system. Bit0 is for Function 1, Bit1 is for Function 2 and
Bit2 is for function 3. Note Bit3 should be set to ‘0’ and the Function 0 is always enabled in
AX99100.
1: Enabled the corresponding PCIe Function.
0: Disabled the corresponding PCIe Function.

Hardware Default value:

0x0: For LB mode (CHIP_MODE= 000)
0x3: For PP related mode (CHIP_MODE=001 and 010)
0x5: For SPI related mode (CHIP_MODE=100 and 110)
0x7: Others
4 ECRC forwarding to and from the Application Layer implemented.
This field should always set to 0b
7:5 Reserved

Check-Sum (0x5B)
Bit Description
Check-Sum Value
Hardware Check-Sum verification is the sum of the all bytes from offset 0x00 to 0x5B with an 8bit adder
and the carry need to be added back to bit0. The final value should equal to the Hardware pre-define, 0x79.
So the Check-Sum value should be used to adjust the final value to 0x79 to pass the Check-Sum
verification. If the check-sum verification failed, Hardware will not load the EEPROM contents and use
7:0
the Hardware default value to replace it. Please reference section 3.3.3 in detail.

For example, if the summation is 0x7A from offset 0x00 to 0x5A. Due to 0x7A is large than 0x79, the
Check-Sum Value should be 0xFE (0x79-0x7A-0x01). If the summation is 0x79, Check-Sum Value will
be 0x00 (0x79-0x79).

Reserved (0x5C-0x7F)
EEPROM address 0x5C~0x7F are Reserved.

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3.3.2 Configuration EEPROM Memory Map for Local Bus Interface

Table 3-5: Configuration EEPROM Memory Map for Local Bus

EEPROM Offset Parameter
0x00 Divide Clock Selection
0x01 Clock Divider
0x03~0x02 Vendor ID_F0
0x05~0x04 Device ID_F0
0x06 Revision ID
0x07 Programming IF_F0
0x08 Sub-Class Code_F0
0x09 Base Class Code_F0
0x0B~0x0A Subsystem Vendor ID_F0
0x0D~0x0C Subsystem Device ID_F0
0x0F~0x0E Power Management Capabilities_F0
0x17~0x10 Reserved
0x19~0x18 Local Bus Interrupt Enable/Miscellaneous Setting
0x1B~0x1A PCIe BAR0 Range
0x1D~0x1C PCIe BAR1 Range
0x1F~0x1E Reserved
0x21~0x20 Local Address Space 0 Setting
0x25~0x22 Local Address Space 0 Timing Setting
0x29~0x26 Local Address Space 0 Address Setting
0x2B~0x2A Local Address Space 1 Setting
0x2F~0x2C Local Address Space 1 Timing Setting
0x33~0x30 Local Address Space 1 Address Setting
0x52~0x34 Reserved
0x54~0x53 INT Mask
0x55 Port Disable Register
0x56 Global Setting
0x5A~0x57 Reserved
0x5B Check-Sum
0x7F ~ 0x5C Reserved

Offset 0x00~0x16:
Please reference section 3.3.1.

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Local Bus Interrupt Enable/Miscellaneous Setting (0x19~0x18)
Bit Description
0 INT0 Wakeup Enable
1: Enable INT0 wakeup
0: Disable INT0 wakeup

Hardware Default Value: 0x0

1 INT1 Wakeup Enable
1: Enable INT1 wakeup
0: Disable INT1 wakeup

Hardware Default Value: 0x0

2 RDY Timeout Enable
1: Enables RDY timeout.
0: Disable RDY timeout.

Hardware Default Value: 0x0

3 RDY Timeout Select
1: 128 CLKOs
0: 32 CLKOs

Hardware Default Value: 0x0

4 Ready Polarity
1: Active high
0: Active low

Hardware Default Value: 0x1

5 ALE Polarity
1: Active High
0: Active Low

Hardware Default Value: 0x1

6 Synchronous Bus
1: Synchronous Bus
0: Asynchronous Bus

Hardware Default Value: 0x0

7 Multiplexed Bus
1: Address and Data multiplexed
0: Address and Data bus separated

Hardware Default Value: 0x0

8 CLKO Driven Strength
1: 8mA
0: 4mA

Hardware Default Value: 0x1

9 CLKO Output Enable
1: Enable clock output
0: Disable clock output

Hardware Default Value: 0x1

10 ALE Remap to A[10]
1: Re-assigned ALE pin to A[10], only valid when set bit7 to ‘0’
0: ALE pin is for ALE function

Hardware Default Value: 0x0

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11 Reserved
12 CLKO Output Invert
1: Bus cycle active with rising edge
0: Bus cycle active with falling edge

Hardware Default Value: 0x0

13 Reserved
14 DREQ0 Wakeup Enable
1: Enable DREQ0 wakeup
0: Disable DREQ0 wakeup

Hardware Default Value: 0x0

15 DREQ1 Wakeup Enable
1: Enable DREQ1 wakeup
0: Disable DREQ1 wakeup

Hardware Default Value: 0x0

PCIe BAR0 Range (0x1B~0x1A)

Bit Description
0 IO SPACE
1: Indicates Local Address Space 0 maps into I/O space.
0: Indicates Local Address Space 0 maps into Memory space.

Hardware Default Value: 0x0

2:1 Space Decode
When mapped into Memory space, the only valid value is 00. (32-bit access space with
non-prefetchable)
When mapped into I/O space, bit 1 should be ‘0’ and bit 2 will be loaded to BADDR0[2] to indicate the
decoding range.

Hardware Default Value: 0x0

3 Prefetchable
When mapped into Memory space, ‘1’ indicates reads are prefetchable.
When mapped into I/O space, this bit will be loaded to BADDR0[3] to indicate the decoding range.

Hardware Default Value: 0x0

15:4 BADDR0[15:4]
Specifies which Address bits to be used for decoding the PCIe access to Local Address Space 0. Each
bit corresponds to Address bit. ‘1’ is for PCI address decoding and ‘0’ means the occupied range for the
BAR0 access. The address bit 31 to 16 of BAR0 is always ‘1’.

Hardware Default Value: 0x000 (64KByte)

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PCIe BAR1 Range (0x1D~0x1C)
Bit Description
0 IO SPACE
1: Indicates Local Address Space 1 maps into I/O space.
0: Indicates Local Address Space 1 maps into Memory space.

Hardware Default Value: 0x0

2:1 Space Decode
When mapped into Memory space, the only valid value is 00. (32-bit access space with
non-prefetchable)
When mapped into I/O space, bit 1 should be ‘0’ and bit 2 will be loaded to BADDR1[2] to indicate the
decoding range.

Hardware Default Value: 0x0

3 Prefetchable
When mapped into Memory space, ‘1’ indicates reads are prefetchable.
When mapped into I/O space, this bit will be loaded to BADDR1[3] to indicate the decoding range.

Hardware Default Value: 0x0

15:4 BADDR1[15:4]
Specifies which Address bits to be used for decoding the PCIe access to Local Address Space 1. Each
bit corresponds to Address bit. ‘1’ is for PCI address decoding and ‘0’ means the occupied range for the
BAR1 access. The address bit 31 to 16 of BAR1 is always ‘1’.

Hardware Default Value: 0x000 (64KByte)

Local Address Space 0 Setting (0x21~0x20)

Bit Description
0 INT0 Polarity
1: Active High
0: Active Low

Hardware Default Value: 0x0

1 INT0 Trigger Style
1: Level Trigger
0: Edge Trigger

Hardware Default Value: 0x0

2 DREQ0 Polarity
1: Active High
0: Active Low

Hardware Default Value: 0x0

3 DACK0 Polarity
1: Active High
0: Active Low

Hardware Default Value: 0x1

4 Local Address Space 0 External Ready Control
1: External RDY control usage for Local Address Space 0 bus access
0: Internal counter used for Local Address Space 0 bus access

Hardware Default Value: 0x0

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5 Bus Endian and Alignment for Local Address Space 0
When data bus width is 16-bit,
1: Big endian
0: Little endian

When data bus width is 8-bit,

1: Data place to/from DA[15:8]
0: Data place to/from DA[7:0]

Hardware Default Value: 0x0

6 Data Bus Width for Local Address Space 0
1: Bus width 16-bit width
0: Bus width 8-bit width

Hardware Default Value: 0x1

7 ALE Insertion Enable for Local Address Space 0
1: Enable ALE insertion
0: Disable ALE insertion

Note: This bit should be set to ‘1’ when bit7 of “Local Bus Interrupt Enable/Miscellaneous Setting”,
offset 0x19~0x18, is ‘1’.

Hardware Default Value: 0x0

8 Chip Select (CS0n) Enable for Local address Space 0
1: Enable Local Address Space 0 Chip Select
0: Disable Local Address Space 0 Chip Select

Hardware Default Value: 0x1

9 Local address Space 0 Enable
1: Enable the address mapping from PCIe BAR0 access to Local Address Space 0.
0: Disable the address mapping.

Hardware Default Value: 0x1

11:10 Reserved
Hardware Default Value: 0x3
12 Burst Read Enable ford Local Address Space 0
1: Enable burst read access
0: Disable burst read access

Hardware Default Value: 0x1

14:13 Reserved
Hardware Default Value: 0x0
15 BAR0 Enable
1: Enable BAR0 access
0: Disable BAR0 access even offset 0x1B~0x1A, Local Bus PCIe BAR0 Range, are valid.

Hardware Default Value: 0x1

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Local Address Space 0 Timing Setting (0x25~0x22)
Bit Description
3:0 ALE Pulse Width (ALE_PW)
ALE pulse width cycle = (ALE_PW +1) * clock period

Hardware Default Value: 0x0

5:4 Data and Address Setup Time (DA_SET)
Address stable or ALE de-assert before RD_N or WR_N assert
Address setup time = DA_SET * clock period

Hardware Default Value: 0x0

7:6 Data and Address Hold Time (DA_HD)
Address and data de-assert after RD_N or WR_N de-assert
Address hold time = DA_HD * clock period

Hardware Default Value: 0x0

11:8 Read Access Time (RD_ACC)
For single access or burst read first cycle
Read access time = (RD_ACC + 1) * clock period

Hardware Default Value: 0x1

15:12 Burst Read Access Time (BRD_ACC)
For burst read second and late cycle
Burst read access time = (BRD_ACC + 1) * clock period

Note: BRD_ACC should large than 0x0.

Hardware Default Value: 0x1
19:16 Write Access Time (WR_ACC)
Write access time = (WR_ACC + 1) * clock period

Hardware Default Value: 0x0

23:20 Access GAP Time (AGAP)
Access back to back time = (AGAP + 1) * clock period

Hardware Default Value: 0x0

27:24 CS0n Space Range
Local Address Space 0 Range for CS0n
CS0n Space Range = 2(LCS0RAN + 1)

Hardware Default Value: 0xF

31:28 Reserved

Local Address Space 0 Address Setting (0x29~0x26)

Bit Description
15:0 Local Address Space 0 address shift Base

Hardware Default Value: 0x0000

31:16 CS0n space Starting Address
Starting Address Shift of CS0n for Local Address Space 0

Hardware Default Value: 0x0000

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Local Address Space 1 Setting (0x2B~0x2A)

Bit Description
0 INT1 Polarity
1: Active High
0: Active Low

Hardware Default Value: 0x0

1 INT1 Trigger Style
1: Level Trigger
0: Edge Trigger

Hardware Default Value: 0x0

2 DREQ1 Polarity
1: Active High
0: Active Low

Hardware Default Value: 0x0

3 DACK1 Polarity
1: Active High
0: Active Low

Hardware Default Value: 0x1

4 Local address Space 1 External Ready control
1: External RDY control usage for Local Address Space 1 bus access
0: Internal counter used for Local Address Space 1 bus access

Hardware Default Value: 0x0

5 Bus Endian and Alignment for Local Address Space 1
When data bus width is 16-bit,
1: Big endian
0: Little endian

When data bus width is 8-bit,

1: Data place to/from DA[15:8]
0: Data place to/from DA[7:0]

Hardware Default Value: 0x0

6 Data Bus Width for Local Address Space 1
1: Bus width 16-bit width
0: Bus width 8-bit width

Hardware Default Value: 0x1

7 ALE Insertion Enable for Local Address Space 1
1: Enable ALE insertion
0: Disable ALE insertion

Note: This bit should be set to ‘1’ when bit7 of “Local Bus Interrupt Enable/Miscellaneous Setting”,
offset 0x19~0x18, is ‘1’.

Hardware Default Value: 0x0

8 Chip Select (CS1n) Enable for Local address Space 1
1: Enable Local Address Space 1 Chip Select
0: Disable Local Address Space 1 Chip Select

Hardware Default Value: 0x1

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9 Local address Space 1 Enable
1: Enable the address mapping from PCIe BAR1 access to Local Address Space 1.
0: Disable the address mapping.

Hardware Default Value: 0x1

11:10 Reserved
Hardware Default Value: 0x3
12 Burst Read Enable for Local Address Space 1
1: Enable burst read access
0: Disable burst read access

Hardware Default Value: 0x1

14:13 Reserved
Hardware Default Value: 0x0
15 BAR1 Enable
1: Enable BAR1 access
0: Disable BAR1 access even offset 0x1D~0x1C, Local Bus PCIe BAR1 Range, are valid.

Hardware Default Value: 0x1

Local Address Space 1 Timing Setting (0x2F~0x2C)

Bit Description
3:0 ALE Pulse Width (ALE_PW)
ALE pulse width cycle = (ALE_PW +1) * clock period

Hardware Default Value: 0x0

5:4 Data and Address Setup Time (DA_SET)
Address stable or ALE de-assert before RD_N or WR_N assert
Address setup time = DA_SET * clock period

Hardware Default Value: 0x0

7:6 Data and Address Hold Time (DA_HD)
Address and data de-assert after RD_N or WR_N de-assert
Address hold time = DA_HD * clock period

Hardware Default Value: 0x0

11:8 Read Access Time (RD_ACC)
For single access or burst read first cycle
Read access time = (RD_ACC + 1) * clock period

Hardware Default Value: 0x1

15:12 Burst Read Access Time (BRD_ACC)
For burst read second and late cycle
Burst read access time = (BRD_ACC + 1) * clock period

Note: BRD_ACC should large than 0x0.

Hardware Default Value: 0x1
19:16 Write Access Time (WR_ACC)
Write access time = (WR_ACC + 1) * clock period

Hardware Default Value: 0x0

23:20 Access GAP Time (AGAP)
Access back to back time = (AGAP + 1) * clock period

Hardware Default Value: 0x0

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27:24 CS1n space Range
Local Address Space 1 Range for CS1n
CS1n Space Range = 2(LCS1RAN + 1)

Hardware Default Value: 0xF

31:28 Reserved

Local Address Space 1 Address Setting (0x33~0x30)

Bit Description
15:0 Local Address Space 1 address shift Base

Hardware Default Value: 0x0000

31:16 CS1n space Starting Address
Starting Address Shift of CS1n for Local Address Space 0

Hardware Default Value: 0x0000

Offset 0x53~0x7F:
Please reference section 3.3.1.

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3.3.3 Hardware Default Values Summary
This section summarizes all hardware default values in section 3.3.1 and 3.3.2.

Table 3-6: Hardware Default Values in each CHIP_MODE Setting

CHIP_MODE
4S(011),
2S1P(001), 2S1SPI(110),
EEPROM offset LB(000) 4MP(111),
2MP1P(010) 2MP1SPI(100)
2S2MP(101)
0x00 05 00 00 05
0x01 02 00 00 02
0x02 5B 5B 5B 5B
0x03 12 12 12 12
0x04 10 00 00 00
0x05 91 91 91 91
0x06 00 00 00 00
0x07 00 02 02 02
0x08 80 00 00 00
0x09 06 07 07 07
0x0A 00 00 00 00
0x0B A0 A0 A0 A0
0x0C 00 00 00 00
0x0D 70 10 10 10
0x0E FF FF FF FF
0x0F 07 07 07 07
0x10 01 01 01 01
0x11 00 00 00 00
0x12 02 02 02 02
0x13 83 83 83 83
0x14 FD FD FD FD
0x15 41 31 31 31
0x16 01 01 01 01
0x17 00 5B 5B 5B
0x18 30 12 12 12
0x19 03 00 00 00
0x1A 00 91 91 91
0x1B 00 02 02 02
0x1C 00 00 00 00
0x1D 00 07 07 07
0x1E 00 00 00 00
0x1F 00 A0 A0 A0
0x20 48 00 00 00
0x21 9F 10 10 10
0x22 00 FF FF FF
0x23 11 07 07 07
0x24 00 11 11 11
0x25 0F 00 00 00
0x26 00 02 02 02
0x27 00 83 83 83
0x28 00 FD FD FD
0x29 00 31 31 31

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CHIP_MODE
4S(011),
2S1P(001), 2S1SPI(110),
EEPROM offset LB(000) 4MP(111),
2MP1P(010) 2MP1SPI(100)
2S2MP(101)
0x2A 48 02 02 02
0x2B 9F 5B 5B FF
0x2C 00 12 12 FF
0x2D 11 00 00 FF
0x2E 00 91 91 FF
0x2F 0F 03 02 00
0x30 00 01 00 00
0x31 00 07 07 00
0x32 00 00 00 00
0x33 00 A0 A0 00
0x34 00 00 00 00
0x35 00 20 10 00
0x36 00 FF FF 00
0x37 00 07 07 00
0x38 00 11 11 00
0x39 00 00 00 00
0x3A 00 02 02 00
0x3B 00 83 83 00
0x3C 00 FD FD 00
0x3D 00 31 31 00
0x3E 00 03 03 00
0x3F 00 FF 5B 5B
0x40 00 FF 12 12
0x41 00 FF 00 00
0x42 00 FF 91 91
0x43 00 00 02 00
0x44 00 00 00 00
0x45 00 00 07 FF
0x46 00 00 00 00
0x47 00 00 A0 A0
0x48 00 00 00 00
0x49 00 00 10 60
0x4A 00 00 FF FF
0x4B 00 00 07 07
0x4C 00 00 11 11
0x4D 00 00 00 00
0x4E 00 00 02 02
0x4F 00 00 83 83
0x50 00 00 FD FD
0x51 00 00 31 31
0x52 00 00 04 04
0x53 01 21 21 21
0x54 00 04 84 80
0x55 7C 72 42 32
0x56 00 03 07 05
0x57 00 E4 E4 E4
0x58 00 00 00 00

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CHIP_MODE
4S(011),
2S1P(001), 2S1SPI(110),
EEPROM offset LB(000) 4MP(111),
2MP1P(010) 2MP1SPI(100)
2S2MP(101)
0x59 00 00 00 00
0x5A 00 00 00 00
0x5B - - - -

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3.3.4 Disable Unused PCIe Function in HWCFGEE
The AX99100 supports to disable the unused PCIe function via HWCFGEE. For example, if user would like to use
one Serial Port and hope AX99100 just occupy only one PCIe function (1S) in system. User can set CHIP_MODE =
011b to select 4S mode and use the proper setting in HWCFGEE to disable PCIe function 1~3. Following
descriptions will introduce how to fill the HWCFGEE content to disable PCIe function.

※ Set the field of “Vendor ID” and “Device ID” to 0xFFFF in the corresponding PCIe function which would like to
be disabled.
※ Set others fields to 0x00 in the corresponding PCIe function which would like to be disabled.
※ Set ‘1’ to disable the corresponding function in offset 0x55, bit 2~6.
※ Set ‘0x0’ to bit15:4 for those unused Functions in offset 0x54~0x33.
※ Set ‘0’ to bit3:0 to disable those unused Functions in offset 0x56.
Notice:
◎ The PCIe function 0 can’t be disabled.
◎ If PCIe function 1 or 3 disabled, the Serial Port GPIO of function 0 or 2 will be redirected to the IO of Serial Port
2 and 4 in Serial Port related CHIP_MODE setting. Please reference section 1.4.5.
◎ If PCIe function 3 disabled, the IO of Port 4 will be redirected to GPIO in SPI related CHIP_MODE setting.

Following table show an example for configuring AX99100 to 1S mode in CHIP_MODE = 011 (4S). The PCIe
function 1~3 will be disabled via HWCFGEE.

Table 3-7: The HWCHGEE content for 1S setting

EEPROM offset CHIP_MODE = 011 (4S) PCIe Function No.
0x00 00
0x01 00
0x02 5B
0x03 12
0x04 00
0x05 91
0x06 00
0x07 02
0x08 00
0x09 07
0x0A 00
0x0B A0
0x0C 00 Function 0
0x0D 10
0x0E FF
0x0F 07
0x10 01
0x11 00
0x12 02
0x13 83
0x14 FD
0x15 31
0x16 01
0x17 FF
0x18 FF Function 1
0x19 FF

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EEPROM offset CHIP_MODE = 011 (4S) PCIe Function No.
0x1A FF
0x1B 00
0x1C 00
0x1D 00
0x1E 00
0x1F 00
0x20 00
0x21 00
0x22 00
0x23 00
0x24 00
0x25 00
0x26 00
0x27 00
0x28 00
0x29 00
0x2A 00
0x2B FF
0x2C FF
0x2D FF
0x2E FF
0x2F 00
0x30 00
0x31 00
0x32 00
0x33 00
0x34 00
Function 2
0x35 00
0x36 00
0x37 00
0x38 00
0x39 00
0x3A 00
0x3B 00
0x3C 00
0x3D 00
0x3E 00
0x3F FF
0x40 FF
0x41 FF
0x42 FF
0x43 00 Function 3
0x44 00
0x45 00
0x46 00
0x47 00

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EEPROM offset CHIP_MODE = 011 (4S) PCIe Function No.
0x48 00
0x49 00
0x4A 00
0x4B 00
0x4C 00
0x4D 00
0x4E 00
0x4F 00
0x50 00
0x51 00
0x52 00
0x53 01
0x54 00
0x55 7A
0x56 00
0x57 E4
0x58 00
0x59 00
0x5A 00
0x5B A2

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PCIe Configuration Space Map
Following tables show the BAR usages in different interfaces. The detail function description, please reference in
PCIe base specification Revision 1.1. About the interrupt mapping in chip default, the function 0~3 will be mapped
to INTA~D.

PCI Configuration Space Map for SP (Function 0~3)

Offset Register Name
31 24 23 16 15 8 7 0
0x00 Device ID Vendor ID
0x04 Status Command
0x08 Class Code Revision ID
0x0C
0x10 Base Address Registers 0
0x14 Base Address Registers 1
0x18
0x1C
0x20
0x24 Base Address Registers 5
0x28
0x2C Subsystem ID Subsystem Vendor ID
0x30
0x34
0x38
0x3C Interrupt Pin Interrupt Line

PCI Configuration Space Map for PP (Function 2)

Offset Register Name
31 24 23 16 15 8 7 0
0x00 Device ID Vendor ID
0x04 Status Command
0x08 Class Code Revision ID
0x0C
0x10 Base Address Registers 0
0x14 Base Address Registers 1
0x18 Base Address Registers 2
0x1C
0x20
0x24 Base Address Registers 5
0x28
0x2C Subsystem ID Subsystem Vendor ID
0x30
0x34
0x38
0x3C Interrupt Pin (0x03) Interrupt Line

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PCI Configuration Space Map for SPI (Function 3)

Offset Register Name
31 24 23 16 15 8 7 0
0x00 Device ID Vendor ID
0x04 Status Command
0x08 Class Code Revision ID
0x0C
0x10 Base Address Registers 0
0x14 Base Address Registers 1
0x18
0x1C
0x20
0x24 Base Address Registers 5
0x28
0x2C Subsystem ID Subsystem Vendor ID
0x30
0x34
0x38
0x3C Interrupt Pin (0x04) Interrupt Line

PCI Configuration Space Map for LB (Function 0)

Offset Register Name
31 24 23 16 15 8 7 0
0x00 Device ID Vendor ID
0x04 Status Command
0x08 Class Code Revision ID
0x0C
0x10 Base Address Registers 0
0x14 Base Address Registers 1
0x18
0x1C
0x20 Base Address Registers 4
0x24 Base Address Registers 5
0x28
0x2C Subsystem ID Subsystem Vendor ID
0x30
0x34
0x38
0x3C Interrupt Pin (0x01) Interrupt Line
(0x00)

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4 Electrical Specifications
DC Characteristics
4.1.1 Absolute Maximum Ratings
Symbol Parameter Rating Units
VCCK Digital core power supply. - 0.5 to 1.6 V
VCCIO, VCC33A_REG Power supply of 3.3V I/O and Regulator. - 0.5 to 4.6 V
VCC12A_TX, VCC12A_AUX, Analog power supply for PCIe PHY. - 0.5 to 1.6 V
VCC12A_D
VIN Input voltage of 3.3V I/O with 5V tolerant. - 0.5 to 5.8 V
TSTG Storage temperature. - 65 to 150 ℃
I IN DC input current. 50 mA
I OUT Output short circuit current. 50 mA
Note:
Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be
restricted in the recommended operating condition section of this datasheet. Exposure to absolute maximum rating
condition for extended periods may affect device reliability.

ESD/Latch-Up Tests
Symbol Test Condition Value Units
HBM ANSI/ESDA/JEDEC JS-001-2011 ±2000 V
MM JEDEC EIA/JESD22 A115-C ±200 V
CDM JEDEC JESD22 C101-E ±500 V
I-test JESD78C, Class I ±100 mA
Vsupply JESD78C, Class I 1.5 x VCCIO V
Over-voltage Test

4.1.2 Recommended Operating Condition

Symbol Parameter Min Typ Max Units
VCCIO Power supply of 3.3V I/O. 2.97 3.3 3.63 V
VCCK Digital core power supply. 1.08 1.2 1.32 V
VCC33A_REG Analog power supply for Regulator. 2.0 3.3 3.6 V
VCC12A_TX, VCC12A_AUX, Analog power supply for PCIe PHY. V
1.14 1.2 1.26
VCC12A_D
Tj AX99100 QF operating junction temperature. 0 125 ℃
25
AX99100 QI operating junction temperature. -40 125
Ta AX99100 QF operating ambient temperature. 0 70 ℃
-
AX99100 QI operating ambient temperature. -40 85

4.1.3 Leakage Current and Capacitance

Symbol Parameter Conditions Min Typ Max Units
IIN Input leakage current. No pull-up 3.3V with 5V tolerant I/O pins. - < ±1 - μA
or pull-down. Vin = 5 or 0V.
CIN Input capacitance. 3.3V with 5V tolerant I/O pins. - 2.3 - pF

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4.1.4 DC Characteristics of 3.3V with 5V Tolerant I/O Pins
Symbol Parameter Conditions Min Typ Max Units
VCCIO Power supply of 3.3V I/O. 3.3V I/O 2.97 3.3 3.63 V
Vil Input low voltage. - - 0.8 V
Vih Input high voltage. LVTTL 2.0 - - V
Vt- Schmitt trigger negative going threshold LVTTL 0.8 1.1 - V
voltage.
Vt+ Schmitt trigger positive going threshold - 1.6 2.0 V
voltage
Vol Output low voltage. Iol = 2 ~ 4mA - - 0.4 V
Voh Output high voltage. Ioh = -2 ~ -4mA 2.4 - - V
Vopu (1) Output pull-up voltage for 5V tolerant IO With internal VCCIO - - V
pull-up resistor – 0.9
Rpu Input pull-up resistance. 40 75 190 KΩ
Rpd Input pull-down resistance. 40 75 190 KΩ
Input leakage current. Vin = 5 or 0V - ±1 - μA
Iin Input leakage current with pull-up resistance. Vin = 0 V - -45 - μA
Input leakage current with pull-down Vin = VCCIO - 45 - μA
resistance.
Note: This parameter indicates that the pull-up resistor for the 5V tolerant I/O pins cannot reach VCCIO DC level
even without DC loading current.

4.1.5 DC Characteristics of Voltage Regulator

Symbol Description Condition Min Typ Max Unit
VCC33A_REG Power supply of on-chip 2.0 3.3 3.6 V
voltage regulator.
VO12 Output voltage of on-chip VCC33A_REG = 3.3V 1.14 1.2 1.26 V
voltage regulator.
Tj Operating junction -40 25 125 ℃
temperature.
Iload Driving current. VCC33A_REG = 3.3V - - 150 mA
△VO12 Line regulation. Iload = 10mA - 0.5 1.0 %/V
(△VCC33A_REG x
VO12)
△VO12 Load regulation. VCC33A_REG = 3.3V, - 0.05 0.1 %/mA
(△Iload x VO12) 1mA ≦ Iload ≦ 150mA
△VO12 Temperature coefficient. VCC33A_REG = 3.3V, - 0.1 0.3 mV/℃
△Tj -40℃ ≦ Tj ≦ 125℃
IQ Quiescent current VCC33A_REG = 3.3V, - 110 310 μA
consumption Iload = 0 mA
Cout Output external capacitor. 3.3 - - μF
ESR Allowable effective series 0.5 - - Ω
resistance of external
capacitor.

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PCIe Specifications
Symbol Parameter Conditions Min Typ Max Units
UI Unit Interval Each UI is 400 ps +/-300 ppm. UI 399.88 400 400.12 ps
does not account for SSC dictated
variations
Input Levels
VRX-DIFF-PP Differential RX peak-peak 2*|VRX(DIP)-VRX(DIN)|, measured 175 - 1200 mV
voltage at the connection of the near-end
receiver
VIDLE Electrical idle detect threshold Peak voltage 65 - 175 mV
VRX-CM-AC RX AC common-mode voltage Peak voltage - - 150 mV
TRX-EYE Minimum Receiver Eye Width 0.4 - - UI
RLRX-DIFF Differential Return Loss Measured over 50 MHz to 1.25 10 - - dB
GHz.
RLRX-cm Common Mode Return Loss Measured over 50 MHz to 1.25 6 - - dB
GHz.
Output Levels
VTX-DIFF-PP Differential TX peak-peak 2*|VTX(DOP)-VTX(DON)|, measured 800 - 1200 mV
voltage swing at the connection of the near-end
transmitter
TTX-EYE Transmitter eye, including all SSC or Refclk jitter is not included 0.75 - - UI
jitter sources
VTX-IDLE-AC Electrical idle differential peak - - 20 mV
output voltage
VT-D-R Amount of voltage change The total amount of voltage - - 600 mV
allowed during the receiver change during TX-Detect-RX
detection
VTX-CM-AC TX AC common-mode voltage Measured as the AC RMS value - - 20 mV
VTX-DEM-ratio TX de-emphasis level Non-transient bits are driven out -3.0 - -4.0 dB
with degrading amplitude
FBEACON A signal of wakeup mechanism Signal frequency 2.0 - 15 MHz
Resistance
RRX Built-in receiver input 40 50 60 Ω
impedance
RTX Built-in driver output impedance 40 50 60 Ω

Capacitance
CTX AC coupling capacitor 75 - 200 nF

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Power Consumption

Interface Configuration Loading Condition VCCIO VCCK VCC12A_TX VCC12A_D VCC12A_AUX Unit
Idle 2.5 36.7 12 19.2 17.1 mA
L0
Full load 4 Serial Ports with 25Mhz Baud Rate 5.5 53.3 12 19.2 17.1 mA
L1 0 30.8 2.8 16.2 12.5 mA
4S
L2 1.2 0.1 3.6 0.7 8.3 mA
Idle 3.1 35.6 13.2 17.7 14.8 mA
ASPM L0s
Full load 4 Serial Ports with 25Mhz Baud Rate 4.6 51.8 13.2 17.7 16.4 mA
Idle 5.9 35.9 12.6 18.8 14.6 mA
L0 Full load Synchronous 16-bit Multiplexed Bus 24.7 38.1 12.6 18.8 14.6 mA
with 62.5MHz Local Bus clock
LB L1 5.5 34.4 10.7 17.0 12.2 mA
L2 1.0 0.0 3.79 0.5 8.6 mA
Idle 4.9 30.0 13.4 16.9 15.7 mA
ASPM L0s
Full load 24.0 36.7 13.4 16.9 15.7 mA
Note: The measurement is for the operation at Typical Condition and used ASIX 4S and Local Bus test board.

Symbol Description Condition Min Typ Max Unit

ΘJC Thermal resistance of junction to case - 11.9 - °C/W
ΘJA Thermal resistance of junction to ambient Still air - 28.3 - °C/W
JT Junction to Top of the Package Characterization Parameter - 0.30 - °C/W

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Power–up/down and Power Management Sequence

The AX99100 related power up/down and power management sequences are designed to meet the PCI Express
Card Electromechanical Specification Revision 2.0. Please reference the section 2.2.1 for power up sequence,
section 2.2.2 for power management sequence and section 2.2.3 for power down sequence for the detail in this
standard.

Note: There is NO power plane separation between 3.3V AUX and VCCIO in AX99100. In D3 Cold, the chip
VCCIO and VCC33A_REG should be powered from 3.3V AUX to support remote wake up.

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AC Timing Characteristics
4.5.1 PCIe Reference Clock Timing
The reference clock (CLKP and CLKN) of AX99100 is designed for the PCI Express Card Electromechanical
Specification Revision 2.0. Please reference the section 2.1.3 in this standard for the detail.

4.5.2 I2C Timing

Tbuf
SDA

Tlow
Tsu_dat Thd_sta
Thd_sta Thigh Thd_dat Tsu_sta Tsu_sto
SCL

Symbol Parameter Min Typ Max Units

SCL clock frequency - - 100, KHz
2 SCL will use 100KHz during the configuration 400
Fclk
EEPORM loading and can be changed to support
400KHz operating.
Thigh High period of the SCL clock - SCL_HP+5 - Tsys_clk1
Tlow Low period of the SCL clock - SCL_LP+2 - Tsys_clk
Hold time of (repeated) START condition. After - SHSC+1 - Tsys_clk
Thd_sta
this period, the first clock pulse is generated
Tsu_sta Setup time for a repeated START condition - SHSC+1 - Tsys_clk
Tsu_dat Data Setup time - (SCL_LP/2)+1 - Tsys_clk
Thd_dat Data hold time - (SCL_LP/2)+1 - Tsys_clk
Tsu_sto Setup time for STOP condition - SCL_HP+5 - Tsys_clk
Bus free time between a STOP and START - (SCL_HP/2)+BFT+2 - Tsys_clk
Tbuf
condition
Note 1: Tsys_clk = 16ns for 62.5 MHz operating system clock.
Note 2: Fclk = 1/Tclk, where Tclk = ((SCL_HP + SCL_LP) * Tsys_clk). The SCL_HP and SCL_LP are I2C SCL
Period Register.

Table 4-1: I2C Master Controller Timing Table

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4.5.3 Serial Port Timing
The Serial Port data transmit and receive is via TXD[4:1] and RXD[4:1] pins. The complete data transmit/receive
includes 1 start bit, 5~8 data bit, 1 parity bit (if supported parity check) and 1~2 stop bit.

Figure 4-1: TXD1 and RXD1 Timing Diagram

Symbol Parameter Min Typ Max Units

t0 is start bit time; - 1/Baud Rate S
t0~t9 t1 ~ t8 is data bit time;
t9 is parity bit time;
stop bit time : - - S
1 bit 1/Baud Rate
t10
1.5 bit 1.5*(1/Baud Rate)
2 bit 2*(1/Baud Rate)
Note: RXD[4:1] baud rate tolerance ±3%.

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4.5.4 SPI Timing

1
SCLK(output)

5
MOSI(output)

6 7
MISO(input)

9
8 2 3 4
SS0(output)

Symbol Description Min Typ Max Units

SCLK clock frequency - Fsys_clk - MHz
1
SPIBRR
Setup time of SS[2:0] to the first SCLK - Mode0, 1: (1.0 + DBS) * Tsclk. - ns
2
edge Mode2, 3: (0.5 + DBS) * Tsclk.
Hold time of SS[2:0] after the last SCLK - Mode0, 1: (0.5 + DBS) * Tsclk. - ns
3
edge Mode2, 3: (1.0 + DBS) * Tsclk.
Minimum idle time between transfers - (2 + DT) * Tsclk. - ns
4
(minimum SS[2:0] high time)
5 MOSI data valid time, after SCLK edge - - 2 ns
6 MISO data setup time before SCLK edge 7 - - ns
7 MISO data hold time after SCLK edge 0 - - ns
Bus drive time before SS[2:0] assertion - Tsclk -
8, 9
and after SS[2:0] de-assertion
Note: Fsys_clk is from 125MHz, 100MHz or EXT_CLK and the SCLK frequency is same as “Desired clock
frequency”. Please reference section 3.3.1, Divide Register. The SPIBRR is SPI Baud Rate Register and same
as N.

Figure 4-2: High Speed SPI Master Controller Timing Diagram and Table

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4.5.5 Local Bus Timing

4.5.5.1 Synchronous Bus Mode

Tck Tck__h Tck_l

CLKO

Tcs_dly Tagap Tcs_dly

CS0n/CS1n

Ta_dly Ta_set Ta_dly

A[10:0]

Trd_wd Trd_dly
RDn

Twr_wd Ta_hd Twr_dly

WRn

Tdwr_set
Tda_dly Tdwr_hd
AD[15:0]

RDY

DREQ[1:0]

Tdak_dly
DACK[1:0]

Figure 4-3: Non-multiplexed Bus Type with External RDY Timing Diagram

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CLKO

Tcs_dly Tcs_dly Tcs_hd

CS0n/CS1n

Tale_ctrl Tale_dly Tale_ctrl Tale_wd

ALE

Ta_dly Ta_hd
A[9:0] N N+1 M M+1

Trd_wd Trd_dly
RDn

Twr_wd Twr_dly
WRn

Tda_dly Tdwr_hd
AD[15:0] (N) (N+1) (M) (M+1)

RDY

DREQx

Tdak_dly
DACK[1:0]

Figure 4-4: ISA-Like Bus Type with External RDY Timing Diagram

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CLKO

Tcs_dly Tcs_dly Tagap Tcs_hd

CS0n/CS1n

Ta_dly Ta_hd Ta_set

A[10:0] N N+1 M M+1

Trd_dly
Trd_wd Tbrd_wd
RDn

Twr_dly Twr_wd
WRn

Tdwr_set
Tda_dly Tdwr_hd
AD[15:0] (N) (N+1) (M) (M+1)

DREQ[1:0]

Tdak_dly
DACK[1:0]

Figure 4-5: Non-multiplexed Bus Type with Internal Cycle Count Timing Diagram

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CLKO

T agap T c s_dly T c s_hd

CS 0n/CS 1n

T ale_dly T ale_c trl T ale_wd T ale_c trl

A LE

T da_dly T da_dly
T daf
A D[15:0] N (N) N+1 (N+1) M (M) M+1 (M+1)

T rd_wd T rd_dl y
RDn

T dwr_hd
T wr_dl y T wr_wd
W Rn

RDY

DREQ[1:0]

T dak_dly
DA CK [1:0]

Figure 4-6: Multiplexed Bus Type with External RDY Timing Diagram

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CLKO

T agap T c s_dly T c s_hd

CS0n/CS1n

T ale_dly T ale_c trl T ale_wd T ale_c trl

ALE

T da_dly T da_dly
T daf
AD[15:0] N (N) N+1 (N+1) M (M) M+1 (M+1)

T rd_wd T rd_dly
RDn

T dwr_hd
T wr_dly T wr_wd
WRn

DREQ[1:0]

T dak_dly
DACK[1:0]

Figure 4-7: Multiplexed Bus Type with Internal Cycle Count Timing Diagram

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4.5.5.2 Asynchronous Bus Mode

Tagap Tcs_hd
Tcs_set Tcs_set
CS0n/CS1n

A[10:0] N N+1 M M+1

Trd_wd Ta_set
RDn

Ta_set Ta_hd Twr_wd

WRn

Tdwr_set Tdwr_hd
AD[15:0] (N) (N+1) (M) (M+1)

RDY

DREQ[1:0]

DACK[1:0]

Figure 4-8: Non-multiplexed Bus Type with External RDY Timing Diagram

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T agap T c s_hd
CS0n/CS1n

T ale_wd T c s_ale T ale_wd

ALE

T adr_s et T adr_s et
A[9:0] N N+1 M M+1

T rd_wd T ale_c trl

RDn

T ale_c trl
T wr_wd T a_hd
W Rn

T dwr_s et T dwr_hd
AD[15:0] (N) (N+1) (M) (M+1)

RDY

DREQ[1:0]

DACK[1:0]

Figure 4-9: ISA-Like Bus Type with External RDY Timing Diagram

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Tagap
Tcs_set Tcs_set Tcs_hd
CS0n/CS1n

A[10:0] N N+1 M M+1

Ta_set

Trd_wd Tbrd_wd
RDn

Ta_set Ta_hd Twr_wd

WRn

Tdwr_set Tdwr_hd
AD[15:0] (N) (N+1) (M) (M+1)

DREQ[1:0]

DACK[1:0]

Figure 4-10: Non-multiplexed Bus Type with Internal Cycle Count Timing Diagram

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T agap T cs _hd
CS 0n/CS 1n

T al e_wd T cs _al e
A LE

T adr_hd
T adr_s et T adr_hd T adr_s et T dwr_hd
A D[15:0] N (N) N+1 (N+1) M (M) M+1 (M+1)

T al e_c trl
T rd_wd T a_daf
RDn

T wr_wd
T al e_c trl T dwr_s et
W Rn

RDY

DREQ[1:0]

DA CK [1:0]

Figure 4-11: Multiplexed Bus Type with External RDY Timing Diagram

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Tagap Tcs_hd
CS0n/CS1n

Tale_wd Tcs_ale
ALE

Tadr_hd
Tadr_set Tadr_hd Tadr_set Tdwr_hd
AD[15:0] N (N) N+1 (N+1) M (M) M+1 (M+1)

Tale_ctrl
Trd_wd Ta_daf
RDn

Twr_wd
Tale_ctrl Tdwr_set
WRn

DREQ[1:0]

DACK[1:0]

Figure 4-12: Non-multiplexed Bus Type with Internal Cycle Count Timing Diagram

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Symbol Description Min Typ Max Units
Clock
Tck Clock Period 16 - - ns
Tck_h Clock Low Time - Tck/2-1 - ns
Tck_l Clock High Time - Tck/2-1 - ns
Tck_ris Clock Rising Time - 1 - ns
Tck_fall Clock Falling Time - 1 - ns
Bus Timing
Tcs_dly Chip Select Delay 0.2 1 ns
Tcs_set Chip Select Setup Time -0.2 - Tck/2+0.2 ns
Chip Select active to Read/Write active
Tcs_hd Chip Select Hold Time Tck/2-1.3 - Tck*DA_ ns
Write inactive to Chip Select inactive HD
Tale_ctrl ALE to control active Tck/4-0.2 - Tck*DA_S ns
ALE inactive to read or write active ET-0.1
Tale_dly ALE Delay Tck/4+0.3 - Tck/4+1 ns
Tale_wd ALE Width - Tck*(ALE_PW+1) - ns
Trd_dly Read Delay 0.1 - 1 ns
Trd_wd Read Width - Tck*(RD_ACC+1) , - ns
or RDY active,
or RDY timeout
Tbrd_wd Burst Read Width - Tck*(BRD_ACC+1) - ns
Twr_dly Write Delay 0.3 - 1 ns
Twr_wd Write Width - Tck*(WR_ACC+1), - ns
RDY active
or RDY timeout
Tagap Access Gap Tck*(AGAP - - ns
+1)
Ta_dly Address Delay - - 0.5 ns
Tcs_ale ALE with Chip Select - Tck/4 + 0.1 - ns
Chip Select active to ALE inactive
Ta_set Address Setup 0.4 Tck*DA_SET - ns
Address valid to Read/Write active
Ta_hd Address hold Tck/2 - Tck*DA_ ns
Write inactive to Address invalid HD
Tadr_set Address Setup Tck*(ALE_P - Tck*(ALE ns
Address valid to ALE inactive W+3/4) _PW+3/4)
+1.1
Tadr_hd Address Hold Tck/4 - 1.2 - Tck/4 ns
ALE inactive to Address invalid
Tda_dly Data bus Delay -0.5 - 0.5 ns
Tdaf Data Float -1.1 - 0.2 ns
Read active to Data bus float
Tdwr_set Data Write Setup 0.4 - Tck*DA_S ns
Data valid to Write active ET
Tdwr_hd Data Write Hold Tck/2 - Tck*DA_ ns
Write inactive to Data invalid (bus floating) HD
Trdy_set RDY Setup 0 - - ns
Tdak_dly DACK[1:0] Delay 0 - 0.6 ns
Tint_wd INT[1:0] Width Tck*2 - - ns
Table 4-2: Local Bus Timing Table

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5 Package Information

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6 Ordering Information
Part Number Description
AX99100 QF 68-pin QFN lead Free package, commercial temperature range: 0 to 70°C.
AX99100 QI 68-pin QFN lead Free package, Industrial temperature range: -40 to 85°C.

7 Revision History

Revision Date Comments

V0.20 2016/04/18 Preliminary release.
V0.21 2016/04/22 1. Added some descriptions for offset 0x55 bit2~6 in Section 3.3.1.
2. Changed offset 0x20 and 0x2A, Active 0/1 to Low/High in Section 3.3.2.
3. Added offset 0x5A~0x56 as Reserved fields in Section 3.3.2.
4. Added some descriptions for Local Address Space 0/1 Timing Setting, Local
Address Space 0/1 Address Setting in Section 3.3.2.
V0.22 2016/04/29 1. Changed offset 0x14 from 0xFF to 0xFD, offset 0x58 from 1 to 00 and offset
0x5B from 0x9F to 0xA2 in Table 3-7.
2. Added offset 0x53 ~ 0x54 and 0x56 in Table 3-4, Table 3-5 and section 3.3.1.
3. Added more descriptions in section 3.3 and 3.3.4.
V0.23 2016/05/06 1. Changed the offset 0x56 naming from “PCIe Function Enable” to “Global
Setting” in Table 3-4 and Table 3-5.
V0.24 2016/06/06 1. Changed the offset 0x58 from 0x01 to 0x00 for LB mode in Table 3-6.
2. Changed bit11:10 to “Reserved” for offset 0x21~0x20 and 0x2B~0x2A in
section 3.3.2.
V0.25 2015/02/02 1. Changed the naming from clock to CLKOs in RDY Timeout Select
V1.00 2018/11/07 1. Corrected the typo in section 2.6
V1.01 2019/05/03 1. Added the Max. frequency and Slot Clock information for EXT_CLK in Table
1-1
2. Modified the description for the external clock power down in Table 1-1
3. Corrected the typo of Space 0 to 1 for BAR1 in EEPROM and internal register
4. Modified all Local Bus timing diagrams and added two diagrams for
Multiplexed Bus Type access in section 4.5.5

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4F, No. 8, Hsin Ann Rd., HsinChu Science Park,

HsinChu, Taiwan, R.O.C.

TEL: 886-3-5799500
FAX: 886-3-5799558

Email: [email protected]
Web: http://www.asix.com.tw

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