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2023 Digital System Chapter 1 Part3

The document discusses the timing requirements for proper operation of sequential circuits. It states that the clock period must be long enough to satisfy the setup and hold times of flip-flops. It also notes that external inputs to the circuit must satisfy the setup and hold times of flip-flops. The document also covers Mealy sequential networks and their use of a combinational network, next state logic, and state register with a clock. Finally, it discusses tristate logic and how tristate buffers can be used with a bus to implement a point-to-point connection scheme for data transfer.

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22 views6 pages

2023 Digital System Chapter 1 Part3

The document discusses the timing requirements for proper operation of sequential circuits. It states that the clock period must be long enough to satisfy the setup and hold times of flip-flops. It also notes that external inputs to the circuit must satisfy the setup and hold times of flip-flops. The document also covers Mealy sequential networks and their use of a combinational network, next state logic, and state register with a clock. Finally, it discusses tristate logic and how tristate buffers can be used with a bus to implement a point-to-point connection scheme for data transfer.

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Digital System

Chapter #01:
Review of Logic Design Fundamentals
Part 3

Digital Systems Design Using VHDL


Charles H. Roth, Jr. and Lizy Kurian John

Ch.1 Review of Logic Design Fundamentals

Digital System

1.10 Sequential Circuit Timing

2 Ch.1 Review of Logic Design Fundamentals

 1
Digital System

1.10 Sequential Circuit Timing

3 Ch.1 Review of Logic Design Fundamentals

Digital System

1.10 Sequential Circuit Timing


 Timing Conditions for Proper Operation

1. Clock period should be long enough to satisfy flip-flop setup time

2. Clock period should be long enough to satisfy flip-flop hold time

3. External input changes to the circuit should satisfy flip-flop setup time

4. External input changes to the circuit should satisfy flip-flop hold times

4 Ch.1 Review of Logic Design Fundamentals

 2
Digital System

1.7 Mealy Sequential Network Design

Input (X) Output (Z)


Combinational
Next State State
Network State
Reg
Clock

• Clock period and setup time / hold time

5 Ch.1 Review of Logic Design Fundamentals

Digital System

1.10 Sequential Circuit Timing

tsu

6 Ch.1 Review of Logic Design Fundamentals

 3
Digital System

1.10 Sequential Circuit Timing

th

7 Ch.1 Review of Logic Design Fundamentals

Digital System

1.10 Sequential Circuit Timing

• Input X and setup time / hold time

8 Ch.1 Review of Logic Design Fundamentals

 4
Digital System

1.10 Sequential Circuit Timing

9 Ch.1 Review of Logic Design Fundamentals

Digital System

1.11 Tristate Logic and Busses

B B B B

A C A C A C A C

B A C B A C B A C B A C
0 0 Hi-Z 0 0 Hi-Z 0 0 0 0 0 1
0 1 Hi-Z 0 1 Hi-Z 0 1 1 0 1 0
1 0 0 1 0 1 1 0 Hi-Z 1 0 Hi-Z
1 1 1 1 1 0 1 1 Hi-Z 1 1 Hi-Z

(a) (b) (c) (d)

<Figure 1-35 Four Kinds of Tristate Buffers>

10 Ch.1 Review of Logic Design Fundamentals

 5
Digital System

1.11 Tristate Logic and Busses

<Figure 1-36 Data Transfer Using Tristate Bus>

11 Ch.1 Review of Logic Design Fundamentals

Digital System

1.11 Tristate Logic and Busses

 Point-to-Point Connection Scheme

S0<1:0> S1<1:0> S2<1:0> S3<1:0>


MUX MUX MUX MUX

LD0 LD1 LD2 LD3


R0 R1 R2 R3

12 Ch.1 Review of Logic Design Fundamentals

 6

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