Sample Exam
Sample Exam
Spring 2015
EE513-Power Electronics
04/28/15
Time Limit: 90 Minutes Advisor Name
This exam contains 12 pages (including this cover page) and 3 problems. Check to see if any pages
are missing. Enter all requested information on the top of this page, and put your initials on the
top of every page, in case the pages become separated.
You are required to show your work on each problem in this exam. The following rules apply:
1. (40 points) A buck converter is to be designed to deliver power from a DC input with voltage
12V to an output of 5V . The switching frequency is chosen to be f = 25kHz. The specifications
call for a 20mV peak-to-peak output-voltage ripple, and a 0.8A peak-to-peak inductor-current
ripple. Assume all switching and filter components are ideal.
(a) (10 points) What is the duty cycle that the converter should operate at?
(b) (10 points) What value of filter inductance would meet the specifications?
(c) (10 points) What value of filter capacitance would meet the specifications?
(d) (10 points) Assuming a load resistance, R = 500Ω, what is the critical filter inductance
for the converter?
Midterm Exam EE513-Power Electronics - Page 3 of 12 04/28/15
Midterm Exam EE513-Power Electronics - Page 4 of 12 04/28/15
2. (20 points) In the buck-boost converter, the inductor has winding resistance of RL . All other
losses can be ignored.
(a) (8 points) Derive and plot the equivalent circuit model of this converter utilizing the dc
transformer.
(b) (6 points) Derive an expression for the nonideal voltage converter ratio V /Vg .
(c) (6 points) Derive an expression for the conversion efficiency.
3. (40 points) A DCM boost converter is to be designed to operate under the following conditions:
18V ≤ Vg ≤ 36V
5W ≤ Pload ≤ 100W
V = 48V
fs = 150kHz
You may assume that a feedback loop will vary to transistor duty cycle as necessary to maintain
a constant output voltage of 48V .
Design the converter, subject to the following considerations:
• The converter should operate in the discontinuous conduction mode at all times. To ensure
2L
an adequate design margin, the inductance L should be chosen such that K (K = RT s
) is
no greater than 75% of Kcrit at all operating points.
• Given the above requirements, choose the element values to minimize the peak inductor
current.
• The output voltage peak ripple should be less than 1V .
Specify:
(a) (8 points) The expression for Kcrit .
(b) (8 points) The inductor value L.
(c) (8 points) The output capacitor value C.
(d) (8 points) The worst case peak inductor current ipk .
(e) (8 points) The maximum and minimum values of the transistor duty cycle D.