9/22/23, 10:03 AM Draw the instruction word format and indicate the number of bits in each part

Main page
Draw the instruction word format and following program
indicate the number of bits in each
part same task

✕ binary value

Chapter 5

#13 A computer uses a memory unit 256k words of

32 bits each. A binary instruction code is stored in
one word of memory. The instruction has four parts
: indirect bit , an operation code , a register code
part to specify one of 64 registers, and an address
part.

1.
How many bits are there in the operation
code , the register code part , and the address
part?
2.
Draw the instruction word format and
indicate the number of bits in each part.
3.
How many bits are there in the data and
address inputs of the memory?

Ans:

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9/22/23, 10:03 AM Draw the instruction word format and indicate the number of bits in each part

#14 What is the difference between a direct and an

indirect address instruction?

How many references to memory are needed for

each type of instruction to bring an operand into a
processor register?

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#15 What are the two instructions needed in the

basic computer in order to set the E flip–flop to 1?

Ans:

#16 Draw a timing diagram similar to fig 5-7(refer

morris mano) assuming that SC is cleared to 0 at
time T3 if control signal C7 is active.

C7T3 : SC←0

C7 is activated with the positive clock transition

associated with T1.

Ans:
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Chapter 8

#17 A bus – organized CPU has 16 registers with

32 bits in each , an ALU , and a destination
decoder.

1.
How many multiplexers are there in the A
bus , and what is the size of each
multiplexer?
2.
How many selection inputs are needed for
mux A and mux B?
3.
How many inputs and outputs are there in
the decoder?
4.
How many inputs and outputs are there in
the ALU for data, including input and output
carries?
5.
Formulate a control word for the system
assuming that the ALU has 35 operations.

Ans:

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9/22/23, 10:03 AM Draw the instruction word format and indicate the number of bits in each part

#18 Specify the control word that must be applied

to the processor of fig 8-2(refer morris mano) to
implement the following microoperations

1.
R1 ← R2 +R3
2.
R4 ← R4
3.
R5 ← R5 – 1
4.
R6 ← shl R1
5.
R7 ← input

Ans:

#19 Convert the following arithmetic expressions

from infix to reverse polish notation.

1.
A*B + C*D + E*F
2.
A*B+A*(B*D + C*E)
3.
A + B *[(C*D + E*(F +G)]
4.
A*[B +C * (D
+E)]

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F* (G +H)

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#20 Convert the following arithmetic expressions

from reverse polish notation to infix polish
notation.

1.
A B C D E +*-/
2.
A B C D E */-+
3.
A B C D E F G +*+*+*
4.
A B C */D – E F /+

Ans:

#21 A computer has 32-bit instructions and 12-bit

addresses.If there are 250 two address instructions,
how many one – address instruction can be
formulated ?

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9/22/23, 10:03 AM Draw the instruction word format and indicate the number of bits in each part

Ans:

#22 Write a program to evaluate the arithmetic

statement:

X= A – B + C * (D*E
– F)

G + H *K

1.
Using a general register computer with three
address instructions.
2.
Using a general register computer with two
address instructions.
3.
Using an accumulator type computer with
one address instructions.
4.
Using a stack organized computer with zero-
address operation instructions.

#23 A two-word instruction is stored in memory at

an address designated by the symbol W. The
address field of the instruction (stored at W +1 ) is
designated by the symbol Y . the operand used
during the execution of the instruction is stored at
an address symbolized by z. An index register
containsthe value X. State how Z is calculated from
other addresses if the addressing of the instruction
is

1.
Direct
2.
Indirect

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3.
Relative
4.
Indexed

Ans:

#24 A relative mode branch type of instruction is

stored in memory at an address equivalent to
decimal 750 . the branch is made to an address
equivalent to decimal 500.

1.
What should be the value of the relative
address field of the instruction (in decimal)?
2.
Determine the relative address value in
binary using 12 bits .(why must the number
be in 2’s complement?)
3.
Determine the binary value in PC after the
fetch phase and calculate the binary value of
500. Then show that the binary in PC plus
the relative address calculated in part b is
equal to the binary value of 500.

Ans:

#25 An instruction is stored at location 300 with its

address field at location 301 . the address field has
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9/22/23, 10:03 AM Draw the instruction word format and indicate the number of bits in each part

the value 400 . A processor register R1 contains the

number 200. Evaluate the effective address if the
addressing mode of the instruction is (a) direct (b)
immediate (c)relative (d) register indirect (e) index
with R1 as the index register.

Chapter -9

#26 In certain scientific computations it is

necessary to perform the arithmetic operation (Ai
+Bi)(Ci + Di) with a stream of numbers . Specify a
pipeline configuration to carry out this task . List
the contents of all registers in the pipeline for i=1
through 6.

Ans:

#27 Draw a space-time diagram for a six-segment

pipeline showing the time it takes to process eight
tasks.

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9/22/23, 10:03 AM Draw the instruction word format and indicate the number of bits in each part

Ans:

#28 Determine the number of clock cycles that it

takes to process 200 tasks in a six-segment
pipeline.

Ans:

#29 The nonpipeline system takes 50 ns to process

a task . the same task can be processed in a six –
segment pipeline with clock cycle of 10ns .
Determine the speedup ratio of the pipeline for
100ns task . what is the maximum speedup that can
be achieved?

Ans:

#30 consider the four instructions in the following

program . suppose that the first instruction starts
from step 1 in the pipeline used in fig 9-8 . specify
what operation are performed in the four segments
during step 4.

Load R1 ← M[312]

ADD R2 ← R2 + M[313]

Inc R3 ← R3 +1
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9/22/23, 10:03 AM Draw the instruction word format and indicate the number of bits in each part

Store M[314] ← R3

Ans:

#31 Give an Example that uses delayed load with

the three-segment pipeline of sec 9-5 (refer morris
mano)

Ans:

#32 Consider the multiplication of two 40 ×40

matrices using a vector processor .

1.
How many product terms are there in each
inner product , and how many inner products
must be evaluated?
2.
How many multiply-add operations are
needed to calculate the product matrix?

Ans:

#33 Show the contents of registers E,A,Q and SC

(as in fig 10-12, refer morris mano) during the
process of multiplication of two binary numbers
,11111 (multiplicand) and 10101 (multiplier) .the
signs are not included.

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9/22/23, 10:03 AM Draw the instruction word format and indicate the number of bits in each part

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#34 Why should the sign of the remainder after a

division be the same as the sign of the dividend ?

Ans:

#35 Show the contents of registers E,A,Q and SC

(as in fig 10-12, refer morris mano) during the
process of division of (a) 10100011 by 1011; (b)
00001111 by 0011.(use a dividend of eight bits.)

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9/22/23, 10:03 AM Draw the instruction word format and indicate the number of bits in each part

Ans:

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