Deliverable’s:

You are to do this project individually. You have to show your results in a report as well as in a
PROJECT ET4521 Winter 2016 presentation. You have to deliver the following:
- Report with:
- your name and student number on the first page
DUE DATE: Thursday March 31, 2016 - Table 1 filled out with results on the first page
- short explanation (half a page is sufficient, no more than 1 page) of:
FINAL PRESENTATION: Thursday April 7, 2016 - how you did your design,
- what was your biggest problem and
- what could be a next step to improve this design
Introduction: - Table 2 filled out with check-marks on the last page
This Final Project is about the design of a Hifi Head-Phone Amplifier for driving an equivalent load
impedance of 16//100pF with high quality audio specifications in 0.18um CMOS. - Final Presentation:
- the total group will be divided over 2 sessions
- you will see all presentations in your session
Project Description: - 10 minutes per person
The amplifier is going to be used in a gain configuration as shown in the figure below. The feedback - avoid explaining the obvious (you will see all other presentation in your session)
has to be designed such that 4x gain is achieved in the audio-band (20Hz - 20kHz) with less than or - focus on:
equal to 0.1dB deviation. The values of the resistors and capacitor in the feedback are free to - what you did different
choose. The equivalent load-impedance of the headphone to be driven by this amplifier is 16in - what your specific problems were
parallel to 100pF. Any type of amplifier design is allowed, as long as a set of minimum specifications - what you could improve
(shown in table 2) is achieved. The goal of this project is to achieve all the specifications at a mini-
mum power dissipation.
Approach:
You will need to keep all transistors biased properly, have your timing set up correctly for the
Specifications: FFTs and slowly converge to a working solution, meeting all the specifications and obtain low
The Headphone Amplifier has to be designed with the following minimum specifications: power at the same time. You will find that it is pretty hard to do that if you go for the ultimate goal
immediately. A better route is to start simple and very gradually add more complexity to slowly
- all specifications of table 2 approach your final goal. You may find the following approach useful:
- 1.8 [V] supply - make only 1 change at a time and always keep a back-up of the last good
- Load Capacitance: Cload = 100pF working circuit
- Load Resistance: Rload = 16 - make a set-up of the simulations that are asked for (see deliverable’s table 2)
- Power as small as possible - if you decide to use Gain-boosting, start with ideal gain-boost amplifiers
- OpAmp architecture free to choose - your priority is always (in this order):
- make sure your biasing is correct (also after changes)
- make sure your stability is ok (check also with step-response)
- check your linearity in a 2-tone test (make sure your FFT-timing is set-up
Cfb correctly, check section 1.4 from the textbook)
- achieve the required linearity at low frequencies (1.25kHz)
- achieve the required linearity at high frequencies (20kHz)
- optimize the white-noise by sizing the gm of relevant transistors

Rin Rfb - optimize the 1/f-noise by sizing the area of relevant transistors
- obtain the lowest total power dissipation
- in all of the above keep checking the above mentioned list of priorities
Vin Vout Advice:
The hardest part of this project is the complexity of the total circuit to be simulated. It is very easy
Rload Cload to lose yourself in that. To prevent that from happening you have to keep things as simple as pos-
sible and work very disciplined. It is also very important to start on this project as early as possi-
ble, which really means: start now. I hope you have seen from the project in Part 1 of this
course, that is very easy to under-estimate the task. Therefore, do the majority of the work now,
get it to work (I am not yet talking about getting perfect performance or low power yet) and spend
the last weeks only on optimizations to realize the performance asked for and obtain the lowest Table 2: Please print this table filled out on page 1 of your report
possible power-dissipation. Don’t hesitate to ask me or the TA’s for help, which usually works
best when we sit together in front of the PC and look at the simulations. Don’t waste a lot of time Specification Goal Your Result
when you don’t see any progress: get help. The most important part of the advice at this
moment: work disciplined (keep the previous version, make only 1 change at a time) and keep Output Swing 1.2 [Vpp]
things simple. You can always decide to make it complicated in the end :)
Output Swing 424 [mVrms]
Delivery:
0.1dB Bandwidth > 20 [kHz]
To submit your report we will ask you to upload it to BlackBoard. Detailed instructions on how to
do this will follow later. Closed Loop Gain (20Hz - 20kHz) 12 +/- 0.1 [dB]

Grading: Closed Loop Gain at 20Hz 12 +/- 0.1 [dB]

All your results will be entered in a large Excel-file. If you don’t meet certain specifications, you
Closed Loop Gain at 20kHz 12 +/- 0.1 [dB]
will be given a penalty, proportional to how much you are short. If you are exceeding the specifi-
cations, you will get a small bonus (smaller than the penaly you will receive for specification you Output Integrated Noise power -
fall short on). For the Power Dissipation you will get points expressed in dB’s, compared to a ref-
erence power. After all results are entered, a ranking occurs and the ranking will be mapped on SNR 96 [dB]
grades between 1 and 10.. After taking in to account the points for the report and the presenta-
tion, a final grade will be calculated. Please note that low power-dissipation is important.
SFDR (6.25Hz) [only in the audio band] 96 [dB]
SFDR (1.25kHz) [only in the audio band] 96 [dB]
Table 1: Deliverable’s - use this as check-list and print on last page
SFDR (2.5kHz) [only in the audio band] 96 [dB]
Deliverable Check
SFDR (5.0kHz) [only in the audio band] 96 [dB]
Transient simulation results for Output Swing
SFDR (10kHz) [only in the audio band] 96 [dB]
AC simulation results showing closed-loop Bandwidth
SFDR (20kHz) [only in the audio band] 96 [dB]
AC simulations results showing the output Noise Spectrum
IM3 (6.25Hz) [worst-case side-tone] 105 [dB]
Integrated Noise number from AC simulation
IM3 (1.25kHz) [worst-case side-tone] 105 [dB]
SNR calculation
IM3 (2.5kHz) [worst-case side-tone] 105 [dB]
Spectrum showing the SFDR for all requested frequencies
IM3 (5.0kHz) [worst-case side-tone] 105 [dB]
Spectrum showing the IM3 for all requested frequencies
IM3 (10kHz) [worst-case side-tone] 105 [dB]
Circuit Diagram with annotated branch currents
IM3 (20kHz) [worst-case side-tone] 105 [dB]
AC simulation results of the loop gain A
Power Dissipation (active circuit excluding bias) -
Indication of the Phase Margin in the plot of the loop gain
Amplifier Architecture -
Indication of the Gain Margin in the plot of the loop gain
Openloop Gain (A) -
Circuit used for open-loop simulation
Openloop Unity-Gain Frequency -
Circuit set-up for IM3 / SFDR simulations
Openloop Phase Margin > 60 [o]
Table 1 filled out completely
Openloop Gain Margin > 14 [dB]
Circuit Diagram with annotated node voltages
IM3 versus frequency in 1 single graph
SFDR versus frequency in 1 single graph